1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
6 * Copyright(c) 2018 Intel Corporation. All rights reserved.
9 #ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__
10 #define __INCLUDE_SOUND_SOF_TOPOLOGY_H__
12 #include <sound/sof/header.h>
18 /* types of component */
23 SOF_COMP_SG_HOST, /**< scatter gather variant */
24 SOF_COMP_SG_DAI, /**< scatter gather variant */
29 SOF_COMP_DEPRECATED0, /* Formerly SOF_COMP_SPLITTER */
31 SOF_COMP_DEPRECATED1, /* Formerly SOF_COMP_SWITCH */
35 SOF_COMP_KEYWORD_DETECT,
36 SOF_COMP_KPB, /* A key phrase buffer component */
37 SOF_COMP_SELECTOR, /**< channel selector component */
39 SOF_COMP_ASRC, /**< Asynchronous sample rate converter */
41 SOF_COMP_SMART_AMP, /**< smart amplifier component */
42 SOF_COMP_MODULE_ADAPTER, /**< module adapter */
43 /* keep FILEREAD/FILEWRITE as the last ones */
44 SOF_COMP_FILEREAD = 10000, /**< host test based file IO */
45 SOF_COMP_FILEWRITE = 10001, /**< host test based file IO */
48 /* XRUN action for component */
49 #define SOF_XRUN_STOP 1 /**< stop stream */
50 #define SOF_XRUN_UNDER_ZERO 2 /**< send 0s to sink */
51 #define SOF_XRUN_OVER_NULL 4 /**< send data to NULL */
53 /* create new generic component - SOF_IPC_TPLG_COMP_NEW */
55 struct sof_ipc_cmd_hdr hdr;
57 enum sof_comp_type type;
61 /* extended data length, 0 if no extended data */
62 uint32_t ext_data_length;
63 } __packed __aligned(4);
70 * SOF memory capabilities, add new ones at the end
72 #define SOF_MEM_CAPS_RAM BIT(0)
73 #define SOF_MEM_CAPS_ROM BIT(1)
74 #define SOF_MEM_CAPS_EXT BIT(2) /**< external */
75 #define SOF_MEM_CAPS_LP BIT(3) /**< low power */
76 #define SOF_MEM_CAPS_HP BIT(4) /**< high performance */
77 #define SOF_MEM_CAPS_DMA BIT(5) /**< DMA'able */
78 #define SOF_MEM_CAPS_CACHE BIT(6) /**< cacheable */
79 #define SOF_MEM_CAPS_EXEC BIT(7) /**< executable */
80 #define SOF_MEM_CAPS_L3 BIT(8) /**< L3 memory */
83 * overrun will cause ring buffer overwrite, instead of XRUN.
85 #define SOF_BUF_OVERRUN_PERMITTED BIT(0)
88 * underrun will cause readback of 0s, instead of XRUN.
90 #define SOF_BUF_UNDERRUN_PERMITTED BIT(1)
92 /* the UUID size in bytes, shared between FW and host */
93 #define SOF_UUID_SIZE 16
95 /* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */
96 struct sof_ipc_buffer {
97 struct sof_ipc_comp comp;
98 uint32_t size; /**< buffer size in bytes */
99 uint32_t caps; /**< SOF_MEM_CAPS_ */
100 uint32_t flags; /**< SOF_BUF_ flags defined above */
101 uint32_t reserved; /**< reserved for future use */
102 } __packed __aligned(4);
104 /* generic component config data - must always be after struct sof_ipc_comp */
105 struct sof_ipc_comp_config {
106 struct sof_ipc_cmd_hdr hdr;
107 uint32_t periods_sink; /**< 0 means variable */
108 uint32_t periods_source;/**< 0 means variable */
109 uint32_t reserved1; /**< reserved */
110 uint32_t frame_fmt; /**< SOF_IPC_FRAME_ */
111 uint32_t xrun_action;
113 /* reserved for future use */
114 uint32_t reserved[2];
115 } __packed __aligned(4);
117 /* generic host component */
118 struct sof_ipc_comp_host {
119 struct sof_ipc_comp comp;
120 struct sof_ipc_comp_config config;
121 uint32_t direction; /**< SOF_IPC_STREAM_ */
122 uint32_t no_irq; /**< don't send periodic IRQ to host/DSP */
123 uint32_t dmac_config; /**< DMA engine specific */
124 } __packed __aligned(4);
126 /* generic DAI component */
127 struct sof_ipc_comp_dai {
128 struct sof_ipc_comp comp;
129 struct sof_ipc_comp_config config;
130 uint32_t direction; /**< SOF_IPC_STREAM_ */
131 uint32_t dai_index; /**< index of this type dai */
132 uint32_t type; /**< DAI type - SOF_DAI_ */
133 uint32_t reserved; /**< reserved */
134 } __packed __aligned(4);
136 /* generic mixer component */
137 struct sof_ipc_comp_mixer {
138 struct sof_ipc_comp comp;
139 struct sof_ipc_comp_config config;
140 } __packed __aligned(4);
142 /* volume ramping types */
143 enum sof_volume_ramp {
144 SOF_VOLUME_LINEAR = 0,
146 SOF_VOLUME_LINEAR_ZC,
148 SOF_VOLUME_WINDOWS_FADE,
149 SOF_VOLUME_WINDOWS_NO_FADE,
152 /* generic volume component */
153 struct sof_ipc_comp_volume {
154 struct sof_ipc_comp comp;
155 struct sof_ipc_comp_config config;
159 uint32_t ramp; /**< SOF_VOLUME_ */
160 uint32_t initial_ramp; /**< ramp space in ms */
161 } __packed __aligned(4);
163 /* generic SRC component */
164 struct sof_ipc_comp_src {
165 struct sof_ipc_comp comp;
166 struct sof_ipc_comp_config config;
167 /* either source or sink rate must be non zero */
168 uint32_t source_rate; /**< source rate or 0 for variable */
169 uint32_t sink_rate; /**< sink rate or 0 for variable */
170 uint32_t rate_mask; /**< SOF_RATE_ supported rates */
171 } __packed __aligned(4);
173 /* generic ASRC component */
174 struct sof_ipc_comp_asrc {
175 struct sof_ipc_comp comp;
176 struct sof_ipc_comp_config config;
177 /* either source or sink rate must be non zero */
178 uint32_t source_rate; /**< Define fixed source rate or */
179 /**< use 0 to indicate need to get */
180 /**< the rate from stream */
181 uint32_t sink_rate; /**< Define fixed sink rate or */
182 /**< use 0 to indicate need to get */
183 /**< the rate from stream */
184 uint32_t asynchronous_mode; /**< synchronous 0, asynchronous 1 */
185 /**< When 1 the ASRC tracks and */
186 /**< compensates for drift. */
187 uint32_t operation_mode; /**< push 0, pull 1, In push mode the */
188 /**< ASRC consumes a defined number */
189 /**< of frames at input, with varying */
190 /**< number of frames at output. */
191 /**< In pull mode the ASRC outputs */
192 /**< a defined number of frames while */
193 /**< number of input frames varies. */
195 /* reserved for future use */
196 uint32_t reserved[4];
197 } __packed __aligned(4);
199 /* generic MUX component */
200 struct sof_ipc_comp_mux {
201 struct sof_ipc_comp comp;
202 struct sof_ipc_comp_config config;
203 } __packed __aligned(4);
205 /* generic tone generator component */
206 struct sof_ipc_comp_tone {
207 struct sof_ipc_comp comp;
208 struct sof_ipc_comp_config config;
218 } __packed __aligned(4);
220 /** \brief Types of processing components */
221 enum sof_ipc_process_type {
222 SOF_PROCESS_NONE = 0, /**< None */
223 SOF_PROCESS_EQFIR, /**< Intel FIR */
224 SOF_PROCESS_EQIIR, /**< Intel IIR */
225 SOF_PROCESS_KEYWORD_DETECT, /**< Keyword Detection */
226 SOF_PROCESS_KPB, /**< KeyPhrase Buffer Manager */
227 SOF_PROCESS_CHAN_SELECTOR, /**< Channel Selector */
231 SOF_PROCESS_SMART_AMP, /**< Smart Amplifier */
234 /* generic "effect", "codec" or proprietary processing component */
235 struct sof_ipc_comp_process {
236 struct sof_ipc_comp comp;
237 struct sof_ipc_comp_config config;
238 uint32_t size; /**< size of bespoke data section in bytes */
239 uint32_t type; /**< sof_ipc_process_type */
241 /* reserved for future use */
242 uint32_t reserved[7];
244 unsigned char data[];
245 } __packed __aligned(4);
247 /* frees components, buffers and pipelines
248 * SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_FREE, SOF_IPC_TPLG_BUFFER_FREE
250 struct sof_ipc_free {
251 struct sof_ipc_cmd_hdr hdr;
253 } __packed __aligned(4);
255 struct sof_ipc_comp_reply {
256 struct sof_ipc_reply rhdr;
259 } __packed __aligned(4);
265 /** \brief Types of pipeline scheduling time domains */
266 enum sof_ipc_pipe_sched_time_domain {
267 SOF_TIME_DOMAIN_DMA = 0, /**< DMA interrupt */
268 SOF_TIME_DOMAIN_TIMER, /**< Timer interrupt */
271 /* new pipeline - SOF_IPC_TPLG_PIPE_NEW */
272 struct sof_ipc_pipe_new {
273 struct sof_ipc_cmd_hdr hdr;
274 uint32_t comp_id; /**< component id for pipeline */
275 uint32_t pipeline_id; /**< pipeline id */
276 uint32_t sched_id; /**< Scheduling component id */
277 uint32_t core; /**< core we run on */
278 uint32_t period; /**< execution period in us*/
279 uint32_t priority; /**< priority level 0 (low) to 10 (max) */
280 uint32_t period_mips; /**< worst case instruction count per period */
281 uint32_t frames_per_sched;/**< output frames of pipeline, 0 is variable */
282 uint32_t xrun_limit_usecs; /**< report xruns greater than limit */
283 uint32_t time_domain; /**< scheduling time domain */
284 } __packed __aligned(4);
286 /* pipeline construction complete - SOF_IPC_TPLG_PIPE_COMPLETE */
287 struct sof_ipc_pipe_ready {
288 struct sof_ipc_cmd_hdr hdr;
290 } __packed __aligned(4);
292 struct sof_ipc_pipe_free {
293 struct sof_ipc_cmd_hdr hdr;
295 } __packed __aligned(4);
297 /* connect two components in pipeline - SOF_IPC_TPLG_COMP_CONNECT */
298 struct sof_ipc_pipe_comp_connect {
299 struct sof_ipc_cmd_hdr hdr;
302 } __packed __aligned(4);
304 /* external events */
305 enum sof_event_types {
307 SOF_KEYWORD_DETECT_DAPM_EVENT,