include/sound/sof/ipc4/header.h

   1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
   2 /*
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * Copyright(c) 2022 Intel Corporation. All rights reserved.
   7  */
   8
   9 #ifndef __INCLUDE_SOUND_SOF_IPC4_HEADER_H__
  10 #define __INCLUDE_SOUND_SOF_IPC4_HEADER_H__
  11
  12 #include <linux/types.h>
  13 #include <uapi/sound/sof/abi.h>
  14
  15 /* maximum message size for mailbox Tx/Rx */
  16 #define SOF_IPC4_MSG_MAX_SIZE                   4096
  17
  18 /** \addtogroup sof_uapi uAPI
  19  *  SOF uAPI specification.
  20  *  @{
  21  */
  22
  23 /**
  24  * struct sof_ipc4_msg - Placeholder of an IPC4 message
  25  * @header_u64:         IPC4 header as single u64 number
  26  * @primary:            Primary, mandatory part of the header
  27  * @extension:          Extended part of the header, if not used it should be
  28  *                      set to 0
  29  * @data_size:          Size of data in bytes pointed by @data_ptr
  30  * @data_ptr:           Pointer to the optional payload of a message
  31  */
  32 struct sof_ipc4_msg {
  33         union {
  34                 u64 header_u64;
  35                 struct {
  36                         u32 primary;
  37                         u32 extension;
  38                 };
  39         };
  40
  41         size_t data_size;
  42         void *data_ptr;
  43 };
  44
  45 /**
  46  * struct sof_ipc4_tuple - Generic type/ID and parameter tuple
  47  * @type:               type/ID
  48  * @size:               size of the @value array in bytes
  49  * @value:              value for the given type
  50  */
  51 struct sof_ipc4_tuple {
  52         uint32_t type;
  53         uint32_t size;
  54         uint32_t value[];
  55 } __packed;
  56
  57 /*
  58  * IPC4 messages have two 32 bit identifier made up as follows :-
  59  *
  60  * header - msg type, msg id, msg direction ...
  61  * extension - extra params such as msg data size in mailbox
  62  *
  63  * These are sent at the start of the IPC message in the mailbox. Messages
  64  * should not be sent in the doorbell (special exceptions for firmware).
  65  */
  66
  67 /*
  68  * IPC4 primary header bit allocation for messages
  69  * bit 0-23:    message type specific
  70  * bit 24-28:   type:   enum sof_ipc4_global_msg if target is SOF_IPC4_FW_GEN_MSG
  71  *                      enum sof_ipc4_module_type if target is SOF_IPC4_MODULE_MSG
  72  * bit 29:      response - sof_ipc4_msg_dir
  73  * bit 30:      target - enum sof_ipc4_msg_target
  74  * bit 31:      reserved, unused
  75  */
  76
  77 /* Value of target field - must fit into 1 bit */
  78 enum sof_ipc4_msg_target {
  79         /* Global FW message */
  80         SOF_IPC4_FW_GEN_MSG,
  81
  82         /* Module message */
  83         SOF_IPC4_MODULE_MSG
  84 };
  85
  86 /* Value of type field - must fit into 5 bits */
  87 enum sof_ipc4_global_msg {
  88         SOF_IPC4_GLB_BOOT_CONFIG,
  89         SOF_IPC4_GLB_ROM_CONTROL,
  90         SOF_IPC4_GLB_IPCGATEWAY_CMD,
  91
  92         /* 3 .. 12: RESERVED - do not use */
  93
  94         SOF_IPC4_GLB_PERF_MEASUREMENTS_CMD = 13,
  95         SOF_IPC4_GLB_CHAIN_DMA,
  96
  97         SOF_IPC4_GLB_LOAD_MULTIPLE_MODULES,
  98         SOF_IPC4_GLB_UNLOAD_MULTIPLE_MODULES,
  99
 100         /* pipeline settings */
 101         SOF_IPC4_GLB_CREATE_PIPELINE,
 102         SOF_IPC4_GLB_DELETE_PIPELINE,
 103         SOF_IPC4_GLB_SET_PIPELINE_STATE,
 104         SOF_IPC4_GLB_GET_PIPELINE_STATE,
 105         SOF_IPC4_GLB_GET_PIPELINE_CONTEXT_SIZE,
 106         SOF_IPC4_GLB_SAVE_PIPELINE,
 107         SOF_IPC4_GLB_RESTORE_PIPELINE,
 108
 109         /* Loads library (using Code Load or HD/A Host Output DMA) */
 110         SOF_IPC4_GLB_LOAD_LIBRARY,
 111
 112         /* 25: RESERVED - do not use */
 113
 114         SOF_IPC4_GLB_INTERNAL_MESSAGE = 26,
 115
 116         /* Notification (FW to SW driver) */
 117         SOF_IPC4_GLB_NOTIFICATION,
 118
 119         /* 28 .. 31: RESERVED - do not use */
 120
 121         SOF_IPC4_GLB_TYPE_LAST,
 122 };
 123
 124 /* Value of response field - must fit into 1 bit */
 125 enum sof_ipc4_msg_dir {
 126         SOF_IPC4_MSG_REQUEST,
 127         SOF_IPC4_MSG_REPLY,
 128 };
 129
 130 enum sof_ipc4_pipeline_state {
 131         SOF_IPC4_PIPE_INVALID_STATE,
 132         SOF_IPC4_PIPE_UNINITIALIZED,
 133         SOF_IPC4_PIPE_RESET,
 134         SOF_IPC4_PIPE_PAUSED,
 135         SOF_IPC4_PIPE_RUNNING,
 136         SOF_IPC4_PIPE_EOS
 137 };
 138
 139 /* Generic message fields (bit 24-30) */
 140
 141 /* encoded to header's msg_tgt field */
 142 #define SOF_IPC4_MSG_TARGET_SHIFT               30
 143 #define SOF_IPC4_MSG_TARGET_MASK                BIT(30)
 144 #define SOF_IPC4_MSG_TARGET(x)                  ((x) << SOF_IPC4_MSG_TARGET_SHIFT)
 145 #define SOF_IPC4_MSG_IS_MODULE_MSG(x)           ((x) & SOF_IPC4_MSG_TARGET_MASK ? 1 : 0)
 146
 147 /* encoded to header's rsp field */
 148 #define SOF_IPC4_MSG_DIR_SHIFT                  29
 149 #define SOF_IPC4_MSG_DIR_MASK                   BIT(29)
 150 #define SOF_IPC4_MSG_DIR(x)                     ((x) << SOF_IPC4_MSG_DIR_SHIFT)
 151
 152 /* encoded to header's type field */
 153 #define SOF_IPC4_MSG_TYPE_SHIFT                 24
 154 #define SOF_IPC4_MSG_TYPE_MASK                  GENMASK(28, 24)
 155 #define SOF_IPC4_MSG_TYPE_SET(x)                (((x) << SOF_IPC4_MSG_TYPE_SHIFT) & \
 156                                                  SOF_IPC4_MSG_TYPE_MASK)
 157 #define SOF_IPC4_MSG_TYPE_GET(x)                (((x) & SOF_IPC4_MSG_TYPE_MASK) >> \
 158                                                  SOF_IPC4_MSG_TYPE_SHIFT)
 159
 160 /* Global message type specific field definitions */
 161
 162 /* pipeline creation ipc msg */
 163 #define SOF_IPC4_GLB_PIPE_INSTANCE_SHIFT        16
 164 #define SOF_IPC4_GLB_PIPE_INSTANCE_MASK         GENMASK(23, 16)
 165 #define SOF_IPC4_GLB_PIPE_INSTANCE_ID(x)        ((x) << SOF_IPC4_GLB_PIPE_INSTANCE_SHIFT)
 166
 167 #define SOF_IPC4_GLB_PIPE_PRIORITY_SHIFT        11
 168 #define SOF_IPC4_GLB_PIPE_PRIORITY_MASK         GENMASK(15, 11)
 169 #define SOF_IPC4_GLB_PIPE_PRIORITY(x)           ((x) << SOF_IPC4_GLB_PIPE_PRIORITY_SHIFT)
 170
 171 #define SOF_IPC4_GLB_PIPE_MEM_SIZE_SHIFT        0
 172 #define SOF_IPC4_GLB_PIPE_MEM_SIZE_MASK         GENMASK(10, 0)
 173 #define SOF_IPC4_GLB_PIPE_MEM_SIZE(x)           ((x) << SOF_IPC4_GLB_PIPE_MEM_SIZE_SHIFT)
 174
 175 #define SOF_IPC4_GLB_PIPE_EXT_LP_SHIFT          0
 176 #define SOF_IPC4_GLB_PIPE_EXT_LP_MASK           BIT(0)
 177 #define SOF_IPC4_GLB_PIPE_EXT_LP(x)             ((x) << SOF_IPC4_GLB_PIPE_EXT_LP_SHIFT)
 178
 179 /* pipeline set state ipc msg */
 180 #define SOF_IPC4_GLB_PIPE_STATE_ID_SHIFT                16
 181 #define SOF_IPC4_GLB_PIPE_STATE_ID_MASK         GENMASK(23, 16)
 182 #define SOF_IPC4_GLB_PIPE_STATE_ID(x)           ((x) << SOF_IPC4_GLB_PIPE_STATE_ID_SHIFT)
 183
 184 #define SOF_IPC4_GLB_PIPE_STATE_SHIFT           0
 185 #define SOF_IPC4_GLB_PIPE_STATE_MASK            GENMASK(15, 0)
 186 #define SOF_IPC4_GLB_PIPE_STATE(x)              ((x) << SOF_IPC4_GLB_PIPE_STATE_SHIFT)
 187
 188 enum sof_ipc4_channel_config {
 189         /* one channel only. */
 190         SOF_IPC4_CHANNEL_CONFIG_MONO,
 191         /* L & R. */
 192         SOF_IPC4_CHANNEL_CONFIG_STEREO,
 193         /* L, R & LFE; PCM only. */
 194         SOF_IPC4_CHANNEL_CONFIG_2_POINT_1,
 195         /* L, C & R; MP3 & AAC only. */
 196         SOF_IPC4_CHANNEL_CONFIG_3_POINT_0,
 197         /* L, C, R & LFE; PCM only. */
 198         SOF_IPC4_CHANNEL_CONFIG_3_POINT_1,
 199         /* L, R, Ls & Rs; PCM only. */
 200         SOF_IPC4_CHANNEL_CONFIG_QUATRO,
 201         /* L, C, R & Cs; MP3 & AAC only. */
 202         SOF_IPC4_CHANNEL_CONFIG_4_POINT_0,
 203         /* L, C, R, Ls & Rs. */
 204         SOF_IPC4_CHANNEL_CONFIG_5_POINT_0,
 205         /* L, C, R, Ls, Rs & LFE. */
 206         SOF_IPC4_CHANNEL_CONFIG_5_POINT_1,
 207         /* one channel replicated in two. */
 208         SOF_IPC4_CHANNEL_CONFIG_DUAL_MONO,
 209         /* Stereo (L,R) in 4 slots, 1st stream: [ L, R, -, - ] */
 210         SOF_IPC4_CHANNEL_CONFIG_I2S_DUAL_STEREO_0,
 211         /* Stereo (L,R) in 4 slots, 2nd stream: [ -, -, L, R ] */
 212         SOF_IPC4_CHANNEL_CONFIG_I2S_DUAL_STEREO_1,
 213         /* L, C, R, Ls, Rs & LFE., LS, RS */
 214         SOF_IPC4_CHANNEL_CONFIG_7_POINT_1,
 215 };
 216
 217 enum sof_ipc4_interleaved_style {
 218         SOF_IPC4_CHANNELS_INTERLEAVED,
 219         SOF_IPC4_CHANNELS_NONINTERLEAVED,
 220 };
 221
 222 enum sof_ipc4_sample_type {
 223         SOF_IPC4_MSB_INTEGER, /* integer with Most Significant Byte first */
 224         SOF_IPC4_LSB_INTEGER, /* integer with Least Significant Byte first */
 225 };
 226
 227 struct sof_ipc4_audio_format {
 228         uint32_t sampling_frequency;
 229         uint32_t bit_depth;
 230         uint32_t ch_map;
 231         uint32_t ch_cfg; /* sof_ipc4_channel_config */
 232         uint32_t interleaving_style;
 233         uint32_t fmt_cfg; /* channels_count valid_bit_depth s_type */
 234 } __packed __aligned(4);
 235
 236 #define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_SHIFT  0
 237 #define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_MASK   GENMASK(7, 0)
 238 #define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(x)     \
 239         ((x) & SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_MASK)
 240 #define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_SHIFT     8
 241 #define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_MASK      GENMASK(15, 8)
 242 #define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(x)        \
 243         (((x) & SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_MASK) >> \
 244          SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_SHIFT)
 245 #define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_SHIFT     16
 246 #define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_MASK      GENMASK(23, 16)
 247 #define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE(x)        \
 248         (((x) & SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_MASK) >>  \
 249          SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_SHIFT)
 250
 251 /* Module message type specific field definitions */
 252
 253 enum sof_ipc4_module_type {
 254         SOF_IPC4_MOD_INIT_INSTANCE,
 255         SOF_IPC4_MOD_CONFIG_GET,
 256         SOF_IPC4_MOD_CONFIG_SET,
 257         SOF_IPC4_MOD_LARGE_CONFIG_GET,
 258         SOF_IPC4_MOD_LARGE_CONFIG_SET,
 259         SOF_IPC4_MOD_BIND,
 260         SOF_IPC4_MOD_UNBIND,
 261         SOF_IPC4_MOD_SET_DX,
 262         SOF_IPC4_MOD_SET_D0IX,
 263         SOF_IPC4_MOD_ENTER_MODULE_RESTORE,
 264         SOF_IPC4_MOD_EXIT_MODULE_RESTORE,
 265         SOF_IPC4_MOD_DELETE_INSTANCE,
 266
 267         SOF_IPC4_MOD_TYPE_LAST,
 268 };
 269
 270 struct sof_ipc4_base_module_cfg {
 271         uint32_t cpc; /* the max count of Cycles Per Chunk processing */
 272         uint32_t ibs; /* input Buffer Size (in bytes)  */
 273         uint32_t obs; /* output Buffer Size (in bytes) */
 274         uint32_t is_pages; /* number of physical pages used */
 275         struct sof_ipc4_audio_format audio_fmt;
 276 } __packed __aligned(4);
 277
 278 /* common module ipc msg */
 279 #define SOF_IPC4_MOD_INSTANCE_SHIFT             16
 280 #define SOF_IPC4_MOD_INSTANCE_MASK              GENMASK(23, 16)
 281 #define SOF_IPC4_MOD_INSTANCE(x)                ((x) << SOF_IPC4_MOD_INSTANCE_SHIFT)
 282
 283 #define SOF_IPC4_MOD_ID_SHIFT                   0
 284 #define SOF_IPC4_MOD_ID_MASK                    GENMASK(15, 0)
 285 #define SOF_IPC4_MOD_ID(x)                      ((x) << SOF_IPC4_MOD_ID_SHIFT)
 286
 287 /* init module ipc msg */
 288 #define SOF_IPC4_MOD_EXT_PARAM_SIZE_SHIFT       0
 289 #define SOF_IPC4_MOD_EXT_PARAM_SIZE_MASK        GENMASK(15, 0)
 290 #define SOF_IPC4_MOD_EXT_PARAM_SIZE(x)          ((x) << SOF_IPC4_MOD_EXT_PARAM_SIZE_SHIFT)
 291
 292 #define SOF_IPC4_MOD_EXT_PPL_ID_SHIFT           16
 293 #define SOF_IPC4_MOD_EXT_PPL_ID_MASK            GENMASK(23, 16)
 294 #define SOF_IPC4_MOD_EXT_PPL_ID(x)              ((x) << SOF_IPC4_MOD_EXT_PPL_ID_SHIFT)
 295
 296 #define SOF_IPC4_MOD_EXT_CORE_ID_SHIFT          24
 297 #define SOF_IPC4_MOD_EXT_CORE_ID_MASK           GENMASK(27, 24)
 298 #define SOF_IPC4_MOD_EXT_CORE_ID(x)             ((x) << SOF_IPC4_MOD_EXT_CORE_ID_SHIFT)
 299
 300 #define SOF_IPC4_MOD_EXT_DOMAIN_SHIFT           28
 301 #define SOF_IPC4_MOD_EXT_DOMAIN_MASK            BIT(28)
 302 #define SOF_IPC4_MOD_EXT_DOMAIN(x)              ((x) << SOF_IPC4_MOD_EXT_DOMAIN_SHIFT)
 303
 304 /*  bind/unbind module ipc msg */
 305 #define SOF_IPC4_MOD_EXT_DST_MOD_ID_SHIFT       0
 306 #define SOF_IPC4_MOD_EXT_DST_MOD_ID_MASK        GENMASK(15, 0)
 307 #define SOF_IPC4_MOD_EXT_DST_MOD_ID(x)          ((x) << SOF_IPC4_MOD_EXT_DST_MOD_ID_SHIFT)
 308
 309 #define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_SHIFT 16
 310 #define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_MASK  GENMASK(23, 16)
 311 #define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE(x)    ((x) << SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_SHIFT)
 312
 313 #define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_SHIFT 24
 314 #define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_MASK  GENMASK(26, 24)
 315 #define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID(x)    ((x) << SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_SHIFT)
 316
 317 #define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_SHIFT 27
 318 #define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_MASK  GENMASK(29, 27)
 319 #define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID(x)    ((x) << SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_SHIFT)
 320
 321 #define MOD_ENABLE_LOG  6
 322 #define MOD_SYSTEM_TIME 20
 323
 324 /* set module large config */
 325 #define SOF_IPC4_MOD_EXT_MSG_SIZE_SHIFT         0
 326 #define SOF_IPC4_MOD_EXT_MSG_SIZE_MASK          GENMASK(19, 0)
 327 #define SOF_IPC4_MOD_EXT_MSG_SIZE(x)            ((x) << SOF_IPC4_MOD_EXT_MSG_SIZE_SHIFT)
 328
 329 #define SOF_IPC4_MOD_EXT_MSG_PARAM_ID_SHIFT     20
 330 #define SOF_IPC4_MOD_EXT_MSG_PARAM_ID_MASK      GENMASK(27, 20)
 331 #define SOF_IPC4_MOD_EXT_MSG_PARAM_ID(x)        ((x) << SOF_IPC4_MOD_EXT_MSG_PARAM_ID_SHIFT)
 332
 333 #define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_SHIFT   28
 334 #define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_MASK    BIT(28)
 335 #define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK(x)      ((x) << SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_SHIFT)
 336
 337 #define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_SHIFT  29
 338 #define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_MASK   BIT(29)
 339 #define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK(x)     ((x) << SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_SHIFT)
 340
 341 /* Init instance messagees */
 342 #define SOF_IPC4_MOD_INIT_BASEFW_MOD_ID         0
 343 #define SOF_IPC4_MOD_INIT_BASEFW_INSTANCE_ID    0
 344
 345 enum sof_ipc4_base_fw_params {
 346         SOF_IPC4_FW_PARAM_ENABLE_LOGS = 6,
 347         SOF_IPC4_FW_PARAM_FW_CONFIG,
 348         SOF_IPC4_FW_PARAM_HW_CONFIG_GET,
 349         SOF_IPC4_FW_PARAM_MODULES_INFO_GET,
 350         SOF_IPC4_FW_PARAM_LIBRARIES_INFO_GET = 16,
 351         SOF_IPC4_FW_PARAM_SYSTEM_TIME = 20,
 352 };
 353
 354 enum sof_ipc4_fw_config_params {
 355         SOF_IPC4_FW_CFG_FW_VERSION,
 356         SOF_IPC4_FW_CFG_MEMORY_RECLAIMED,
 357         SOF_IPC4_FW_CFG_SLOW_CLOCK_FREQ_HZ,
 358         SOF_IPC4_FW_CFG_FAST_CLOCK_FREQ_HZ,
 359         SOF_IPC4_FW_CFG_DMA_BUFFER_CONFIG,
 360         SOF_IPC4_FW_CFG_ALH_SUPPORT_LEVEL,
 361         SOF_IPC4_FW_CFG_DL_MAILBOX_BYTES,
 362         SOF_IPC4_FW_CFG_UL_MAILBOX_BYTES,
 363         SOF_IPC4_FW_CFG_TRACE_LOG_BYTES,
 364         SOF_IPC4_FW_CFG_MAX_PPL_COUNT,
 365         SOF_IPC4_FW_CFG_MAX_ASTATE_COUNT,
 366         SOF_IPC4_FW_CFG_MAX_MODULE_PIN_COUNT,
 367         SOF_IPC4_FW_CFG_MODULES_COUNT,
 368         SOF_IPC4_FW_CFG_MAX_MOD_INST_COUNT,
 369         SOF_IPC4_FW_CFG_MAX_LL_TASKS_PER_PRI_COUNT,
 370         SOF_IPC4_FW_CFG_LL_PRI_COUNT,
 371         SOF_IPC4_FW_CFG_MAX_DP_TASKS_COUNT,
 372         SOF_IPC4_FW_CFG_MAX_LIBS_COUNT,
 373         SOF_IPC4_FW_CFG_SCHEDULER_CONFIG,
 374         SOF_IPC4_FW_CFG_XTAL_FREQ_HZ,
 375         SOF_IPC4_FW_CFG_CLOCKS_CONFIG,
 376         SOF_IPC4_FW_CFG_RESERVED,
 377         SOF_IPC4_FW_CFG_POWER_GATING_POLICY,
 378         SOF_IPC4_FW_CFG_ASSERT_MODE,
 379 };
 380
 381 struct sof_ipc4_fw_version {
 382         uint16_t major;
 383         uint16_t minor;
 384         uint16_t hotfix;
 385         uint16_t build;
 386 } __packed;
 387
 388 /* Reply messages */
 389
 390 /*
 391  * IPC4 primary header bit allocation for replies
 392  * bit 0-23:    status
 393  * bit 24-28:   type:   enum sof_ipc4_global_msg if target is SOF_IPC4_FW_GEN_MSG
 394  *                      enum sof_ipc4_module_type if target is SOF_IPC4_MODULE_MSG
 395  * bit 29:      response - sof_ipc4_msg_dir
 396  * bit 30:      target - enum sof_ipc4_msg_target
 397  * bit 31:      reserved, unused
 398  */
 399
 400 #define SOF_IPC4_REPLY_STATUS                   GENMASK(23, 0)
 401
 402 /* Notification messages */
 403
 404 /*
 405  * IPC4 primary header bit allocation for notifications
 406  * bit 0-15:    notification type specific
 407  * bit 16-23:   enum sof_ipc4_notification_type
 408  * bit 24-28:   SOF_IPC4_GLB_NOTIFICATION
 409  * bit 29:      response - sof_ipc4_msg_dir
 410  * bit 30:      target - enum sof_ipc4_msg_target
 411  * bit 31:      reserved, unused
 412  */
 413
 414 #define SOF_IPC4_MSG_IS_NOTIFICATION(x)         (SOF_IPC4_MSG_TYPE_GET(x) == \
 415                                                  SOF_IPC4_GLB_NOTIFICATION)
 416
 417 #define SOF_IPC4_NOTIFICATION_TYPE_SHIFT        16
 418 #define SOF_IPC4_NOTIFICATION_TYPE_MASK         GENMASK(23, 16)
 419 #define SOF_IPC4_NOTIFICATION_TYPE_GET(x)       (((x) & SOF_IPC4_NOTIFICATION_TYPE_MASK) >> \
 420                                                  SOF_IPC4_NOTIFICATION_TYPE_SHIFT)
 421
 422 /* Value of notification type field - must fit into 8 bits */
 423 enum sof_ipc4_notification_type {
 424         /* Phrase detected (notification from WoV module) */
 425         SOF_IPC4_NOTIFY_PHRASE_DETECTED = 4,
 426         /* Event from a resource (pipeline or module instance) */
 427         SOF_IPC4_NOTIFY_RESOURCE_EVENT,
 428         /* Debug log buffer status changed */
 429         SOF_IPC4_NOTIFY_LOG_BUFFER_STATUS,
 430         /* Timestamp captured at the link */
 431         SOF_IPC4_NOTIFY_TIMESTAMP_CAPTURED,
 432         /* FW complete initialization */
 433         SOF_IPC4_NOTIFY_FW_READY,
 434         /* Audio classifier result (ACA) */
 435         SOF_IPC4_NOTIFY_FW_AUD_CLASS_RESULT,
 436         /* Exception caught by DSP FW */
 437         SOF_IPC4_NOTIFY_EXCEPTION_CAUGHT,
 438         /* 11 is skipped by the existing cavs firmware */
 439         /* Custom module notification */
 440         SOF_IPC4_NOTIFY_MODULE_NOTIFICATION = 12,
 441         /* 13 is reserved - do not use */
 442         /* Probe notify data available */
 443         SOF_IPC4_NOTIFY_PROBE_DATA_AVAILABLE = 14,
 444         /* AM module notifications */
 445         SOF_IPC4_NOTIFY_ASYNC_MSG_SRVC_MESSAGE,
 446
 447         SOF_IPC4_NOTIFY_TYPE_LAST,
 448 };
 449
 450 struct sof_ipc4_notify_resource_data {
 451         uint32_t resource_type;
 452         uint32_t resource_id;
 453         uint32_t event_type;
 454         uint32_t reserved;
 455         uint32_t data[6];
 456 } __packed __aligned(4);
 457
 458 /** @}*/
 459
 460 #endif