1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2014 NVIDIA Corporation
6 #ifndef __SOC_TEGRA_MC_H__
7 #define __SOC_TEGRA_MC_H__
9 #include <linux/bits.h>
10 #include <linux/debugfs.h>
11 #include <linux/err.h>
12 #include <linux/interconnect-provider.h>
13 #include <linux/reset-controller.h>
14 #include <linux/types.h>
20 struct tegra_smmu_enable {
25 struct tegra_mc_timing {
31 /* latency allowance */
39 struct tegra_mc_client {
44 unsigned int fifo_size;
46 struct tegra_smmu_enable smmu;
47 struct tegra_mc_la la;
50 struct tegra_smmu_swgroup {
56 struct tegra_smmu_group_soc {
58 const unsigned int *swgroups;
59 unsigned int num_swgroups;
62 struct tegra_smmu_soc {
63 const struct tegra_mc_client *clients;
64 unsigned int num_clients;
66 const struct tegra_smmu_swgroup *swgroups;
67 unsigned int num_swgroups;
69 const struct tegra_smmu_group_soc *groups;
70 unsigned int num_groups;
72 bool supports_round_robin_arbitration;
73 bool supports_request_limit;
75 unsigned int num_tlb_lines;
76 unsigned int num_asids;
83 #ifdef CONFIG_TEGRA_IOMMU_SMMU
84 struct tegra_smmu *tegra_smmu_probe(struct device *dev,
85 const struct tegra_smmu_soc *soc,
87 void tegra_smmu_remove(struct tegra_smmu *smmu);
89 static inline struct tegra_smmu *
90 tegra_smmu_probe(struct device *dev, const struct tegra_smmu_soc *soc,
96 static inline void tegra_smmu_remove(struct tegra_smmu *smmu)
101 #ifdef CONFIG_TEGRA_IOMMU_GART
102 struct gart_device *tegra_gart_probe(struct device *dev, struct tegra_mc *mc);
103 int tegra_gart_suspend(struct gart_device *gart);
104 int tegra_gart_resume(struct gart_device *gart);
106 static inline struct gart_device *
107 tegra_gart_probe(struct device *dev, struct tegra_mc *mc)
109 return ERR_PTR(-ENODEV);
112 static inline int tegra_gart_suspend(struct gart_device *gart)
117 static inline int tegra_gart_resume(struct gart_device *gart)
123 struct tegra_mc_reset {
126 unsigned int control;
132 struct tegra_mc_reset_ops {
133 int (*hotreset_assert)(struct tegra_mc *mc,
134 const struct tegra_mc_reset *rst);
135 int (*hotreset_deassert)(struct tegra_mc *mc,
136 const struct tegra_mc_reset *rst);
137 int (*block_dma)(struct tegra_mc *mc,
138 const struct tegra_mc_reset *rst);
139 bool (*dma_idling)(struct tegra_mc *mc,
140 const struct tegra_mc_reset *rst);
141 int (*unblock_dma)(struct tegra_mc *mc,
142 const struct tegra_mc_reset *rst);
143 int (*reset_status)(struct tegra_mc *mc,
144 const struct tegra_mc_reset *rst);
147 #define TEGRA_MC_ICC_TAG_DEFAULT 0
148 #define TEGRA_MC_ICC_TAG_ISO BIT(0)
150 struct tegra_mc_icc_ops {
151 int (*set)(struct icc_node *src, struct icc_node *dst);
152 int (*aggregate)(struct icc_node *node, u32 tag, u32 avg_bw,
153 u32 peak_bw, u32 *agg_avg, u32 *agg_peak);
154 struct icc_node_data *(*xlate_extended)(struct of_phandle_args *spec,
158 struct tegra_mc_soc {
159 const struct tegra_mc_client *clients;
160 unsigned int num_clients;
162 const unsigned long *emem_regs;
163 unsigned int num_emem_regs;
165 unsigned int num_address_bits;
166 unsigned int atom_size;
170 const struct tegra_smmu_soc *smmu;
174 const struct tegra_mc_reset_ops *reset_ops;
175 const struct tegra_mc_reset *resets;
176 unsigned int num_resets;
178 const struct tegra_mc_icc_ops *icc_ops;
180 int (*init)(struct tegra_mc *mc);
185 struct tegra_smmu *smmu;
186 struct gart_device *gart;
191 const struct tegra_mc_soc *soc;
194 struct tegra_mc_timing *timings;
195 unsigned int num_timings;
197 struct reset_controller_dev reset;
199 struct icc_provider provider;
208 int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate);
209 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc);
211 #ifdef CONFIG_TEGRA_MC
212 struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev);
214 static inline struct tegra_mc *
215 devm_tegra_memory_controller_get(struct device *dev)
217 return ERR_PTR(-ENODEV);
221 #endif /* __SOC_TEGRA_MC_H__ */