1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2012-2023, NVIDIA CORPORATION. All rights reserved.
6 #ifndef __SOC_TEGRA_FUSE_H__
7 #define __SOC_TEGRA_FUSE_H__
9 #include <linux/types.h>
23 #define TEGRA_FUSE_SKU_CALIB_0 0xf0
24 #define TEGRA30_FUSE_SATA_CALIB 0x124
25 #define TEGRA_FUSE_USB_CALIB_EXT_0 0x250
30 TEGRA_REVISION_UNKNOWN = 0,
40 TEGRA_PLATFORM_SILICON = 0,
42 TEGRA_PLATFORM_SYSTEM_FPGA,
43 TEGRA_PLATFORM_UNIT_FPGA,
44 TEGRA_PLATFORM_ASIM_QT,
45 TEGRA_PLATFORM_ASIM_LINSIM,
46 TEGRA_PLATFORM_DSIM_ASIM_LINSIM,
47 TEGRA_PLATFORM_VERIFICATION_SIMULATION,
53 struct tegra_sku_info {
65 enum tegra_revision revision;
66 enum tegra_platform platform;
69 #ifdef CONFIG_ARCH_TEGRA
70 extern struct tegra_sku_info tegra_sku_info;
71 u32 tegra_read_straps(void);
72 u32 tegra_read_ram_code(void);
73 int tegra_fuse_readl(unsigned long offset, u32 *value);
74 u32 tegra_read_chipid(void);
75 u8 tegra_get_chip_id(void);
76 u8 tegra_get_platform(void);
77 bool tegra_is_silicon(void);
78 int tegra194_miscreg_mask_serror(void);
80 static struct tegra_sku_info tegra_sku_info __maybe_unused;
82 static inline u32 tegra_read_straps(void)
87 static inline u32 tegra_read_ram_code(void)
92 static inline int tegra_fuse_readl(unsigned long offset, u32 *value)
97 static inline u32 tegra_read_chipid(void)
102 static inline u8 tegra_get_chip_id(void)
107 static inline u8 tegra_get_platform(void)
112 static inline bool tegra_is_silicon(void)
117 static inline int tegra194_miscreg_mask_serror(void)
123 struct device *tegra_soc_device_register(void);
125 #endif /* __ASSEMBLY__ */
127 #endif /* __SOC_TEGRA_FUSE_H__ */