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33 #ifndef SOC_NPS_COMMON_H
34 #define SOC_NPS_COMMON_H
40 #define NPS_HOST_REG_BASE 0xF6000000
42 #define NPS_MSU_BLKID 0x018
44 #define CTOP_INST_RSPI_GIC_0_R12 0x3C56117E
45 #define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60
46 #define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 0x00010422
49 #define AUX_IENABLE 0x40c
52 #define CTOP_AUX_IACK (0xFFFFF800 + 0x088)
56 /* In order to increase compilation test coverage */
58 static inline void nps_ack_gic(void)
60 __asm__ __volatile__ (
63 : "i"(CTOP_INST_RSPI_GIC_0_R12)
67 static inline void nps_ack_gic(void) { }
68 #define write_aux_reg(r, v)
69 #define read_aux_reg(r) 0
76 #ifdef CONFIG_EZNPS_MTM_EXT
77 u32 __reserved:20, cluster:4, core:4, thread:4;
79 u32 __reserved:24, cluster:4, core:4;
87 * Convert logical to physical CPU IDs
89 * The conversion swap bits 1 and 2 of cluster id (out of 4 bits)
90 * Now quad of logical clusters id's are adjacent physically,
91 * and not like the id's physically came with each cluster.
92 * Below table is 4x4 mesh of core clusters as it layout on chip.
93 * Cluster ids are in format: logical (physical)
95 * ----------------- ------------------
96 * 3 | 5 (3) 7 (7) | | 13 (11) 15 (15)|
98 * 2 | 4 (2) 6 (6) | | 12 (10) 14 (14)|
99 * ----------------- ------------------
100 * 1 | 1 (1) 3 (5) | | 9 (9) 11 (13)|
102 * 0 | 0 (0) 2 (4) | | 8 (8) 10 (12)|
103 * ----------------- ------------------
106 static inline int nps_cluster_logic_to_phys(int cluster)
109 __asm__ __volatile__(
115 : "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST),
116 "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM)
123 #define NPS_CPU_TO_CLUSTER_NUM(cpu) \
124 ({ struct global_id gid; gid.value = cpu; \
125 nps_cluster_logic_to_phys(gid.cluster); })
127 struct nps_host_reg_address {
130 u32 base:8, cl_x:4, cl_y:4,
131 blkid:6, reg:8, __reserved:2;
137 struct nps_host_reg_address_non_cl {
140 u32 base:7, blkid:11, reg:12, __reserved:2;
146 static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg)
148 struct nps_host_reg_address_non_cl reg_address;
150 reg_address.value = NPS_HOST_REG_BASE;
151 reg_address.blkid = blkid;
152 reg_address.reg = reg;
154 return (void *)reg_address.value;
157 static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg)
159 struct nps_host_reg_address reg_address;
160 u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu);
162 reg_address.value = NPS_HOST_REG_BASE;
163 reg_address.cl_x = (cl >> 2) & 0x3;
164 reg_address.cl_y = cl & 0x3;
165 reg_address.blkid = blkid;
166 reg_address.reg = reg;
168 return (void *)reg_address.value;
170 #endif /* __ASSEMBLY__ */
172 #endif /* SOC_NPS_COMMON_H */