2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #ifndef __CARL9170_SHARED_PHY_H
18 #define __CARL9170_SHARED_PHY_H
20 #define AR9170_PHY_REG_BASE (0x1bc000 + 0x9800)
21 #define AR9170_PHY_REG(_n) (AR9170_PHY_REG_BASE + ((_n)<<2))
23 #define AR9170_PHY_REG_TEST (AR9170_PHY_REG_BASE + 0x0000)
24 #define AR9170_PHY_TEST_AGC_CLR 0x10000000
25 #define AR9170_PHY_TEST_RFSILENT_BB 0x00002000
27 #define AR9170_PHY_REG_TURBO (AR9170_PHY_REG_BASE + 0x0004)
28 #define AR9170_PHY_TURBO_FC_TURBO_MODE 0x00000001
29 #define AR9170_PHY_TURBO_FC_TURBO_SHORT 0x00000002
30 #define AR9170_PHY_TURBO_FC_DYN2040_EN 0x00000004
31 #define AR9170_PHY_TURBO_FC_DYN2040_PRI_ONLY 0x00000008
32 #define AR9170_PHY_TURBO_FC_DYN2040_PRI_CH 0x00000010
33 /* For 25 MHz channel spacing -- not used but supported by hw */
34 #define AR9170_PHY_TURBO_FC_DYN2040_EXT_CH 0x00000020
35 #define AR9170_PHY_TURBO_FC_HT_EN 0x00000040
36 #define AR9170_PHY_TURBO_FC_SHORT_GI_40 0x00000080
37 #define AR9170_PHY_TURBO_FC_WALSH 0x00000100
38 #define AR9170_PHY_TURBO_FC_SINGLE_HT_LTF1 0x00000200
39 #define AR9170_PHY_TURBO_FC_ENABLE_DAC_FIFO 0x00000800
41 #define AR9170_PHY_REG_TEST2 (AR9170_PHY_REG_BASE + 0x0008)
43 #define AR9170_PHY_REG_TIMING2 (AR9170_PHY_REG_BASE + 0x0010)
44 #define AR9170_PHY_TIMING2_USE_FORCE 0x00001000
45 #define AR9170_PHY_TIMING2_FORCE 0x00000fff
46 #define AR9170_PHY_TIMING2_FORCE_S 0
48 #define AR9170_PHY_REG_TIMING3 (AR9170_PHY_REG_BASE + 0x0014)
49 #define AR9170_PHY_TIMING3_DSC_EXP 0x0001e000
50 #define AR9170_PHY_TIMING3_DSC_EXP_S 13
51 #define AR9170_PHY_TIMING3_DSC_MAN 0xfffe0000
52 #define AR9170_PHY_TIMING3_DSC_MAN_S 17
54 #define AR9170_PHY_REG_CHIP_ID (AR9170_PHY_REG_BASE + 0x0018)
55 #define AR9170_PHY_CHIP_ID_REV_0 0x80
56 #define AR9170_PHY_CHIP_ID_REV_1 0x81
57 #define AR9170_PHY_CHIP_ID_9160_REV_0 0xb0
59 #define AR9170_PHY_REG_ACTIVE (AR9170_PHY_REG_BASE + 0x001c)
60 #define AR9170_PHY_ACTIVE_EN 0x00000001
61 #define AR9170_PHY_ACTIVE_DIS 0x00000000
63 #define AR9170_PHY_REG_RF_CTL2 (AR9170_PHY_REG_BASE + 0x0024)
64 #define AR9170_PHY_RF_CTL2_TX_END_DATA_START 0x000000ff
65 #define AR9170_PHY_RF_CTL2_TX_END_DATA_START_S 0
66 #define AR9170_PHY_RF_CTL2_TX_END_PA_ON 0x0000ff00
67 #define AR9170_PHY_RF_CTL2_TX_END_PA_ON_S 8
69 #define AR9170_PHY_REG_RF_CTL3 (AR9170_PHY_REG_BASE + 0x0028)
70 #define AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON 0x00ff0000
71 #define AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON_S 16
73 #define AR9170_PHY_REG_ADC_CTL (AR9170_PHY_REG_BASE + 0x002c)
74 #define AR9170_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003
75 #define AR9170_PHY_ADC_CTL_OFF_INBUFGAIN_S 0
76 #define AR9170_PHY_ADC_CTL_OFF_PWDDAC 0x00002000
77 #define AR9170_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000
78 #define AR9170_PHY_ADC_CTL_OFF_PWDADC 0x00008000
79 #define AR9170_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000
80 #define AR9170_PHY_ADC_CTL_ON_INBUFGAIN_S 16
82 #define AR9170_PHY_REG_ADC_SERIAL_CTL (AR9170_PHY_REG_BASE + 0x0030)
83 #define AR9170_PHY_ADC_SCTL_SEL_INTERNAL_ADDAC 0x00000000
84 #define AR9170_PHY_ADC_SCTL_SEL_EXTERNAL_RADIO 0x00000001
86 #define AR9170_PHY_REG_RF_CTL4 (AR9170_PHY_REG_BASE + 0x0034)
87 #define AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF 0xff000000
88 #define AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
89 #define AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00ff0000
90 #define AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
91 #define AR9170_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000ff00
92 #define AR9170_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
93 #define AR9170_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000ff
94 #define AR9170_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
96 #define AR9170_PHY_REG_TSTDAC_CONST (AR9170_PHY_REG_BASE + 0x003c)
98 #define AR9170_PHY_REG_SETTLING (AR9170_PHY_REG_BASE + 0x0044)
99 #define AR9170_PHY_SETTLING_SWITCH 0x00003f80
100 #define AR9170_PHY_SETTLING_SWITCH_S 7
102 #define AR9170_PHY_REG_RXGAIN (AR9170_PHY_REG_BASE + 0x0048)
103 #define AR9170_PHY_REG_RXGAIN_CHAIN_2 (AR9170_PHY_REG_BASE + 0x2048)
104 #define AR9170_PHY_RXGAIN_TXRX_ATTEN 0x0003f000
105 #define AR9170_PHY_RXGAIN_TXRX_ATTEN_S 12
106 #define AR9170_PHY_RXGAIN_TXRX_RF_MAX 0x007c0000
107 #define AR9170_PHY_RXGAIN_TXRX_RF_MAX_S 18
109 #define AR9170_PHY_REG_DESIRED_SZ (AR9170_PHY_REG_BASE + 0x0050)
110 #define AR9170_PHY_DESIRED_SZ_ADC 0x000000ff
111 #define AR9170_PHY_DESIRED_SZ_ADC_S 0
112 #define AR9170_PHY_DESIRED_SZ_PGA 0x0000ff00
113 #define AR9170_PHY_DESIRED_SZ_PGA_S 8
114 #define AR9170_PHY_DESIRED_SZ_TOT_DES 0x0ff00000
115 #define AR9170_PHY_DESIRED_SZ_TOT_DES_S 20
117 #define AR9170_PHY_REG_FIND_SIG (AR9170_PHY_REG_BASE + 0x0058)
118 #define AR9170_PHY_FIND_SIG_FIRSTEP 0x0003f000
119 #define AR9170_PHY_FIND_SIG_FIRSTEP_S 12
120 #define AR9170_PHY_FIND_SIG_FIRPWR 0x03fc0000
121 #define AR9170_PHY_FIND_SIG_FIRPWR_S 18
123 #define AR9170_PHY_REG_AGC_CTL1 (AR9170_PHY_REG_BASE + 0x005c)
124 #define AR9170_PHY_AGC_CTL1_COARSE_LOW 0x00007f80
125 #define AR9170_PHY_AGC_CTL1_COARSE_LOW_S 7
126 #define AR9170_PHY_AGC_CTL1_COARSE_HIGH 0x003f8000
127 #define AR9170_PHY_AGC_CTL1_COARSE_HIGH_S 15
129 #define AR9170_PHY_REG_AGC_CONTROL (AR9170_PHY_REG_BASE + 0x0060)
130 #define AR9170_PHY_AGC_CONTROL_CAL 0x00000001
131 #define AR9170_PHY_AGC_CONTROL_NF 0x00000002
132 #define AR9170_PHY_AGC_CONTROL_ENABLE_NF 0x00008000
133 #define AR9170_PHY_AGC_CONTROL_FLTR_CAL 0x00010000
134 #define AR9170_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000
136 #define AR9170_PHY_REG_CCA (AR9170_PHY_REG_BASE + 0x0064)
137 #define AR9170_PHY_CCA_MINCCA_PWR 0x0ff80000
138 #define AR9170_PHY_CCA_MINCCA_PWR_S 19
139 #define AR9170_PHY_CCA_THRESH62 0x0007f000
140 #define AR9170_PHY_CCA_THRESH62_S 12
142 #define AR9170_PHY_REG_SFCORR (AR9170_PHY_REG_BASE + 0x0068)
143 #define AR9170_PHY_SFCORR_M2COUNT_THR 0x0000001f
144 #define AR9170_PHY_SFCORR_M2COUNT_THR_S 0
145 #define AR9170_PHY_SFCORR_M1_THRESH 0x00fe0000
146 #define AR9170_PHY_SFCORR_M1_THRESH_S 17
147 #define AR9170_PHY_SFCORR_M2_THRESH 0x7f000000
148 #define AR9170_PHY_SFCORR_M2_THRESH_S 24
150 #define AR9170_PHY_REG_SFCORR_LOW (AR9170_PHY_REG_BASE + 0x006c)
151 #define AR9170_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
152 #define AR9170_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003f00
153 #define AR9170_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
154 #define AR9170_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001fc000
155 #define AR9170_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
156 #define AR9170_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0fe00000
157 #define AR9170_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
159 #define AR9170_PHY_REG_SLEEP_CTR_CONTROL (AR9170_PHY_REG_BASE + 0x0070)
160 #define AR9170_PHY_REG_SLEEP_CTR_LIMIT (AR9170_PHY_REG_BASE + 0x0074)
161 /* ??? same address ??? */
162 #define AR9170_PHY_REG_SYNTH_CONTROL (AR9170_PHY_REG_BASE + 0x0074)
163 #define AR9170_PHY_REG_SLEEP_SCAL (AR9170_PHY_REG_BASE + 0x0078)
165 #define AR9170_PHY_REG_PLL_CTL (AR9170_PHY_REG_BASE + 0x007c)
166 #define AR9170_PHY_PLL_CTL_40 0xaa
167 #define AR9170_PHY_PLL_CTL_40_5413 0x04
168 #define AR9170_PHY_PLL_CTL_44 0xab
169 #define AR9170_PHY_PLL_CTL_44_2133 0xeb
170 #define AR9170_PHY_PLL_CTL_40_2133 0xea
172 #define AR9170_PHY_REG_BIN_MASK_1 (AR9170_PHY_REG_BASE + 0x0100)
173 #define AR9170_PHY_REG_BIN_MASK_2 (AR9170_PHY_REG_BASE + 0x0104)
174 #define AR9170_PHY_REG_BIN_MASK_3 (AR9170_PHY_REG_BASE + 0x0108)
175 #define AR9170_PHY_REG_MASK_CTL (AR9170_PHY_REG_BASE + 0x010c)
177 /* analogue power on time (100ns) */
178 #define AR9170_PHY_REG_RX_DELAY (AR9170_PHY_REG_BASE + 0x0114)
179 #define AR9170_PHY_REG_SEARCH_START_DELAY (AR9170_PHY_REG_BASE + 0x0118)
180 #define AR9170_PHY_RX_DELAY_DELAY 0x00003fff
182 #define AR9170_PHY_REG_TIMING_CTRL4(_i) (AR9170_PHY_REG_BASE + (0x0120 + ((_i) << 12)))
183 #define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01f
184 #define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0
185 #define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7e0
186 #define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5
187 #define AR9170_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800
188 #define AR9170_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xf000
189 #define AR9170_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12
190 #define AR9170_PHY_TIMING_CTRL4_DO_IQCAL 0x10000
191 #define AR9170_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000
192 #define AR9170_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000
193 #define AR9170_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000
194 #define AR9170_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000
196 #define AR9170_PHY_REG_TIMING5 (AR9170_PHY_REG_BASE + 0x0124)
197 #define AR9170_PHY_TIMING5_CYCPWR_THR1 0x000000fe
198 #define AR9170_PHY_TIMING5_CYCPWR_THR1_S 1
200 #define AR9170_PHY_REG_POWER_TX_RATE1 (AR9170_PHY_REG_BASE + 0x0134)
201 #define AR9170_PHY_REG_POWER_TX_RATE2 (AR9170_PHY_REG_BASE + 0x0138)
202 #define AR9170_PHY_REG_POWER_TX_RATE_MAX (AR9170_PHY_REG_BASE + 0x013c)
203 #define AR9170_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
205 #define AR9170_PHY_REG_FRAME_CTL (AR9170_PHY_REG_BASE + 0x0144)
206 #define AR9170_PHY_FRAME_CTL_TX_CLIP 0x00000038
207 #define AR9170_PHY_FRAME_CTL_TX_CLIP_S 3
209 #define AR9170_PHY_REG_TXPWRADJ (AR9170_PHY_REG_BASE + 0x014c)
210 #define AR9170_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000fc0
211 #define AR9170_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6
212 #define AR9170_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00fc0000
213 #define AR9170_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18
215 /* ??? same address ??? */
216 #define AR9170_PHY_REG_SPUR_REG (AR9170_PHY_REG_BASE + 0x014c)
217 #define AR9170_PHY_SPUR_REG_MASK_RATE_CNTL (0xff << 18)
218 #define AR9170_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
219 #define AR9170_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000
220 #define AR9170_PHY_SPUR_REG_MASK_RATE_SELECT (0xff << 9)
221 #define AR9170_PHY_SPUR_REG_MASK_RATE_SELECT_S 9
222 #define AR9170_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100
223 #define AR9170_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7f
224 #define AR9170_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
226 #define AR9170_PHY_REG_RADAR_EXT (AR9170_PHY_REG_BASE + 0x0140)
227 #define AR9170_PHY_RADAR_EXT_ENA 0x00004000
229 #define AR9170_PHY_REG_RADAR_0 (AR9170_PHY_REG_BASE + 0x0154)
230 #define AR9170_PHY_RADAR_0_ENA 0x00000001
231 #define AR9170_PHY_RADAR_0_FFT_ENA 0x80000000
232 /* inband pulse threshold */
233 #define AR9170_PHY_RADAR_0_INBAND 0x0000003e
234 #define AR9170_PHY_RADAR_0_INBAND_S 1
235 /* pulse RSSI threshold */
236 #define AR9170_PHY_RADAR_0_PRSSI 0x00000fc0
237 #define AR9170_PHY_RADAR_0_PRSSI_S 6
238 /* pulse height threshold */
239 #define AR9170_PHY_RADAR_0_HEIGHT 0x0003f000
240 #define AR9170_PHY_RADAR_0_HEIGHT_S 12
241 /* radar RSSI threshold */
242 #define AR9170_PHY_RADAR_0_RRSSI 0x00fc0000
243 #define AR9170_PHY_RADAR_0_RRSSI_S 18
244 /* radar firepower threshold */
245 #define AR9170_PHY_RADAR_0_FIRPWR 0x7f000000
246 #define AR9170_PHY_RADAR_0_FIRPWR_S 24
248 #define AR9170_PHY_REG_RADAR_1 (AR9170_PHY_REG_BASE + 0x0158)
249 #define AR9170_PHY_RADAR_1_RELPWR_ENA 0x00800000
250 #define AR9170_PHY_RADAR_1_USE_FIR128 0x00400000
251 #define AR9170_PHY_RADAR_1_RELPWR_THRESH 0x003f0000
252 #define AR9170_PHY_RADAR_1_RELPWR_THRESH_S 16
253 #define AR9170_PHY_RADAR_1_BLOCK_CHECK 0x00008000
254 #define AR9170_PHY_RADAR_1_MAX_RRSSI 0x00004000
255 #define AR9170_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
256 #define AR9170_PHY_RADAR_1_RELSTEP_THRESH 0x00001f00
257 #define AR9170_PHY_RADAR_1_RELSTEP_THRESH_S 8
258 #define AR9170_PHY_RADAR_1_MAXLEN 0x000000ff
259 #define AR9170_PHY_RADAR_1_MAXLEN_S 0
261 #define AR9170_PHY_REG_SWITCH_CHAIN_0 (AR9170_PHY_REG_BASE + 0x0160)
262 #define AR9170_PHY_REG_SWITCH_CHAIN_2 (AR9170_PHY_REG_BASE + 0x2160)
264 #define AR9170_PHY_REG_SWITCH_COM (AR9170_PHY_REG_BASE + 0x0164)
266 #define AR9170_PHY_REG_CCA_THRESHOLD (AR9170_PHY_REG_BASE + 0x0168)
268 #define AR9170_PHY_REG_SIGMA_DELTA (AR9170_PHY_REG_BASE + 0x016c)
269 #define AR9170_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
270 #define AR9170_PHY_SIGMA_DELTA_ADC_SEL_S 0
271 #define AR9170_PHY_SIGMA_DELTA_FILT2 0x000000f8
272 #define AR9170_PHY_SIGMA_DELTA_FILT2_S 3
273 #define AR9170_PHY_SIGMA_DELTA_FILT1 0x00001f00
274 #define AR9170_PHY_SIGMA_DELTA_FILT1_S 8
275 #define AR9170_PHY_SIGMA_DELTA_ADC_CLIP 0x01ffe000
276 #define AR9170_PHY_SIGMA_DELTA_ADC_CLIP_S 13
278 #define AR9170_PHY_REG_RESTART (AR9170_PHY_REG_BASE + 0x0170)
279 #define AR9170_PHY_RESTART_DIV_GC 0x001c0000
280 #define AR9170_PHY_RESTART_DIV_GC_S 18
282 #define AR9170_PHY_REG_RFBUS_REQ (AR9170_PHY_REG_BASE + 0x017c)
283 #define AR9170_PHY_RFBUS_REQ_EN 0x00000001
285 #define AR9170_PHY_REG_TIMING7 (AR9170_PHY_REG_BASE + 0x0180)
286 #define AR9170_PHY_REG_TIMING8 (AR9170_PHY_REG_BASE + 0x0184)
287 #define AR9170_PHY_TIMING8_PILOT_MASK_2 0x000fffff
288 #define AR9170_PHY_TIMING8_PILOT_MASK_2_S 0
290 #define AR9170_PHY_REG_BIN_MASK2_1 (AR9170_PHY_REG_BASE + 0x0188)
291 #define AR9170_PHY_REG_BIN_MASK2_2 (AR9170_PHY_REG_BASE + 0x018c)
292 #define AR9170_PHY_REG_BIN_MASK2_3 (AR9170_PHY_REG_BASE + 0x0190)
293 #define AR9170_PHY_REG_BIN_MASK2_4 (AR9170_PHY_REG_BASE + 0x0194)
294 #define AR9170_PHY_BIN_MASK2_4_MASK_4 0x00003fff
295 #define AR9170_PHY_BIN_MASK2_4_MASK_4_S 0
297 #define AR9170_PHY_REG_TIMING9 (AR9170_PHY_REG_BASE + 0x0198)
298 #define AR9170_PHY_REG_TIMING10 (AR9170_PHY_REG_BASE + 0x019c)
299 #define AR9170_PHY_TIMING10_PILOT_MASK_2 0x000fffff
300 #define AR9170_PHY_TIMING10_PILOT_MASK_2_S 0
302 #define AR9170_PHY_REG_TIMING11 (AR9170_PHY_REG_BASE + 0x01a0)
303 #define AR9170_PHY_TIMING11_SPUR_DELTA_PHASE 0x000fffff
304 #define AR9170_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
305 #define AR9170_PHY_TIMING11_SPUR_FREQ_SD 0x3ff00000
306 #define AR9170_PHY_TIMING11_SPUR_FREQ_SD_S 20
307 #define AR9170_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000
308 #define AR9170_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
310 #define AR9170_PHY_REG_RX_CHAINMASK (AR9170_PHY_REG_BASE + 0x01a4)
311 #define AR9170_PHY_REG_NEW_ADC_DC_GAIN_CORR(_i) (AR9170_PHY_REG_BASE + 0x01b4 + ((_i) << 12))
312 #define AR9170_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
313 #define AR9170_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
315 #define AR9170_PHY_REG_MULTICHAIN_GAIN_CTL (AR9170_PHY_REG_BASE + 0x01ac)
316 #define AR9170_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000
317 #define AR9170_PHY_9285_ANT_DIV_CTL 0x01000000
318 #define AR9170_PHY_9285_ANT_DIV_CTL_S 24
319 #define AR9170_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000
320 #define AR9170_PHY_9285_ANT_DIV_ALT_LNACONF_S 25
321 #define AR9170_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000
322 #define AR9170_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27
323 #define AR9170_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000
324 #define AR9170_PHY_9285_ANT_DIV_ALT_GAINTB_S 29
325 #define AR9170_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000
326 #define AR9170_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30
327 #define AR9170_PHY_9285_ANT_DIV_LNA1 2
328 #define AR9170_PHY_9285_ANT_DIV_LNA2 1
329 #define AR9170_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3
330 #define AR9170_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0
331 #define AR9170_PHY_9285_ANT_DIV_GAINTB_0 0
332 #define AR9170_PHY_9285_ANT_DIV_GAINTB_1 1
334 #define AR9170_PHY_REG_EXT_CCA0 (AR9170_PHY_REG_BASE + 0x01b8)
335 #define AR9170_PHY_REG_EXT_CCA0_THRESH62 0x000000ff
336 #define AR9170_PHY_REG_EXT_CCA0_THRESH62_S 0
338 #define AR9170_PHY_REG_EXT_CCA (AR9170_PHY_REG_BASE + 0x01bc)
339 #define AR9170_PHY_EXT_CCA_CYCPWR_THR1 0x0000fe00
340 #define AR9170_PHY_EXT_CCA_CYCPWR_THR1_S 9
341 #define AR9170_PHY_EXT_CCA_THRESH62 0x007f0000
342 #define AR9170_PHY_EXT_CCA_THRESH62_S 16
343 #define AR9170_PHY_EXT_MINCCA_PWR 0xff800000
344 #define AR9170_PHY_EXT_MINCCA_PWR_S 23
346 #define AR9170_PHY_REG_SFCORR_EXT (AR9170_PHY_REG_BASE + 0x01c0)
347 #define AR9170_PHY_SFCORR_EXT_M1_THRESH 0x0000007f
348 #define AR9170_PHY_SFCORR_EXT_M1_THRESH_S 0
349 #define AR9170_PHY_SFCORR_EXT_M2_THRESH 0x00003f80
350 #define AR9170_PHY_SFCORR_EXT_M2_THRESH_S 7
351 #define AR9170_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001fc000
352 #define AR9170_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
353 #define AR9170_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0fe00000
354 #define AR9170_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
355 #define AR9170_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
357 #define AR9170_PHY_REG_HALFGI (AR9170_PHY_REG_BASE + 0x01d0)
358 #define AR9170_PHY_HALFGI_DSC_MAN 0x0007fff0
359 #define AR9170_PHY_HALFGI_DSC_MAN_S 4
360 #define AR9170_PHY_HALFGI_DSC_EXP 0x0000000f
361 #define AR9170_PHY_HALFGI_DSC_EXP_S 0
363 #define AR9170_PHY_REG_CHANNEL_MASK_01_30 (AR9170_PHY_REG_BASE + 0x01d4)
364 #define AR9170_PHY_REG_CHANNEL_MASK_31_60 (AR9170_PHY_REG_BASE + 0x01d8)
366 #define AR9170_PHY_REG_CHAN_INFO_MEMORY (AR9170_PHY_REG_BASE + 0x01dc)
367 #define AR9170_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
369 #define AR9170_PHY_REG_HEAVY_CLIP_ENABLE (AR9170_PHY_REG_BASE + 0x01e0)
370 #define AR9170_PHY_REG_HEAVY_CLIP_FACTOR_RIFS (AR9170_PHY_REG_BASE + 0x01ec)
371 #define AR9170_PHY_RIFS_INIT_DELAY 0x03ff0000
373 #define AR9170_PHY_REG_CALMODE (AR9170_PHY_REG_BASE + 0x01f0)
374 #define AR9170_PHY_CALMODE_IQ 0x00000000
375 #define AR9170_PHY_CALMODE_ADC_GAIN 0x00000001
376 #define AR9170_PHY_CALMODE_ADC_DC_PER 0x00000002
377 #define AR9170_PHY_CALMODE_ADC_DC_INIT 0x00000003
379 /* ??? same register ??? */
380 #define AR9170_PHY_REG_M_SLEEP (AR9170_PHY_REG_BASE + 0x01f0)
382 #define AR9170_PHY_REG_REFCLKDLY (AR9170_PHY_REG_BASE + 0x01f4)
383 #define AR9170_PHY_REG_REFCLKPD (AR9170_PHY_REG_BASE + 0x01f8)
386 #define AR9170_PHY_REG_CAL_MEAS_0(_i) (AR9170_PHY_REG_BASE + 0x0410 + ((_i) << 12))
387 #define AR9170_PHY_REG_CAL_MEAS_1(_i) (AR9170_PHY_REG_BASE + 0x0414 + ((_i) << 12))
388 #define AR9170_PHY_REG_CAL_MEAS_2(_i) (AR9170_PHY_REG_BASE + 0x0418 + ((_i) << 12))
389 #define AR9170_PHY_REG_CAL_MEAS_3(_i) (AR9170_PHY_REG_BASE + 0x041c + ((_i) << 12))
391 #define AR9170_PHY_REG_CURRENT_RSSI (AR9170_PHY_REG_BASE + 0x041c)
393 #define AR9170_PHY_REG_RFBUS_GRANT (AR9170_PHY_REG_BASE + 0x0420)
394 #define AR9170_PHY_RFBUS_GRANT_EN 0x00000001
396 #define AR9170_PHY_REG_CHAN_INFO_GAIN_DIFF (AR9170_PHY_REG_BASE + 0x04f4)
397 #define AR9170_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
399 #define AR9170_PHY_REG_CHAN_INFO_GAIN (AR9170_PHY_REG_BASE + 0x04fc)
401 #define AR9170_PHY_REG_MODE (AR9170_PHY_REG_BASE + 0x0a00)
402 #define AR9170_PHY_MODE_ASYNCFIFO 0x80
403 #define AR9170_PHY_MODE_AR2133 0x08
404 #define AR9170_PHY_MODE_AR5111 0x00
405 #define AR9170_PHY_MODE_AR5112 0x08
406 #define AR9170_PHY_MODE_DYNAMIC 0x04
407 #define AR9170_PHY_MODE_RF2GHZ 0x02
408 #define AR9170_PHY_MODE_RF5GHZ 0x00
409 #define AR9170_PHY_MODE_CCK 0x01
410 #define AR9170_PHY_MODE_OFDM 0x00
411 #define AR9170_PHY_MODE_DYN_CCK_DISABLE 0x100
413 #define AR9170_PHY_REG_CCK_TX_CTRL (AR9170_PHY_REG_BASE + 0x0a04)
414 #define AR9170_PHY_CCK_TX_CTRL_JAPAN 0x00000010
415 #define AR9170_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000c
416 #define AR9170_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2
418 #define AR9170_PHY_REG_CCK_DETECT (AR9170_PHY_REG_BASE + 0x0a08)
419 #define AR9170_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003f
420 #define AR9170_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
421 /* [12:6] settling time for antenna switch */
422 #define AR9170_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001fc0
423 #define AR9170_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
424 #define AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
425 #define AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13
427 #define AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2 (AR9170_PHY_REG_BASE + 0x2a0c)
428 #define AR9170_PHY_REG_GAIN_2GHZ (AR9170_PHY_REG_BASE + 0x0a0c)
429 #define AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00fc0000
430 #define AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
431 #define AR9170_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003c00
432 #define AR9170_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
433 #define AR9170_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001f
434 #define AR9170_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
435 #define AR9170_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003e0000
436 #define AR9170_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
437 #define AR9170_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001f000
438 #define AR9170_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
439 #define AR9170_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000fc0
440 #define AR9170_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
441 #define AR9170_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003f
442 #define AR9170_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
444 #define AR9170_PHY_REG_CCK_RXCTRL4 (AR9170_PHY_REG_BASE + 0x0a1c)
445 #define AR9170_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01f80000
446 #define AR9170_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
448 #define AR9170_PHY_REG_DAG_CTRLCCK (AR9170_PHY_REG_BASE + 0x0a28)
449 #define AR9170_REG_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
450 #define AR9170_REG_DAG_CTRLCCK_RSSI_THR 0x0001fc00
451 #define AR9170_REG_DAG_CTRLCCK_RSSI_THR_S 10
453 #define AR9170_PHY_REG_FORCE_CLKEN_CCK (AR9170_PHY_REG_BASE + 0x0a2c)
454 #define AR9170_FORCE_CLKEN_CCK_MRC_MUX 0x00000040
456 #define AR9170_PHY_REG_POWER_TX_RATE3 (AR9170_PHY_REG_BASE + 0x0a34)
457 #define AR9170_PHY_REG_POWER_TX_RATE4 (AR9170_PHY_REG_BASE + 0x0a38)
459 #define AR9170_PHY_REG_SCRM_SEQ_XR (AR9170_PHY_REG_BASE + 0x0a3c)
460 #define AR9170_PHY_REG_HEADER_DETECT_XR (AR9170_PHY_REG_BASE + 0x0a40)
461 #define AR9170_PHY_REG_CHIRP_DETECTED_XR (AR9170_PHY_REG_BASE + 0x0a44)
462 #define AR9170_PHY_REG_BLUETOOTH (AR9170_PHY_REG_BASE + 0x0a54)
464 #define AR9170_PHY_REG_TPCRG1 (AR9170_PHY_REG_BASE + 0x0a58)
465 #define AR9170_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
466 #define AR9170_PHY_TPCRG1_NUM_PD_GAIN_S 14
467 #define AR9170_PHY_TPCRG1_PD_GAIN_1 0x00030000
468 #define AR9170_PHY_TPCRG1_PD_GAIN_1_S 16
469 #define AR9170_PHY_TPCRG1_PD_GAIN_2 0x000c0000
470 #define AR9170_PHY_TPCRG1_PD_GAIN_2_S 18
471 #define AR9170_PHY_TPCRG1_PD_GAIN_3 0x00300000
472 #define AR9170_PHY_TPCRG1_PD_GAIN_3_S 20
473 #define AR9170_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
474 #define AR9170_PHY_TPCRG1_PD_CAL_ENABLE_S 22
476 #define AR9170_PHY_REG_TX_PWRCTRL4 (AR9170_PHY_REG_BASE + 0x0a64)
477 #define AR9170_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001
478 #define AR9170_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0
479 #define AR9170_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001fe
480 #define AR9170_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1
482 #define AR9170_PHY_REG_ANALOG_SWAP (AR9170_PHY_REG_BASE + 0x0a68)
483 #define AR9170_PHY_ANALOG_SWAP_AB 0x0001
484 #define AR9170_PHY_ANALOG_SWAP_ALT_CHAIN 0x00000040
486 #define AR9170_PHY_REG_TPCRG5 (AR9170_PHY_REG_BASE + 0x0a6c)
487 #define AR9170_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000f
488 #define AR9170_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
489 #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003f0
490 #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
491 #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000fc00
492 #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
493 #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003f0000
494 #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
495 #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0fc00000
496 #define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
498 #define AR9170_PHY_REG_TX_PWRCTRL6_0 (AR9170_PHY_REG_BASE + 0x0a70)
499 #define AR9170_PHY_REG_TX_PWRCTRL6_1 (AR9170_PHY_REG_BASE + 0x1a70)
500 #define AR9170_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000
501 #define AR9170_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24
503 #define AR9170_PHY_REG_TX_PWRCTRL7 (AR9170_PHY_REG_BASE + 0x0a74)
504 #define AR9170_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01f80000
505 #define AR9170_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19
507 #define AR9170_PHY_REG_TX_PWRCTRL9 (AR9170_PHY_REG_BASE + 0x0a7c)
508 #define AR9170_PHY_TX_DESIRED_SCALE_CCK 0x00007c00
509 #define AR9170_PHY_TX_DESIRED_SCALE_CCK_S 10
510 #define AR9170_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000
511 #define AR9170_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31
513 #define AR9170_PHY_REG_TX_GAIN_TBL1 (AR9170_PHY_REG_BASE + 0x0b00)
514 #define AR9170_PHY_TX_GAIN 0x0007f000
515 #define AR9170_PHY_TX_GAIN_S 12
517 /* Carrier leak calibration control, do it after AGC calibration */
518 #define AR9170_PHY_REG_CL_CAL_CTL (AR9170_PHY_REG_BASE + 0x0b58)
519 #define AR9170_PHY_CL_CAL_ENABLE 0x00000002
520 #define AR9170_PHY_CL_CAL_PARALLEL_CAL_ENABLE 0x00000001
522 #define AR9170_PHY_REG_POWER_TX_RATE5 (AR9170_PHY_REG_BASE + 0x0b8c)
523 #define AR9170_PHY_REG_POWER_TX_RATE6 (AR9170_PHY_REG_BASE + 0x0b90)
525 #define AR9170_PHY_REG_CH0_TX_PWRCTRL11 (AR9170_PHY_REG_BASE + 0x0b98)
526 #define AR9170_PHY_REG_CH1_TX_PWRCTRL11 (AR9170_PHY_REG_BASE + 0x1b98)
527 #define AR9170_PHY_TX_CHX_PWRCTRL_OLPC_TEMP_COMP 0x0000fc00
528 #define AR9170_PHY_TX_CHX_PWRCTRL_OLPC_TEMP_COMP_S 10
530 #define AR9170_PHY_REG_CAL_CHAINMASK (AR9170_PHY_REG_BASE + 0x0b9c)
531 #define AR9170_PHY_REG_VIT_MASK2_M_46_61 (AR9170_PHY_REG_BASE + 0x0ba0)
532 #define AR9170_PHY_REG_MASK2_M_31_45 (AR9170_PHY_REG_BASE + 0x0ba4)
533 #define AR9170_PHY_REG_MASK2_M_16_30 (AR9170_PHY_REG_BASE + 0x0ba8)
534 #define AR9170_PHY_REG_MASK2_M_00_15 (AR9170_PHY_REG_BASE + 0x0bac)
535 #define AR9170_PHY_REG_PILOT_MASK_01_30 (AR9170_PHY_REG_BASE + 0x0bb0)
536 #define AR9170_PHY_REG_PILOT_MASK_31_60 (AR9170_PHY_REG_BASE + 0x0bb4)
537 #define AR9170_PHY_REG_MASK2_P_15_01 (AR9170_PHY_REG_BASE + 0x0bb8)
538 #define AR9170_PHY_REG_MASK2_P_30_16 (AR9170_PHY_REG_BASE + 0x0bbc)
539 #define AR9170_PHY_REG_MASK2_P_45_31 (AR9170_PHY_REG_BASE + 0x0bc0)
540 #define AR9170_PHY_REG_MASK2_P_61_45 (AR9170_PHY_REG_BASE + 0x0bc4)
541 #define AR9170_PHY_REG_POWER_TX_SUB (AR9170_PHY_REG_BASE + 0x0bc8)
542 #define AR9170_PHY_REG_POWER_TX_RATE7 (AR9170_PHY_REG_BASE + 0x0bcc)
543 #define AR9170_PHY_REG_POWER_TX_RATE8 (AR9170_PHY_REG_BASE + 0x0bd0)
544 #define AR9170_PHY_REG_POWER_TX_RATE9 (AR9170_PHY_REG_BASE + 0x0bd4)
545 #define AR9170_PHY_REG_XPA_CFG (AR9170_PHY_REG_BASE + 0x0bd8)
546 #define AR9170_PHY_FORCE_XPA_CFG 0x000000001
547 #define AR9170_PHY_FORCE_XPA_CFG_S 0
549 #define AR9170_PHY_REG_CH1_CCA (AR9170_PHY_REG_BASE + 0x1064)
550 #define AR9170_PHY_CH1_MINCCA_PWR 0x0ff80000
551 #define AR9170_PHY_CH1_MINCCA_PWR_S 19
553 #define AR9170_PHY_REG_CH2_CCA (AR9170_PHY_REG_BASE + 0x2064)
554 #define AR9170_PHY_CH2_MINCCA_PWR 0x0ff80000
555 #define AR9170_PHY_CH2_MINCCA_PWR_S 19
557 #define AR9170_PHY_REG_CH1_EXT_CCA (AR9170_PHY_REG_BASE + 0x11bc)
558 #define AR9170_PHY_CH1_EXT_MINCCA_PWR 0xff800000
559 #define AR9170_PHY_CH1_EXT_MINCCA_PWR_S 23
561 #define AR9170_PHY_REG_CH2_EXT_CCA (AR9170_PHY_REG_BASE + 0x21bc)
562 #define AR9170_PHY_CH2_EXT_MINCCA_PWR 0xff800000
563 #define AR9170_PHY_CH2_EXT_MINCCA_PWR_S 23
565 #define REDUCE_CHAIN_0 0x00000050
566 #define REDUCE_CHAIN_1 0x00000051
568 #endif /* __CARL9170_SHARED_PHY_H */