1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
20 /*****************************************************************************
22 * Module: __RTW_MP_PHY_REGDEF_H_
25 * Note: 1. Define PMAC/BB register map
26 * 2. Define RF register map
27 * 3. PMAC/BB register bit mask.
29 * 5. Other BB/RF relative definition.
32 * Export: Constants, macro, functions(API), global variables(None).
38 * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
39 * 2. Reorganize code architecture.
40 * 09/25/2008 MH 1. Add RL6052 register definition
42 *****************************************************************************/
43 #ifndef __RTW_MP_PHY_REGDEF_H_
44 #define __RTW_MP_PHY_REGDEF_H_
47 /*--------------------------Define Parameters-------------------------------*/
50 /* 8192S Regsiter offset definition */
54 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
55 /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */
56 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
57 /* 3. RF register 0x00-2E */
58 /* 4. Bit Mask for BB/RF register */
59 /* 5. Other definition for BB/RF R/W */
64 /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */
67 #define rPMAC_Reset 0x100
68 #define rPMAC_TxStart 0x104
69 #define rPMAC_TxLegacySIG 0x108
70 #define rPMAC_TxHTSIG1 0x10c
71 #define rPMAC_TxHTSIG2 0x110
72 #define rPMAC_PHYDebug 0x114
73 #define rPMAC_TxPacketNum 0x118
74 #define rPMAC_TxIdle 0x11c
75 #define rPMAC_TxMACHeader0 0x120
76 #define rPMAC_TxMACHeader1 0x124
77 #define rPMAC_TxMACHeader2 0x128
78 #define rPMAC_TxMACHeader3 0x12c
79 #define rPMAC_TxMACHeader4 0x130
80 #define rPMAC_TxMACHeader5 0x134
81 #define rPMAC_TxDataType 0x138
82 #define rPMAC_TxRandomSeed 0x13c
83 #define rPMAC_CCKPLCPPreamble 0x140
84 #define rPMAC_CCKPLCPHeader 0x144
85 #define rPMAC_CCKCRC16 0x148
86 #define rPMAC_OFDMRxCRC32OK 0x170
87 #define rPMAC_OFDMRxCRC32Er 0x174
88 #define rPMAC_OFDMRxParityEr 0x178
89 #define rPMAC_OFDMRxCRC8Er 0x17c
90 #define rPMAC_CCKCRxRC16Er 0x180
91 #define rPMAC_CCKCRxRC32Er 0x184
92 #define rPMAC_CCKCRxRC32OK 0x188
93 #define rPMAC_TxStatus 0x18c
98 /* The following two definition are only used for USB interface. */
99 /* define RF_BB_CMD_ADDR 0x02c0 RF/BB read/write command address. */
100 /* define RF_BB_CMD_DATA 0x02c4 RF/BB read/write command data. */
103 /* 3. Page8(0x800) */
105 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */
107 #define rFPGA0_TxInfo 0x804 /* Status report?? */
108 #define rFPGA0_PSDFunction 0x808
110 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
112 #define rFPGA0_RFTiming1 0x810 /* Useless now */
113 #define rFPGA0_RFTiming2 0x814
114 /* define rFPGA0_XC_RFTiming 0x818 */
115 /* define rFPGA0_XD_RFTiming 0x81c */
117 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
118 #define rFPGA0_XA_HSSIParameter2 0x824
119 #define rFPGA0_XB_HSSIParameter1 0x828
120 #define rFPGA0_XB_HSSIParameter2 0x82c
121 #define rFPGA0_XC_HSSIParameter1 0x830
122 #define rFPGA0_XC_HSSIParameter2 0x834
123 #define rFPGA0_XD_HSSIParameter1 0x838
124 #define rFPGA0_XD_HSSIParameter2 0x83c
125 #define rFPGA0_XA_LSSIParameter 0x840
126 #define rFPGA0_XB_LSSIParameter 0x844
127 #define rFPGA0_XC_LSSIParameter 0x848
128 #define rFPGA0_XD_LSSIParameter 0x84c
130 #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */
131 #define rFPGA0_RFSleepUpParameter 0x854
133 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */
134 #define rFPGA0_XCD_SwitchControl 0x85c
136 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */
137 #define rFPGA0_XB_RFInterfaceOE 0x864
138 #define rFPGA0_XC_RFInterfaceOE 0x868
139 #define rFPGA0_XD_RFInterfaceOE 0x86c
141 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */
142 #define rFPGA0_XCD_RFInterfaceSW 0x874
144 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */
145 #define rFPGA0_XCD_RFParameter 0x87c
147 #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */
148 #define rFPGA0_AnalogParameter2 0x884
149 #define rFPGA0_AnalogParameter3 0x888 /* Useless now */
150 #define rFPGA0_AnalogParameter4 0x88c
152 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */
153 #define rFPGA0_XB_LSSIReadBack 0x8a4
154 #define rFPGA0_XC_LSSIReadBack 0x8a8
155 #define rFPGA0_XD_LSSIReadBack 0x8ac
157 #define rFPGA0_PSDReport 0x8b4 /* Useless now */
158 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now RF Interface Readback Value */
159 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */
162 /* 4. Page9(0x900) */
164 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC RF BW Setting?? */
166 #define rFPGA1_TxBlock 0x904 /* Useless now */
167 #define rFPGA1_DebugSelect 0x908 /* Useless now */
168 #define rFPGA1_TxInfo 0x90c /* Useless now Status report?? */
171 /* 5. PageA(0xA00) */
173 /* Set Control channel to upper or lower. These settings are required only for 40MHz */
174 #define rCCK0_System 0xa00
176 #define rCCK0_AFESetting 0xa04 /* Disable init gain now Select RX path by RSSI */
177 #define rCCK0_CCA 0xa08 /* Disable init gain now Init gain */
179 #define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
180 #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */
182 #define rCCK0_RxHP 0xa14
184 #define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */
185 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */
187 #define rCCK0_TxFilter1 0xa20
188 #define rCCK0_TxFilter2 0xa24
189 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */
190 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */
191 #define rCCK0_TRSSIReport 0xa50
192 #define rCCK0_RxReport 0xa54 /* 0xa57 */
193 #define rCCK0_FACounterLower 0xa5c /* 0xa5b */
194 #define rCCK0_FACounterUpper 0xa58 /* 0xa5c */
197 /* 6. PageC(0xC00) */
199 #define rOFDM0_LSTF 0xc00
201 #define rOFDM0_TRxPathEnable 0xc04
202 #define rOFDM0_TRMuxPar 0xc08
203 #define rOFDM0_TRSWIsolation 0xc0c
205 #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */
206 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */
207 #define rOFDM0_XBRxAFE 0xc18
208 #define rOFDM0_XBRxIQImbalance 0xc1c
209 #define rOFDM0_XCRxAFE 0xc20
210 #define rOFDM0_XCRxIQImbalance 0xc24
211 #define rOFDM0_XDRxAFE 0xc28
212 #define rOFDM0_XDRxIQImbalance 0xc2c
214 #define rOFDM0_RxDetector1 0xc30 /* PD,BW & SBD DM tune init gain */
215 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */
216 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */
217 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */
219 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
220 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */
221 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */
222 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */
224 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */
225 #define rOFDM0_XAAGCCore2 0xc54
226 #define rOFDM0_XBAGCCore1 0xc58
227 #define rOFDM0_XBAGCCore2 0xc5c
228 #define rOFDM0_XCAGCCore1 0xc60
229 #define rOFDM0_XCAGCCore2 0xc64
230 #define rOFDM0_XDAGCCore1 0xc68
231 #define rOFDM0_XDAGCCore2 0xc6c
233 #define rOFDM0_AGCParameter1 0xc70
234 #define rOFDM0_AGCParameter2 0xc74
235 #define rOFDM0_AGCRSSITable 0xc78
236 #define rOFDM0_HTSTFAGC 0xc7c
238 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */
239 #define rOFDM0_XATxAFE 0xc84
240 #define rOFDM0_XBTxIQImbalance 0xc88
241 #define rOFDM0_XBTxAFE 0xc8c
242 #define rOFDM0_XCTxIQImbalance 0xc90
243 #define rOFDM0_XCTxAFE 0xc94
244 #define rOFDM0_XDTxIQImbalance 0xc98
245 #define rOFDM0_XDTxAFE 0xc9c
246 #define rOFDM0_RxIQExtAnta 0xca0
248 #define rOFDM0_RxHPParameter 0xce0
249 #define rOFDM0_TxPseudoNoiseWgt 0xce4
250 #define rOFDM0_FrameSync 0xcf0
251 #define rOFDM0_DFSReport 0xcf4
252 #define rOFDM0_TxCoeff1 0xca4
253 #define rOFDM0_TxCoeff2 0xca8
254 #define rOFDM0_TxCoeff3 0xcac
255 #define rOFDM0_TxCoeff4 0xcb0
256 #define rOFDM0_TxCoeff5 0xcb4
257 #define rOFDM0_TxCoeff6 0xcb8
259 /* 7. PageD(0xD00) */
260 #define rOFDM1_LSTF 0xd00
261 #define rOFDM1_TRxPathEnable 0xd04
263 #define rOFDM1_CFO 0xd08 /* No setting now */
264 #define rOFDM1_CSI1 0xd10
265 #define rOFDM1_SBD 0xd14
266 #define rOFDM1_CSI2 0xd18
267 #define rOFDM1_CFOTracking 0xd2c
268 #define rOFDM1_TRxMesaure1 0xd34
269 #define rOFDM1_IntfDet 0xd3c
270 #define rOFDM1_PseudoNoiseStateAB 0xd50
271 #define rOFDM1_PseudoNoiseStateCD 0xd54
272 #define rOFDM1_RxPseudoNoiseWgt 0xd58
274 #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */
275 #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */
276 #define rOFDM_PHYCounter3 0xda8 /* MCS not support */
278 #define rOFDM_ShortCFOAB 0xdac /* No setting now */
279 #define rOFDM_ShortCFOCD 0xdb0
280 #define rOFDM_LongCFOAB 0xdb4
281 #define rOFDM_LongCFOCD 0xdb8
282 #define rOFDM_TailCFOAB 0xdbc
283 #define rOFDM_TailCFOCD 0xdc0
284 #define rOFDM_PWMeasure1 0xdc4
285 #define rOFDM_PWMeasure2 0xdc8
286 #define rOFDM_BWReport 0xdcc
287 #define rOFDM_AGCReport 0xdd0
288 #define rOFDM_RxSNR 0xdd4
289 #define rOFDM_RxEVMCSI 0xdd8
290 #define rOFDM_SIGReport 0xddc
294 /* 8. PageE(0xE00) */
296 #define rTxAGC_Rate18_06 0xe00
297 #define rTxAGC_Rate54_24 0xe04
298 #define rTxAGC_CCK_Mcs32 0xe08
299 #define rTxAGC_Mcs03_Mcs00 0xe10
300 #define rTxAGC_Mcs07_Mcs04 0xe14
301 #define rTxAGC_Mcs11_Mcs08 0xe18
302 #define rTxAGC_Mcs15_Mcs12 0xe1c
304 /* Analog- control in RX_WAIT_CCA : REG: EE0 [Analog- Power & Control Register] */
305 #define rRx_Wait_CCCA 0xe70
306 #define rAnapar_Ctrl_BB 0xee0
309 /* 7. RF Register 0x00-0x2E (RF 8256) */
310 /* RF-0222D 0x00-3F */
313 #define RTL92SE_FPGA_VERIFY 0
314 #define rZebra1_HSSIEnable 0x0 /* Useless now */
315 #define rZebra1_TRxEnable1 0x1
316 #define rZebra1_TRxEnable2 0x2
317 #define rZebra1_AGC 0x4
318 #define rZebra1_ChargePump 0x5
319 /* if (RTL92SE_FPGA_VERIFY == 1) */
320 #define rZebra1_Channel 0x7 /* RF channel switch */
324 #define rZebra1_TxGain 0x8 /* Useless now */
325 #define rZebra1_TxLPF 0x9
326 #define rZebra1_RxLPF 0xb
327 #define rZebra1_RxHPFCorner 0xc
330 #define rGlobalCtrl 0 /* Useless now */
331 #define rRTL8256_TxLPF 19
332 #define rRTL8256_RxLPF 11
335 #define rRTL8258_TxLPF 0x11 /* Useless now */
336 #define rRTL8258_RxLPF 0x13
337 #define rRTL8258_RSSILPF 0xa
340 /* RL6052 Register definition */
341 #define RF_AC 0x00 /* */
343 #define RF_IQADJ_G1 0x01 /* */
344 #define RF_IQADJ_G2 0x02 /* */
345 #define RF_POW_TRSW 0x05 /* */
347 #define RF_GAIN_RX 0x06 /* */
348 #define RF_GAIN_TX 0x07 /* */
350 #define RF_TXM_IDAC 0x08 /* */
351 #define RF_BS_IQGEN 0x0F /* */
353 #define RF_MODE1 0x10 /* */
354 #define RF_MODE2 0x11 /* */
356 #define RF_RX_AGC_HP 0x12 /* */
357 #define RF_TX_AGC 0x13 /* */
358 #define RF_BIAS 0x14 /* */
359 #define RF_IPA 0x15 /* */
360 #define RF_TXBIAS 0x16 /* */
361 #define RF_POW_ABILITY 0x17 /* */
362 #define RF_MODE_AG 0x18 /* */
363 #define rRfChannel 0x18 /* RF channel and BW switch */
364 #define RF_CHNLBW 0x18 /* RF channel and BW switch */
365 #define RF_TOP 0x19 /* */
367 #define RF_RX_G1 0x1A /* */
368 #define RF_RX_G2 0x1B /* */
370 #define RF_RX_BB2 0x1C /* */
371 #define RF_RX_BB1 0x1D /* */
373 #define RF_RCK1 0x1E /* */
374 #define RF_RCK2 0x1F /* */
376 #define RF_TX_G1 0x20 /* */
377 #define RF_TX_G2 0x21 /* */
378 #define RF_TX_G3 0x22 /* */
380 #define RF_TX_BB1 0x23 /* */
382 #define RF_T_METER 0x24 /* */
384 #define RF_SYN_G1 0x25 /* RF TX Power control */
385 #define RF_SYN_G2 0x26 /* RF TX Power control */
386 #define RF_SYN_G3 0x27 /* RF TX Power control */
387 #define RF_SYN_G4 0x28 /* RF TX Power control */
388 #define RF_SYN_G5 0x29 /* RF TX Power control */
389 #define RF_SYN_G6 0x2A /* RF TX Power control */
390 #define RF_SYN_G7 0x2B /* RF TX Power control */
391 #define RF_SYN_G8 0x2C /* RF TX Power control */
393 #define RF_RCK_OS 0x30 /* RF TX PA control */
394 #define RF_TXPA_G1 0x31 /* RF TX PA control */
395 #define RF_TXPA_G2 0x32 /* RF TX PA control */
396 #define RF_TXPA_G3 0x33 /* RF TX PA control */
401 /* 1. Page1(0x100) */
402 #define bBBResetB 0x100 /* Useless now? */
403 #define bGlobalResetB 0x200
404 #define bOFDMTxStart 0x4
405 #define bCCKTxStart 0x8
406 #define bCRC32Debug 0x100
407 #define bPMACLoopback 0x10
408 #define bTxLSIG 0xffffff
409 #define bOFDMTxRate 0xf
410 #define bOFDMTxReserved 0x10
411 #define bOFDMTxLength 0x1ffe0
412 #define bOFDMTxParity 0x20000
413 #define bTxHTSIG1 0xffffff
414 #define bTxHTMCSRate 0x7f
416 #define bTxHTLength 0xffff00
417 #define bTxHTSIG2 0xffffff
418 #define bTxHTSmoothing 0x1
419 #define bTxHTSounding 0x2
420 #define bTxHTReserved 0x4
421 #define bTxHTAggreation 0x8
422 #define bTxHTSTBC 0x30
423 #define bTxHTAdvanceCoding 0x40
424 #define bTxHTShortGI 0x80
425 #define bTxHTNumberHT_LTF 0x300
426 #define bTxHTCRC8 0x3fc00
427 #define bCounterReset 0x10000
428 #define bNumOfOFDMTx 0xffff
429 #define bNumOfCCKTx 0xffff0000
430 #define bTxIdleInterval 0xffff
431 #define bOFDMService 0xffff0000
432 #define bTxMACHeader 0xffffffff
433 #define bTxDataInit 0xff
434 #define bTxHTMode 0x100
435 #define bTxDataType 0x30000
436 #define bTxRandomSeed 0xffffffff
437 #define bCCKTxPreamble 0x1
438 #define bCCKTxSFD 0xffff0000
439 #define bCCKTxSIG 0xff
440 #define bCCKTxService 0xff00
441 #define bCCKLengthExt 0x8000
442 #define bCCKTxLength 0xffff0000
443 #define bCCKTxCRC16 0xffff
444 #define bCCKTxStatus 0x1
445 #define bOFDMTxStatus 0x2
447 #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
449 /* 2. Page8(0x800) */
450 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */
451 #define bJapanMode 0x2
452 #define bCCKTxSC 0x30
453 #define bCCKEn 0x1000000
454 #define bOFDMEn 0x2000000
456 #define bOFDMRxADCPhase 0x10000 /* Useless now */
457 #define bOFDMTxDACPhase 0x40000
458 #define bXATxAGC 0x3f
460 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */
461 #define bXCTxAGC 0xf000
462 #define bXDTxAGC 0xf0000
464 #define bPAStart 0xf0000000 /* Useless now */
465 #define bTRStart 0x00f00000
466 #define bRFStart 0x0000f000
467 #define bBBStart 0x000000f0
468 #define bBBCCKStart 0x0000000f
469 #define bPAEnd 0xf /* Reg0x814 */
470 #define bTREnd 0x0f000000
471 #define bRFEnd 0x000f0000
472 #define bCCAMask 0x000000f0 /* T2R */
473 #define bR2RCCAMask 0x00000f00
474 #define bHSSI_R2TDelay 0xf8000000
475 #define bHSSI_T2RDelay 0xf80000
476 #define bContTxHSSI 0x400 /* chane gain at continue Tx */
477 #define bIGFromCCK 0x200
478 #define bAGCAddress 0x3f
479 #define bRxHPTx 0x7000
480 #define bRxHPT2R 0x38000
481 #define bRxHPCCKIni 0xc0000
482 #define bAGCTxCode 0xc00000
483 #define bAGCRxCode 0x300000
485 #define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
486 #define b3WireAddressLength 0x400
488 #define b3WireRFPowerDown 0x1 /* Useless now */
489 /* define bHWSISelect 0x8 */
490 #define b5GPAPEPolarity 0x40000000
491 #define b2GPAPEPolarity 0x80000000
492 #define bRFSW_TxDefaultAnt 0x3
493 #define bRFSW_TxOptionAnt 0x30
494 #define bRFSW_RxDefaultAnt 0x300
495 #define bRFSW_RxOptionAnt 0x3000
496 #define bRFSI_3WireData 0x1
497 #define bRFSI_3WireClock 0x2
498 #define bRFSI_3WireLoad 0x4
499 #define bRFSI_3WireRW 0x8
500 #define bRFSI_3Wire 0xf
502 #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
504 #define bRFSI_TRSW 0x20 /* Useless now */
505 #define bRFSI_TRSWB 0x40
506 #define bRFSI_ANTSW 0x100
507 #define bRFSI_ANTSWB 0x200
508 #define bRFSI_PAPE 0x400
509 #define bRFSI_PAPE5G 0x800
510 #define bBandSelect 0x1
511 #define bHTSIG2_GI 0x80
512 #define bHTSIG2_Smoothing 0x01
513 #define bHTSIG2_Sounding 0x02
514 #define bHTSIG2_Aggreaton 0x08
515 #define bHTSIG2_STBC 0x30
516 #define bHTSIG2_AdvCoding 0x40
517 #define bHTSIG2_NumOfHTLTF 0x300
518 #define bHTSIG2_CRC8 0x3fc
519 #define bHTSIG1_MCS 0x7f
520 #define bHTSIG1_BandWidth 0x80
521 #define bHTSIG1_HTLength 0xffff
522 #define bLSIG_Rate 0xf
523 #define bLSIG_Reserved 0x10
524 #define bLSIG_Length 0x1fffe
525 #define bLSIG_Parity 0x20
526 #define bCCKRxPhase 0x4
527 #if (RTL92SE_FPGA_VERIFY == 1)
528 #define bLSSIReadAddress 0x3f000000 /* LSSI "Read" Address
529 Reg 0x824 rFPGA0_XA_HSSIParameter2 */
531 #define bLSSIReadAddress 0x7f800000 /* T65 RF */
533 #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */
534 #if (RTL92SE_FPGA_VERIFY == 1)
535 #define bLSSIReadBackData 0xfff /* Reg 0x8a0
536 rFPGA0_XA_LSSIReadBack */
538 #define bLSSIReadBackData 0xfffff /* T65 RF */
540 #define bLSSIReadOKFlag 0x1000 /* Useless now */
541 #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */
542 #define bRegulator0Standby 0x1
543 #define bRegulatorPLLStandby 0x2
544 #define bRegulator1Standby 0x4
545 #define bPLLPowerUp 0x8
546 #define bDPLLPowerUp 0x10
547 #define bDA10PowerUp 0x20
548 #define bAD7PowerUp 0x200
549 #define bDA6PowerUp 0x2000
550 #define bXtalPowerUp 0x4000
551 #define b40MDClkPowerUP 0x8000
552 #define bDA6DebugMode 0x20000
553 #define bDA6Swing 0x380000
555 #define bADClkPhase 0x4000000 /* Reg 0x880
556 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
558 #define b80MClkDelay 0x18000000 /* Useless */
559 #define bAFEWatchDogEnable 0x20000000
561 #define bXtalCap01 0xc0000000 /* Reg 0x884
562 rFPGA0_AnalogParameter2 Crystal cap */
563 #define bXtalCap23 0x3
564 #define bXtalCap92x 0x0f000000
565 #define bXtalCap 0x0f000000
567 #define bIntDifClkEnable 0x400 /* Useless */
568 #define bExtSigClkEnable 0x800
569 #define bBandgapMbiasPowerUp 0x10000
570 #define bAD11SHGain 0xc0000
571 #define bAD11InputRange 0x700000
572 #define bAD11OPCurrent 0x3800000
573 #define bIPathLoopback 0x4000000
574 #define bQPathLoopback 0x8000000
575 #define bAFELoopback 0x10000000
576 #define bDA10Swing 0x7e0
577 #define bDA10Reverse 0x800
578 #define bDAClkSource 0x1000
579 #define bAD7InputRange 0x6000
580 #define bAD7Gain 0x38000
581 #define bAD7OutputCMMode 0x40000
582 #define bAD7InputCMMode 0x380000
583 #define bAD7Current 0xc00000
584 #define bRegulatorAdjust 0x7000000
585 #define bAD11PowerUpAtTx 0x1
586 #define bDA10PSAtTx 0x10
587 #define bAD11PowerUpAtRx 0x100
588 #define bDA10PSAtRx 0x1000
589 #define bCCKRxAGCFormat 0x200
590 #define bPSDFFTSamplepPoint 0xc000
591 #define bPSDAverageNum 0x3000
592 #define bIQPathControl 0xc00
593 #define bPSDFreq 0x3ff
594 #define bPSDAntennaPath 0x30
595 #define bPSDIQSwitch 0x40
596 #define bPSDRxTrigger 0x400000
597 #define bPSDTxTrigger 0x80000000
598 #define bPSDSineToneScale 0x7f000000
599 #define bPSDReport 0xffff
601 /* 3. Page9(0x900) */
602 #define bOFDMTxSC 0x30000000 /* Useless */
604 #define bOFDMTxOn 0x2
605 #define bDebugPage 0xfff /* reset debug page and HWord,
607 #define bDebugItem 0xff /* reset debug page and LWord */
609 #define bAntNonHT 0x100
610 #define bAntHT1 0x1000
611 #define bAntHT2 0x10000
612 #define bAntHT1S1 0x100000
613 #define bAntNonHTS1 0x1000000
615 /* 4. PageA(0xA00) */
616 #define bCCKBBMode 0x3 /* Useless */
617 #define bCCKTxPowerSaving 0x80
618 #define bCCKRxPowerSaving 0x40
620 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0 20/40 sw */
622 #define bCCKScramble 0x8 /* Useless */
623 #define bCCKAntDiversity 0x8000
624 #define bCCKCarrierRecovery 0x4000
625 #define bCCKTxRate 0x3000
626 #define bCCKDCCancel 0x0800
627 #define bCCKISICancel 0x0400
628 #define bCCKMatchFilter 0x0200
629 #define bCCKEqualizer 0x0100
630 #define bCCKPreambleDetect 0x800000
631 #define bCCKFastFalseCCA 0x400000
632 #define bCCKChEstStart 0x300000
633 #define bCCKCCACount 0x080000
634 #define bCCKcs_lim 0x070000
635 #define bCCKBistMode 0x80000000
636 #define bCCKCCAMask 0x40000000
637 #define bCCKTxDACPhase 0x4
638 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */
639 #define bCCKr_cp_mode0 0x0100
640 #define bCCKTxDCOffset 0xf0
641 #define bCCKRxDCOffset 0xf
642 #define bCCKCCAMode 0xc000
643 #define bCCKFalseCS_lim 0x3f00
644 #define bCCKCS_ratio 0xc00000
645 #define bCCKCorgBit_sel 0x300000
646 #define bCCKPD_lim 0x0f0000
647 #define bCCKNewCCA 0x80000000
648 #define bCCKRxHPofIG 0x8000
649 #define bCCKRxIG 0x7f00
650 #define bCCKLNAPolarity 0x800000
651 #define bCCKRx1stGain 0x7f0000
652 #define bCCKRFExtend 0x20000000 /* CCK Rx init gain polar */
653 #define bCCKRxAGCSatLevel 0x1f000000
654 #define bCCKRxAGCSatCount 0xe0
655 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */
656 #define bCCKFixedRxAGC 0x8000
657 #define bCCKAntennaPolarity 0x2000
658 #define bCCKTxFilterType 0x0c00
659 #define bCCKRxAGCReportType 0x0300
660 #define bCCKRxDAGCEn 0x80000000
661 #define bCCKRxDAGCPeriod 0x20000000
662 #define bCCKRxDAGCSatLevel 0x1f000000
663 #define bCCKTimingRecovery 0x800000
664 #define bCCKTxC0 0x3f0000
665 #define bCCKTxC1 0x3f000000
666 #define bCCKTxC2 0x3f
667 #define bCCKTxC3 0x3f00
668 #define bCCKTxC4 0x3f0000
669 #define bCCKTxC5 0x3f000000
670 #define bCCKTxC6 0x3f
671 #define bCCKTxC7 0x3f00
672 #define bCCKDebugPort 0xff0000
673 #define bCCKDACDebug 0x0f000000
674 #define bCCKFalseAlarmEnable 0x8000
675 #define bCCKFalseAlarmRead 0x4000
676 #define bCCKTRSSI 0x7f
677 #define bCCKRxAGCReport 0xfe
678 #define bCCKRxReport_AntSel 0x80000000
679 #define bCCKRxReport_MFOff 0x40000000
680 #define bCCKRxRxReport_SQLoss 0x20000000
681 #define bCCKRxReport_Pktloss 0x10000000
682 #define bCCKRxReport_Lockedbit 0x08000000
683 #define bCCKRxReport_RateError 0x04000000
684 #define bCCKRxReport_RxRate 0x03000000
685 #define bCCKRxFACounterLower 0xff
686 #define bCCKRxFACounterUpper 0xff000000
687 #define bCCKRxHPAGCStart 0xe000
688 #define bCCKRxHPAGCFinal 0x1c00
689 #define bCCKRxFalseAlarmEnable 0x8000
690 #define bCCKFACounterFreeze 0x4000
691 #define bCCKTxPathSel 0x10000000
692 #define bCCKDefaultRxPath 0xc000000
693 #define bCCKOptionRxPath 0x3000000
695 /* 5. PageC(0xC00) */
696 #define bNumOfSTF 0x3 /* Useless */
697 #define bShift_L 0xc0
707 #define bTRSSIFreq 0x200
708 #define bADCBackoff 0x3000
709 #define bDFIRBackoff 0xc000
710 #define bTRSSILatchPhase 0x10000
711 #define bRxIDCOffset 0xff
712 #define bRxQDCOffset 0xff00
713 #define bRxDFIRMode 0x1800000
714 #define bRxDCNFType 0xe000000
715 #define bRXIQImb_A 0x3ff
716 #define bRXIQImb_B 0xfc00
717 #define bRXIQImb_C 0x3f0000
718 #define bRXIQImb_D 0xffc00000
719 #define bDC_dc_Notch 0x60000
720 #define bRxNBINotch 0x1f000000
722 #define bPD_TH_Opt2 0xc000
723 #define bPWED_TH 0x700
724 #define bIfMF_Win_L 0x800
725 #define bPD_Option 0x1000
726 #define bMF_Win_L 0xe000
727 #define bBW_Search_L 0x30000
728 #define bwin_enh_L 0xc0000
729 #define bBW_TH 0x700000
730 #define bED_TH2 0x3800000
731 #define bBW_option 0x4000000
732 #define bRatio_TH 0x18000000
733 #define bWindow_L 0xe0000000
734 #define bSBD_Option 0x1
735 #define bFrame_TH 0x1c
736 #define bFS_Option 0x60
737 #define bDC_Slope_check 0x80
738 #define bFGuard_Counter_DC_L 0xe00
739 #define bFrame_Weight_Short 0x7000
740 #define bSub_Tune 0xe00000
741 #define bFrame_DC_Length 0xe000000
742 #define bSBD_start_offset 0x30000000
743 #define bFrame_TH_2 0x7
744 #define bFrame_GI2_TH 0x38
745 #define bGI2_Sync_en 0x40
746 #define bSarch_Short_Early 0x300
747 #define bSarch_Short_Late 0xc00
748 #define bSarch_GI2_Late 0x70000
749 #define bCFOAntSum 0x1
751 #define bCFOStartOffset 0xc
752 #define bCFOLookBack 0x70
753 #define bCFOSumWeight 0x80
754 #define bDAGCEnable 0x10000
755 #define bTXIQImb_A 0x3ff
756 #define bTXIQImb_B 0xfc00
757 #define bTXIQImb_C 0x3f0000
758 #define bTXIQImb_D 0xffc00000
759 #define bTxIDCOffset 0xff
760 #define bTxQDCOffset 0xff00
761 #define bTxDFIRMode 0x10000
762 #define bTxPesudoNoiseOn 0x4000000
763 #define bTxPesudoNoise_A 0xff
764 #define bTxPesudoNoise_B 0xff00
765 #define bTxPesudoNoise_C 0xff0000
766 #define bTxPesudoNoise_D 0xff000000
767 #define bCCADropOption 0x20000
768 #define bCCADropThres 0xfff00000
770 #define bEDCCA_L 0xf0
771 #define bLambda_ED 0x300
772 #define bRxInitialGain 0x7f
773 #define bRxAntDivEn 0x80
774 #define bRxAGCAddressForLNA 0x7f00
775 #define bRxHighPowerFlow 0x8000
776 #define bRxAGCFreezeThres 0xc0000
777 #define bRxFreezeStep_AGC1 0x300000
778 #define bRxFreezeStep_AGC2 0xc00000
779 #define bRxFreezeStep_AGC3 0x3000000
780 #define bRxFreezeStep_AGC0 0xc000000
781 #define bRxRssi_Cmp_En 0x10000000
782 #define bRxQuickAGCEn 0x20000000
783 #define bRxAGCFreezeThresMode 0x40000000
784 #define bRxOverFlowCheckType 0x80000000
785 #define bRxAGCShift 0x7f
786 #define bTRSW_Tri_Only 0x80
787 #define bPowerThres 0x300
789 #define bRxAGCTogetherEn 0x2
790 #define bRxAGCMin 0x4
791 #define bRxHP_Ini 0x7
792 #define bRxHP_TRLNA 0x70
793 #define bRxHP_RSSI 0x700
794 #define bRxHP_BBP1 0x7000
795 #define bRxHP_BBP2 0x70000
796 #define bRxHP_BBP3 0x700000
797 #define bRSSI_H 0x7f0000 /* thresh for hi power */
798 #define bRSSI_Gen 0x7f000000 /* thresh for ant div */
799 #define bRxSettle_TRSW 0x7
800 #define bRxSettle_LNA 0x38
801 #define bRxSettle_RSSI 0x1c0
802 #define bRxSettle_BBP 0xe00
803 #define bRxSettle_RxHP 0x7000
804 #define bRxSettle_AntSW_RSSI 0x38000
805 #define bRxSettle_AntSW 0xc0000
806 #define bRxProcessTime_DAGC 0x300000
807 #define bRxSettle_HSSI 0x400000
808 #define bRxProcessTime_BBPPW 0x800000
809 #define bRxAntennaPowerShift 0x3000000
810 #define bRSSITableSelect 0xc000000
811 #define bRxHP_Final 0x7000000
812 #define bRxHTSettle_BBP 0x7
813 #define bRxHTSettle_HSSI 0x8
814 #define bRxHTSettle_RxHP 0x70
815 #define bRxHTSettle_BBPPW 0x80
816 #define bRxHTSettle_Idle 0x300
817 #define bRxHTSettle_Reserved 0x1c00
818 #define bRxHTRxHPEn 0x8000
819 #define bRxHTAGCFreezeThres 0x30000
820 #define bRxHTAGCTogetherEn 0x40000
821 #define bRxHTAGCMin 0x80000
822 #define bRxHTAGCEn 0x100000
823 #define bRxHTDAGCEn 0x200000
824 #define bRxHTRxHP_BBP 0x1c00000
825 #define bRxHTRxHP_Final 0xe0000000
826 #define bRxPWRatioTH 0x3
827 #define bRxPWRatioEn 0x4
828 #define bRxMFHold 0x3800
829 #define bRxPD_Delay_TH1 0x38
830 #define bRxPD_Delay_TH2 0x1c0
831 #define bRxPD_DC_COUNT_MAX 0x600
832 /* define bRxMF_Hold 0x3800 */
833 #define bRxPD_Delay_TH 0x8000
834 #define bRxProcess_Delay 0xf0000
835 #define bRxSearchrange_GI2_Early 0x700000
836 #define bRxFrame_Guard_Counter_L 0x3800000
837 #define bRxSGI_Guard_L 0xc000000
838 #define bRxSGI_Search_L 0x30000000
839 #define bRxSGI_TH 0xc0000000
840 #define bDFSCnt0 0xff
841 #define bDFSCnt1 0xff00
842 #define bDFSFlag 0xf0000
843 #define bMFWeightSum 0x300000
844 #define bMinIdxTH 0x7f000000
845 #define bDAFormat 0x40000
846 #define bTxChEmuEnable 0x01000000
847 #define bTRSWIsolation_A 0x7f
848 #define bTRSWIsolation_B 0x7f00
849 #define bTRSWIsolation_C 0x7f0000
850 #define bTRSWIsolation_D 0x7f000000
851 #define bExtLNAGain 0x7c00
853 /* 6. PageE(0xE00) */
854 #define bSTBCEn 0x4 /* Useless */
855 #define bAntennaMapping 0x10
857 #define bCFOAntSumD 0x200
858 #define bPHYCounterReset 0x8000000
859 #define bCFOReportGet 0x4000000
860 #define bOFDMContinueTx 0x10000000
861 #define bOFDMSingleCarrier 0x20000000
862 #define bOFDMSingleTone 0x40000000
863 /* define bRxPath1 0x01 */
864 /* define bRxPath2 0x02 */
865 /* define bRxPath3 0x04 */
866 /* define bRxPath4 0x08 */
867 /* define bTxPath1 0x10 */
868 /* define bTxPath2 0x20 */
869 #define bHTDetect 0x100
870 #define bCFOEn 0x10000
871 #define bCFOValue 0xfff00000
872 #define bSigTone_Re 0x3f
873 #define bSigTone_Im 0x7f00
874 #define bCounter_CCA 0xffff
875 #define bCounter_ParityFail 0xffff0000
876 #define bCounter_RateIllegal 0xffff
877 #define bCounter_CRC8Fail 0xffff0000
878 #define bCounter_MCSNoSupport 0xffff
879 #define bCounter_FastSync 0xffff
880 #define bShortCFO 0xfff
881 #define bShortCFOTLength 12 /* total */
882 #define bShortCFOFLength 11 /* fraction */
883 #define bLongCFO 0x7ff
884 #define bLongCFOTLength 11
885 #define bLongCFOFLength 11
886 #define bTailCFO 0x1fff
887 #define bTailCFOTLength 13
888 #define bTailCFOFLength 12
889 #define bmax_en_pwdB 0xffff
890 #define bCC_power_dB 0xffff0000
891 #define bnoise_pwdB 0xffff
892 #define bPowerMeasTLength 10
893 #define bPowerMeasFLength 3
894 #define bRx_HT_BW 0x1
897 #define bNB_intf_det_on 0x1
898 #define bIntf_win_len_cfg 0x30
899 #define bNB_Intf_TH_cfg 0x1c0
901 #define bTableSel 0x40
903 #define bRxSNR_A 0xff
904 #define bRxSNR_B 0xff00
905 #define bRxSNR_C 0xff0000
906 #define bRxSNR_D 0xff000000
907 #define bSNREVMTLength 8
908 #define bSNREVMFLength 1
910 #define bCSI2nd 0xff00
911 #define bRxEVM1st 0xff0000
912 #define bRxEVM2nd 0xff000000
915 #define bSGIEN 0x10000
917 #define bSFactorQAM1 0xf /* Useless */
918 #define bSFactorQAM2 0xf0
919 #define bSFactorQAM3 0xf00
920 #define bSFactorQAM4 0xf000
921 #define bSFactorQAM5 0xf0000
922 #define bSFactorQAM6 0xf0000
923 #define bSFactorQAM7 0xf00000
924 #define bSFactorQAM8 0xf000000
925 #define bSFactorQAM9 0xf0000000
926 #define bCSIScheme 0x100000
928 #define bNoiseLvlTopSet 0x3 /* Useless */
929 #define bChSmooth 0x4
930 #define bChSmoothCfg1 0x38
931 #define bChSmoothCfg2 0x1c0
932 #define bChSmoothCfg3 0xe00
933 #define bChSmoothCfg4 0x7000
934 #define bMRCMode 0x800000
935 #define bTHEVMCfg 0x7000000
937 #define bLoopFitType 0x1 /* Useless */
939 #define bUpdCFOOffData 0x80
940 #define bAdvUpdCFO 0x100
941 #define bAdvTimeCtrl 0x800
942 #define bUpdClko 0x1000
944 #define bTrackingMode 0x8000
945 #define bPhCmpEnable 0x10000
946 #define bUpdClkoLTF 0x20000
947 #define bComChCFO 0x40000
948 #define bCSIEstiMode 0x80000
949 #define bAdvUpdEqz 0x100000
950 #define bUChCfg 0x7000000
951 #define bUpdEqz 0x8000000
953 #define bTxAGCRate18_06 0x7f7f7f7f /* Useless */
954 #define bTxAGCRate54_24 0x7f7f7f7f
955 #define bTxAGCRateMCS32 0x7f
956 #define bTxAGCRateCCK 0x7f00
957 #define bTxAGCRateMCS3_MCS0 0x7f7f7f7f
958 #define bTxAGCRateMCS7_MCS4 0x7f7f7f7f
959 #define bTxAGCRateMCS11_MCS8 0x7f7f7f7f
960 #define bTxAGCRateMCS15_MCS12 0x7f7f7f7f
962 /* Rx Pseduo noise */
963 #define bRxPesudoNoiseOn 0x20000000 /* Useless */
964 #define bRxPesudoNoise_A 0xff
965 #define bRxPesudoNoise_B 0xff00
966 #define bRxPesudoNoise_C 0xff0000
967 #define bRxPesudoNoise_D 0xff000000
968 #define bPesudoNoiseState_A 0xffff
969 #define bPesudoNoiseState_B 0xffff0000
970 #define bPesudoNoiseState_C 0xffff
971 #define bPesudoNoiseState_D 0xffff0000
975 #define bZebra1_HSSIEnable 0x8 /* Useless */
976 #define bZebra1_TRxControl 0xc00
977 #define bZebra1_TRxGainSetting 0x07f
978 #define bZebra1_RxCorner 0xc00
979 #define bZebra1_TxChargePump 0x38
980 #define bZebra1_RxChargePump 0x7
981 #define bZebra1_ChannelNum 0xf80
982 #define bZebra1_TxLPFBW 0x400
983 #define bZebra1_RxLPFBW 0x600
986 #define bRTL8256RegModeCtrl1 0x100 /* Useless */
987 #define bRTL8256RegModeCtrl0 0x40
988 #define bRTL8256_TxLPFBW 0x18
989 #define bRTL8256_RxLPFBW 0x600
992 #define bRTL8258_TxLPFBW 0xc /* Useless */
993 #define bRTL8258_RxLPFBW 0xc00
994 #define bRTL8258_RSSILPFBW 0xc0
998 /* Other Definition */
1001 /* byte endable for sb_write */
1002 #define bByte0 0x1 /* Useless */
1010 /* for PutRegsetting & GetRegSetting BitMask */
1011 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
1012 #define bMaskByte1 0xff00
1013 #define bMaskByte2 0xff0000
1014 #define bMaskByte3 0xff000000
1015 #define bMaskHWord 0xffff0000
1016 #define bMaskLWord 0x0000ffff
1017 #define bMaskDWord 0xffffffff
1018 #define bMaskH4Bits 0xf0000000
1019 #define bMaskOFDM_D 0xffc00000
1020 #define bMaskCCK 0x3f3f3f3f
1021 #define bMask12Bits 0xfff
1023 /* for PutRFRegsetting & GetRFRegSetting BitMask */
1024 #if (RTL92SE_FPGA_VERIFY == 1)
1025 #define bRFRegOffsetMask 0xfff
1027 #define bRFRegOffsetMask 0xfffff
1029 #define bEnable 0x1 /* Useless */
1032 #define LeftAntenna 0x0 /* Useless */
1033 #define RightAntenna 0x1
1035 #define tCheckTxStatus 500 /* 500ms Useless */
1036 #define tUpdateRxCounter 100 /* 100ms */
1038 #define rateCCK 0 /* Useless */
1042 /* define Register-End */
1043 #define bPMAC_End 0x1ff /* Useless */
1044 #define bFPGAPHY0_End 0x8ff
1045 #define bFPGAPHY1_End 0x9ff
1046 #define bCCKPHY0_End 0xaff
1047 #define bOFDMPHY0_End 0xcff
1048 #define bOFDMPHY1_End 0xdff
1050 /* define max debug item in each debug page */
1051 /* define bMaxItem_FPGA_PHY0 0x9 */
1052 /* define bMaxItem_FPGA_PHY1 0x3 */
1053 /* define bMaxItem_PHY_11B 0x16 */
1054 /* define bMaxItem_OFDM_PHY0 0x29 */
1055 /* define bMaxItem_OFDM_PHY1 0x0 */
1057 #define bPMACControl 0x0 /* Useless */
1058 #define bWMACControl 0x1
1059 #define bWNICControl 0x2
1061 #define RCR_AAP BIT(0) /* accept all physical address */
1062 #define RCR_APM BIT(1) /* accept physical match */
1063 #define RCR_AM BIT(2) /* accept multicast */
1064 #define RCR_AB BIT(3) /* accept broadcast */
1065 #define RCR_ACRC32 BIT(5) /* accept error packet */
1066 #define RCR_9356SEL BIT(6)
1067 #define RCR_AICV BIT(12) /* Accept ICV error packet */
1068 #define RCR_RXFTH0 (BIT(13)|BIT(14)|BIT(15)) /* Rx FIFO threshold */
1069 #define RCR_ADF BIT(18) /* Accept Data(frame type) frame */
1070 #define RCR_ACF BIT(19) /* Accept control frame */
1071 #define RCR_AMF BIT(20) /* Accept management frame */
1072 #define RCR_ADD3 BIT(21)
1073 #define RCR_APWRMGT BIT(22) /* Accept power management packet */
1074 #define RCR_CBSSID BIT(23) /* Accept BSSID match packet */
1075 #define RCR_ENMARP BIT(28) /* enable mac auto reset phy */
1076 #define RCR_EnCS1 BIT(29) /* enable carrier sense method 1 */
1077 #define RCR_EnCS2 BIT(30) /* enable carrier sense method 2 */
1078 #define RCR_OnlyErlPkt BIT(31) /* Rx Early mode is performed for
1079 * packet size greater than 1536 */
1081 /*--------------------------Define Parameters-------------------------------*/
1084 #endif /* __INC_HAL8192SPHYREG_H */