1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
21 #ifndef __ODM_REGDEFINE11N_H__
22 #define __ODM_REGDEFINE11N_H__
26 #define ODM_REG_RF_MODE_11N 0x00
27 #define ODM_REG_RF_0B_11N 0x0B
28 #define ODM_REG_CHNBW_11N 0x18
29 #define ODM_REG_T_METER_11N 0x24
30 #define ODM_REG_RF_25_11N 0x25
31 #define ODM_REG_RF_26_11N 0x26
32 #define ODM_REG_RF_27_11N 0x27
33 #define ODM_REG_RF_2B_11N 0x2B
34 #define ODM_REG_RF_2C_11N 0x2C
35 #define ODM_REG_RXRF_A3_11N 0x3C
36 #define ODM_REG_T_METER_92D_11N 0x42
37 #define ODM_REG_T_METER_88E_11N 0x42
43 #define ODM_REG_BB_CTRL_11N 0x800
44 #define ODM_REG_RF_PIN_11N 0x804
45 #define ODM_REG_PSD_CTRL_11N 0x808
46 #define ODM_REG_TX_ANT_CTRL_11N 0x80C
47 #define ODM_REG_BB_PWR_SAV5_11N 0x818
48 #define ODM_REG_CCK_RPT_FORMAT_11N 0x824
49 #define ODM_REG_RX_DEFUALT_A_11N 0x858
50 #define ODM_REG_RX_DEFUALT_B_11N 0x85A
51 #define ODM_REG_BB_PWR_SAV3_11N 0x85C
52 #define ODM_REG_ANTSEL_CTRL_11N 0x860
53 #define ODM_REG_RX_ANT_CTRL_11N 0x864
54 #define ODM_REG_PIN_CTRL_11N 0x870
55 #define ODM_REG_BB_PWR_SAV1_11N 0x874
56 #define ODM_REG_ANTSEL_PATH_11N 0x878
57 #define ODM_REG_BB_3WIRE_11N 0x88C
58 #define ODM_REG_SC_CNT_11N 0x8C4
59 #define ODM_REG_PSD_DATA_11N 0x8B4
61 #define ODM_REG_ANT_MAPPING1_11N 0x914
62 #define ODM_REG_ANT_MAPPING2_11N 0x918
64 #define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
65 #define ODM_REG_CCK_CCA_11N 0xA0A
66 #define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
67 #define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10
68 #define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14
69 #define ODM_REG_CCK_FILTER_PARA1_11N 0xA22
70 #define ODM_REG_CCK_FILTER_PARA2_11N 0xA23
71 #define ODM_REG_CCK_FILTER_PARA3_11N 0xA24
72 #define ODM_REG_CCK_FILTER_PARA4_11N 0xA25
73 #define ODM_REG_CCK_FILTER_PARA5_11N 0xA26
74 #define ODM_REG_CCK_FILTER_PARA6_11N 0xA27
75 #define ODM_REG_CCK_FILTER_PARA7_11N 0xA28
76 #define ODM_REG_CCK_FILTER_PARA8_11N 0xA29
77 #define ODM_REG_CCK_FA_RST_11N 0xA2C
78 #define ODM_REG_CCK_FA_MSB_11N 0xA58
79 #define ODM_REG_CCK_FA_LSB_11N 0xA5C
80 #define ODM_REG_CCK_CCA_CNT_11N 0xA60
81 #define ODM_REG_BB_PWR_SAV4_11N 0xA74
83 #define ODM_REG_LNA_SWITCH_11N 0xB2C
84 #define ODM_REG_PATH_SWITCH_11N 0xB30
85 #define ODM_REG_RSSI_CTRL_11N 0xB38
86 #define ODM_REG_CONFIG_ANTA_11N 0xB68
87 #define ODM_REG_RSSI_BT_11N 0xB9C
89 #define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
90 #define ODM_REG_RX_PATH_11N 0xC04
91 #define ODM_REG_TRMUX_11N 0xC08
92 #define ODM_REG_OFDM_FA_RSTC_11N 0xC0C
93 #define ODM_REG_RXIQI_MATRIX_11N 0xC14
94 #define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
95 #define ODM_REG_IGI_A_11N 0xC50
96 #define ODM_REG_ANTDIV_PARA2_11N 0xC54
97 #define ODM_REG_IGI_B_11N 0xC58
98 #define ODM_REG_ANTDIV_PARA3_11N 0xC5C
99 #define ODM_REG_BB_PWR_SAV2_11N 0xC70
100 #define ODM_REG_RX_OFF_11N 0xC7C
101 #define ODM_REG_TXIQK_MATRIXA_11N 0xC80
102 #define ODM_REG_TXIQK_MATRIXB_11N 0xC88
103 #define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
104 #define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
105 #define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
106 #define ODM_REG_ANTDIV_PARA1_11N 0xCA4
107 #define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
109 #define ODM_REG_OFDM_FA_RSTD_11N 0xD00
110 #define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
111 #define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
112 #define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
114 #define ODM_REG_TXAGC_A_6_18_11N 0xE00
115 #define ODM_REG_TXAGC_A_24_54_11N 0xE04
116 #define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08
117 #define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10
118 #define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14
119 #define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18
120 #define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C
121 #define ODM_REG_FPGA0_IQK_11N 0xE28
122 #define ODM_REG_TXIQK_TONE_A_11N 0xE30
123 #define ODM_REG_RXIQK_TONE_A_11N 0xE34
124 #define ODM_REG_TXIQK_PI_A_11N 0xE38
125 #define ODM_REG_RXIQK_PI_A_11N 0xE3C
126 #define ODM_REG_TXIQK_11N 0xE40
127 #define ODM_REG_RXIQK_11N 0xE44
128 #define ODM_REG_IQK_AGC_PTS_11N 0xE48
129 #define ODM_REG_IQK_AGC_RSP_11N 0xE4C
130 #define ODM_REG_BLUETOOTH_11N 0xE6C
131 #define ODM_REG_RX_WAIT_CCA_11N 0xE70
132 #define ODM_REG_TX_CCK_RFON_11N 0xE74
133 #define ODM_REG_TX_CCK_BBON_11N 0xE78
134 #define ODM_REG_OFDM_RFON_11N 0xE7C
135 #define ODM_REG_OFDM_BBON_11N 0xE80
136 #define ODM_REG_TX2RX_11N 0xE84
137 #define ODM_REG_TX2TX_11N 0xE88
138 #define ODM_REG_RX_CCK_11N 0xE8C
139 #define ODM_REG_RX_OFDM_11N 0xED0
140 #define ODM_REG_RX_WAIT_RIFS_11N 0xED4
141 #define ODM_REG_RX2RX_11N 0xED8
142 #define ODM_REG_STANDBY_11N 0xEDC
143 #define ODM_REG_SLEEP_11N 0xEE0
144 #define ODM_REG_PMPD_ANAEN_11N 0xEEC
153 #define ODM_REG_BB_RST_11N 0x02
154 #define ODM_REG_ANTSEL_PIN_11N 0x4C
155 #define ODM_REG_EARLY_MODE_11N 0x4D0
156 #define ODM_REG_RSSI_MONITOR_11N 0x4FE
157 #define ODM_REG_EDCA_VO_11N 0x500
158 #define ODM_REG_EDCA_VI_11N 0x504
159 #define ODM_REG_EDCA_BE_11N 0x508
160 #define ODM_REG_EDCA_BK_11N 0x50C
161 #define ODM_REG_TXPAUSE_11N 0x522
162 #define ODM_REG_RESP_TX_11N 0x6D8
163 #define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0
164 #define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4
168 #define ODM_BIT_IGI_11N 0x0000007F