1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
22 #ifndef __HALDMOUTSRC_H__
23 #define __HALDMOUTSRC_H__
26 /* Define all team support ability. */
28 /* Define for all teams. Please Define the constant in your precomp header. */
30 /* define DM_ODM_SUPPORT_AP 0 */
31 /* define DM_ODM_SUPPORT_ADSL 0 */
32 /* define DM_ODM_SUPPORT_CE 0 */
33 /* define DM_ODM_SUPPORT_MP 1 */
35 /* Define ODM SW team support flag. */
37 /* Antenna Switch Relative Definition. */
39 /* Add new function SwAntDivCheck8192C(). */
40 /* This is the main function of Antenna diversity function before link. */
41 /* Mainly, it just retains last scan result and scan again. */
42 /* After that, it compares the scan result to see which one gets better
43 * RSSI. It selects antenna with better receiving power and returns better
49 #define TRAFFIC_HIGH 1
51 /* 3 Tx Power Tracking */
52 /* 3============================================================ */
53 #define DPK_DELTA_MAPPING_NUM 13
54 #define index_mapping_HP_NUM 15
59 /* 3============================================================ */
61 #define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */
62 #define MODE_40M 0 /* 0:20M, 1:40M */
64 #define PSD_CHM 20 /* Minimum channel number for BT AFH */
65 #define SIR_STEP_SIZE 3
66 #define Smooth_Size_1 5
68 #define Smooth_Size_2 10
70 #define Smooth_Size_3 20
72 #define Smooth_Step_Size 5
73 #define Adaptive_SIR 1
75 #define PSD_SCAN_INTERVAL 700 /* ms */
77 /* 8723A High Power IGI Setting */
78 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22
79 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
80 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a
83 #define DM_DIG_FA_TH0_LPS 4 /* 4 in lps */
84 #define DM_DIG_FA_TH1_LPS 15 /* 15 lps */
85 #define DM_DIG_FA_TH2_LPS 30 /* 30 lps */
86 #define RSSI_OFFSET_DIG 0x05;
89 #define ANTTESTALL 0x00 /* Ant A or B will be Testing */
90 #define ANTTESTA 0x01 /* Ant A will be Testing */
91 #define ANTTESTB 0x02 /* Ant B will be testing */
95 u8 Dig_Ext_Port_Stage;
103 u8 CurSTAConnectState;
104 u8 PreSTAConnectState;
105 u8 CurMultiSTAConnectState;
112 s8 BackoffVal_range_max;
113 s8 BackoffVal_range_min;
114 u8 rx_gain_range_max;
115 u8 rx_gain_range_min;
127 u8 DIG_Dynamic_MIN_0;
128 u8 DIG_Dynamic_MIN_1;
129 bool bMediaConnect_0;
130 bool bMediaConnect_1;
146 u32 Reg874, RegC70, Reg85C, RegA74;
150 struct false_alarm_stats {
152 u32 Cnt_Rate_Illegal;
159 u32 Cnt_SB_Search_fail;
163 u32 Cnt_BW_USC; /* Gary */
164 u32 Cnt_BW_LSC; /* Gary */
170 u8 PSD_bitmap_RXHP[80];
175 bool First_time_enter;
178 struct timer_list PSDTimer;
181 #define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */
182 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
184 /* This indicates two different steps. */
185 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to
186 * the signal on the air. */
187 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in
188 * SWAW_STEP_PEAK with original RSSI to determine if it is necessary to
191 #define SWAW_STEP_PEAK 0
192 #define SWAW_STEP_DETERMINE 1
196 #define TRAFFIC_LOW 0
197 #define TRAFFIC_HIGH 1
199 struct sw_ant_switch {
206 u8 bTriggerAntennaSwitch;
210 /* Before link Antenna Switch check */
211 u8 SWAS_NoLink_State;
212 u32 SWAS_NoLink_BK_Reg860;
213 bool ANTA_ON; /* To indicate Ant A is or not */
214 bool ANTB_ON; /* To indicate Ant B is on or not */
227 struct timer_list SwAntennaSwitchTimer;
228 /* Hybrid Antenna Diversity */
229 u32 CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
230 u32 CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
231 u32 OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
232 u32 OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
233 u32 RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM];
234 u32 RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM];
235 u8 TxAnt[ASSOCIATE_ENTRY_NUM];
242 bool bCurrentTurboEDCA;
244 u32 prv_traffic_idx; /* edca turbo */
247 struct odm_rate_adapt {
248 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */
249 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */
250 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */
251 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
252 u32 LastRATR; /* RATR Register Content */
255 #define IQK_MAC_REG_NUM 4
256 #define IQK_ADDA_REG_NUM 16
257 #define IQK_BB_REG_NUM_MAX 10
258 #define IQK_BB_REG_NUM 9
259 #define HP_THERMAL_NUM 8
261 #define AVG_THERMAL_NUM 8
262 #define IQK_Matrix_REG_NUM 8
263 #define IQK_Matrix_Settings_NUM 1+24+21
265 #define DM_Type_ByFWi 0
266 #define DM_Type_ByDriver 1
268 /* Declare for common info */
270 struct odm_phy_status_info {
272 u8 SignalQuality; /* in 0-100 index. */
273 u8 RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; /* EVM */
274 u8 RxMIMOSignalStrength[MAX_PATH_NUM_92CS];/* in 0~100 index */
275 s8 RxPower; /* in dBm Translate from PWdB */
276 s8 RecvSignalPower;/* Real power in dBm for this packet, no
277 * beautification and aggregation. Keep this raw
278 * info to be used for the other procedures. */
279 u8 BTRxRSSIPercentage;
280 u8 SignalStrength; /* in 0-100 index. */
281 u8 RxPwr[MAX_PATH_NUM_92CS];/* per-path's pwdb */
282 u8 RxSNR[MAX_PATH_NUM_92CS];/* per-path's SNR */
285 struct odm_phy_dbg_info {
286 /* ODM Write,debug info */
287 s8 RxSNRdB[MAX_PATH_NUM_92CS];
289 u64 NumQryPhyStatusCCK;
290 u64 NumQryPhyStatusOFDM;
292 s32 RxEVM[MAX_PATH_NUM_92CS];
295 struct odm_per_pkt_info {
298 bool bPacketMatchBSSID;
303 struct odm_mac_status_info {
309 ODM_DIG = 0x00000001,
310 ODM_HIGH_POWER = 0x00000002,
311 ODM_CCK_CCA_TH = 0x00000004,
312 ODM_FA_STATISTICS = 0x00000008,
313 ODM_RAMASK = 0x00000010,
314 ODM_RSSI_MONITOR = 0x00000020,
315 ODM_SW_ANTDIV = 0x00000040,
316 ODM_HW_ANTDIV = 0x00000080,
317 ODM_BB_PWRSV = 0x00000100,
318 ODM_2TPATHDIV = 0x00000200,
319 ODM_1TPATHDIV = 0x00000400,
320 ODM_PSD2AFH = 0x00000800
323 /* 2011/20/20 MH For MP driver RT_WLAN_STA = struct sta_info */
324 /* Please declare below ODM relative info in your STA info structure. */
326 struct odm_sta_info {
328 bool bUsed; /* record the sta status link or not? */
329 u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */
332 /* 1 PHY_STATUS_INFO */
333 u8 RSSI_Path[4]; /* */
339 /* 2011/10/20 MH Define Common info enum for all team. */
341 enum odm_common_info_def {
344 /* HOOK BEFORE REG INIT----------- */
345 ODM_CMNINFO_PLATFORM = 0,
346 ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */
347 ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */
348 ODM_CMNINFO_MP_TEST_CHIP,
349 ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */
350 ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */
351 ODM_CMNINFO_FAB_VER, /* ODM_FAB_E */
352 ODM_CMNINFO_RF_TYPE, /* ODM_RF_PATH_E or ODM_RF_TYPE_E? */
353 ODM_CMNINFO_BOARD_TYPE, /* ODM_BOARD_TYPE_E */
354 ODM_CMNINFO_EXT_LNA, /* true */
356 ODM_CMNINFO_EXT_TRSW,
357 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */
358 ODM_CMNINFO_BINHCT_TEST,
359 ODM_CMNINFO_BWIFI_TEST,
360 ODM_CMNINFO_SMART_CONCURRENT,
361 /* HOOK BEFORE REG INIT----------- */
364 /* POINTER REFERENCE----------- */
365 ODM_CMNINFO_MAC_PHY_MODE, /* ODM_MAC_PHY_MODE_E */
368 ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */
369 ODM_CMNINFO_BAND, /* ODM_BAND_TYPE_E */
370 ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */
371 ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */
372 ODM_CMNINFO_BW, /* ODM_BW_E */
375 ODM_CMNINFO_DMSP_GET_VALUE,
376 ODM_CMNINFO_BUDDY_ADAPTOR,
377 ODM_CMNINFO_DMSP_IS_MASTER,
379 ODM_CMNINFO_POWER_SAVING,
380 ODM_CMNINFO_ONE_PATH_CCA, /* ODM_CCA_PATH_E */
381 ODM_CMNINFO_DRV_STOP,
384 ODM_CMNINFO_ANT_TEST,
385 ODM_CMNINFO_NET_CLOSED,
387 /* POINTER REFERENCE----------- */
389 /* CALL BY VALUE------------- */
390 ODM_CMNINFO_WIFI_DIRECT,
391 ODM_CMNINFO_WIFI_DISPLAY,
393 ODM_CMNINFO_RSSI_MIN,
394 ODM_CMNINFO_DBG_COMP, /* u64 */
395 ODM_CMNINFO_DBG_LEVEL, /* u32 */
396 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */
397 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */
398 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */
399 ODM_CMNINFO_BT_DISABLED,
400 ODM_CMNINFO_BT_OPERATION,
402 ODM_CMNINFO_BT_BUSY, /* Check Bt is using or not */
403 ODM_CMNINFO_BT_DISABLE_EDCA,
404 /* CALL BY VALUE-------------*/
406 /* Dynamic ptr array hook itms. */
407 ODM_CMNINFO_STA_STATUS,
408 ODM_CMNINFO_PHY_STATUS,
409 ODM_CMNINFO_MAC_STATUS,
413 /* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */
415 enum odm_ability_def {
416 /* BB ODM section BIT 0-15 */
418 ODM_BB_RA_MASK = BIT(1),
419 ODM_BB_DYNAMIC_TXPWR = BIT(2),
420 ODM_BB_FA_CNT = BIT(3),
421 ODM_BB_RSSI_MONITOR = BIT(4),
422 ODM_BB_CCK_PD = BIT(5),
423 ODM_BB_ANT_DIV = BIT(6),
424 ODM_BB_PWR_SAVE = BIT(7),
425 ODM_BB_PWR_TRA = BIT(8),
426 ODM_BB_RATE_ADAPTIVE = BIT(9),
427 ODM_BB_PATH_DIV = BIT(10),
428 ODM_BB_PSD = BIT(11),
429 ODM_BB_RXHP = BIT(12),
431 /* MAC DM section BIT 16-23 */
432 ODM_MAC_EDCA_TURBO = BIT(16),
433 ODM_MAC_EARLY_MODE = BIT(17),
435 /* RF ODM section BIT 24-31 */
436 ODM_RF_TX_PWR_TRACK = BIT(24),
437 ODM_RF_RX_GAIN_TRACK = BIT(25),
438 ODM_RF_CALIBRATION = BIT(26),
441 #define ODM_RTL8188E BIT(4)
443 /* ODM_CMNINFO_CUT_VER */
444 enum odm_cut_version {
454 /* ODM_CMNINFO_FAB_VER */
455 enum odm_fab_Version {
460 /* ODM_CMNINFO_RF_TYPE */
461 /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */
463 ODM_RF_TX_A = BIT(0),
464 ODM_RF_TX_B = BIT(1),
465 ODM_RF_TX_C = BIT(2),
466 ODM_RF_TX_D = BIT(3),
467 ODM_RF_RX_A = BIT(4),
468 ODM_RF_RX_B = BIT(5),
469 ODM_RF_RX_C = BIT(6),
470 ODM_RF_RX_D = BIT(7),
484 /* ODM Dynamic common info value definition */
486 enum odm_mac_phy_mode {
492 enum odm_bt_coexist {
499 /* ODM_CMNINFO_OP_MODE */
500 enum odm_operation_mode {
501 ODM_NO_LINK = BIT(0),
504 ODM_POWERSAVE = BIT(3),
505 ODM_AP_MODE = BIT(4),
506 ODM_CLIENT_MODE = BIT(5),
508 ODM_WIFI_DIRECT = BIT(7),
509 ODM_WIFI_DISPLAY = BIT(8),
512 /* ODM_CMNINFO_WM_MODE */
513 enum odm_wireless_mode {
518 ODM_WM_N24G = BIT(3),
520 ODM_WM_AUTO = BIT(5),
524 /* ODM_CMNINFO_BAND */
526 ODM_BAND_2_4G = BIT(0),
527 ODM_BAND_5G = BIT(1),
530 /* ODM_CMNINFO_SEC_CHNL_OFFSET */
531 enum odm_sec_chnl_offset {
537 /* ODM_CMNINFO_SEC_MODE */
545 ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */
558 /* ODM_CMNINFO_BOARD_TYPE */
559 enum odm_board_type {
560 ODM_BOARD_NORMAL = 0,
561 ODM_BOARD_HIGHPWR = 1,
562 ODM_BOARD_MINICARD = 2,
567 /* ODM_CMNINFO_ONE_PATH_CCA */
595 u8 PTActive; /* on or off */
596 u8 PTTryState; /* 0 trying state, 1 for decision state */
597 u8 PTStage; /* 0~6 */
598 u8 PTStopCount; /* Stop PT counter */
599 u8 PTPreRate; /* if rate change do PT */
600 u8 PTPreRssi; /* if RSSI change 5% do PT */
601 u8 PTModeSS; /* decide whitch rate should do PT */
602 u8 RAstage; /* StageRA, decide how many times RA will be done
607 struct ijk_matrix_regs_set {
609 s32 Value[1][IQK_Matrix_REG_NUM];
613 /* for tx power tracking */
614 u32 RegA24; /* for TempCCK */
621 bool bTXPowerTrackingInit;
622 bool bTXPowerTracking;
623 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking
626 u8 InternalPA5G[2]; /* pathA / pathB */
628 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0,
634 u8 ThermalValue_AVG[AVG_THERMAL_NUM];
635 u8 ThermalValue_AVG_index;
636 u8 ThermalValue_RxGain;
637 u8 ThermalValue_Crystal;
638 u8 ThermalValue_DPKstore;
639 u8 ThermalValue_DPKtrack;
640 bool TxPowerTrackingInProgress;
643 bool bReloadtxpowerindex;
645 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */
652 u8 ThermalValue_HP[HP_THERMAL_NUM];
653 u8 ThermalValue_HP_index;
654 struct ijk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
669 bool bIQKInitialized;
671 bool bAntennaDetected;
672 u32 ADDA_backup[IQK_ADDA_REG_NUM];
673 u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
674 u32 IQK_BB_backup_recover[9];
675 u32 IQK_BB_backup[IQK_BB_REG_NUM];
678 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
680 u8 bAPKThermalMeterIgnore;
686 /* ODM Dynamic common info value definition */
688 struct fast_ant_train {
698 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
699 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
700 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
701 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
702 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
703 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
704 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
710 FAT_NORMAL_STATE = 0,
711 FAT_TRAINING_STATE = 1,
716 CG_TRX_HW_ANTDIV = 0x01,
717 CGCS_RX_HW_ANTDIV = 0x02,
718 FIXED_HW_ANTDIV = 0x03,
719 CG_TRX_SMART_ANTDIV = 0x04,
720 CGCS_RX_SW_ANTDIV = 0x05,
723 /* Copy from SD4 defined structure. We use to support PHY DM integration. */
724 struct odm_dm_struct {
725 /* Add for different team use temporarily */
726 struct adapter *Adapter; /* For CE/NIC team */
727 struct rtl8192cd_priv *priv; /* For AP/ADSL team */
728 /* WHen you use above pointers, they must be initialized. */
731 struct rtl8192cd_priv *fake_priv;
735 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
737 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */
739 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
741 /* 1 COMMON INFORMATION */
743 /* HOOK BEFORE REG INIT----------- */
744 /* ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */
746 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K */
748 /* ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 */
750 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any
751 * other type = 1/2/3/... */
753 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */
755 /* Fab Version TSMC/UMC = 0/1 */
757 /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */
759 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/. = 0/1/2/3/4/. */
761 /* with external LNA NO/Yes = 0/1 */
763 /* with external PA NO/Yes = 0/1 */
765 /* with external TRSW NO/Yes = 0/1 */
767 u8 PatchID; /* Customer ID */
771 bool bDualMacSmartConcurrent;
772 u32 BK_SupportAbility;
774 /* HOOK BEFORE REG INIT----------- */
777 /* POINTER REFERENCE----------- */
781 struct adapter *adapter_temp;
783 /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */
785 /* TX Unicast byte count */
786 u64 *pNumTxBytesUnicast;
787 /* RX Unicast byte count */
788 u64 *pNumRxBytesUnicast;
789 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */
790 u8 *pWirelessMode; /* ODM_WIRELESS_MODE_E */
791 /* Frequence band 2.4G/5G = 0/1 */
793 /* Secondary channel offset don't_care/below/above = 0/1/2 */
795 /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */
797 /* BW info 20M/40M/80M = 0/1/2 */
799 /* Central channel location Ch1/Ch2/.... */
800 u8 *pChannel; /* central channel number */
801 /* Common info for 92D DMSP */
803 bool *pbGetValueFromOtherMac;
804 struct adapter **pBuddyAdapter;
805 bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */
806 /* Common info for Status */
807 bool *pbScanInProcess;
809 /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */
811 /* pMgntInfo->AntennaTest */
814 /* POINTER REFERENCE----------- */
816 /* CALL BY VALUE------------- */
821 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */
824 /* Common info for BTDM */
825 bool bBtDisabled; /* BT is disabled */
826 bool bBtHsOperation; /* BT HS mode is under progress */
827 u8 btHsDigVal; /* use BT rssi to decide the DIG value */
828 bool bBtDisableEdcaTurbo;/* Under some condition, don't enable the
830 bool bBtBusy; /* BT is busy. */
831 /* CALL BY VALUE------------- */
833 /* 2 Define STA info. */
835 /* For MP, we need to reduce one array pointer for default port.?? */
836 struct sta_info *pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
839 struct odm_ra_info RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; /* Use MacID as
840 * array index. STA MacID=0,
841 * VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} */
843 /* 2012/02/14 MH Add to share 88E ra with other SW team. */
844 /* We need to colelct all support abilit to a proper area. */
848 /* Define ........... */
850 /* Latest packet phy info (ODM write) */
851 struct odm_phy_dbg_info PhyDbgInfo;
853 /* Latest packet phy info (ODM write) */
854 struct odm_mac_status_info *pMacInfo;
856 /* Different Team independt structure?? */
859 struct fast_ant_train DM_FatTable;
860 struct rtw_dig DM_DigTable;
861 struct rtl_ps DM_PSTable;
862 struct rx_hpc DM_RXHP_Table;
863 struct false_alarm_stats FalseAlmCnt;
864 struct false_alarm_stats FlaseAlmCntBuddyAdapter;
865 struct sw_ant_switch DM_SWAT_Table;
868 struct edca_turbo DM_EDCA_Table;
870 /* Copy from SD4 structure */
872 /* ================================================== */
875 bool *pbDriverStopped;
876 bool *pbDriverIsGoingToPnpSetPowerSleep;
877 bool *pinit_adpt_in_progress;
880 bool bUserAssignLevel;
881 struct timer_list PSDTimer;
882 u8 RSSI_BT; /* come from BT */
884 bool bDMInitialGainEnable;
886 /* for rate adaptive, in fact, 88c/92c fw will handle this */
889 struct odm_rate_adapt RateAdaptive;
891 struct odm_rf_cal RFCalibrateInfo;
893 /* TX power tracking */
895 u8 BbSwingIdxOfdmCurrent;
896 u8 BbSwingIdxOfdmBase;
897 bool BbSwingFlagOfdm;
899 u8 BbSwingIdxCckCurrent;
900 u8 BbSwingIdxCckBase;
903 /* ODM system resource. */
905 /* ODM relative time. */
906 struct timer_list PathDivSwitchTimer;
907 /* 2011.09.27 add for Path Diversity */
908 struct timer_list CCKPathDiversityTimer;
909 struct timer_list FastAntTrainingTimer;
910 }; /* DM_Dynamic_Mechanism_Structure */
912 #define ODM_RF_PATH_MAX 3
914 enum ODM_RF_CONTENT {
915 odm_radioa_txt = 0x1000,
916 odm_radiob_txt = 0x1001,
917 odm_radioc_txt = 0x1002,
918 odm_radiod_txt = 0x1003
927 RT_STATUS_INVALID_CONTEXT,
928 RT_STATUS_INVALID_PARAMETER,
929 RT_STATUS_NOT_SUPPORT,
930 RT_STATUS_OS_API_FAILED,
933 /* 3=========================================================== */
935 /* 3=========================================================== */
938 RT_TYPE_THRESH_HIGH = 0,
939 RT_TYPE_THRESH_LOW = 1,
941 RT_TYPE_RX_GAIN_MIN = 3,
942 RT_TYPE_RX_GAIN_MAX = 4,
948 #define DM_DIG_THRESH_HIGH 40
949 #define DM_DIG_THRESH_LOW 35
951 #define DM_SCAN_RSSI_TH 0x14 /* scan return issue for LC */
954 #define DM_false_ALARM_THRESH_LOW 400
955 #define DM_false_ALARM_THRESH_HIGH 1000
957 #define DM_DIG_MAX_NIC 0x4e
958 #define DM_DIG_MIN_NIC 0x1e /* 0x22/0x1c */
960 #define DM_DIG_MAX_AP 0x32
961 #define DM_DIG_MIN_AP 0x20
963 #define DM_DIG_MAX_NIC_HP 0x46
964 #define DM_DIG_MIN_NIC_HP 0x2e
966 #define DM_DIG_MAX_AP_HP 0x42
967 #define DM_DIG_MIN_AP_HP 0x30
969 /* vivi 92c&92d has different definition, 20110504 */
970 /* this is for 92c */
971 #define DM_DIG_FA_TH0 0x200/* 0x20 */
972 #define DM_DIG_FA_TH1 0x300/* 0x100 */
973 #define DM_DIG_FA_TH2 0x400/* 0x200 */
974 /* this is for 92d */
975 #define DM_DIG_FA_TH0_92D 0x100
976 #define DM_DIG_FA_TH1_92D 0x400
977 #define DM_DIG_FA_TH2_92D 0x600
979 #define DM_DIG_BACKOFF_MAX 12
980 #define DM_DIG_BACKOFF_MIN -4
981 #define DM_DIG_BACKOFF_DEFAULT 10
983 /* 3=========================================================== */
984 /* 3 AGC RX High Power Mode */
985 /* 3=========================================================== */
986 #define LNA_Low_Gain_1 0x64
987 #define LNA_Low_Gain_2 0x5A
988 #define LNA_Low_Gain_3 0x58
990 #define FA_RXHP_TH1 5000
991 #define FA_RXHP_TH2 1500
992 #define FA_RXHP_TH3 800
993 #define FA_RXHP_TH4 600
994 #define FA_RXHP_TH5 500
996 /* 3=========================================================== */
998 /* 3=========================================================== */
1000 /* 3=========================================================== */
1001 /* 3 Dynamic Tx Power */
1002 /* 3=========================================================== */
1003 /* Dynamic Tx Power Control Threshold */
1004 #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
1005 #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
1006 #define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F
1008 #define TxHighPwrLevel_Normal 0
1009 #define TxHighPwrLevel_Level1 1
1010 #define TxHighPwrLevel_Level2 2
1011 #define TxHighPwrLevel_BT1 3
1012 #define TxHighPwrLevel_BT2 4
1013 #define TxHighPwrLevel_15 5
1014 #define TxHighPwrLevel_35 6
1015 #define TxHighPwrLevel_50 7
1016 #define TxHighPwrLevel_70 8
1017 #define TxHighPwrLevel_100 9
1019 /* 3=========================================================== */
1020 /* 3 Rate Adaptive */
1021 /* 3=========================================================== */
1022 #define DM_RATR_STA_INIT 0
1023 #define DM_RATR_STA_HIGH 1
1024 #define DM_RATR_STA_MIDDLE 2
1025 #define DM_RATR_STA_LOW 3
1027 /* 3=========================================================== */
1028 /* 3 BB Power Save */
1029 /* 3=========================================================== */
1044 /* 3=========================================================== */
1045 /* 3 Antenna Diversity */
1046 /* 3=========================================================== */
1053 /* Maximal number of antenna detection mechanism needs to perform. */
1054 #define MAX_ANTENNA_DETECTION_CNT 10
1056 /* Extern Global Variables. */
1057 #define OFDM_TABLE_SIZE_92C 37
1058 #define OFDM_TABLE_SIZE_92D 43
1059 #define CCK_TABLE_SIZE 33
1061 extern u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D];
1062 extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
1063 extern u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8];
1065 /* check Sta pointer valid or not */
1066 #define IS_STA_VALID(pSta) (pSta)
1067 /* 20100514 Joseph: Add definition for antenna switching test after link. */
1068 /* This indicates two different the steps. */
1069 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the
1070 * signal on the air. */
1071 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in
1073 /* with original RSSI to determine if it is necessary to switch antenna. */
1074 #define SWAW_STEP_PEAK 0
1075 #define SWAW_STEP_DETERMINE 1
1077 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
1078 #define dm_RF_Saving ODM_RF_Saving
1080 void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal);
1081 void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm);
1082 void odm_DIGbyRSSI_LPS(struct odm_dm_struct *pDM_Odm);
1083 void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres);
1084 bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI,
1085 bool bForceUpdate, u8 *pRATRState);
1086 u32 ConvertTo_dB(u32 Value);
1087 u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid,
1088 u32 ra_mask, u8 rssi_level);
1089 void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm,
1090 enum odm_common_info_def CmnInfo, u32 Value);
1091 void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value);
1092 void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm,
1093 enum odm_common_info_def CmnInfo, void *pValue);
1094 void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm,
1095 enum odm_common_info_def CmnInfo,
1096 u16 Index, void *pValue);
1097 void ODM_DMInit(struct odm_dm_struct *pDM_Odm);
1098 void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm);
1099 void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI);