1 /* SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2005 David Brownell
9 #include <linux/device.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/slab.h>
12 #include <linux/kthread.h>
13 #include <linux/completion.h>
14 #include <linux/scatterlist.h>
15 #include <linux/gpio/consumer.h>
18 struct property_entry;
19 struct spi_controller;
21 struct spi_controller_mem_ops;
24 * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
25 * and SPI infrastructure.
27 extern struct bus_type spi_bus_type;
30 * struct spi_statistics - statistics for spi transfers
31 * @lock: lock protecting this structure
33 * @messages: number of spi-messages handled
34 * @transfers: number of spi_transfers handled
35 * @errors: number of errors during spi_transfer
36 * @timedout: number of timeouts during spi_transfer
38 * @spi_sync: number of times spi_sync is used
39 * @spi_sync_immediate:
40 * number of times spi_sync is executed immediately
41 * in calling context without queuing and scheduling
42 * @spi_async: number of times spi_async is used
44 * @bytes: number of bytes transferred to/from device
45 * @bytes_tx: number of bytes sent to device
46 * @bytes_rx: number of bytes received from device
48 * @transfer_bytes_histo:
49 * transfer bytes histogramm
51 * @transfers_split_maxsize:
52 * number of transfers that have been split because of
55 struct spi_statistics {
56 spinlock_t lock; /* lock for the whole structure */
58 unsigned long messages;
59 unsigned long transfers;
61 unsigned long timedout;
63 unsigned long spi_sync;
64 unsigned long spi_sync_immediate;
65 unsigned long spi_async;
67 unsigned long long bytes;
68 unsigned long long bytes_rx;
69 unsigned long long bytes_tx;
71 #define SPI_STATISTICS_HISTO_SIZE 17
72 unsigned long transfer_bytes_histo[SPI_STATISTICS_HISTO_SIZE];
74 unsigned long transfers_split_maxsize;
77 void spi_statistics_add_transfer_stats(struct spi_statistics *stats,
78 struct spi_transfer *xfer,
79 struct spi_controller *ctlr);
81 #define SPI_STATISTICS_ADD_TO_FIELD(stats, field, count) \
83 unsigned long flags; \
84 spin_lock_irqsave(&(stats)->lock, flags); \
85 (stats)->field += count; \
86 spin_unlock_irqrestore(&(stats)->lock, flags); \
89 #define SPI_STATISTICS_INCREMENT_FIELD(stats, field) \
90 SPI_STATISTICS_ADD_TO_FIELD(stats, field, 1)
93 * struct spi_device - Controller side proxy for an SPI slave device
94 * @dev: Driver model representation of the device.
95 * @controller: SPI controller used with the device.
96 * @master: Copy of controller, for backwards compatibility.
97 * @max_speed_hz: Maximum clock rate to be used with this chip
98 * (on this board); may be changed by the device's driver.
99 * The spi_transfer.speed_hz can override this for each transfer.
100 * @chip_select: Chipselect, distinguishing chips handled by @controller.
101 * @mode: The spi mode defines how data is clocked out and in.
102 * This may be changed by the device's driver.
103 * The "active low" default for chipselect mode can be overridden
104 * (by specifying SPI_CS_HIGH) as can the "MSB first" default for
105 * each word in a transfer (by specifying SPI_LSB_FIRST).
106 * @bits_per_word: Data transfers involve one or more words; word sizes
107 * like eight or 12 bits are common. In-memory wordsizes are
108 * powers of two bytes (e.g. 20 bit samples use 32 bits).
109 * This may be changed by the device's driver, or left at the
110 * default (0) indicating protocol words are eight bit bytes.
111 * The spi_transfer.bits_per_word can override this for each transfer.
112 * @rt: Make the pump thread real time priority.
113 * @irq: Negative, or the number passed to request_irq() to receive
114 * interrupts from this device.
115 * @controller_state: Controller's runtime state
116 * @controller_data: Board-specific definitions for controller, such as
117 * FIFO initialization parameters; from board_info.controller_data
118 * @modalias: Name of the driver to use with this device, or an alias
119 * for that name. This appears in the sysfs "modalias" attribute
120 * for driver coldplugging, and in uevents used for hotplugging
121 * @cs_gpio: LEGACY: gpio number of the chipselect line (optional, -ENOENT when
122 * not using a GPIO line) use cs_gpiod in new drivers by opting in on
124 * @cs_gpiod: gpio descriptor of the chipselect line (optional, NULL when
125 * not using a GPIO line)
126 * @word_delay_usecs: microsecond delay to be inserted between consecutive
127 * words of a transfer
129 * @statistics: statistics for the spi_device
131 * A @spi_device is used to interchange data between an SPI slave
132 * (usually a discrete chip) and CPU memory.
134 * In @dev, the platform_data is used to hold information about this
135 * device that's meaningful to the device's protocol driver, but not
136 * to its controller. One example might be an identifier for a chip
137 * variant with slightly different functionality; another might be
138 * information about how this particular board wires the chip's pins.
142 struct spi_controller *controller;
143 struct spi_controller *master; /* compatibility layer */
149 #define SPI_CPHA 0x01 /* clock phase */
150 #define SPI_CPOL 0x02 /* clock polarity */
151 #define SPI_MODE_0 (0|0) /* (original MicroWire) */
152 #define SPI_MODE_1 (0|SPI_CPHA)
153 #define SPI_MODE_2 (SPI_CPOL|0)
154 #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
155 #define SPI_CS_HIGH 0x04 /* chipselect active high? */
156 #define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
157 #define SPI_3WIRE 0x10 /* SI/SO signals shared */
158 #define SPI_LOOP 0x20 /* loopback mode */
159 #define SPI_NO_CS 0x40 /* 1 dev/bus, no chipselect */
160 #define SPI_READY 0x80 /* slave pulls low to pause */
161 #define SPI_TX_DUAL 0x100 /* transmit with 2 wires */
162 #define SPI_TX_QUAD 0x200 /* transmit with 4 wires */
163 #define SPI_RX_DUAL 0x400 /* receive with 2 wires */
164 #define SPI_RX_QUAD 0x800 /* receive with 4 wires */
165 #define SPI_CS_WORD 0x1000 /* toggle cs after each word */
166 #define SPI_TX_OCTAL 0x2000 /* transmit with 8 wires */
167 #define SPI_RX_OCTAL 0x4000 /* receive with 8 wires */
168 #define SPI_3WIRE_HIZ 0x8000 /* high impedance turnaround */
170 void *controller_state;
171 void *controller_data;
172 char modalias[SPI_NAME_SIZE];
173 const char *driver_override;
174 int cs_gpio; /* LEGACY: chip select gpio */
175 struct gpio_desc *cs_gpiod; /* chip select gpio desc */
176 uint8_t word_delay_usecs; /* inter-word delay */
179 struct spi_statistics statistics;
182 * likely need more hooks for more protocol options affecting how
183 * the controller talks to each chip, like:
184 * - memory packing (12 bit samples into low bits, others zeroed)
186 * - chipselect delays
191 static inline struct spi_device *to_spi_device(struct device *dev)
193 return dev ? container_of(dev, struct spi_device, dev) : NULL;
196 /* most drivers won't need to care about device refcounting */
197 static inline struct spi_device *spi_dev_get(struct spi_device *spi)
199 return (spi && get_device(&spi->dev)) ? spi : NULL;
202 static inline void spi_dev_put(struct spi_device *spi)
205 put_device(&spi->dev);
208 /* ctldata is for the bus_controller driver's runtime state */
209 static inline void *spi_get_ctldata(struct spi_device *spi)
211 return spi->controller_state;
214 static inline void spi_set_ctldata(struct spi_device *spi, void *state)
216 spi->controller_state = state;
219 /* device driver data */
221 static inline void spi_set_drvdata(struct spi_device *spi, void *data)
223 dev_set_drvdata(&spi->dev, data);
226 static inline void *spi_get_drvdata(struct spi_device *spi)
228 return dev_get_drvdata(&spi->dev);
235 * struct spi_driver - Host side "protocol" driver
236 * @id_table: List of SPI devices supported by this driver
237 * @probe: Binds this driver to the spi device. Drivers can verify
238 * that the device is actually present, and may need to configure
239 * characteristics (such as bits_per_word) which weren't needed for
240 * the initial configuration done during system setup.
241 * @remove: Unbinds this driver from the spi device
242 * @shutdown: Standard shutdown callback used during system state
243 * transitions such as powerdown/halt and kexec
244 * @driver: SPI device drivers should initialize the name and owner
245 * field of this structure.
247 * This represents the kind of device driver that uses SPI messages to
248 * interact with the hardware at the other end of a SPI link. It's called
249 * a "protocol" driver because it works through messages rather than talking
250 * directly to SPI hardware (which is what the underlying SPI controller
251 * driver does to pass those messages). These protocols are defined in the
252 * specification for the device(s) supported by the driver.
254 * As a rule, those device protocols represent the lowest level interface
255 * supported by a driver, and it will support upper level interfaces too.
256 * Examples of such upper levels include frameworks like MTD, networking,
257 * MMC, RTC, filesystem character device nodes, and hardware monitoring.
260 const struct spi_device_id *id_table;
261 int (*probe)(struct spi_device *spi);
262 int (*remove)(struct spi_device *spi);
263 void (*shutdown)(struct spi_device *spi);
264 struct device_driver driver;
267 static inline struct spi_driver *to_spi_driver(struct device_driver *drv)
269 return drv ? container_of(drv, struct spi_driver, driver) : NULL;
272 extern int __spi_register_driver(struct module *owner, struct spi_driver *sdrv);
275 * spi_unregister_driver - reverse effect of spi_register_driver
276 * @sdrv: the driver to unregister
279 static inline void spi_unregister_driver(struct spi_driver *sdrv)
282 driver_unregister(&sdrv->driver);
285 /* use a define to avoid include chaining to get THIS_MODULE */
286 #define spi_register_driver(driver) \
287 __spi_register_driver(THIS_MODULE, driver)
290 * module_spi_driver() - Helper macro for registering a SPI driver
291 * @__spi_driver: spi_driver struct
293 * Helper macro for SPI drivers which do not do anything special in module
294 * init/exit. This eliminates a lot of boilerplate. Each module may only
295 * use this macro once, and calling it replaces module_init() and module_exit()
297 #define module_spi_driver(__spi_driver) \
298 module_driver(__spi_driver, spi_register_driver, \
299 spi_unregister_driver)
302 * struct spi_controller - interface to SPI master or slave controller
303 * @dev: device interface to this driver
304 * @list: link with the global spi_controller list
305 * @bus_num: board-specific (and often SOC-specific) identifier for a
306 * given SPI controller.
307 * @num_chipselect: chipselects are used to distinguish individual
308 * SPI slaves, and are numbered from zero to num_chipselects.
309 * each slave has a chipselect signal, but it's common that not
310 * every chipselect is connected to a slave.
311 * @dma_alignment: SPI controller constraint on DMA buffers alignment.
312 * @mode_bits: flags understood by this controller driver
313 * @bits_per_word_mask: A mask indicating which values of bits_per_word are
314 * supported by the driver. Bit n indicates that a bits_per_word n+1 is
315 * supported. If set, the SPI core will reject any transfer with an
316 * unsupported bits_per_word. If not set, this value is simply ignored,
317 * and it's up to the individual driver to perform any validation.
318 * @min_speed_hz: Lowest supported transfer speed
319 * @max_speed_hz: Highest supported transfer speed
320 * @flags: other constraints relevant to this driver
321 * @slave: indicates that this is an SPI slave controller
322 * @max_transfer_size: function that returns the max transfer size for
323 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used.
324 * @max_message_size: function that returns the max message size for
325 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used.
326 * @io_mutex: mutex for physical bus access
327 * @bus_lock_spinlock: spinlock for SPI bus locking
328 * @bus_lock_mutex: mutex for exclusion of multiple callers
329 * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use
330 * @setup: updates the device mode and clocking records used by a
331 * device's SPI controller; protocol code may call this. This
332 * must fail if an unrecognized or unsupported mode is requested.
333 * It's always safe to call this unless transfers are pending on
334 * the device whose settings are being modified.
335 * @set_cs_timing: optional hook for SPI devices to request SPI master
336 * controller for configuring specific CS setup time, hold time and inactive
337 * delay interms of clock counts
338 * @transfer: adds a message to the controller's transfer queue.
339 * @cleanup: frees controller-specific state
340 * @can_dma: determine whether this controller supports DMA
341 * @queued: whether this controller is providing an internal message queue
342 * @kworker: thread struct for message pump
343 * @kworker_task: pointer to task for message pump kworker thread
344 * @pump_messages: work struct for scheduling work to the message pump
345 * @queue_lock: spinlock to syncronise access to message queue
346 * @queue: message queue
347 * @idling: the device is entering idle state
348 * @cur_msg: the currently in-flight message
349 * @cur_msg_prepared: spi_prepare_message was called for the currently
351 * @cur_msg_mapped: message has been mapped for DMA
352 * @xfer_completion: used by core transfer_one_message()
353 * @busy: message pump is busy
354 * @running: message pump is running
355 * @rt: whether this queue is set to run as a realtime task
356 * @auto_runtime_pm: the core should ensure a runtime PM reference is held
357 * while the hardware is prepared, using the parent
358 * device for the spidev
359 * @max_dma_len: Maximum length of a DMA transfer for the device.
360 * @prepare_transfer_hardware: a message will soon arrive from the queue
361 * so the subsystem requests the driver to prepare the transfer hardware
362 * by issuing this call
363 * @transfer_one_message: the subsystem calls the driver to transfer a single
364 * message while queuing transfers that arrive in the meantime. When the
365 * driver is finished with this message, it must call
366 * spi_finalize_current_message() so the subsystem can issue the next
368 * @unprepare_transfer_hardware: there are currently no more messages on the
369 * queue so the subsystem notifies the driver that it may relax the
370 * hardware by issuing this call
372 * @set_cs: set the logic level of the chip select line. May be called
373 * from interrupt context.
374 * @prepare_message: set up the controller to transfer a single message,
375 * for example doing DMA mapping. Called from threaded
377 * @transfer_one: transfer a single spi_transfer.
378 * - return 0 if the transfer is finished,
379 * - return 1 if the transfer is still in progress. When
380 * the driver is finished with this transfer it must
381 * call spi_finalize_current_transfer() so the subsystem
382 * can issue the next transfer. Note: transfer_one and
383 * transfer_one_message are mutually exclusive; when both
384 * are set, the generic subsystem does not call your
385 * transfer_one callback.
386 * @handle_err: the subsystem calls the driver to handle an error that occurs
387 * in the generic implementation of transfer_one_message().
388 * @mem_ops: optimized/dedicated operations for interactions with SPI memory.
389 * This field is optional and should only be implemented if the
390 * controller has native support for memory like operations.
391 * @unprepare_message: undo any work done by prepare_message().
392 * @slave_abort: abort the ongoing transfer request on an SPI slave controller
393 * @cs_gpios: LEGACY: array of GPIO descs to use as chip select lines; one per
394 * CS number. Any individual value may be -ENOENT for CS lines that
395 * are not GPIOs (driven by the SPI controller itself). Use the cs_gpiods
397 * @cs_gpiods: Array of GPIO descs to use as chip select lines; one per CS
398 * number. Any individual value may be NULL for CS lines that
399 * are not GPIOs (driven by the SPI controller itself).
400 * @use_gpio_descriptors: Turns on the code in the SPI core to parse and grab
401 * GPIO descriptors rather than using global GPIO numbers grabbed by the
402 * driver. This will fill in @cs_gpiods and @cs_gpios should not be used,
403 * and SPI devices will have the cs_gpiod assigned rather than cs_gpio.
404 * @statistics: statistics for the spi_controller
405 * @dma_tx: DMA transmit channel
406 * @dma_rx: DMA receive channel
407 * @dummy_rx: dummy receive buffer for full-duplex devices
408 * @dummy_tx: dummy transmit buffer for full-duplex devices
409 * @fw_translate_cs: If the boot firmware uses different numbering scheme
410 * what Linux expects, this optional hook can be used to translate
413 * Each SPI controller can communicate with one or more @spi_device
414 * children. These make a small bus, sharing MOSI, MISO and SCK signals
415 * but not chip select signals. Each device may be configured to use a
416 * different clock rate, since those shared signals are ignored unless
417 * the chip is selected.
419 * The driver for an SPI controller manages access to those devices through
420 * a queue of spi_message transactions, copying data between CPU memory and
421 * an SPI slave device. For each such message it queues, it calls the
422 * message's completion function when the transaction completes.
424 struct spi_controller {
427 struct list_head list;
429 /* other than negative (== assign one dynamically), bus_num is fully
430 * board-specific. usually that simplifies to being SOC-specific.
431 * example: one SOC has three SPI controllers, numbered 0..2,
432 * and one board's schematics might show it using SPI-2. software
433 * would normally use bus_num=2 for that controller.
437 /* chipselects will be integral to many controllers; some others
438 * might use board-specific GPIOs.
442 /* some SPI controllers pose alignment requirements on DMAable
443 * buffers; let protocol drivers know about these requirements.
447 /* spi_device.mode flags understood by this controller driver */
450 /* bitmask of supported bits_per_word for transfers */
451 u32 bits_per_word_mask;
452 #define SPI_BPW_MASK(bits) BIT((bits) - 1)
453 #define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1)
455 /* limits on transfer speed */
459 /* other constraints relevant to this driver */
461 #define SPI_CONTROLLER_HALF_DUPLEX BIT(0) /* can't do full duplex */
462 #define SPI_CONTROLLER_NO_RX BIT(1) /* can't do buffer read */
463 #define SPI_CONTROLLER_NO_TX BIT(2) /* can't do buffer write */
464 #define SPI_CONTROLLER_MUST_RX BIT(3) /* requires rx */
465 #define SPI_CONTROLLER_MUST_TX BIT(4) /* requires tx */
467 #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must select slave */
469 /* flag indicating this is a non-devres managed controller */
472 /* flag indicating this is an SPI slave controller */
476 * on some hardware transfer / message size may be constrained
477 * the limit may depend on device transfer settings
479 size_t (*max_transfer_size)(struct spi_device *spi);
480 size_t (*max_message_size)(struct spi_device *spi);
483 struct mutex io_mutex;
485 /* lock and mutex for SPI bus locking */
486 spinlock_t bus_lock_spinlock;
487 struct mutex bus_lock_mutex;
489 /* flag indicating that the SPI bus is locked for exclusive use */
492 /* Setup mode and clock, etc (spi driver may call many times).
494 * IMPORTANT: this may be called when transfers to another
495 * device are active. DO NOT UPDATE SHARED REGISTERS in ways
496 * which could break those transfers.
498 int (*setup)(struct spi_device *spi);
501 * set_cs_timing() method is for SPI controllers that supports
502 * configuring CS timing.
504 * This hook allows SPI client drivers to request SPI controllers
505 * to configure specific CS timing through spi_set_cs_timing() after
508 void (*set_cs_timing)(struct spi_device *spi, u8 setup_clk_cycles,
509 u8 hold_clk_cycles, u8 inactive_clk_cycles);
511 /* bidirectional bulk transfers
513 * + The transfer() method may not sleep; its main role is
514 * just to add the message to the queue.
515 * + For now there's no remove-from-queue operation, or
516 * any other request management
517 * + To a given spi_device, message queueing is pure fifo
519 * + The controller's main job is to process its message queue,
520 * selecting a chip (for masters), then transferring data
521 * + If there are multiple spi_device children, the i/o queue
522 * arbitration algorithm is unspecified (round robin, fifo,
523 * priority, reservations, preemption, etc)
525 * + Chipselect stays active during the entire message
526 * (unless modified by spi_transfer.cs_change != 0).
527 * + The message transfers use clock and SPI mode parameters
528 * previously established by setup() for this device
530 int (*transfer)(struct spi_device *spi,
531 struct spi_message *mesg);
533 /* called on release() to free memory provided by spi_controller */
534 void (*cleanup)(struct spi_device *spi);
537 * Used to enable core support for DMA handling, if can_dma()
538 * exists and returns true then the transfer will be mapped
539 * prior to transfer_one() being called. The driver should
540 * not modify or store xfer and dma_tx and dma_rx must be set
541 * while the device is prepared.
543 bool (*can_dma)(struct spi_controller *ctlr,
544 struct spi_device *spi,
545 struct spi_transfer *xfer);
548 * These hooks are for drivers that want to use the generic
549 * controller transfer queueing mechanism. If these are used, the
550 * transfer() function above must NOT be specified by the driver.
551 * Over time we expect SPI drivers to be phased over to this API.
554 struct kthread_worker kworker;
555 struct task_struct *kworker_task;
556 struct kthread_work pump_messages;
557 spinlock_t queue_lock;
558 struct list_head queue;
559 struct spi_message *cur_msg;
564 bool auto_runtime_pm;
565 bool cur_msg_prepared;
567 struct completion xfer_completion;
570 int (*prepare_transfer_hardware)(struct spi_controller *ctlr);
571 int (*transfer_one_message)(struct spi_controller *ctlr,
572 struct spi_message *mesg);
573 int (*unprepare_transfer_hardware)(struct spi_controller *ctlr);
574 int (*prepare_message)(struct spi_controller *ctlr,
575 struct spi_message *message);
576 int (*unprepare_message)(struct spi_controller *ctlr,
577 struct spi_message *message);
578 int (*slave_abort)(struct spi_controller *ctlr);
581 * These hooks are for drivers that use a generic implementation
582 * of transfer_one_message() provied by the core.
584 void (*set_cs)(struct spi_device *spi, bool enable);
585 int (*transfer_one)(struct spi_controller *ctlr, struct spi_device *spi,
586 struct spi_transfer *transfer);
587 void (*handle_err)(struct spi_controller *ctlr,
588 struct spi_message *message);
590 /* Optimized handlers for SPI memory-like operations. */
591 const struct spi_controller_mem_ops *mem_ops;
593 /* gpio chip select */
595 struct gpio_desc **cs_gpiods;
596 bool use_gpio_descriptors;
599 struct spi_statistics statistics;
601 /* DMA channels for use with core dmaengine helpers */
602 struct dma_chan *dma_tx;
603 struct dma_chan *dma_rx;
605 /* dummy data for full duplex devices */
609 int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs);
612 static inline void *spi_controller_get_devdata(struct spi_controller *ctlr)
614 return dev_get_drvdata(&ctlr->dev);
617 static inline void spi_controller_set_devdata(struct spi_controller *ctlr,
620 dev_set_drvdata(&ctlr->dev, data);
623 static inline struct spi_controller *spi_controller_get(struct spi_controller *ctlr)
625 if (!ctlr || !get_device(&ctlr->dev))
630 static inline void spi_controller_put(struct spi_controller *ctlr)
633 put_device(&ctlr->dev);
636 static inline bool spi_controller_is_slave(struct spi_controller *ctlr)
638 return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->slave;
641 /* PM calls that need to be issued by the driver */
642 extern int spi_controller_suspend(struct spi_controller *ctlr);
643 extern int spi_controller_resume(struct spi_controller *ctlr);
645 /* Calls the driver make to interact with the message queue */
646 extern struct spi_message *spi_get_next_queued_message(struct spi_controller *ctlr);
647 extern void spi_finalize_current_message(struct spi_controller *ctlr);
648 extern void spi_finalize_current_transfer(struct spi_controller *ctlr);
650 /* the spi driver core manages memory for the spi_controller classdev */
651 extern struct spi_controller *__spi_alloc_controller(struct device *host,
652 unsigned int size, bool slave);
654 static inline struct spi_controller *spi_alloc_master(struct device *host,
657 return __spi_alloc_controller(host, size, false);
660 static inline struct spi_controller *spi_alloc_slave(struct device *host,
663 if (!IS_ENABLED(CONFIG_SPI_SLAVE))
666 return __spi_alloc_controller(host, size, true);
669 struct spi_controller *__devm_spi_alloc_controller(struct device *dev,
673 static inline struct spi_controller *devm_spi_alloc_master(struct device *dev,
676 return __devm_spi_alloc_controller(dev, size, false);
679 static inline struct spi_controller *devm_spi_alloc_slave(struct device *dev,
682 if (!IS_ENABLED(CONFIG_SPI_SLAVE))
685 return __devm_spi_alloc_controller(dev, size, true);
688 extern int spi_register_controller(struct spi_controller *ctlr);
689 extern int devm_spi_register_controller(struct device *dev,
690 struct spi_controller *ctlr);
691 extern void spi_unregister_controller(struct spi_controller *ctlr);
693 extern struct spi_controller *spi_busnum_to_master(u16 busnum);
696 * SPI resource management while processing a SPI message
699 typedef void (*spi_res_release_t)(struct spi_controller *ctlr,
700 struct spi_message *msg,
704 * struct spi_res - spi resource management structure
706 * @release: release code called prior to freeing this resource
707 * @data: extra data allocated for the specific use-case
709 * this is based on ideas from devres, but focused on life-cycle
710 * management during spi_message processing
713 struct list_head entry;
714 spi_res_release_t release;
715 unsigned long long data[]; /* guarantee ull alignment */
718 extern void *spi_res_alloc(struct spi_device *spi,
719 spi_res_release_t release,
720 size_t size, gfp_t gfp);
721 extern void spi_res_add(struct spi_message *message, void *res);
722 extern void spi_res_free(void *res);
724 extern void spi_res_release(struct spi_controller *ctlr,
725 struct spi_message *message);
727 /*---------------------------------------------------------------------------*/
730 * I/O INTERFACE between SPI controller and protocol drivers
732 * Protocol drivers use a queue of spi_messages, each transferring data
733 * between the controller and memory buffers.
735 * The spi_messages themselves consist of a series of read+write transfer
736 * segments. Those segments always read the same number of bits as they
737 * write; but one or the other is easily ignored by passing a null buffer
738 * pointer. (This is unlike most types of I/O API, because SPI hardware
741 * NOTE: Allocation of spi_transfer and spi_message memory is entirely
742 * up to the protocol driver, which guarantees the integrity of both (as
743 * well as the data buffers) for as long as the message is queued.
747 * struct spi_transfer - a read/write buffer pair
748 * @tx_buf: data to be written (dma-safe memory), or NULL
749 * @rx_buf: data to be read (dma-safe memory), or NULL
750 * @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped
751 * @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped
752 * @tx_nbits: number of bits used for writing. If 0 the default
753 * (SPI_NBITS_SINGLE) is used.
754 * @rx_nbits: number of bits used for reading. If 0 the default
755 * (SPI_NBITS_SINGLE) is used.
756 * @len: size of rx and tx buffers (in bytes)
757 * @speed_hz: Select a speed other than the device default for this
758 * transfer. If 0 the default (from @spi_device) is used.
759 * @bits_per_word: select a bits_per_word other than the device default
760 * for this transfer. If 0 the default (from @spi_device) is used.
761 * @cs_change: affects chipselect after this transfer completes
762 * @cs_change_delay: delay between cs deassert and assert when
763 * @cs_change is set and @spi_transfer is not the last in @spi_message
764 * @cs_change_delay_unit: unit of cs_change_delay
765 * @delay_usecs: microseconds to delay after this transfer before
766 * (optionally) changing the chipselect status, then starting
767 * the next transfer or completing this @spi_message.
768 * @word_delay_usecs: microseconds to inter word delay after each word size
769 * (set by bits_per_word) transmission.
770 * @word_delay: clock cycles to inter word delay after each word size
771 * (set by bits_per_word) transmission.
772 * @effective_speed_hz: the effective SCK-speed that was used to
773 * transfer this transfer. Set to 0 if the spi bus driver does
775 * @transfer_list: transfers are sequenced through @spi_message.transfers
776 * @tx_sg: Scatterlist for transmit, currently not for client use
777 * @rx_sg: Scatterlist for receive, currently not for client use
779 * SPI transfers always write the same number of bytes as they read.
780 * Protocol drivers should always provide @rx_buf and/or @tx_buf.
781 * In some cases, they may also want to provide DMA addresses for
782 * the data being transferred; that may reduce overhead, when the
783 * underlying driver uses dma.
785 * If the transmit buffer is null, zeroes will be shifted out
786 * while filling @rx_buf. If the receive buffer is null, the data
787 * shifted in will be discarded. Only "len" bytes shift out (or in).
788 * It's an error to try to shift out a partial word. (For example, by
789 * shifting out three bytes with word size of sixteen or twenty bits;
790 * the former uses two bytes per word, the latter uses four bytes.)
792 * In-memory data values are always in native CPU byte order, translated
793 * from the wire byte order (big-endian except with SPI_LSB_FIRST). So
794 * for example when bits_per_word is sixteen, buffers are 2N bytes long
795 * (@len = 2N) and hold N sixteen bit words in CPU byte order.
797 * When the word size of the SPI transfer is not a power-of-two multiple
798 * of eight bits, those in-memory words include extra bits. In-memory
799 * words are always seen by protocol drivers as right-justified, so the
800 * undefined (rx) or unused (tx) bits are always the most significant bits.
802 * All SPI transfers start with the relevant chipselect active. Normally
803 * it stays selected until after the last transfer in a message. Drivers
804 * can affect the chipselect signal using cs_change.
806 * (i) If the transfer isn't the last one in the message, this flag is
807 * used to make the chipselect briefly go inactive in the middle of the
808 * message. Toggling chipselect in this way may be needed to terminate
809 * a chip command, letting a single spi_message perform all of group of
810 * chip transactions together.
812 * (ii) When the transfer is the last one in the message, the chip may
813 * stay selected until the next transfer. On multi-device SPI busses
814 * with nothing blocking messages going to other devices, this is just
815 * a performance hint; starting a message to another device deselects
816 * this one. But in other cases, this can be used to ensure correctness.
817 * Some devices need protocol transactions to be built from a series of
818 * spi_message submissions, where the content of one message is determined
819 * by the results of previous messages and where the whole transaction
820 * ends when the chipselect goes intactive.
822 * When SPI can transfer in 1x,2x or 4x. It can get this transfer information
823 * from device through @tx_nbits and @rx_nbits. In Bi-direction, these
824 * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x)
825 * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer.
827 * The code that submits an spi_message (and its spi_transfers)
828 * to the lower layers is responsible for managing its memory.
829 * Zero-initialize every field you don't set up explicitly, to
830 * insulate against future API updates. After you submit a message
831 * and its transfers, ignore them until its completion callback.
833 struct spi_transfer {
834 /* it's ok if tx_buf == rx_buf (right?)
835 * for MicroWire, one buffer must be null
836 * buffers must work with dma_*map_single() calls, unless
837 * spi_message.is_dma_mapped reports a pre-existing mapping
845 struct sg_table tx_sg;
846 struct sg_table rx_sg;
848 unsigned cs_change:1;
851 #define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */
852 #define SPI_NBITS_DUAL 0x02 /* 2bits transfer */
853 #define SPI_NBITS_QUAD 0x04 /* 4bits transfer */
858 u8 cs_change_delay_unit;
859 #define SPI_DELAY_UNIT_USECS 0
860 #define SPI_DELAY_UNIT_NSECS 1
861 #define SPI_DELAY_UNIT_SCK 2
865 u32 effective_speed_hz;
867 struct list_head transfer_list;
871 * struct spi_message - one multi-segment SPI transaction
872 * @transfers: list of transfer segments in this transaction
873 * @spi: SPI device to which the transaction is queued
874 * @is_dma_mapped: if true, the caller provided both dma and cpu virtual
875 * addresses for each transfer buffer
876 * @complete: called to report transaction completions
877 * @context: the argument to complete() when it's called
878 * @frame_length: the total number of bytes in the message
879 * @actual_length: the total number of bytes that were transferred in all
880 * successful segments
881 * @status: zero for success, else negative errno
882 * @queue: for use by whichever driver currently owns the message
883 * @state: for use by whichever driver currently owns the message
884 * @resources: for resource management when the spi message is processed
886 * A @spi_message is used to execute an atomic sequence of data transfers,
887 * each represented by a struct spi_transfer. The sequence is "atomic"
888 * in the sense that no other spi_message may use that SPI bus until that
889 * sequence completes. On some systems, many such sequences can execute as
890 * as single programmed DMA transfer. On all systems, these messages are
891 * queued, and might complete after transactions to other devices. Messages
892 * sent to a given spi_device are always executed in FIFO order.
894 * The code that submits an spi_message (and its spi_transfers)
895 * to the lower layers is responsible for managing its memory.
896 * Zero-initialize every field you don't set up explicitly, to
897 * insulate against future API updates. After you submit a message
898 * and its transfers, ignore them until its completion callback.
901 struct list_head transfers;
903 struct spi_device *spi;
905 unsigned is_dma_mapped:1;
907 /* REVISIT: we might want a flag affecting the behavior of the
908 * last transfer ... allowing things like "read 16 bit length L"
909 * immediately followed by "read L bytes". Basically imposing
910 * a specific message scheduling algorithm.
912 * Some controller drivers (message-at-a-time queue processing)
913 * could provide that as their default scheduling algorithm. But
914 * others (with multi-message pipelines) could need a flag to
915 * tell them about such special cases.
918 /* completion is reported through a callback */
919 void (*complete)(void *context);
921 unsigned frame_length;
922 unsigned actual_length;
925 /* for optional use by whatever driver currently owns the
926 * spi_message ... between calls to spi_async and then later
927 * complete(), that's the spi_controller controller driver.
929 struct list_head queue;
932 /* list of spi_res reources when the spi message is processed */
933 struct list_head resources;
936 static inline void spi_message_init_no_memset(struct spi_message *m)
938 INIT_LIST_HEAD(&m->transfers);
939 INIT_LIST_HEAD(&m->resources);
942 static inline void spi_message_init(struct spi_message *m)
944 memset(m, 0, sizeof *m);
945 spi_message_init_no_memset(m);
949 spi_message_add_tail(struct spi_transfer *t, struct spi_message *m)
951 list_add_tail(&t->transfer_list, &m->transfers);
955 spi_transfer_del(struct spi_transfer *t)
957 list_del(&t->transfer_list);
961 * spi_message_init_with_transfers - Initialize spi_message and append transfers
962 * @m: spi_message to be initialized
963 * @xfers: An array of spi transfers
964 * @num_xfers: Number of items in the xfer array
966 * This function initializes the given spi_message and adds each spi_transfer in
967 * the given array to the message.
970 spi_message_init_with_transfers(struct spi_message *m,
971 struct spi_transfer *xfers, unsigned int num_xfers)
976 for (i = 0; i < num_xfers; ++i)
977 spi_message_add_tail(&xfers[i], m);
980 /* It's fine to embed message and transaction structures in other data
981 * structures so long as you don't free them while they're in use.
984 static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags)
986 struct spi_message *m;
988 m = kzalloc(sizeof(struct spi_message)
989 + ntrans * sizeof(struct spi_transfer),
993 struct spi_transfer *t = (struct spi_transfer *)(m + 1);
995 spi_message_init_no_memset(m);
996 for (i = 0; i < ntrans; i++, t++)
997 spi_message_add_tail(t, m);
1002 static inline void spi_message_free(struct spi_message *m)
1007 extern void spi_set_cs_timing(struct spi_device *spi, u8 setup, u8 hold, u8 inactive_dly);
1009 extern int spi_setup(struct spi_device *spi);
1010 extern int spi_async(struct spi_device *spi, struct spi_message *message);
1011 extern int spi_async_locked(struct spi_device *spi,
1012 struct spi_message *message);
1013 extern int spi_slave_abort(struct spi_device *spi);
1015 static inline size_t
1016 spi_max_message_size(struct spi_device *spi)
1018 struct spi_controller *ctlr = spi->controller;
1020 if (!ctlr->max_message_size)
1022 return ctlr->max_message_size(spi);
1025 static inline size_t
1026 spi_max_transfer_size(struct spi_device *spi)
1028 struct spi_controller *ctlr = spi->controller;
1029 size_t tr_max = SIZE_MAX;
1030 size_t msg_max = spi_max_message_size(spi);
1032 if (ctlr->max_transfer_size)
1033 tr_max = ctlr->max_transfer_size(spi);
1035 /* transfer size limit must not be greater than messsage size limit */
1036 return min(tr_max, msg_max);
1040 * spi_is_bpw_supported - Check if bits per word is supported
1042 * @bpw: Bits per word
1044 * This function checks to see if the SPI controller supports @bpw.
1047 * True if @bpw is supported, false otherwise.
1049 static inline bool spi_is_bpw_supported(struct spi_device *spi, u32 bpw)
1051 u32 bpw_mask = spi->master->bits_per_word_mask;
1053 if (bpw == 8 || (bpw <= 32 && bpw_mask & SPI_BPW_MASK(bpw)))
1059 /*---------------------------------------------------------------------------*/
1061 /* SPI transfer replacement methods which make use of spi_res */
1063 struct spi_replaced_transfers;
1064 typedef void (*spi_replaced_release_t)(struct spi_controller *ctlr,
1065 struct spi_message *msg,
1066 struct spi_replaced_transfers *res);
1068 * struct spi_replaced_transfers - structure describing the spi_transfer
1069 * replacements that have occurred
1070 * so that they can get reverted
1071 * @release: some extra release code to get executed prior to
1072 * relasing this structure
1073 * @extradata: pointer to some extra data if requested or NULL
1074 * @replaced_transfers: transfers that have been replaced and which need
1076 * @replaced_after: the transfer after which the @replaced_transfers
1077 * are to get re-inserted
1078 * @inserted: number of transfers inserted
1079 * @inserted_transfers: array of spi_transfers of array-size @inserted,
1080 * that have been replacing replaced_transfers
1082 * note: that @extradata will point to @inserted_transfers[@inserted]
1083 * if some extra allocation is requested, so alignment will be the same
1084 * as for spi_transfers
1086 struct spi_replaced_transfers {
1087 spi_replaced_release_t release;
1089 struct list_head replaced_transfers;
1090 struct list_head *replaced_after;
1092 struct spi_transfer inserted_transfers[];
1095 extern struct spi_replaced_transfers *spi_replace_transfers(
1096 struct spi_message *msg,
1097 struct spi_transfer *xfer_first,
1100 spi_replaced_release_t release,
1101 size_t extradatasize,
1104 /*---------------------------------------------------------------------------*/
1106 /* SPI transfer transformation methods */
1108 extern int spi_split_transfers_maxsize(struct spi_controller *ctlr,
1109 struct spi_message *msg,
1113 /*---------------------------------------------------------------------------*/
1115 /* All these synchronous SPI transfer routines are utilities layered
1116 * over the core async transfer primitive. Here, "synchronous" means
1117 * they will sleep uninterruptibly until the async transfer completes.
1120 extern int spi_sync(struct spi_device *spi, struct spi_message *message);
1121 extern int spi_sync_locked(struct spi_device *spi, struct spi_message *message);
1122 extern int spi_bus_lock(struct spi_controller *ctlr);
1123 extern int spi_bus_unlock(struct spi_controller *ctlr);
1126 * spi_sync_transfer - synchronous SPI data transfer
1127 * @spi: device with which data will be exchanged
1128 * @xfers: An array of spi_transfers
1129 * @num_xfers: Number of items in the xfer array
1130 * Context: can sleep
1132 * Does a synchronous SPI data transfer of the given spi_transfer array.
1134 * For more specific semantics see spi_sync().
1136 * Return: Return: zero on success, else a negative error code.
1139 spi_sync_transfer(struct spi_device *spi, struct spi_transfer *xfers,
1140 unsigned int num_xfers)
1142 struct spi_message msg;
1144 spi_message_init_with_transfers(&msg, xfers, num_xfers);
1146 return spi_sync(spi, &msg);
1150 * spi_write - SPI synchronous write
1151 * @spi: device to which data will be written
1153 * @len: data buffer size
1154 * Context: can sleep
1156 * This function writes the buffer @buf.
1157 * Callable only from contexts that can sleep.
1159 * Return: zero on success, else a negative error code.
1162 spi_write(struct spi_device *spi, const void *buf, size_t len)
1164 struct spi_transfer t = {
1169 return spi_sync_transfer(spi, &t, 1);
1173 * spi_read - SPI synchronous read
1174 * @spi: device from which data will be read
1176 * @len: data buffer size
1177 * Context: can sleep
1179 * This function reads the buffer @buf.
1180 * Callable only from contexts that can sleep.
1182 * Return: zero on success, else a negative error code.
1185 spi_read(struct spi_device *spi, void *buf, size_t len)
1187 struct spi_transfer t = {
1192 return spi_sync_transfer(spi, &t, 1);
1195 /* this copies txbuf and rxbuf data; for small transfers only! */
1196 extern int spi_write_then_read(struct spi_device *spi,
1197 const void *txbuf, unsigned n_tx,
1198 void *rxbuf, unsigned n_rx);
1201 * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read
1202 * @spi: device with which data will be exchanged
1203 * @cmd: command to be written before data is read back
1204 * Context: can sleep
1206 * Callable only from contexts that can sleep.
1208 * Return: the (unsigned) eight bit number returned by the
1209 * device, or else a negative error code.
1211 static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd)
1216 status = spi_write_then_read(spi, &cmd, 1, &result, 1);
1218 /* return negative errno or unsigned value */
1219 return (status < 0) ? status : result;
1223 * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read
1224 * @spi: device with which data will be exchanged
1225 * @cmd: command to be written before data is read back
1226 * Context: can sleep
1228 * The number is returned in wire-order, which is at least sometimes
1231 * Callable only from contexts that can sleep.
1233 * Return: the (unsigned) sixteen bit number returned by the
1234 * device, or else a negative error code.
1236 static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd)
1241 status = spi_write_then_read(spi, &cmd, 1, &result, 2);
1243 /* return negative errno or unsigned value */
1244 return (status < 0) ? status : result;
1248 * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read
1249 * @spi: device with which data will be exchanged
1250 * @cmd: command to be written before data is read back
1251 * Context: can sleep
1253 * This function is similar to spi_w8r16, with the exception that it will
1254 * convert the read 16 bit data word from big-endian to native endianness.
1256 * Callable only from contexts that can sleep.
1258 * Return: the (unsigned) sixteen bit number returned by the device in cpu
1259 * endianness, or else a negative error code.
1261 static inline ssize_t spi_w8r16be(struct spi_device *spi, u8 cmd)
1267 status = spi_write_then_read(spi, &cmd, 1, &result, 2);
1271 return be16_to_cpu(result);
1274 /*---------------------------------------------------------------------------*/
1277 * INTERFACE between board init code and SPI infrastructure.
1279 * No SPI driver ever sees these SPI device table segments, but
1280 * it's how the SPI core (or adapters that get hotplugged) grows
1281 * the driver model tree.
1283 * As a rule, SPI devices can't be probed. Instead, board init code
1284 * provides a table listing the devices which are present, with enough
1285 * information to bind and set up the device's driver. There's basic
1286 * support for nonstatic configurations too; enough to handle adding
1287 * parport adapters, or microcontrollers acting as USB-to-SPI bridges.
1291 * struct spi_board_info - board-specific template for a SPI device
1292 * @modalias: Initializes spi_device.modalias; identifies the driver.
1293 * @platform_data: Initializes spi_device.platform_data; the particular
1294 * data stored there is driver-specific.
1295 * @properties: Additional device properties for the device.
1296 * @controller_data: Initializes spi_device.controller_data; some
1297 * controllers need hints about hardware setup, e.g. for DMA.
1298 * @irq: Initializes spi_device.irq; depends on how the board is wired.
1299 * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits
1300 * from the chip datasheet and board-specific signal quality issues.
1301 * @bus_num: Identifies which spi_controller parents the spi_device; unused
1302 * by spi_new_device(), and otherwise depends on board wiring.
1303 * @chip_select: Initializes spi_device.chip_select; depends on how
1304 * the board is wired.
1305 * @mode: Initializes spi_device.mode; based on the chip datasheet, board
1306 * wiring (some devices support both 3WIRE and standard modes), and
1307 * possibly presence of an inverter in the chipselect path.
1309 * When adding new SPI devices to the device tree, these structures serve
1310 * as a partial device template. They hold information which can't always
1311 * be determined by drivers. Information that probe() can establish (such
1312 * as the default transfer wordsize) is not included here.
1314 * These structures are used in two places. Their primary role is to
1315 * be stored in tables of board-specific device descriptors, which are
1316 * declared early in board initialization and then used (much later) to
1317 * populate a controller's device tree after the that controller's driver
1318 * initializes. A secondary (and atypical) role is as a parameter to
1319 * spi_new_device() call, which happens after those controller drivers
1320 * are active in some dynamic board configuration models.
1322 struct spi_board_info {
1323 /* the device name and module name are coupled, like platform_bus;
1324 * "modalias" is normally the driver name.
1326 * platform_data goes to spi_device.dev.platform_data,
1327 * controller_data goes to spi_device.controller_data,
1328 * device properties are copied and attached to spi_device,
1331 char modalias[SPI_NAME_SIZE];
1332 const void *platform_data;
1333 const struct property_entry *properties;
1334 void *controller_data;
1337 /* slower signaling on noisy or low voltage boards */
1341 /* bus_num is board specific and matches the bus_num of some
1342 * spi_controller that will probably be registered later.
1344 * chip_select reflects how this chip is wired to that master;
1345 * it's less than num_chipselect.
1350 /* mode becomes spi_device.mode, and is essential for chips
1351 * where the default of SPI_CS_HIGH = 0 is wrong.
1355 /* ... may need additional spi_device chip config data here.
1356 * avoid stuff protocol drivers can set; but include stuff
1357 * needed to behave without being bound to a driver:
1358 * - quirks like clock rate mattering when not selected
1364 spi_register_board_info(struct spi_board_info const *info, unsigned n);
1366 /* board init code may ignore whether SPI is configured or not */
1368 spi_register_board_info(struct spi_board_info const *info, unsigned n)
1372 /* If you're hotplugging an adapter with devices (parport, usb, etc)
1373 * use spi_new_device() to describe each device. You can also call
1374 * spi_unregister_device() to start making that device vanish, but
1375 * normally that would be handled by spi_unregister_controller().
1377 * You can also use spi_alloc_device() and spi_add_device() to use a two
1378 * stage registration sequence for each spi_device. This gives the caller
1379 * some more control over the spi_device structure before it is registered,
1380 * but requires that caller to initialize fields that would otherwise
1381 * be defined using the board info.
1383 extern struct spi_device *
1384 spi_alloc_device(struct spi_controller *ctlr);
1387 spi_add_device(struct spi_device *spi);
1389 extern struct spi_device *
1390 spi_new_device(struct spi_controller *, struct spi_board_info *);
1392 extern void spi_unregister_device(struct spi_device *spi);
1394 extern const struct spi_device_id *
1395 spi_get_device_id(const struct spi_device *sdev);
1398 spi_transfer_is_last(struct spi_controller *ctlr, struct spi_transfer *xfer)
1400 return list_is_last(&xfer->transfer_list, &ctlr->cur_msg->transfers);
1403 /* OF support code */
1404 #if IS_ENABLED(CONFIG_OF)
1406 /* must call put_device() when done with returned spi_device device */
1407 extern struct spi_device *
1408 of_find_spi_device_by_node(struct device_node *node);
1412 static inline struct spi_device *
1413 of_find_spi_device_by_node(struct device_node *node)
1418 #endif /* IS_ENABLED(CONFIG_OF) */
1420 /* Compatibility layer */
1421 #define spi_master spi_controller
1423 #define SPI_MASTER_HALF_DUPLEX SPI_CONTROLLER_HALF_DUPLEX
1424 #define SPI_MASTER_NO_RX SPI_CONTROLLER_NO_RX
1425 #define SPI_MASTER_NO_TX SPI_CONTROLLER_NO_TX
1426 #define SPI_MASTER_MUST_RX SPI_CONTROLLER_MUST_RX
1427 #define SPI_MASTER_MUST_TX SPI_CONTROLLER_MUST_TX
1429 #define spi_master_get_devdata(_ctlr) spi_controller_get_devdata(_ctlr)
1430 #define spi_master_set_devdata(_ctlr, _data) \
1431 spi_controller_set_devdata(_ctlr, _data)
1432 #define spi_master_get(_ctlr) spi_controller_get(_ctlr)
1433 #define spi_master_put(_ctlr) spi_controller_put(_ctlr)
1434 #define spi_master_suspend(_ctlr) spi_controller_suspend(_ctlr)
1435 #define spi_master_resume(_ctlr) spi_controller_resume(_ctlr)
1437 #define spi_register_master(_ctlr) spi_register_controller(_ctlr)
1438 #define devm_spi_register_master(_dev, _ctlr) \
1439 devm_spi_register_controller(_dev, _ctlr)
1440 #define spi_unregister_master(_ctlr) spi_unregister_controller(_ctlr)
1442 #endif /* __LINUX_SPI_H */