1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
4 #ifndef __SDW_REGISTERS_H
5 #define __SDW_REGISTERS_H
8 * SDW registers as defined by MIPI 1.2 Spec
10 #define SDW_REGADDR GENMASK(14, 0)
11 #define SDW_SCP_ADDRPAGE2_MASK GENMASK(22, 15)
12 #define SDW_SCP_ADDRPAGE1_MASK GENMASK(30, 23)
14 #define SDW_REG_NO_PAGE 0x00008000
15 #define SDW_REG_OPTIONAL_PAGE 0x00010000
16 #define SDW_REG_MAX 0x80000000
18 #define SDW_DPN_SIZE 0x100
19 #define SDW_BANK1_OFFSET 0x10
22 * DP0 Interrupt register & bits
24 * Spec treats Status (RO) and Clear (WC) as separate but they are same
25 * address, so treat as same register with WC.
28 /* both INT and STATUS register are same */
29 #define SDW_DP0_INT 0x0
30 #define SDW_DP0_INTMASK 0x1
31 #define SDW_DP0_PORTCTRL 0x2
32 #define SDW_DP0_BLOCKCTRL1 0x3
33 #define SDW_DP0_PREPARESTATUS 0x4
34 #define SDW_DP0_PREPARECTRL 0x5
36 #define SDW_DP0_INT_TEST_FAIL BIT(0)
37 #define SDW_DP0_INT_PORT_READY BIT(1)
38 #define SDW_DP0_INT_BRA_FAILURE BIT(2)
39 #define SDW_DP0_SDCA_CASCADE BIT(3)
40 /* BIT(4) not allocated in SoundWire specification 1.2 */
41 #define SDW_DP0_INT_IMPDEF1 BIT(5)
42 #define SDW_DP0_INT_IMPDEF2 BIT(6)
43 #define SDW_DP0_INT_IMPDEF3 BIT(7)
45 #define SDW_DP0_PORTCTRL_DATAMODE GENMASK(3, 2)
46 #define SDW_DP0_PORTCTRL_NXTINVBANK BIT(4)
47 #define SDW_DP0_PORTCTRL_BPT_PAYLD GENMASK(7, 6)
49 #define SDW_DP0_CHANNELEN 0x20
50 #define SDW_DP0_SAMPLECTRL1 0x22
51 #define SDW_DP0_SAMPLECTRL2 0x23
52 #define SDW_DP0_OFFSETCTRL1 0x24
53 #define SDW_DP0_OFFSETCTRL2 0x25
54 #define SDW_DP0_HCTRL 0x26
55 #define SDW_DP0_LANECTRL 0x28
57 /* Both INT and STATUS register are same */
58 #define SDW_SCP_INT1 0x40
59 #define SDW_SCP_INTMASK1 0x41
61 #define SDW_SCP_INT1_PARITY BIT(0)
62 #define SDW_SCP_INT1_BUS_CLASH BIT(1)
63 #define SDW_SCP_INT1_IMPL_DEF BIT(2)
64 #define SDW_SCP_INT1_SCP2_CASCADE BIT(7)
65 #define SDW_SCP_INT1_PORT0_3 GENMASK(6, 3)
67 #define SDW_SCP_INTSTAT2 0x42
68 #define SDW_SCP_INTSTAT2_SCP3_CASCADE BIT(7)
69 #define SDW_SCP_INTSTAT2_PORT4_10 GENMASK(6, 0)
71 #define SDW_SCP_INTSTAT3 0x43
72 #define SDW_SCP_INTSTAT3_PORT11_14 GENMASK(3, 0)
74 /* Number of interrupt status registers */
75 #define SDW_NUM_INT_STAT_REGISTERS 3
77 /* Number of interrupt clear registers */
78 #define SDW_NUM_INT_CLEAR_REGISTERS 1
80 #define SDW_SCP_CTRL 0x44
81 #define SDW_SCP_CTRL_CLK_STP_NOW BIT(1)
82 #define SDW_SCP_CTRL_FORCE_RESET BIT(7)
84 #define SDW_SCP_STAT 0x44
85 #define SDW_SCP_STAT_CLK_STP_NF BIT(0)
86 #define SDW_SCP_STAT_HPHY_NOK BIT(5)
87 #define SDW_SCP_STAT_CURR_BANK BIT(6)
89 #define SDW_SCP_SYSTEMCTRL 0x45
90 #define SDW_SCP_SYSTEMCTRL_CLK_STP_PREP BIT(0)
91 #define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE BIT(2)
92 #define SDW_SCP_SYSTEMCTRL_WAKE_UP_EN BIT(3)
93 #define SDW_SCP_SYSTEMCTRL_HIGH_PHY BIT(4)
95 #define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE0 0
96 #define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE1 BIT(2)
98 #define SDW_SCP_DEVNUMBER 0x46
99 #define SDW_SCP_HIGH_PHY_CHECK 0x47
100 #define SDW_SCP_ADDRPAGE1 0x48
101 #define SDW_SCP_ADDRPAGE2 0x49
102 #define SDW_SCP_KEEPEREN 0x4A
103 #define SDW_SCP_BANKDELAY 0x4B
104 #define SDW_SCP_COMMIT 0x4C
106 #define SDW_SCP_BUS_CLOCK_BASE 0x4D
107 #define SDW_SCP_BASE_CLOCK_FREQ GENMASK(2, 0)
108 #define SDW_SCP_BASE_CLOCK_UNKNOWN 0x0
109 #define SDW_SCP_BASE_CLOCK_19200000_HZ 0x1
110 #define SDW_SCP_BASE_CLOCK_24000000_HZ 0x2
111 #define SDW_SCP_BASE_CLOCK_24576000_HZ 0x3
112 #define SDW_SCP_BASE_CLOCK_22579200_HZ 0x4
113 #define SDW_SCP_BASE_CLOCK_32000000_HZ 0x5
114 #define SDW_SCP_BASE_CLOCK_RESERVED 0x6
115 #define SDW_SCP_BASE_CLOCK_IMP_DEF 0x7
117 /* 0x4E is not allocated in SoundWire specification 1.2 */
118 #define SDW_SCP_TESTMODE 0x4F
119 #define SDW_SCP_DEVID_0 0x50
120 #define SDW_SCP_DEVID_1 0x51
121 #define SDW_SCP_DEVID_2 0x52
122 #define SDW_SCP_DEVID_3 0x53
123 #define SDW_SCP_DEVID_4 0x54
124 #define SDW_SCP_DEVID_5 0x55
126 /* Both INT and STATUS register are same */
127 #define SDW_SCP_SDCA_INT1 0x58
128 #define SDW_SCP_SDCA_INT_SDCA_0 BIT(0)
129 #define SDW_SCP_SDCA_INT_SDCA_1 BIT(1)
130 #define SDW_SCP_SDCA_INT_SDCA_2 BIT(2)
131 #define SDW_SCP_SDCA_INT_SDCA_3 BIT(3)
132 #define SDW_SCP_SDCA_INT_SDCA_4 BIT(4)
133 #define SDW_SCP_SDCA_INT_SDCA_5 BIT(5)
134 #define SDW_SCP_SDCA_INT_SDCA_6 BIT(6)
135 #define SDW_SCP_SDCA_INT_SDCA_7 BIT(7)
137 #define SDW_SCP_SDCA_INT2 0x59
138 #define SDW_SCP_SDCA_INT_SDCA_8 BIT(0)
139 #define SDW_SCP_SDCA_INT_SDCA_9 BIT(1)
140 #define SDW_SCP_SDCA_INT_SDCA_10 BIT(2)
141 #define SDW_SCP_SDCA_INT_SDCA_11 BIT(3)
142 #define SDW_SCP_SDCA_INT_SDCA_12 BIT(4)
143 #define SDW_SCP_SDCA_INT_SDCA_13 BIT(5)
144 #define SDW_SCP_SDCA_INT_SDCA_14 BIT(6)
145 #define SDW_SCP_SDCA_INT_SDCA_15 BIT(7)
147 #define SDW_SCP_SDCA_INT3 0x5A
148 #define SDW_SCP_SDCA_INT_SDCA_16 BIT(0)
149 #define SDW_SCP_SDCA_INT_SDCA_17 BIT(1)
150 #define SDW_SCP_SDCA_INT_SDCA_18 BIT(2)
151 #define SDW_SCP_SDCA_INT_SDCA_19 BIT(3)
152 #define SDW_SCP_SDCA_INT_SDCA_20 BIT(4)
153 #define SDW_SCP_SDCA_INT_SDCA_21 BIT(5)
154 #define SDW_SCP_SDCA_INT_SDCA_22 BIT(6)
155 #define SDW_SCP_SDCA_INT_SDCA_23 BIT(7)
157 #define SDW_SCP_SDCA_INT4 0x5B
158 #define SDW_SCP_SDCA_INT_SDCA_24 BIT(0)
159 #define SDW_SCP_SDCA_INT_SDCA_25 BIT(1)
160 #define SDW_SCP_SDCA_INT_SDCA_26 BIT(2)
161 #define SDW_SCP_SDCA_INT_SDCA_27 BIT(3)
162 #define SDW_SCP_SDCA_INT_SDCA_28 BIT(4)
163 #define SDW_SCP_SDCA_INT_SDCA_29 BIT(5)
164 #define SDW_SCP_SDCA_INT_SDCA_30 BIT(6)
165 /* BIT(7) not allocated in SoundWire 1.2 specification */
167 #define SDW_SCP_SDCA_INTMASK1 0x5C
168 #define SDW_SCP_SDCA_INTMASK_SDCA_0 BIT(0)
169 #define SDW_SCP_SDCA_INTMASK_SDCA_1 BIT(1)
170 #define SDW_SCP_SDCA_INTMASK_SDCA_2 BIT(2)
171 #define SDW_SCP_SDCA_INTMASK_SDCA_3 BIT(3)
172 #define SDW_SCP_SDCA_INTMASK_SDCA_4 BIT(4)
173 #define SDW_SCP_SDCA_INTMASK_SDCA_5 BIT(5)
174 #define SDW_SCP_SDCA_INTMASK_SDCA_6 BIT(6)
175 #define SDW_SCP_SDCA_INTMASK_SDCA_7 BIT(7)
177 #define SDW_SCP_SDCA_INTMASK2 0x5D
178 #define SDW_SCP_SDCA_INTMASK_SDCA_8 BIT(0)
179 #define SDW_SCP_SDCA_INTMASK_SDCA_9 BIT(1)
180 #define SDW_SCP_SDCA_INTMASK_SDCA_10 BIT(2)
181 #define SDW_SCP_SDCA_INTMASK_SDCA_11 BIT(3)
182 #define SDW_SCP_SDCA_INTMASK_SDCA_12 BIT(4)
183 #define SDW_SCP_SDCA_INTMASK_SDCA_13 BIT(5)
184 #define SDW_SCP_SDCA_INTMASK_SDCA_14 BIT(6)
185 #define SDW_SCP_SDCA_INTMASK_SDCA_15 BIT(7)
187 #define SDW_SCP_SDCA_INTMASK3 0x5E
188 #define SDW_SCP_SDCA_INTMASK_SDCA_16 BIT(0)
189 #define SDW_SCP_SDCA_INTMASK_SDCA_17 BIT(1)
190 #define SDW_SCP_SDCA_INTMASK_SDCA_18 BIT(2)
191 #define SDW_SCP_SDCA_INTMASK_SDCA_19 BIT(3)
192 #define SDW_SCP_SDCA_INTMASK_SDCA_20 BIT(4)
193 #define SDW_SCP_SDCA_INTMASK_SDCA_21 BIT(5)
194 #define SDW_SCP_SDCA_INTMASK_SDCA_22 BIT(6)
195 #define SDW_SCP_SDCA_INTMASK_SDCA_23 BIT(7)
197 #define SDW_SCP_SDCA_INTMASK4 0x5F
198 #define SDW_SCP_SDCA_INTMASK_SDCA_24 BIT(0)
199 #define SDW_SCP_SDCA_INTMASK_SDCA_25 BIT(1)
200 #define SDW_SCP_SDCA_INTMASK_SDCA_26 BIT(2)
201 #define SDW_SCP_SDCA_INTMASK_SDCA_27 BIT(3)
202 #define SDW_SCP_SDCA_INTMASK_SDCA_28 BIT(4)
203 #define SDW_SCP_SDCA_INTMASK_SDCA_29 BIT(5)
204 #define SDW_SCP_SDCA_INTMASK_SDCA_30 BIT(6)
205 /* BIT(7) not allocated in SoundWire 1.2 specification */
207 /* Banked Registers */
208 #define SDW_SCP_FRAMECTRL_B0 0x60
209 #define SDW_SCP_FRAMECTRL_B1 (0x60 + SDW_BANK1_OFFSET)
210 #define SDW_SCP_NEXTFRAME_B0 0x61
211 #define SDW_SCP_NEXTFRAME_B1 (0x61 + SDW_BANK1_OFFSET)
213 #define SDW_SCP_BUSCLOCK_SCALE_B0 0x62
214 #define SDW_SCP_BUSCLOCK_SCALE_B1 (0x62 + SDW_BANK1_OFFSET)
215 #define SDW_SCP_CLOCK_SCALE GENMASK(3, 0)
217 /* PHY registers - CTRL and STAT are the same address */
218 #define SDW_SCP_PHY_OUT_CTRL_0 0x80
219 #define SDW_SCP_PHY_OUT_CTRL_1 0x81
220 #define SDW_SCP_PHY_OUT_CTRL_2 0x82
221 #define SDW_SCP_PHY_OUT_CTRL_3 0x83
222 #define SDW_SCP_PHY_OUT_CTRL_4 0x84
223 #define SDW_SCP_PHY_OUT_CTRL_5 0x85
224 #define SDW_SCP_PHY_OUT_CTRL_6 0x86
225 #define SDW_SCP_PHY_OUT_CTRL_7 0x87
227 #define SDW_SCP_CAP_LOAD_CTRL GENMASK(2, 0)
228 #define SDW_SCP_DRIVE_STRENGTH_CTRL GENMASK(5, 3)
229 #define SDW_SCP_SLEW_TIME_CTRL GENMASK(7, 6)
231 /* Both INT and STATUS register is same */
232 #define SDW_DPN_INT(n) (0x0 + SDW_DPN_SIZE * (n))
233 #define SDW_DPN_INTMASK(n) (0x1 + SDW_DPN_SIZE * (n))
234 #define SDW_DPN_PORTCTRL(n) (0x2 + SDW_DPN_SIZE * (n))
235 #define SDW_DPN_BLOCKCTRL1(n) (0x3 + SDW_DPN_SIZE * (n))
236 #define SDW_DPN_PREPARESTATUS(n) (0x4 + SDW_DPN_SIZE * (n))
237 #define SDW_DPN_PREPARECTRL(n) (0x5 + SDW_DPN_SIZE * (n))
239 #define SDW_DPN_INT_TEST_FAIL BIT(0)
240 #define SDW_DPN_INT_PORT_READY BIT(1)
241 #define SDW_DPN_INT_IMPDEF1 BIT(5)
242 #define SDW_DPN_INT_IMPDEF2 BIT(6)
243 #define SDW_DPN_INT_IMPDEF3 BIT(7)
245 #define SDW_DPN_PORTCTRL_FLOWMODE GENMASK(1, 0)
246 #define SDW_DPN_PORTCTRL_DATAMODE GENMASK(3, 2)
247 #define SDW_DPN_PORTCTRL_NXTINVBANK BIT(4)
249 #define SDW_DPN_BLOCKCTRL1_WDLEN GENMASK(5, 0)
251 #define SDW_DPN_PREPARECTRL_CH_PREP GENMASK(7, 0)
253 #define SDW_DPN_CHANNELEN_B0(n) (0x20 + SDW_DPN_SIZE * (n))
254 #define SDW_DPN_CHANNELEN_B1(n) (0x30 + SDW_DPN_SIZE * (n))
256 #define SDW_DPN_BLOCKCTRL2_B0(n) (0x21 + SDW_DPN_SIZE * (n))
257 #define SDW_DPN_BLOCKCTRL2_B1(n) (0x31 + SDW_DPN_SIZE * (n))
259 #define SDW_DPN_SAMPLECTRL1_B0(n) (0x22 + SDW_DPN_SIZE * (n))
260 #define SDW_DPN_SAMPLECTRL1_B1(n) (0x32 + SDW_DPN_SIZE * (n))
262 #define SDW_DPN_SAMPLECTRL2_B0(n) (0x23 + SDW_DPN_SIZE * (n))
263 #define SDW_DPN_SAMPLECTRL2_B1(n) (0x33 + SDW_DPN_SIZE * (n))
265 #define SDW_DPN_OFFSETCTRL1_B0(n) (0x24 + SDW_DPN_SIZE * (n))
266 #define SDW_DPN_OFFSETCTRL1_B1(n) (0x34 + SDW_DPN_SIZE * (n))
268 #define SDW_DPN_OFFSETCTRL2_B0(n) (0x25 + SDW_DPN_SIZE * (n))
269 #define SDW_DPN_OFFSETCTRL2_B1(n) (0x35 + SDW_DPN_SIZE * (n))
271 #define SDW_DPN_HCTRL_B0(n) (0x26 + SDW_DPN_SIZE * (n))
272 #define SDW_DPN_HCTRL_B1(n) (0x36 + SDW_DPN_SIZE * (n))
274 #define SDW_DPN_BLOCKCTRL3_B0(n) (0x27 + SDW_DPN_SIZE * (n))
275 #define SDW_DPN_BLOCKCTRL3_B1(n) (0x37 + SDW_DPN_SIZE * (n))
277 #define SDW_DPN_LANECTRL_B0(n) (0x28 + SDW_DPN_SIZE * (n))
278 #define SDW_DPN_LANECTRL_B1(n) (0x38 + SDW_DPN_SIZE * (n))
280 #define SDW_DPN_SAMPLECTRL_LOW GENMASK(7, 0)
281 #define SDW_DPN_SAMPLECTRL_HIGH GENMASK(15, 8)
283 #define SDW_DPN_HCTRL_HSTART GENMASK(7, 4)
284 #define SDW_DPN_HCTRL_HSTOP GENMASK(3, 0)
286 #define SDW_NUM_CASC_PORT_INTSTAT1 4
287 #define SDW_CASC_PORT_START_INTSTAT1 0
288 #define SDW_CASC_PORT_MASK_INTSTAT1 0x8
289 #define SDW_CASC_PORT_REG_OFFSET_INTSTAT1 0x0
291 #define SDW_NUM_CASC_PORT_INTSTAT2 7
292 #define SDW_CASC_PORT_START_INTSTAT2 4
293 #define SDW_CASC_PORT_MASK_INTSTAT2 1
294 #define SDW_CASC_PORT_REG_OFFSET_INTSTAT2 1
296 #define SDW_NUM_CASC_PORT_INTSTAT3 4
297 #define SDW_CASC_PORT_START_INTSTAT3 11
298 #define SDW_CASC_PORT_MASK_INTSTAT3 1
299 #define SDW_CASC_PORT_REG_OFFSET_INTSTAT3 2
301 #endif /* __SDW_REGISTERS_H */