1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
7 #include <linux/irqreturn.h>
8 #include <linux/soundwire/sdw.h>
10 #define SDW_SHIM_BASE 0x2C000
11 #define SDW_ALH_BASE 0x2C800
12 #define SDW_SHIM_BASE_ACE 0x38000
13 #define SDW_ALH_BASE_ACE 0x24000
14 #define SDW_LINK_BASE 0x30000
15 #define SDW_LINK_SIZE 0x10000
17 /* Intel SHIM Registers Definition */
18 #define SDW_SHIM_LCAP 0x0
19 #define SDW_SHIM_LCTL 0x4
20 #define SDW_SHIM_IPPTR 0x8
21 #define SDW_SHIM_SYNC 0xC
23 #define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
24 #define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
25 #define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
26 #define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
27 #define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
28 #define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
30 #define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
31 #define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
32 #define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x))
33 #define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
34 #define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
36 #define SDW_SHIM_WAKEEN 0x190
37 #define SDW_SHIM_WAKESTS 0x192
39 #define SDW_SHIM_LCTL_SPA BIT(0)
40 #define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0)
41 #define SDW_SHIM_LCTL_CPA BIT(8)
42 #define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8)
44 #define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
45 #define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
46 #define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
47 #define SDW_SHIM_SYNC_SYNCCPU BIT(15)
48 #define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
49 #define SDW_SHIM_SYNC_CMDSYNC BIT(16)
50 #define SDW_SHIM_SYNC_SYNCGO BIT(24)
52 #define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
53 #define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
54 #define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
56 #define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
57 #define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
58 #define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
59 #define SDW_SHIM_PCMSYCM_DIR BIT(15)
61 #define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0)
62 #define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4)
63 #define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8)
64 #define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13)
66 #define SDW_SHIM_IOCTL_MIF BIT(0)
67 #define SDW_SHIM_IOCTL_CO BIT(1)
68 #define SDW_SHIM_IOCTL_COE BIT(2)
69 #define SDW_SHIM_IOCTL_DO BIT(3)
70 #define SDW_SHIM_IOCTL_DOE BIT(4)
71 #define SDW_SHIM_IOCTL_BKE BIT(5)
72 #define SDW_SHIM_IOCTL_WPDD BIT(6)
73 #define SDW_SHIM_IOCTL_CIBD BIT(8)
74 #define SDW_SHIM_IOCTL_DIBD BIT(9)
76 #define SDW_SHIM_CTMCTL_DACTQE BIT(0)
77 #define SDW_SHIM_CTMCTL_DODS BIT(1)
78 #define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
80 #define SDW_SHIM_WAKEEN_ENABLE BIT(0)
81 #define SDW_SHIM_WAKESTS_STATUS BIT(0)
83 /* Intel ALH Register definitions */
84 #define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
85 #define SDW_ALH_NUM_STREAMS 64
87 #define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
88 #define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
89 #define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
92 * struct sdw_intel_stream_params_data: configuration passed during
93 * the @params_stream callback, e.g. for interaction with DSP
96 struct sdw_intel_stream_params_data {
98 struct snd_soc_dai *dai;
99 struct snd_pcm_hw_params *hw_params;
105 * struct sdw_intel_stream_free_data: configuration passed during
106 * the @free_stream callback, e.g. for interaction with DSP
109 struct sdw_intel_stream_free_data {
111 struct snd_soc_dai *dai;
116 * struct sdw_intel_ops: Intel audio driver callback ops
119 struct sdw_intel_ops {
120 int (*params_stream)(struct device *dev,
121 struct sdw_intel_stream_params_data *params_data);
122 int (*free_stream)(struct device *dev,
123 struct sdw_intel_stream_free_data *free_data);
124 int (*trigger)(struct snd_soc_dai *dai, int cmd, int stream);
128 * struct sdw_intel_acpi_info - Soundwire Intel information found in ACPI tables
129 * @handle: ACPI controller handle
130 * @count: link count found with "sdw-master-count" property
131 * @link_mask: bit-wise mask listing links enabled by BIOS menu
133 * this structure could be expanded to e.g. provide all the _ADR
134 * information in case the link_mask is not sufficient to identify
135 * platform capabilities.
137 struct sdw_intel_acpi_info {
143 struct sdw_intel_link_dev;
145 /* Intel clock-stop/pm_runtime quirk definitions */
148 * Force the clock to remain on during pm_runtime suspend. This might
149 * be needed if Slave devices do not have an alternate clock source or
150 * if the latency requirements are very strict.
152 #define SDW_INTEL_CLK_STOP_NOT_ALLOWED BIT(0)
155 * Stop the bus during pm_runtime suspend. If set, a complete bus
156 * reset and re-enumeration will be performed when the bus
157 * restarts. This mode shall not be used if Slave devices can generate
160 #define SDW_INTEL_CLK_STOP_TEARDOWN BIT(1)
163 * Stop the bus during pm_suspend if Slaves are not wake capable
164 * (e.g. speaker amplifiers). The clock-stop mode is typically
165 * slightly higher power than when the IP is completely powered-off.
167 #define SDW_INTEL_CLK_STOP_WAKE_CAPABLE_ONLY BIT(2)
170 * Require a bus reset (and complete re-enumeration) when exiting
171 * clock stop modes. This may be needed if the controller power was
172 * turned off and all context lost. This quirk shall not be used if a
173 * Slave device needs to remain enumerated and keep its context,
174 * e.g. to provide the reasons for the wake, report acoustic events or
175 * pass a history buffer.
177 #define SDW_INTEL_CLK_STOP_BUS_RESET BIT(3)
179 struct sdw_intel_slave_id {
181 struct sdw_slave_id id;
185 * struct sdw_intel_ctx - context allocated by the controller
188 * @mmio_base: mmio base of SoundWire registers, only used to check
189 * hardware capabilities after all power dependencies are settled.
190 * @link_mask: bit-wise mask listing SoundWire links reported by the
192 * @num_slaves: total number of devices exposed across all enabled links
193 * @handle: ACPI parent handle
194 * @ldev: information for each link (controller-specific and kept
196 * @ids: array of slave_id, representing Slaves exposed across all enabled
198 * @link_list: list to handle interrupts across all links
199 * @shim_lock: mutex to handle concurrent rmw access to shared SHIM registers.
200 * @shim_mask: flags to track initialization of SHIM shared registers
201 * @shim_base: sdw shim base.
202 * @alh_base: sdw alh base.
204 struct sdw_intel_ctx {
206 void __iomem *mmio_base;
210 struct sdw_intel_link_dev **ldev;
211 struct sdw_intel_slave_id *ids;
212 struct list_head link_list;
213 struct mutex shim_lock; /* lock for access to shared SHIM registers */
220 * struct sdw_intel_res - Soundwire Intel global resource structure,
221 * typically populated by the DSP driver
224 * @mmio_base: mmio base of SoundWire registers
225 * @irq: interrupt number
226 * @handle: ACPI parent handle
227 * @parent: parent device
229 * @dev: device implementing hwparams and free callbacks
230 * @link_mask: bit-wise mask listing links selected by the DSP driver
231 * This mask may be a subset of the one reported by the controller since
232 * machine-specific quirks are handled in the DSP driver.
233 * @clock_stop_quirks: mask array of possible behaviors requested by the
234 * DSP driver. The quirks are common for all links for now.
235 * @shim_base: sdw shim base.
236 * @alh_base: sdw alh base.
238 struct sdw_intel_res {
240 void __iomem *mmio_base;
243 struct device *parent;
244 const struct sdw_intel_ops *ops;
247 u32 clock_stop_quirks;
253 * On Intel platforms, the SoundWire IP has dependencies on power
254 * rails shared with the DSP, and the initialization steps are split
255 * in three. First an ACPI scan to check what the firmware describes
256 * in DSDT tables, then an allocation step (with no hardware
257 * configuration but with all the relevant devices created) and last
258 * the actual hardware configuration. The final stage is a global
259 * interrupt enable which is controlled by the DSP driver. Splitting
260 * these phases helps simplify the boot flow and make early decisions
261 * on e.g. which machine driver to select (I2S mode, HDaudio or
264 int sdw_intel_acpi_scan(acpi_handle *parent_handle,
265 struct sdw_intel_acpi_info *info);
267 void sdw_intel_process_wakeen_event(struct sdw_intel_ctx *ctx);
269 struct sdw_intel_ctx *
270 sdw_intel_probe(struct sdw_intel_res *res);
272 int sdw_intel_startup(struct sdw_intel_ctx *ctx);
274 void sdw_intel_exit(struct sdw_intel_ctx *ctx);
276 void sdw_intel_enable_irq(void __iomem *mmio_base, bool enable);
278 irqreturn_t sdw_intel_thread(int irq, void *dev_id);
280 #define SDW_INTEL_QUIRK_MASK_BUS_DISABLE BIT(1)