1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
7 #include <linux/mod_devicetable.h>
8 #include <linux/bitfield.h>
13 /* SDW spec defines and enums, as defined by MIPI 1.1. Spec */
15 /* SDW Broadcast Device Number */
16 #define SDW_BROADCAST_DEV_NUM 15
18 /* SDW Enumeration Device Number */
19 #define SDW_ENUM_DEV_NUM 0
21 /* SDW Group Device Numbers */
22 #define SDW_GROUP12_DEV_NUM 12
23 #define SDW_GROUP13_DEV_NUM 13
25 /* SDW Master Device Number, not supported yet */
26 #define SDW_MASTER_DEV_NUM 14
28 #define SDW_NUM_DEV_ID_REGISTERS 6
29 /* frame shape defines */
32 * Note: The maximum row define in SoundWire spec 1.1 is 23. In order to
33 * fill hole with 0, one more dummy entry is added
35 #define SDW_FRAME_ROWS 24
36 #define SDW_FRAME_COLS 8
37 #define SDW_FRAME_ROW_COLS (SDW_FRAME_ROWS * SDW_FRAME_COLS)
39 #define SDW_FRAME_CTRL_BITS 48
40 #define SDW_MAX_DEVICES 11
42 #define SDW_MAX_PORTS 15
43 #define SDW_VALID_PORT_RANGE(n) ((n) < SDW_MAX_PORTS && (n) >= 1)
46 SDW_PORT_DIRN_SINK = 0,
52 * constants for flow control, ports and transport
54 * these are bit masks as devices can have multiple capabilities
58 * flow modes for SDW port. These can be isochronous, tx controlled,
59 * rx controlled or async
61 #define SDW_PORT_FLOW_MODE_ISOCH 0
62 #define SDW_PORT_FLOW_MODE_TX_CNTRL BIT(0)
63 #define SDW_PORT_FLOW_MODE_RX_CNTRL BIT(1)
64 #define SDW_PORT_FLOW_MODE_ASYNC GENMASK(1, 0)
66 /* sample packaging for block. It can be per port or per channel */
67 #define SDW_BLOCK_PACKG_PER_PORT BIT(0)
68 #define SDW_BLOCK_PACKG_PER_CH BIT(1)
71 * enum sdw_slave_status - Slave status
72 * @SDW_SLAVE_UNATTACHED: Slave is not attached with the bus.
73 * @SDW_SLAVE_ATTACHED: Slave is attached with bus.
74 * @SDW_SLAVE_ALERT: Some alert condition on the Slave
75 * @SDW_SLAVE_RESERVED: Reserved for future use
77 enum sdw_slave_status {
78 SDW_SLAVE_UNATTACHED = 0,
79 SDW_SLAVE_ATTACHED = 1,
81 SDW_SLAVE_RESERVED = 3,
85 * enum sdw_clk_stop_type: clock stop operations
87 * @SDW_CLK_PRE_PREPARE: pre clock stop prepare
88 * @SDW_CLK_POST_PREPARE: post clock stop prepare
89 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
90 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare
92 enum sdw_clk_stop_type {
93 SDW_CLK_PRE_PREPARE = 0,
95 SDW_CLK_PRE_DEPREPARE,
96 SDW_CLK_POST_DEPREPARE,
100 * enum sdw_command_response - Command response as defined by SDW spec
101 * @SDW_CMD_OK: cmd was successful
102 * @SDW_CMD_IGNORED: cmd was ignored
103 * @SDW_CMD_FAIL: cmd was NACKed
104 * @SDW_CMD_TIMEOUT: cmd timedout
105 * @SDW_CMD_FAIL_OTHER: cmd failed due to other reason than above
107 * NOTE: The enum is different than actual Spec as response in the Spec is
108 * combination of ACK/NAK bits
110 * SDW_CMD_TIMEOUT/FAIL_OTHER is defined for SW use, not in spec
112 enum sdw_command_response {
117 SDW_CMD_FAIL_OTHER = 4,
120 /* block group count enum */
121 enum sdw_dpn_grouping {
122 SDW_BLK_GRP_CNT_1 = 0,
123 SDW_BLK_GRP_CNT_2 = 1,
124 SDW_BLK_GRP_CNT_3 = 2,
125 SDW_BLK_GRP_CNT_4 = 3,
129 * enum sdw_stream_type: data stream type
131 * @SDW_STREAM_PCM: PCM data stream
132 * @SDW_STREAM_PDM: PDM data stream
134 * spec doesn't define this, but is used in implementation
136 enum sdw_stream_type {
142 * enum sdw_data_direction: Data direction
144 * @SDW_DATA_DIR_RX: Data into Port
145 * @SDW_DATA_DIR_TX: Data out of Port
147 enum sdw_data_direction {
153 * enum sdw_port_data_mode: Data Port mode
155 * @SDW_PORT_DATA_MODE_NORMAL: Normal data mode where audio data is received
157 * @SDW_PORT_DATA_MODE_PRBS: Test mode which uses a PRBS generator to produce
158 * a pseudo random data pattern that is transferred
159 * @SDW_PORT_DATA_MODE_STATIC_0: Simple test mode which uses static value of
160 * logic 0. The encoding will result in no signal transitions
161 * @SDW_PORT_DATA_MODE_STATIC_1: Simple test mode which uses static value of
162 * logic 1. The encoding will result in signal transitions at every bitslot
165 enum sdw_port_data_mode {
166 SDW_PORT_DATA_MODE_NORMAL = 0,
167 SDW_PORT_DATA_MODE_PRBS = 1,
168 SDW_PORT_DATA_MODE_STATIC_0 = 2,
169 SDW_PORT_DATA_MODE_STATIC_1 = 3,
173 * SDW properties, defined in MIPI DisCo spec v1.0
175 enum sdw_clk_stop_reset_behave {
176 SDW_CLK_STOP_KEEP_STATUS = 1,
180 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
182 * @SDW_P15_READ_IGNORED: Read is ignored
183 * @SDW_P15_CMD_OK: Command is ok
185 enum sdw_p15_behave {
186 SDW_P15_READ_IGNORED = 0,
191 * enum sdw_dpn_type - Data port types
192 * @SDW_DPN_FULL: Full Data Port is supported
193 * @SDW_DPN_SIMPLE: Simplified Data Port as defined in spec.
194 * DPN_SampleCtrl2, DPN_OffsetCtrl2, DPN_HCtrl and DPN_BlockCtrl3
195 * are not implemented.
196 * @SDW_DPN_REDUCED: Reduced Data Port as defined in spec.
197 * DPN_SampleCtrl2, DPN_HCtrl are not implemented.
206 * enum sdw_clk_stop_mode - Clock Stop modes
207 * @SDW_CLK_STOP_MODE0: Slave can continue operation seamlessly on clock
209 * @SDW_CLK_STOP_MODE1: Slave may have entered a deeper power-saving mode,
210 * not capable of continuing operation seamlessly when the clock restarts
212 enum sdw_clk_stop_mode {
213 SDW_CLK_STOP_MODE0 = 0,
214 SDW_CLK_STOP_MODE1 = 1,
218 * struct sdw_dp0_prop - DP0 properties
219 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64
221 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64
223 * @num_words: number of wordlengths supported
224 * @words: wordlengths supported
225 * @BRA_flow_controlled: Slave implementation results in an OK_NotReady
227 * @simple_ch_prep_sm: If channel prepare sequence is required
228 * @imp_def_interrupts: If set, each bit corresponds to support for
229 * implementation-defined interrupts
231 * The wordlengths are specified by Spec as max, min AND number of
232 * discrete values, implementation can define based on the wordlengths they
235 struct sdw_dp0_prop {
240 bool BRA_flow_controlled;
241 bool simple_ch_prep_sm;
242 bool imp_def_interrupts;
246 * struct sdw_dpn_audio_mode - Audio mode properties for DPn
247 * @bus_min_freq: Minimum bus frequency, in Hz
248 * @bus_max_freq: Maximum bus frequency, in Hz
249 * @bus_num_freq: Number of discrete frequencies supported
250 * @bus_freq: Discrete bus frequencies, in Hz
251 * @min_freq: Minimum sampling frequency, in Hz
252 * @max_freq: Maximum sampling bus frequency, in Hz
253 * @num_freq: Number of discrete sampling frequency supported
254 * @freq: Discrete sampling frequencies, in Hz
255 * @prep_ch_behave: Specifies the dependencies between Channel Prepare
256 * sequence and bus clock configuration
257 * If 0, Channel Prepare can happen at any Bus clock rate
258 * If 1, Channel Prepare sequence shall happen only after Bus clock is
259 * changed to a frequency supported by this mode or compatible modes
260 * described by the next field
261 * @glitchless: Bitmap describing possible glitchless transitions from this
262 * Audio Mode to other Audio Modes
264 struct sdw_dpn_audio_mode {
278 * struct sdw_dpn_prop - Data Port DPn properties
280 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64
282 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64
284 * @num_words: Number of discrete supported wordlengths
285 * @words: Discrete supported wordlength
286 * @type: Data port type. Full, Simplified or Reduced
287 * @max_grouping: Maximum number of samples that can be grouped together for
289 * @simple_ch_prep_sm: If the port supports simplified channel prepare state
291 * @ch_prep_timeout: Port-specific timeout value, in milliseconds
292 * @imp_def_interrupts: If set, each bit corresponds to support for
293 * implementation-defined interrupts
294 * @max_ch: Maximum channels supported
295 * @min_ch: Minimum channels supported
296 * @num_channels: Number of discrete channels supported
297 * @channels: Discrete channels supported
298 * @num_ch_combinations: Number of channel combinations supported
299 * @ch_combinations: Channel combinations supported
300 * @modes: SDW mode supported
301 * @max_async_buffer: Number of samples that this port can buffer in
303 * @block_pack_mode: Type of block port mode supported
304 * @read_only_wordlength: Read Only wordlength field in DPN_BlockCtrl1 register
305 * @port_encoding: Payload Channel Sample encoding schemes supported
306 * @audio_modes: Audio modes supported
308 struct sdw_dpn_prop {
314 enum sdw_dpn_type type;
316 bool simple_ch_prep_sm;
318 u32 imp_def_interrupts;
323 u32 num_ch_combinations;
324 u32 *ch_combinations;
326 u32 max_async_buffer;
327 bool block_pack_mode;
328 bool read_only_wordlength;
330 struct sdw_dpn_audio_mode *audio_modes;
334 * struct sdw_slave_prop - SoundWire Slave properties
335 * @mipi_revision: Spec version of the implementation
336 * @wake_capable: Wake-up events are supported
337 * @test_mode_capable: If test mode is supported
338 * @clk_stop_mode1: Clock-Stop Mode 1 is supported
339 * @simple_clk_stop_capable: Simple clock mode is supported
340 * @clk_stop_timeout: Worst-case latency of the Clock Stop Prepare State
341 * Machine transitions, in milliseconds
342 * @ch_prep_timeout: Worst-case latency of the Channel Prepare State Machine
343 * transitions, in milliseconds
344 * @reset_behave: Slave keeps the status of the SlaveStopClockPrepare
345 * state machine (P=1 SCSP_SM) after exit from clock-stop mode1
346 * @high_PHY_capable: Slave is HighPHY capable
347 * @paging_support: Slave implements paging registers SCP_AddrPage1 and
349 * @bank_delay_support: Slave implements bank delay/bridge support registers
350 * SCP_BankDelay and SCP_NextFrame
351 * @p15_behave: Slave behavior when the Master attempts a read to the Port15
353 * @lane_control_support: Slave supports lane control
354 * @master_count: Number of Masters present on this Slave
355 * @source_ports: Bitmap identifying source ports
356 * @sink_ports: Bitmap identifying sink ports
357 * @dp0_prop: Data Port 0 properties
358 * @src_dpn_prop: Source Data Port N properties
359 * @sink_dpn_prop: Sink Data Port N properties
360 * @scp_int1_mask: SCP_INT1_MASK desired settings
361 * @quirks: bitmask identifying deltas from the MIPI specification
363 struct sdw_slave_prop {
366 bool test_mode_capable;
368 bool simple_clk_stop_capable;
369 u32 clk_stop_timeout;
371 enum sdw_clk_stop_reset_behave reset_behave;
372 bool high_PHY_capable;
374 bool bank_delay_support;
375 enum sdw_p15_behave p15_behave;
376 bool lane_control_support;
380 struct sdw_dp0_prop *dp0_prop;
381 struct sdw_dpn_prop *src_dpn_prop;
382 struct sdw_dpn_prop *sink_dpn_prop;
387 #define SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY BIT(0)
390 * struct sdw_master_prop - Master properties
391 * @revision: MIPI spec version of the implementation
392 * @clk_stop_modes: Bitmap, bit N set when clock-stop-modeN supported
393 * @max_clk_freq: Maximum Bus clock frequency, in Hz
394 * @num_clk_gears: Number of clock gears supported
395 * @clk_gears: Clock gears supported
396 * @num_clk_freq: Number of clock frequencies supported, in Hz
397 * @clk_freq: Clock frequencies supported, in Hz
398 * @default_frame_rate: Controller default Frame rate, in Hz
399 * @default_row: Number of rows
400 * @default_col: Number of columns
401 * @dynamic_frame: Dynamic frame shape supported
402 * @err_threshold: Number of times that software may retry sending a single
404 * @mclk_freq: clock reference passed to SoundWire Master, in Hz.
405 * @hw_disabled: if true, the Master is not functional, typically due to pin-mux
407 struct sdw_master_prop {
415 u32 default_frame_rate;
424 int sdw_master_read_prop(struct sdw_bus *bus);
425 int sdw_slave_read_prop(struct sdw_slave *slave);
428 * SDW Slave Structures and APIs
431 #define SDW_IGNORED_UNIQUE_ID 0xFF
434 * struct sdw_slave_id - Slave ID
435 * @mfg_id: MIPI Manufacturer ID
436 * @part_id: Device Part ID
437 * @class_id: MIPI Class ID (defined starting with SoundWire 1.2 spec)
438 * @unique_id: Device unique ID
439 * @sdw_version: SDW version implemented
441 * The order of the IDs here does not follow the DisCo spec definitions
443 struct sdw_slave_id {
452 * Helper macros to extract the MIPI-defined IDs
455 * Register Bit Contents
456 * DevId_0 [7:4] 47:44 sdw_version
457 * DevId_0 [3:0] 43:40 unique_id
458 * DevId_1 39:32 mfg_id [15:8]
459 * DevId_2 31:24 mfg_id [7:0]
460 * DevId_3 23:16 part_id [15:8]
461 * DevId_4 15:08 part_id [7:0]
462 * DevId_5 07:00 class_id
464 * The MIPI DisCo for SoundWire defines in addition the link_id as bits 51:48
466 #define SDW_DISCO_LINK_ID_MASK GENMASK_ULL(51, 48)
467 #define SDW_VERSION_MASK GENMASK_ULL(47, 44)
468 #define SDW_UNIQUE_ID_MASK GENMASK_ULL(43, 40)
469 #define SDW_MFG_ID_MASK GENMASK_ULL(39, 24)
470 #define SDW_PART_ID_MASK GENMASK_ULL(23, 8)
471 #define SDW_CLASS_ID_MASK GENMASK_ULL(7, 0)
473 #define SDW_DISCO_LINK_ID(addr) FIELD_GET(SDW_DISCO_LINK_ID_MASK, addr)
474 #define SDW_VERSION(addr) FIELD_GET(SDW_VERSION_MASK, addr)
475 #define SDW_UNIQUE_ID(addr) FIELD_GET(SDW_UNIQUE_ID_MASK, addr)
476 #define SDW_MFG_ID(addr) FIELD_GET(SDW_MFG_ID_MASK, addr)
477 #define SDW_PART_ID(addr) FIELD_GET(SDW_PART_ID_MASK, addr)
478 #define SDW_CLASS_ID(addr) FIELD_GET(SDW_CLASS_ID_MASK, addr)
481 * struct sdw_slave_intr_status - Slave interrupt status
482 * @control_port: control port status
483 * @port: data port status
485 struct sdw_slave_intr_status {
491 * sdw_reg_bank - SoundWire register banks
492 * @SDW_BANK0: Soundwire register bank 0
493 * @SDW_BANK1: Soundwire register bank 1
501 * struct sdw_bus_conf: Bus configuration
503 * @clk_freq: Clock frequency, in Hz
504 * @num_rows: Number of rows in frame
505 * @num_cols: Number of columns in frame
506 * @bank: Next register bank
508 struct sdw_bus_conf {
509 unsigned int clk_freq;
510 unsigned int num_rows;
511 unsigned int num_cols;
516 * struct sdw_prepare_ch: Prepare/De-prepare Data Port channel
519 * @ch_mask: Active channel mask
520 * @prepare: Prepare (true) /de-prepare (false) channel
521 * @bank: Register bank, which bank Slave/Master driver should program for
522 * implementation defined registers. This is always updated to next_bank
523 * value read from bus params.
526 struct sdw_prepare_ch {
528 unsigned int ch_mask;
534 * enum sdw_port_prep_ops: Prepare operations for Data Port
536 * @SDW_OPS_PORT_PRE_PREP: Pre prepare operation for the Port
537 * @SDW_OPS_PORT_PREP: Prepare operation for the Port
538 * @SDW_OPS_PORT_POST_PREP: Post prepare operation for the Port
540 enum sdw_port_prep_ops {
541 SDW_OPS_PORT_PRE_PREP = 0,
542 SDW_OPS_PORT_PREP = 1,
543 SDW_OPS_PORT_POST_PREP = 2,
547 * struct sdw_bus_params: Structure holding bus configuration
549 * @curr_bank: Current bank in use (BANK0/BANK1)
550 * @next_bank: Next bank to use (BANK0/BANK1). next_bank will always be
552 * @max_dr_freq: Maximum double rate clock frequency supported, in Hz
553 * @curr_dr_freq: Current double rate clock frequency, in Hz
554 * @bandwidth: Current bandwidth
555 * @col: Active columns
557 * @s_data_mode: NORMAL, STATIC or PRBS mode for all Slave ports
558 * @m_data_mode: NORMAL, STATIC or PRBS mode for all Master ports. The value
559 * should be the same to detect transmission issues, but can be different to
560 * test the interrupt reports
562 struct sdw_bus_params {
563 enum sdw_reg_bank curr_bank;
564 enum sdw_reg_bank next_bank;
565 unsigned int max_dr_freq;
566 unsigned int curr_dr_freq;
567 unsigned int bandwidth;
575 * struct sdw_slave_ops: Slave driver callback ops
577 * @read_prop: Read Slave properties
578 * @interrupt_callback: Device interrupt notification (invoked in thread
580 * @update_status: Update Slave status
581 * @bus_config: Update the bus config for Slave
582 * @port_prep: Prepare the port with parameters
584 struct sdw_slave_ops {
585 int (*read_prop)(struct sdw_slave *sdw);
586 int (*interrupt_callback)(struct sdw_slave *slave,
587 struct sdw_slave_intr_status *status);
588 int (*update_status)(struct sdw_slave *slave,
589 enum sdw_slave_status status);
590 int (*bus_config)(struct sdw_slave *slave,
591 struct sdw_bus_params *params);
592 int (*port_prep)(struct sdw_slave *slave,
593 struct sdw_prepare_ch *prepare_ch,
594 enum sdw_port_prep_ops pre_ops);
595 int (*get_clk_stop_mode)(struct sdw_slave *slave);
596 int (*clk_stop)(struct sdw_slave *slave,
597 enum sdw_clk_stop_mode mode,
598 enum sdw_clk_stop_type type);
603 * struct sdw_slave - SoundWire Slave
604 * @id: MIPI device ID
606 * @status: Status reported by the Slave
608 * @ops: Slave callback ops
609 * @prop: Slave properties
610 * @debugfs: Slave debugfs
611 * @node: node for bus list
612 * @port_ready: Port ready completion flag for each Slave port
613 * @dev_num: Current Device Number, values can be 0 or dev_num_sticky
614 * @dev_num_sticky: one-time static Device Number assigned by Bus
615 * @probed: boolean tracking driver state
616 * @probe_complete: completion utility to control potential races
617 * on startup between driver probe/initialization and SoundWire
618 * Slave state changes/implementation-defined interrupts
619 * @enumeration_complete: completion utility to control potential races
620 * on startup between device enumeration and read/write access to the
622 * @initialization_complete: completion utility to control potential races
623 * on startup between device enumeration and settings being restored
624 * @unattach_request: mask field to keep track why the Slave re-attached and
625 * was re-initialized. This is useful to deal with potential race conditions
626 * between the Master suspending and the codec resuming, and make sure that
627 * when the Master triggered a reset the Slave is properly enumerated and
629 * @first_interrupt_done: status flag tracking if the interrupt handling
630 * for a Slave happens for the first time after enumeration
633 struct sdw_slave_id id;
635 enum sdw_slave_status status;
637 const struct sdw_slave_ops *ops;
638 struct sdw_slave_prop prop;
639 #ifdef CONFIG_DEBUG_FS
640 struct dentry *debugfs;
642 struct list_head node;
643 struct completion port_ready[SDW_MAX_PORTS];
644 enum sdw_clk_stop_mode curr_clk_stop_mode;
648 struct completion probe_complete;
649 struct completion enumeration_complete;
650 struct completion initialization_complete;
651 u32 unattach_request;
652 bool first_interrupt_done;
655 #define dev_to_sdw_dev(_dev) container_of(_dev, struct sdw_slave, dev)
658 * struct sdw_master_device - SoundWire 'Master Device' representation
659 * @dev: Linux device for this Master
660 * @bus: Bus handle shortcut
662 struct sdw_master_device {
667 #define dev_to_sdw_master_device(d) \
668 container_of(d, struct sdw_master_device, dev)
673 int (*probe)(struct sdw_slave *sdw,
674 const struct sdw_device_id *id);
675 int (*remove)(struct sdw_slave *sdw);
676 void (*shutdown)(struct sdw_slave *sdw);
678 const struct sdw_device_id *id_table;
679 const struct sdw_slave_ops *ops;
681 struct device_driver driver;
684 #define SDW_SLAVE_ENTRY_EXT(_mfg_id, _part_id, _version, _c_id, _drv_data) \
685 { .mfg_id = (_mfg_id), .part_id = (_part_id), \
686 .sdw_version = (_version), .class_id = (_c_id), \
687 .driver_data = (unsigned long)(_drv_data) }
689 #define SDW_SLAVE_ENTRY(_mfg_id, _part_id, _drv_data) \
690 SDW_SLAVE_ENTRY_EXT((_mfg_id), (_part_id), 0, 0, (_drv_data))
692 int sdw_handle_slave_status(struct sdw_bus *bus,
693 enum sdw_slave_status status[]);
696 * SDW master structures and APIs
700 * struct sdw_port_params: Data Port parameters
703 * @bps: Word length of the Port
704 * @flow_mode: Port Data flow mode
705 * @data_mode: Test modes or normal mode
707 * This is used to program the Data Port based on Data Port stream
710 struct sdw_port_params {
713 unsigned int flow_mode;
714 unsigned int data_mode;
718 * struct sdw_transport_params: Data Port Transport Parameters
720 * @blk_grp_ctrl_valid: Port implements block group control
722 * @blk_grp_ctrl: Block group control value
723 * @sample_interval: Sample interval
724 * @offset1: Blockoffset of the payload data
725 * @offset2: Blockoffset of the payload data
726 * @hstart: Horizontal start of the payload data
727 * @hstop: Horizontal stop of the payload data
728 * @blk_pkg_mode: Block per channel or block per port
729 * @lane_ctrl: Data lane Port uses for Data transfer. Currently only single
730 * data lane is supported in bus
732 * This is used to program the Data Port based on Data Port transport
733 * parameters. All these parameters are banked and can be modified
734 * during a bank switch without any artifacts in audio stream.
736 struct sdw_transport_params {
737 bool blk_grp_ctrl_valid;
738 unsigned int port_num;
739 unsigned int blk_grp_ctrl;
740 unsigned int sample_interval;
741 unsigned int offset1;
742 unsigned int offset2;
745 unsigned int blk_pkg_mode;
746 unsigned int lane_ctrl;
750 * struct sdw_enable_ch: Enable/disable Data Port channel
753 * @ch_mask: Active channel mask
754 * @enable: Enable (true) /disable (false) channel
756 struct sdw_enable_ch {
757 unsigned int port_num;
758 unsigned int ch_mask;
763 * struct sdw_master_port_ops: Callback functions from bus to Master
764 * driver to set Master Data ports.
766 * @dpn_set_port_params: Set the Port parameters for the Master Port.
768 * @dpn_set_port_transport_params: Set transport parameters for the Master
769 * Port. Mandatory callback
770 * @dpn_port_prep: Port prepare operations for the Master Data Port.
771 * @dpn_port_enable_ch: Enable the channels of Master Port.
773 struct sdw_master_port_ops {
774 int (*dpn_set_port_params)(struct sdw_bus *bus,
775 struct sdw_port_params *port_params,
777 int (*dpn_set_port_transport_params)(struct sdw_bus *bus,
778 struct sdw_transport_params *transport_params,
779 enum sdw_reg_bank bank);
780 int (*dpn_port_prep)(struct sdw_bus *bus,
781 struct sdw_prepare_ch *prepare_ch);
782 int (*dpn_port_enable_ch)(struct sdw_bus *bus,
783 struct sdw_enable_ch *enable_ch, unsigned int bank);
789 * struct sdw_defer - SDW deffered message
790 * @length: message length
791 * @complete: message completion
796 struct completion complete;
801 * struct sdw_master_ops - Master driver ops
802 * @read_prop: Read Master properties
803 * @xfer_msg: Transfer message callback
804 * @xfer_msg_defer: Defer version of transfer message callback
805 * @reset_page_addr: Reset the SCP page address registers
806 * @set_bus_conf: Set the bus configuration
807 * @pre_bank_switch: Callback for pre bank switch
808 * @post_bank_switch: Callback for post bank switch
810 struct sdw_master_ops {
811 int (*read_prop)(struct sdw_bus *bus);
813 enum sdw_command_response (*xfer_msg)
814 (struct sdw_bus *bus, struct sdw_msg *msg);
815 enum sdw_command_response (*xfer_msg_defer)
816 (struct sdw_bus *bus, struct sdw_msg *msg,
817 struct sdw_defer *defer);
818 enum sdw_command_response (*reset_page_addr)
819 (struct sdw_bus *bus, unsigned int dev_num);
820 int (*set_bus_conf)(struct sdw_bus *bus,
821 struct sdw_bus_params *params);
822 int (*pre_bank_switch)(struct sdw_bus *bus);
823 int (*post_bank_switch)(struct sdw_bus *bus);
828 * struct sdw_bus - SoundWire bus
829 * @dev: Shortcut to &bus->md->dev to avoid changing the entire code.
831 * @link_id: Link id number, can be 0 to N, unique for each Master
832 * @id: bus system-wide unique id
833 * @slaves: list of Slaves on this bus
834 * @assigned: Bitmap for Slave device numbers.
835 * Bit set implies used number, bit clear implies unused number.
836 * @bus_lock: bus lock
837 * @msg_lock: message lock
838 * @compute_params: points to Bus resource management implementation
839 * @ops: Master callback ops
840 * @port_ops: Master port callback ops
841 * @params: Current bus parameters
842 * @prop: Master properties
843 * @m_rt_list: List of Master instance of all stream(s) running on Bus. This
844 * is used to compute and program bus bandwidth, clock, frame shape,
845 * transport and port parameters
846 * @debugfs: Bus debugfs
847 * @defer_msg: Defer message
848 * @clk_stop_timeout: Clock stop timeout computed
849 * @bank_switch_timeout: Bank switch timeout computed
850 * @multi_link: Store bus property that indicates if multi links
851 * are supported. This flag is populated by drivers after reading
852 * appropriate firmware (ACPI/DT).
853 * @hw_sync_min_links: Number of links used by a stream above which
854 * hardware-based synchronization is required. This value is only
855 * meaningful if multi_link is set. If set to 1, hardware-based
856 * synchronization will be used even if a stream only uses a single
861 struct sdw_master_device *md;
862 unsigned int link_id;
864 struct list_head slaves;
865 DECLARE_BITMAP(assigned, SDW_MAX_DEVICES);
866 struct mutex bus_lock;
867 struct mutex msg_lock;
868 int (*compute_params)(struct sdw_bus *bus);
869 const struct sdw_master_ops *ops;
870 const struct sdw_master_port_ops *port_ops;
871 struct sdw_bus_params params;
872 struct sdw_master_prop prop;
873 struct list_head m_rt_list;
874 #ifdef CONFIG_DEBUG_FS
875 struct dentry *debugfs;
877 struct sdw_defer defer_msg;
878 unsigned int clk_stop_timeout;
879 u32 bank_switch_timeout;
881 int hw_sync_min_links;
884 int sdw_bus_master_add(struct sdw_bus *bus, struct device *parent,
885 struct fwnode_handle *fwnode);
886 void sdw_bus_master_delete(struct sdw_bus *bus);
889 * sdw_port_config: Master or Slave Port configuration
892 * @ch_mask: channels mask for port
894 struct sdw_port_config {
896 unsigned int ch_mask;
900 * sdw_stream_config: Master or Slave stream configuration
902 * @frame_rate: Audio frame rate of the stream, in Hz
903 * @ch_count: Channel count of the stream
904 * @bps: Number of bits per audio sample
905 * @direction: Data direction
906 * @type: Stream type PCM or PDM
908 struct sdw_stream_config {
909 unsigned int frame_rate;
910 unsigned int ch_count;
912 enum sdw_data_direction direction;
913 enum sdw_stream_type type;
917 * sdw_stream_state: Stream states
919 * @SDW_STREAM_ALLOCATED: New stream allocated.
920 * @SDW_STREAM_CONFIGURED: Stream configured
921 * @SDW_STREAM_PREPARED: Stream prepared
922 * @SDW_STREAM_ENABLED: Stream enabled
923 * @SDW_STREAM_DISABLED: Stream disabled
924 * @SDW_STREAM_DEPREPARED: Stream de-prepared
925 * @SDW_STREAM_RELEASED: Stream released
927 enum sdw_stream_state {
928 SDW_STREAM_ALLOCATED = 0,
929 SDW_STREAM_CONFIGURED = 1,
930 SDW_STREAM_PREPARED = 2,
931 SDW_STREAM_ENABLED = 3,
932 SDW_STREAM_DISABLED = 4,
933 SDW_STREAM_DEPREPARED = 5,
934 SDW_STREAM_RELEASED = 6,
938 * sdw_stream_params: Stream parameters
940 * @rate: Sampling frequency, in Hz
941 * @ch_count: Number of channels
942 * @bps: bits per channel sample
944 struct sdw_stream_params {
946 unsigned int ch_count;
951 * sdw_stream_runtime: Runtime stream parameters
953 * @name: SoundWire stream name
954 * @params: Stream parameters
955 * @state: Current state of the stream
956 * @type: Stream type PCM or PDM
957 * @master_list: List of Master runtime(s) in this stream.
958 * master_list can contain only one m_rt per Master instance
960 * @m_rt_count: Count of Master runtime(s) in this stream
962 struct sdw_stream_runtime {
964 struct sdw_stream_params params;
965 enum sdw_stream_state state;
966 enum sdw_stream_type type;
967 struct list_head master_list;
971 struct sdw_stream_runtime *sdw_alloc_stream(const char *stream_name);
972 void sdw_release_stream(struct sdw_stream_runtime *stream);
974 int sdw_compute_params(struct sdw_bus *bus);
976 int sdw_stream_add_master(struct sdw_bus *bus,
977 struct sdw_stream_config *stream_config,
978 struct sdw_port_config *port_config,
979 unsigned int num_ports,
980 struct sdw_stream_runtime *stream);
981 int sdw_stream_add_slave(struct sdw_slave *slave,
982 struct sdw_stream_config *stream_config,
983 struct sdw_port_config *port_config,
984 unsigned int num_ports,
985 struct sdw_stream_runtime *stream);
986 int sdw_stream_remove_master(struct sdw_bus *bus,
987 struct sdw_stream_runtime *stream);
988 int sdw_stream_remove_slave(struct sdw_slave *slave,
989 struct sdw_stream_runtime *stream);
990 int sdw_startup_stream(void *sdw_substream);
991 int sdw_prepare_stream(struct sdw_stream_runtime *stream);
992 int sdw_enable_stream(struct sdw_stream_runtime *stream);
993 int sdw_disable_stream(struct sdw_stream_runtime *stream);
994 int sdw_deprepare_stream(struct sdw_stream_runtime *stream);
995 void sdw_shutdown_stream(void *sdw_substream);
996 int sdw_bus_prep_clk_stop(struct sdw_bus *bus);
997 int sdw_bus_clk_stop(struct sdw_bus *bus);
998 int sdw_bus_exit_clk_stop(struct sdw_bus *bus);
1000 /* messaging and data APIs */
1002 int sdw_read(struct sdw_slave *slave, u32 addr);
1003 int sdw_write(struct sdw_slave *slave, u32 addr, u8 value);
1004 int sdw_write_no_pm(struct sdw_slave *slave, u32 addr, u8 value);
1005 int sdw_read_no_pm(struct sdw_slave *slave, u32 addr);
1006 int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val);
1007 int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, u8 *val);
1009 #endif /* __SOUNDWIRE_H */