1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2016 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 #ifndef _QED_ROCE_IF_H
33 #define _QED_ROCE_IF_H
34 #include <linux/types.h>
35 #include <linux/delay.h>
36 #include <linux/list.h>
37 #include <linux/mutex.h>
38 #include <linux/pci.h>
39 #include <linux/slab.h>
40 #include <linux/qed/qed_if.h>
41 #include <linux/qed/qed_ll2_if.h>
42 #include <linux/qed/rdma_common.h>
44 enum qed_roce_ll2_tx_dest {
45 /* Light L2 TX Destination to the Network */
46 QED_ROCE_LL2_TX_DEST_NW,
48 /* Light L2 TX Destination to the Loopback */
49 QED_ROCE_LL2_TX_DEST_LB,
50 QED_ROCE_LL2_TX_DEST_MAX
53 #define QED_RDMA_MAX_CNQ_SIZE (0xFFFF)
57 enum qed_roce_qp_state {
58 QED_ROCE_QP_STATE_RESET,
59 QED_ROCE_QP_STATE_INIT,
60 QED_ROCE_QP_STATE_RTR,
61 QED_ROCE_QP_STATE_RTS,
62 QED_ROCE_QP_STATE_SQD,
63 QED_ROCE_QP_STATE_ERR,
67 enum qed_rdma_tid_type {
68 QED_RDMA_TID_REGISTERED_MR,
70 QED_RDMA_TID_MW_TYPE1,
71 QED_RDMA_TID_MW_TYPE2A
74 struct qed_rdma_events {
76 void (*affiliated_event)(void *context, u8 fw_event_code,
78 void (*unaffiliated_event)(void *context, u8 event_code);
81 struct qed_rdma_device {
96 u8 max_qp_resp_rd_atomic_resc;
97 u8 max_qp_req_rd_atomic_resc;
98 u64 max_dev_resp_rd_atomic_resc;
107 u32 max_mr_mw_fmr_pbl;
108 u64 max_mr_mw_fmr_size;
116 /* Abilty to support RNR-NAK generation */
118 #define QED_RDMA_DEV_CAP_RNR_NAK_MASK 0x1
119 #define QED_RDMA_DEV_CAP_RNR_NAK_SHIFT 0
120 /* Abilty to support shutdown port */
121 #define QED_RDMA_DEV_CAP_SHUTDOWN_PORT_MASK 0x1
122 #define QED_RDMA_DEV_CAP_SHUTDOWN_PORT_SHIFT 1
123 /* Abilty to support port active event */
124 #define QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_MASK 0x1
125 #define QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_SHIFT 2
126 /* Abilty to support port change event */
127 #define QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT_MASK 0x1
128 #define QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT_SHIFT 3
129 /* Abilty to support system image GUID */
130 #define QED_RDMA_DEV_CAP_SYS_IMAGE_MASK 0x1
131 #define QED_RDMA_DEV_CAP_SYS_IMAGE_SHIFT 4
132 /* Abilty to support bad P_Key counter support */
133 #define QED_RDMA_DEV_CAP_BAD_PKEY_CNT_MASK 0x1
134 #define QED_RDMA_DEV_CAP_BAD_PKEY_CNT_SHIFT 5
135 /* Abilty to support atomic operations */
136 #define QED_RDMA_DEV_CAP_ATOMIC_OP_MASK 0x1
137 #define QED_RDMA_DEV_CAP_ATOMIC_OP_SHIFT 6
138 #define QED_RDMA_DEV_CAP_RESIZE_CQ_MASK 0x1
139 #define QED_RDMA_DEV_CAP_RESIZE_CQ_SHIFT 7
140 /* Abilty to support modifying the maximum number of
141 * outstanding work requests per QP
143 #define QED_RDMA_DEV_CAP_RESIZE_MAX_WR_MASK 0x1
144 #define QED_RDMA_DEV_CAP_RESIZE_MAX_WR_SHIFT 8
145 /* Abilty to support automatic path migration */
146 #define QED_RDMA_DEV_CAP_AUTO_PATH_MIG_MASK 0x1
147 #define QED_RDMA_DEV_CAP_AUTO_PATH_MIG_SHIFT 9
148 /* Abilty to support the base memory management extensions */
149 #define QED_RDMA_DEV_CAP_BASE_MEMORY_EXT_MASK 0x1
150 #define QED_RDMA_DEV_CAP_BASE_MEMORY_EXT_SHIFT 10
151 #define QED_RDMA_DEV_CAP_BASE_QUEUE_EXT_MASK 0x1
152 #define QED_RDMA_DEV_CAP_BASE_QUEUE_EXT_SHIFT 11
153 /* Abilty to support multipile page sizes per memory region */
154 #define QED_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_MASK 0x1
155 #define QED_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_SHIFT 12
156 /* Abilty to support block list physical buffer list */
157 #define QED_RDMA_DEV_CAP_BLOCK_MODE_MASK 0x1
158 #define QED_RDMA_DEV_CAP_BLOCK_MODE_SHIFT 13
159 /* Abilty to support zero based virtual addresses */
160 #define QED_RDMA_DEV_CAP_ZBVA_MASK 0x1
161 #define QED_RDMA_DEV_CAP_ZBVA_SHIFT 14
162 /* Abilty to support local invalidate fencing */
163 #define QED_RDMA_DEV_CAP_LOCAL_INV_FENCE_MASK 0x1
164 #define QED_RDMA_DEV_CAP_LOCAL_INV_FENCE_SHIFT 15
165 /* Abilty to support Loopback on QP */
166 #define QED_RDMA_DEV_CAP_LB_INDICATOR_MASK 0x1
167 #define QED_RDMA_DEV_CAP_LB_INDICATOR_SHIFT 16
171 u32 bad_pkey_counter;
172 struct qed_rdma_events events;
175 enum qed_port_state {
180 enum qed_roce_capability {
181 QED_ROCE_V1 = 1 << 0,
182 QED_ROCE_V2 = 1 << 1,
185 struct qed_rdma_port {
186 enum qed_port_state port_state;
189 u8 source_gid_table_len;
190 void *source_gid_table_ptr;
192 void *pkey_table_ptr;
193 u32 pkey_bad_counter;
194 enum qed_roce_capability capability;
197 struct qed_rdma_cnq_params {
202 /* The CQ Mode affects the CQ doorbell transaction size.
203 * 64/32 bit machines should configure to 32/16 bits respectively.
205 enum qed_rdma_cq_mode {
206 QED_RDMA_CQ_MODE_16_BITS,
207 QED_RDMA_CQ_MODE_32_BITS,
210 struct qed_roce_dcqcn_params {
211 u8 notification_point;
214 /* fields for notification point */
215 u32 cnp_send_timeout;
217 /* fields for reaction point */
224 u32 dcqcn_timeout_us;
227 struct qed_rdma_start_in_params {
228 struct qed_rdma_events *events;
229 struct qed_rdma_cnq_params cnq_pbl_list[128];
231 enum qed_rdma_cq_mode cq_mode;
232 struct qed_roce_dcqcn_params dcqcn_params;
234 u8 mac_addr[ETH_ALEN];
238 struct qed_rdma_add_user_out_params {
260 struct qed_rdma_register_tid_in_params {
262 enum qed_rdma_tid_type tid_type;
273 u8 pbl_page_size_log;
287 struct qed_rdma_create_cq_in_params {
295 u8 pbl_page_size_log;
300 struct qed_rdma_create_srq_in_params {
308 struct qed_rdma_destroy_cq_in_params {
312 struct qed_rdma_destroy_cq_out_params {
316 struct qed_rdma_create_qp_in_params {
319 u32 qp_handle_async_lo;
320 u32 qp_handle_async_hi;
323 bool fmr_and_reserved_lkey;
337 struct qed_rdma_create_qp_out_params {
341 dma_addr_t rq_pbl_phys;
343 dma_addr_t sq_pbl_phys;
346 struct qed_rdma_modify_qp_in_params {
348 #define QED_RDMA_MODIFY_QP_VALID_NEW_STATE_MASK 0x1
349 #define QED_RDMA_MODIFY_QP_VALID_NEW_STATE_SHIFT 0
350 #define QED_ROCE_MODIFY_QP_VALID_PKEY_MASK 0x1
351 #define QED_ROCE_MODIFY_QP_VALID_PKEY_SHIFT 1
352 #define QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN_MASK 0x1
353 #define QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN_SHIFT 2
354 #define QED_ROCE_MODIFY_QP_VALID_DEST_QP_MASK 0x1
355 #define QED_ROCE_MODIFY_QP_VALID_DEST_QP_SHIFT 3
356 #define QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR_MASK 0x1
357 #define QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR_SHIFT 4
358 #define QED_ROCE_MODIFY_QP_VALID_RQ_PSN_MASK 0x1
359 #define QED_ROCE_MODIFY_QP_VALID_RQ_PSN_SHIFT 5
360 #define QED_ROCE_MODIFY_QP_VALID_SQ_PSN_MASK 0x1
361 #define QED_ROCE_MODIFY_QP_VALID_SQ_PSN_SHIFT 6
362 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ_MASK 0x1
363 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ_SHIFT 7
364 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP_MASK 0x1
365 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP_SHIFT 8
366 #define QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT_MASK 0x1
367 #define QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT_SHIFT 9
368 #define QED_ROCE_MODIFY_QP_VALID_RETRY_CNT_MASK 0x1
369 #define QED_ROCE_MODIFY_QP_VALID_RETRY_CNT_SHIFT 10
370 #define QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT_MASK 0x1
371 #define QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT_SHIFT 11
372 #define QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER_MASK 0x1
373 #define QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER_SHIFT 12
374 #define QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN_MASK 0x1
375 #define QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN_SHIFT 13
376 #define QED_ROCE_MODIFY_QP_VALID_ROCE_MODE_MASK 0x1
377 #define QED_ROCE_MODIFY_QP_VALID_ROCE_MODE_SHIFT 14
379 enum qed_roce_qp_state new_state;
381 bool incoming_rdma_read_en;
382 bool incoming_rdma_write_en;
383 bool incoming_atomic_en;
384 bool e2e_flow_control_en;
388 u8 traffic_class_tos;
399 u8 max_rd_atomic_resp;
400 u8 max_rd_atomic_req;
404 u8 min_rnr_nak_timer;
406 u8 remote_mac_addr[6];
407 u8 local_mac_addr[6];
409 enum roce_mode roce_mode;
412 struct qed_rdma_query_qp_out_params {
413 enum qed_roce_qp_state state;
419 bool incoming_rdma_read_en;
420 bool incoming_rdma_write_en;
421 bool incoming_atomic_en;
422 bool e2e_flow_control_en;
427 u8 traffic_class_tos;
431 u8 min_rnr_nak_timer;
434 u8 max_dest_rd_atomic;
438 struct qed_rdma_create_srq_out_params {
442 struct qed_rdma_destroy_srq_in_params {
446 struct qed_rdma_modify_srq_in_params {
451 struct qed_rdma_stats_out_params {
458 struct qed_rdma_counters_out_params {
471 #define QED_ROCE_TX_HEAD_FAILURE (1)
472 #define QED_ROCE_TX_FRAG_FAILURE (2)
474 struct qed_roce_ll2_header {
480 struct qed_roce_ll2_buffer {
485 struct qed_roce_ll2_packet {
486 struct qed_roce_ll2_header header;
488 struct qed_roce_ll2_buffer payload[RDMA_MAX_SGE_PER_SQ_WQE];
490 enum qed_roce_ll2_tx_dest tx_dest;
493 struct qed_roce_ll2_tx_params {
497 struct qed_roce_ll2_rx_params {
503 struct qed_roce_ll2_cbs {
504 void (*tx_cb)(void *pdev, struct qed_roce_ll2_packet *pkt);
506 void (*rx_cb)(void *pdev, struct qed_roce_ll2_packet *pkt,
507 struct qed_roce_ll2_rx_params *params);
510 struct qed_roce_ll2_params {
514 u8 mac_address[ETH_ALEN];
515 struct qed_roce_ll2_cbs cbs;
519 struct qed_roce_ll2_info {
521 struct qed_roce_ll2_cbs cbs;
522 u8 mac_address[ETH_ALEN];
525 /* Lock to protect ll2 */
533 struct qed_dev_rdma_info {
534 struct qed_dev_info common;
535 enum qed_rdma_type rdma_type;
538 struct qed_rdma_ops {
539 const struct qed_common_ops *common;
541 int (*fill_dev_info)(struct qed_dev *cdev,
542 struct qed_dev_rdma_info *info);
543 void *(*rdma_get_rdma_ctx)(struct qed_dev *cdev);
545 int (*rdma_init)(struct qed_dev *dev,
546 struct qed_rdma_start_in_params *iparams);
548 int (*rdma_add_user)(void *rdma_cxt,
549 struct qed_rdma_add_user_out_params *oparams);
551 void (*rdma_remove_user)(void *rdma_cxt, u16 dpi);
552 int (*rdma_stop)(void *rdma_cxt);
553 struct qed_rdma_device* (*rdma_query_device)(void *rdma_cxt);
554 struct qed_rdma_port* (*rdma_query_port)(void *rdma_cxt);
555 int (*rdma_get_start_sb)(struct qed_dev *cdev);
556 int (*rdma_get_min_cnq_msix)(struct qed_dev *cdev);
557 void (*rdma_cnq_prod_update)(void *rdma_cxt, u8 cnq_index, u16 prod);
558 int (*rdma_get_rdma_int)(struct qed_dev *cdev,
559 struct qed_int_info *info);
560 int (*rdma_set_rdma_int)(struct qed_dev *cdev, u16 cnt);
561 int (*rdma_alloc_pd)(void *rdma_cxt, u16 *pd);
562 void (*rdma_dealloc_pd)(void *rdma_cxt, u16 pd);
563 int (*rdma_create_cq)(void *rdma_cxt,
564 struct qed_rdma_create_cq_in_params *params,
566 int (*rdma_destroy_cq)(void *rdma_cxt,
567 struct qed_rdma_destroy_cq_in_params *iparams,
568 struct qed_rdma_destroy_cq_out_params *oparams);
570 (*rdma_create_qp)(void *rdma_cxt,
571 struct qed_rdma_create_qp_in_params *iparams,
572 struct qed_rdma_create_qp_out_params *oparams);
574 int (*rdma_modify_qp)(void *roce_cxt, struct qed_rdma_qp *qp,
575 struct qed_rdma_modify_qp_in_params *iparams);
577 int (*rdma_query_qp)(void *rdma_cxt, struct qed_rdma_qp *qp,
578 struct qed_rdma_query_qp_out_params *oparams);
579 int (*rdma_destroy_qp)(void *rdma_cxt, struct qed_rdma_qp *qp);
581 (*rdma_register_tid)(void *rdma_cxt,
582 struct qed_rdma_register_tid_in_params *iparams);
583 int (*rdma_deregister_tid)(void *rdma_cxt, u32 itid);
584 int (*rdma_alloc_tid)(void *rdma_cxt, u32 *itid);
585 void (*rdma_free_tid)(void *rdma_cxt, u32 itid);
586 int (*roce_ll2_start)(struct qed_dev *cdev,
587 struct qed_roce_ll2_params *params);
588 int (*roce_ll2_stop)(struct qed_dev *cdev);
589 int (*roce_ll2_tx)(struct qed_dev *cdev,
590 struct qed_roce_ll2_packet *packet,
591 struct qed_roce_ll2_tx_params *params);
592 int (*roce_ll2_post_rx_buffer)(struct qed_dev *cdev,
593 struct qed_roce_ll2_buffer *buf,
594 u64 cookie, u8 notify_fw);
595 int (*roce_ll2_set_mac_filter)(struct qed_dev *cdev,
597 u8 *new_mac_address);
598 int (*roce_ll2_stats)(struct qed_dev *cdev,
599 struct qed_ll2_stats *stats);
602 const struct qed_rdma_ops *qed_get_rdma_ops(void);