1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 #ifndef _QED_RDMA_IF_H
33 #define _QED_RDMA_IF_H
34 #include <linux/types.h>
35 #include <linux/delay.h>
36 #include <linux/list.h>
37 #include <linux/slab.h>
38 #include <linux/qed/qed_if.h>
39 #include <linux/qed/qed_ll2_if.h>
40 #include <linux/qed/rdma_common.h>
42 enum qed_roce_ll2_tx_dest {
43 /* Light L2 TX Destination to the Network */
44 QED_ROCE_LL2_TX_DEST_NW,
46 /* Light L2 TX Destination to the Loopback */
47 QED_ROCE_LL2_TX_DEST_LB,
48 QED_ROCE_LL2_TX_DEST_MAX
51 #define QED_RDMA_MAX_CNQ_SIZE (0xFFFF)
55 enum qed_roce_qp_state {
56 QED_ROCE_QP_STATE_RESET,
57 QED_ROCE_QP_STATE_INIT,
58 QED_ROCE_QP_STATE_RTR,
59 QED_ROCE_QP_STATE_RTS,
60 QED_ROCE_QP_STATE_SQD,
61 QED_ROCE_QP_STATE_ERR,
65 enum qed_rdma_tid_type {
66 QED_RDMA_TID_REGISTERED_MR,
71 struct qed_rdma_events {
73 void (*affiliated_event)(void *context, u8 fw_event_code,
75 void (*unaffiliated_event)(void *context, u8 event_code);
78 struct qed_rdma_device {
93 u8 max_qp_resp_rd_atomic_resc;
94 u8 max_qp_req_rd_atomic_resc;
95 u64 max_dev_resp_rd_atomic_resc;
104 u32 max_mr_mw_fmr_pbl;
105 u64 max_mr_mw_fmr_size;
113 /* Abilty to support RNR-NAK generation */
115 #define QED_RDMA_DEV_CAP_RNR_NAK_MASK 0x1
116 #define QED_RDMA_DEV_CAP_RNR_NAK_SHIFT 0
117 /* Abilty to support shutdown port */
118 #define QED_RDMA_DEV_CAP_SHUTDOWN_PORT_MASK 0x1
119 #define QED_RDMA_DEV_CAP_SHUTDOWN_PORT_SHIFT 1
120 /* Abilty to support port active event */
121 #define QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_MASK 0x1
122 #define QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_SHIFT 2
123 /* Abilty to support port change event */
124 #define QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT_MASK 0x1
125 #define QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT_SHIFT 3
126 /* Abilty to support system image GUID */
127 #define QED_RDMA_DEV_CAP_SYS_IMAGE_MASK 0x1
128 #define QED_RDMA_DEV_CAP_SYS_IMAGE_SHIFT 4
129 /* Abilty to support bad P_Key counter support */
130 #define QED_RDMA_DEV_CAP_BAD_PKEY_CNT_MASK 0x1
131 #define QED_RDMA_DEV_CAP_BAD_PKEY_CNT_SHIFT 5
132 /* Abilty to support atomic operations */
133 #define QED_RDMA_DEV_CAP_ATOMIC_OP_MASK 0x1
134 #define QED_RDMA_DEV_CAP_ATOMIC_OP_SHIFT 6
135 #define QED_RDMA_DEV_CAP_RESIZE_CQ_MASK 0x1
136 #define QED_RDMA_DEV_CAP_RESIZE_CQ_SHIFT 7
137 /* Abilty to support modifying the maximum number of
138 * outstanding work requests per QP
140 #define QED_RDMA_DEV_CAP_RESIZE_MAX_WR_MASK 0x1
141 #define QED_RDMA_DEV_CAP_RESIZE_MAX_WR_SHIFT 8
142 /* Abilty to support automatic path migration */
143 #define QED_RDMA_DEV_CAP_AUTO_PATH_MIG_MASK 0x1
144 #define QED_RDMA_DEV_CAP_AUTO_PATH_MIG_SHIFT 9
145 /* Abilty to support the base memory management extensions */
146 #define QED_RDMA_DEV_CAP_BASE_MEMORY_EXT_MASK 0x1
147 #define QED_RDMA_DEV_CAP_BASE_MEMORY_EXT_SHIFT 10
148 #define QED_RDMA_DEV_CAP_BASE_QUEUE_EXT_MASK 0x1
149 #define QED_RDMA_DEV_CAP_BASE_QUEUE_EXT_SHIFT 11
150 /* Abilty to support multipile page sizes per memory region */
151 #define QED_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_MASK 0x1
152 #define QED_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_SHIFT 12
153 /* Abilty to support block list physical buffer list */
154 #define QED_RDMA_DEV_CAP_BLOCK_MODE_MASK 0x1
155 #define QED_RDMA_DEV_CAP_BLOCK_MODE_SHIFT 13
156 /* Abilty to support zero based virtual addresses */
157 #define QED_RDMA_DEV_CAP_ZBVA_MASK 0x1
158 #define QED_RDMA_DEV_CAP_ZBVA_SHIFT 14
159 /* Abilty to support local invalidate fencing */
160 #define QED_RDMA_DEV_CAP_LOCAL_INV_FENCE_MASK 0x1
161 #define QED_RDMA_DEV_CAP_LOCAL_INV_FENCE_SHIFT 15
162 /* Abilty to support Loopback on QP */
163 #define QED_RDMA_DEV_CAP_LB_INDICATOR_MASK 0x1
164 #define QED_RDMA_DEV_CAP_LB_INDICATOR_SHIFT 16
168 u32 bad_pkey_counter;
169 struct qed_rdma_events events;
172 enum qed_port_state {
177 enum qed_roce_capability {
178 QED_ROCE_V1 = 1 << 0,
179 QED_ROCE_V2 = 1 << 1,
182 struct qed_rdma_port {
183 enum qed_port_state port_state;
186 u8 source_gid_table_len;
187 void *source_gid_table_ptr;
189 void *pkey_table_ptr;
190 u32 pkey_bad_counter;
191 enum qed_roce_capability capability;
194 struct qed_rdma_cnq_params {
199 /* The CQ Mode affects the CQ doorbell transaction size.
200 * 64/32 bit machines should configure to 32/16 bits respectively.
202 enum qed_rdma_cq_mode {
203 QED_RDMA_CQ_MODE_16_BITS,
204 QED_RDMA_CQ_MODE_32_BITS,
207 struct qed_roce_dcqcn_params {
208 u8 notification_point;
211 /* fields for notification point */
212 u32 cnp_send_timeout;
214 /* fields for reaction point */
221 u32 dcqcn_timeout_us;
224 struct qed_rdma_start_in_params {
225 struct qed_rdma_events *events;
226 struct qed_rdma_cnq_params cnq_pbl_list[128];
228 enum qed_rdma_cq_mode cq_mode;
229 struct qed_roce_dcqcn_params dcqcn_params;
231 u8 mac_addr[ETH_ALEN];
235 struct qed_rdma_add_user_out_params {
258 struct qed_rdma_register_tid_in_params {
260 enum qed_rdma_tid_type tid_type;
271 u8 pbl_page_size_log;
284 struct qed_rdma_create_cq_in_params {
292 u8 pbl_page_size_log;
297 struct qed_rdma_create_srq_in_params {
305 struct qed_rdma_destroy_cq_in_params {
309 struct qed_rdma_destroy_cq_out_params {
313 struct qed_rdma_create_qp_in_params {
316 u32 qp_handle_async_lo;
317 u32 qp_handle_async_hi;
320 bool fmr_and_reserved_lkey;
334 struct qed_rdma_create_qp_out_params {
338 dma_addr_t rq_pbl_phys;
340 dma_addr_t sq_pbl_phys;
343 struct qed_rdma_modify_qp_in_params {
345 #define QED_RDMA_MODIFY_QP_VALID_NEW_STATE_MASK 0x1
346 #define QED_RDMA_MODIFY_QP_VALID_NEW_STATE_SHIFT 0
347 #define QED_ROCE_MODIFY_QP_VALID_PKEY_MASK 0x1
348 #define QED_ROCE_MODIFY_QP_VALID_PKEY_SHIFT 1
349 #define QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN_MASK 0x1
350 #define QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN_SHIFT 2
351 #define QED_ROCE_MODIFY_QP_VALID_DEST_QP_MASK 0x1
352 #define QED_ROCE_MODIFY_QP_VALID_DEST_QP_SHIFT 3
353 #define QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR_MASK 0x1
354 #define QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR_SHIFT 4
355 #define QED_ROCE_MODIFY_QP_VALID_RQ_PSN_MASK 0x1
356 #define QED_ROCE_MODIFY_QP_VALID_RQ_PSN_SHIFT 5
357 #define QED_ROCE_MODIFY_QP_VALID_SQ_PSN_MASK 0x1
358 #define QED_ROCE_MODIFY_QP_VALID_SQ_PSN_SHIFT 6
359 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ_MASK 0x1
360 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ_SHIFT 7
361 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP_MASK 0x1
362 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP_SHIFT 8
363 #define QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT_MASK 0x1
364 #define QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT_SHIFT 9
365 #define QED_ROCE_MODIFY_QP_VALID_RETRY_CNT_MASK 0x1
366 #define QED_ROCE_MODIFY_QP_VALID_RETRY_CNT_SHIFT 10
367 #define QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT_MASK 0x1
368 #define QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT_SHIFT 11
369 #define QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER_MASK 0x1
370 #define QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER_SHIFT 12
371 #define QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN_MASK 0x1
372 #define QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN_SHIFT 13
373 #define QED_ROCE_MODIFY_QP_VALID_ROCE_MODE_MASK 0x1
374 #define QED_ROCE_MODIFY_QP_VALID_ROCE_MODE_SHIFT 14
376 enum qed_roce_qp_state new_state;
378 bool incoming_rdma_read_en;
379 bool incoming_rdma_write_en;
380 bool incoming_atomic_en;
381 bool e2e_flow_control_en;
385 u8 traffic_class_tos;
396 u8 max_rd_atomic_resp;
397 u8 max_rd_atomic_req;
401 u8 min_rnr_nak_timer;
403 u8 remote_mac_addr[6];
404 u8 local_mac_addr[6];
406 enum roce_mode roce_mode;
409 struct qed_rdma_query_qp_out_params {
410 enum qed_roce_qp_state state;
416 bool incoming_rdma_read_en;
417 bool incoming_rdma_write_en;
418 bool incoming_atomic_en;
419 bool e2e_flow_control_en;
424 u8 traffic_class_tos;
428 u8 min_rnr_nak_timer;
431 u8 max_dest_rd_atomic;
435 struct qed_rdma_create_srq_out_params {
439 struct qed_rdma_destroy_srq_in_params {
443 struct qed_rdma_modify_srq_in_params {
448 struct qed_rdma_stats_out_params {
455 struct qed_rdma_counters_out_params {
468 #define QED_ROCE_TX_HEAD_FAILURE (1)
469 #define QED_ROCE_TX_FRAG_FAILURE (2)
471 enum qed_iwarp_event_type {
472 QED_IWARP_EVENT_MPA_REQUEST, /* Passive side request received */
473 QED_IWARP_EVENT_PASSIVE_COMPLETE, /* ack on mpa response */
474 QED_IWARP_EVENT_ACTIVE_COMPLETE, /* Active side reply received */
475 QED_IWARP_EVENT_DISCONNECT,
476 QED_IWARP_EVENT_CLOSE,
477 QED_IWARP_EVENT_IRQ_FULL,
478 QED_IWARP_EVENT_RQ_EMPTY,
479 QED_IWARP_EVENT_LLP_TIMEOUT,
480 QED_IWARP_EVENT_REMOTE_PROTECTION_ERROR,
481 QED_IWARP_EVENT_CQ_OVERFLOW,
482 QED_IWARP_EVENT_QP_CATASTROPHIC,
483 QED_IWARP_EVENT_ACTIVE_MPA_REPLY,
484 QED_IWARP_EVENT_LOCAL_ACCESS_ERROR,
485 QED_IWARP_EVENT_REMOTE_OPERATION_ERROR,
486 QED_IWARP_EVENT_TERMINATE_RECEIVED,
487 QED_IWARP_EVENT_SRQ_LIMIT,
488 QED_IWARP_EVENT_SRQ_EMPTY,
491 enum qed_tcp_ip_version {
496 struct qed_iwarp_cm_info {
497 enum qed_tcp_ip_version ip_version;
505 u16 private_data_len;
506 const void *private_data;
509 struct qed_iwarp_cm_event_params {
510 enum qed_iwarp_event_type event;
511 const struct qed_iwarp_cm_info *cm_info;
512 void *ep_context; /* To be passed to accept call */
516 typedef int (*iwarp_event_handler) (void *context,
517 struct qed_iwarp_cm_event_params *event);
519 struct qed_iwarp_connect_in {
520 iwarp_event_handler event_cb;
522 struct qed_rdma_qp *qp;
523 struct qed_iwarp_cm_info cm_info;
525 u8 remote_mac_addr[ETH_ALEN];
526 u8 local_mac_addr[ETH_ALEN];
529 struct qed_iwarp_connect_out {
533 struct qed_iwarp_listen_in {
534 iwarp_event_handler event_cb;
535 void *cb_context; /* passed to event_cb */
537 enum qed_tcp_ip_version ip_version;
543 struct qed_iwarp_listen_out {
547 struct qed_iwarp_accept_in {
550 struct qed_rdma_qp *qp;
551 const void *private_data;
552 u16 private_data_len;
557 struct qed_iwarp_reject_in {
560 const void *private_data;
561 u16 private_data_len;
564 struct qed_iwarp_send_rtr_in {
568 struct qed_roce_ll2_header {
574 struct qed_roce_ll2_buffer {
579 struct qed_roce_ll2_packet {
580 struct qed_roce_ll2_header header;
582 struct qed_roce_ll2_buffer payload[RDMA_MAX_SGE_PER_SQ_WQE];
584 enum qed_roce_ll2_tx_dest tx_dest;
592 struct qed_dev_rdma_info {
593 struct qed_dev_info common;
594 enum qed_rdma_type rdma_type;
598 struct qed_rdma_ops {
599 const struct qed_common_ops *common;
601 int (*fill_dev_info)(struct qed_dev *cdev,
602 struct qed_dev_rdma_info *info);
603 void *(*rdma_get_rdma_ctx)(struct qed_dev *cdev);
605 int (*rdma_init)(struct qed_dev *dev,
606 struct qed_rdma_start_in_params *iparams);
608 int (*rdma_add_user)(void *rdma_cxt,
609 struct qed_rdma_add_user_out_params *oparams);
611 void (*rdma_remove_user)(void *rdma_cxt, u16 dpi);
612 int (*rdma_stop)(void *rdma_cxt);
613 struct qed_rdma_device* (*rdma_query_device)(void *rdma_cxt);
614 struct qed_rdma_port* (*rdma_query_port)(void *rdma_cxt);
615 int (*rdma_get_start_sb)(struct qed_dev *cdev);
616 int (*rdma_get_min_cnq_msix)(struct qed_dev *cdev);
617 void (*rdma_cnq_prod_update)(void *rdma_cxt, u8 cnq_index, u16 prod);
618 int (*rdma_get_rdma_int)(struct qed_dev *cdev,
619 struct qed_int_info *info);
620 int (*rdma_set_rdma_int)(struct qed_dev *cdev, u16 cnt);
621 int (*rdma_alloc_pd)(void *rdma_cxt, u16 *pd);
622 void (*rdma_dealloc_pd)(void *rdma_cxt, u16 pd);
623 int (*rdma_create_cq)(void *rdma_cxt,
624 struct qed_rdma_create_cq_in_params *params,
626 int (*rdma_destroy_cq)(void *rdma_cxt,
627 struct qed_rdma_destroy_cq_in_params *iparams,
628 struct qed_rdma_destroy_cq_out_params *oparams);
630 (*rdma_create_qp)(void *rdma_cxt,
631 struct qed_rdma_create_qp_in_params *iparams,
632 struct qed_rdma_create_qp_out_params *oparams);
634 int (*rdma_modify_qp)(void *roce_cxt, struct qed_rdma_qp *qp,
635 struct qed_rdma_modify_qp_in_params *iparams);
637 int (*rdma_query_qp)(void *rdma_cxt, struct qed_rdma_qp *qp,
638 struct qed_rdma_query_qp_out_params *oparams);
639 int (*rdma_destroy_qp)(void *rdma_cxt, struct qed_rdma_qp *qp);
642 (*rdma_register_tid)(void *rdma_cxt,
643 struct qed_rdma_register_tid_in_params *iparams);
645 int (*rdma_deregister_tid)(void *rdma_cxt, u32 itid);
646 int (*rdma_alloc_tid)(void *rdma_cxt, u32 *itid);
647 void (*rdma_free_tid)(void *rdma_cxt, u32 itid);
649 int (*rdma_create_srq)(void *rdma_cxt,
650 struct qed_rdma_create_srq_in_params *iparams,
651 struct qed_rdma_create_srq_out_params *oparams);
652 int (*rdma_destroy_srq)(void *rdma_cxt,
653 struct qed_rdma_destroy_srq_in_params *iparams);
654 int (*rdma_modify_srq)(void *rdma_cxt,
655 struct qed_rdma_modify_srq_in_params *iparams);
657 int (*ll2_acquire_connection)(void *rdma_cxt,
658 struct qed_ll2_acquire_data *data);
660 int (*ll2_establish_connection)(void *rdma_cxt, u8 connection_handle);
661 int (*ll2_terminate_connection)(void *rdma_cxt, u8 connection_handle);
662 void (*ll2_release_connection)(void *rdma_cxt, u8 connection_handle);
664 int (*ll2_prepare_tx_packet)(void *rdma_cxt,
665 u8 connection_handle,
666 struct qed_ll2_tx_pkt_info *pkt,
669 int (*ll2_set_fragment_of_tx_packet)(void *rdma_cxt,
670 u8 connection_handle,
673 int (*ll2_post_rx_buffer)(void *rdma_cxt, u8 connection_handle,
674 dma_addr_t addr, u16 buf_len, void *cookie,
676 int (*ll2_get_stats)(void *rdma_cxt,
677 u8 connection_handle,
678 struct qed_ll2_stats *p_stats);
679 int (*ll2_set_mac_filter)(struct qed_dev *cdev,
680 u8 *old_mac_address, u8 *new_mac_address);
682 int (*iwarp_connect)(void *rdma_cxt,
683 struct qed_iwarp_connect_in *iparams,
684 struct qed_iwarp_connect_out *oparams);
686 int (*iwarp_create_listen)(void *rdma_cxt,
687 struct qed_iwarp_listen_in *iparams,
688 struct qed_iwarp_listen_out *oparams);
690 int (*iwarp_accept)(void *rdma_cxt,
691 struct qed_iwarp_accept_in *iparams);
693 int (*iwarp_reject)(void *rdma_cxt,
694 struct qed_iwarp_reject_in *iparams);
696 int (*iwarp_destroy_listen)(void *rdma_cxt, void *handle);
698 int (*iwarp_send_rtr)(void *rdma_cxt,
699 struct qed_iwarp_send_rtr_in *iparams);
702 const struct qed_rdma_ops *qed_get_rdma_ops(void);