1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /* QLogic qed NIC Driver
3 * Copyright (c) 2015-2017 QLogic Corporation
4 * Copyright (c) 2019-2020 Marvell International Ltd.
10 #include <linux/types.h>
11 #include <linux/interrupt.h>
12 #include <linux/netdevice.h>
13 #include <linux/pci.h>
14 #include <linux/skbuff.h>
15 #include <asm/byteorder.h>
17 #include <linux/compiler.h>
18 #include <linux/kernel.h>
19 #include <linux/list.h>
20 #include <linux/slab.h>
21 #include <linux/qed/common_hsi.h>
22 #include <linux/qed/qed_chain.h>
23 #include <linux/io-64-nonatomic-lo-hi.h>
24 #include <net/devlink.h>
26 enum dcbx_protocol_type {
30 DCBX_PROTOCOL_ROCE_V2,
32 DCBX_MAX_PROTOCOL_TYPE
35 #define QED_ROCE_PROTOCOL_INDEX (3)
37 #define QED_LLDP_CHASSIS_ID_STAT_LEN 4
38 #define QED_LLDP_PORT_ID_STAT_LEN 4
39 #define QED_DCBX_MAX_APP_PROTOCOL 32
40 #define QED_MAX_PFC_PRIORITIES 8
41 #define QED_DCBX_DSCP_SIZE 64
43 struct qed_dcbx_lldp_remote {
44 u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
45 u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN];
52 struct qed_dcbx_lldp_local {
53 u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
54 u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN];
57 struct qed_dcbx_app_prio {
65 struct qed_dbcx_pfc_params {
68 u8 prio[QED_MAX_PFC_PRIORITIES];
72 enum qed_dcbx_sf_ieee_type {
73 QED_DCBX_SF_IEEE_ETHTYPE,
74 QED_DCBX_SF_IEEE_TCP_PORT,
75 QED_DCBX_SF_IEEE_UDP_PORT,
76 QED_DCBX_SF_IEEE_TCP_UDP_PORT
79 struct qed_app_entry {
81 enum qed_dcbx_sf_ieee_type sf_ieee;
85 enum dcbx_protocol_type proto_type;
88 struct qed_dcbx_params {
89 struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL];
98 u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES];
99 u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES];
100 u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES];
101 struct qed_dbcx_pfc_params pfc;
105 struct qed_dcbx_admin_params {
106 struct qed_dcbx_params params;
110 struct qed_dcbx_remote_params {
111 struct qed_dcbx_params params;
115 struct qed_dcbx_operational_params {
116 struct qed_dcbx_app_prio app_prio;
117 struct qed_dcbx_params params;
126 struct qed_dcbx_get {
127 struct qed_dcbx_operational_params operational;
128 struct qed_dcbx_lldp_remote lldp_remote;
129 struct qed_dcbx_lldp_local lldp_local;
130 struct qed_dcbx_remote_params remote;
131 struct qed_dcbx_admin_params local;
134 enum qed_nvm_images {
135 QED_NVM_IMAGE_ISCSI_CFG,
136 QED_NVM_IMAGE_FCOE_CFG,
138 QED_NVM_IMAGE_NVM_CFG1,
139 QED_NVM_IMAGE_DEFAULT_CFG,
140 QED_NVM_IMAGE_NVM_META,
143 struct qed_link_eee_params {
145 #define QED_EEE_1G_ADV BIT(0)
146 #define QED_EEE_10G_ADV BIT(1)
148 /* Capabilities are represented using QED_EEE_*_ADV values */
161 struct qed_mfw_tlv_eth {
163 bool lso_maxoff_size_set;
165 bool lso_minseg_size_set;
169 bool tx_descr_size_set;
171 bool rx_descr_size_set;
175 bool tcp4_offloads_set;
177 bool tcp6_offloads_set;
179 bool tx_descr_qdepth_set;
181 bool rx_descr_qdepth_set;
183 #define QED_MFW_TLV_IOV_OFFLOAD_NONE (0)
184 #define QED_MFW_TLV_IOV_OFFLOAD_MULTIQUEUE (1)
185 #define QED_MFW_TLV_IOV_OFFLOAD_VEB (2)
186 #define QED_MFW_TLV_IOV_OFFLOAD_VEPA (3)
187 bool iov_offload_set;
193 bool num_txqs_full_set;
195 bool num_rxqs_full_set;
198 #define QED_MFW_TLV_TIME_SIZE 14
199 struct qed_mfw_tlv_time {
209 struct qed_mfw_tlv_fcoe {
211 bool scsi_timeout_set;
225 bool num_npiv_ids_set;
227 bool switch_name_set;
229 bool switch_portnum_set;
231 bool switch_portid_set;
233 bool vendor_name_set;
235 bool switch_model_set;
236 u8 switch_fw_version[8];
237 bool switch_fw_version_set;
243 #define QED_MFW_TLV_PORT_STATE_OFFLINE (0)
244 #define QED_MFW_TLV_PORT_STATE_LOOP (1)
245 #define QED_MFW_TLV_PORT_STATE_P2P (2)
246 #define QED_MFW_TLV_PORT_STATE_FABRIC (3)
248 u16 fip_tx_descr_size;
249 bool fip_tx_descr_size_set;
250 u16 fip_rx_descr_size;
251 bool fip_rx_descr_size_set;
253 bool link_failures_set;
254 u8 fcoe_boot_progress;
255 bool fcoe_boot_progress_set;
261 bool fcoe_txq_depth_set;
263 bool fcoe_rxq_depth_set;
265 bool fcoe_rx_frames_set;
267 bool fcoe_rx_bytes_set;
269 bool fcoe_tx_frames_set;
271 bool fcoe_tx_bytes_set;
274 u32 crc_err_src_fcid[5];
275 bool crc_err_src_fcid_set[5];
276 struct qed_mfw_tlv_time crc_err[5];
282 bool primtive_err_set;
284 bool disparity_err_set;
285 u16 code_violation_err;
286 bool code_violation_err_set;
288 bool flogi_param_set[4];
289 struct qed_mfw_tlv_time flogi_tstamp;
290 u32 flogi_acc_param[4];
291 bool flogi_acc_param_set[4];
292 struct qed_mfw_tlv_time flogi_acc_tstamp;
295 struct qed_mfw_tlv_time flogi_rjt_tstamp;
308 u32 plogi_dst_fcid[5];
309 bool plogi_dst_fcid_set[5];
310 struct qed_mfw_tlv_time plogi_tstamp[5];
311 u32 plogi_acc_src_fcid[5];
312 bool plogi_acc_src_fcid_set[5];
313 struct qed_mfw_tlv_time plogi_acc_tstamp[5];
320 u32 plogo_src_fcid[5];
321 bool plogo_src_fcid_set[5];
322 struct qed_mfw_tlv_time plogo_tstamp[5];
334 bool rx_abts_acc_set;
336 bool rx_abts_rjt_set;
337 u32 abts_dst_fcid[5];
338 bool abts_dst_fcid_set[5];
339 struct qed_mfw_tlv_time abts_tstamp[5];
342 u32 rx_rscn_nport[4];
343 bool rx_rscn_nport_set[4];
347 bool abort_task_sets_set;
371 bool scsi_cond_met_set;
376 u8 scsi_inter_cond_met;
377 bool scsi_inter_cond_met_set;
378 u8 scsi_rsv_conflicts;
379 bool scsi_rsv_conflicts_set;
381 bool scsi_tsk_full_set;
383 bool scsi_aca_active_set;
385 bool scsi_tsk_abort_set;
387 bool scsi_rx_chk_set[5];
388 struct qed_mfw_tlv_time scsi_chk_tstamp[5];
391 struct qed_mfw_tlv_iscsi {
393 bool target_llmnr_set;
395 bool header_digest_set;
397 bool data_digest_set;
399 #define QED_MFW_TLV_AUTH_METHOD_NONE (1)
400 #define QED_MFW_TLV_AUTH_METHOD_CHAP (2)
401 #define QED_MFW_TLV_AUTH_METHOD_MUTUAL_CHAP (3)
402 bool auth_method_set;
403 u16 boot_taget_portal;
404 bool boot_taget_portal_set;
408 bool tx_desc_size_set;
410 bool rx_desc_size_set;
412 bool boot_progress_set;
414 bool tx_desc_qdepth_set;
416 bool rx_desc_qdepth_set;
427 enum qed_db_rec_width {
432 enum qed_db_rec_space {
437 #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
438 (void __iomem *)(reg_addr))
440 #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
442 #define DIRECT_REG_WR64(reg_addr, val) writeq((u64)val, \
443 (void __iomem *)(reg_addr))
445 #define QED_COALESCE_MAX 0x1FF
446 #define QED_DEFAULT_RX_USECS 12
447 #define QED_DEFAULT_TX_USECS 48
452 struct qed_eth_pf_params {
453 /* The following parameters are used during HW-init
454 * and these parameters need to be passed as arguments
455 * to update_pf_params routine invoked before slowpath start
459 /* per-VF number of CIDs */
461 #define ETH_PF_PARAMS_VF_CONS_DEFAULT (32)
463 /* To enable arfs, previous to HW-init a positive number needs to be
464 * set [as filters require allocated searcher ILT memory].
465 * This will set the maximal number of configured steering-filters.
467 u32 num_arfs_filters;
470 struct qed_fcoe_pf_params {
471 /* The following parameters are used during protocol-init */
472 u64 glbl_q_params_addr;
473 u64 bdq_pbl_base_addr[2];
475 /* The following parameters are used during HW-init
476 * and these parameters need to be passed as arguments
477 * to update_pf_params routine invoked before slowpath start
482 /* The following parameters are used during protocol-init */
483 u16 sq_num_pbl_pages;
486 u16 cmdq_num_entries;
487 u16 rq_buffer_log_size;
490 u16 bdq_xoff_threshold[2];
491 u16 bdq_xon_threshold[2];
493 u8 num_cqs; /* num of global CQs */
499 u8 bdq_pbl_num_entries[2];
502 /* Most of the parameters below are described in the FW iSCSI / TCP HSI */
503 struct qed_iscsi_pf_params {
504 u64 glbl_q_params_addr;
505 u64 bdq_pbl_base_addr[3];
507 u16 cmdq_num_entries;
511 /* The following parameters are used during HW-init
512 * and these parameters need to be passed as arguments
513 * to update_pf_params routine invoked before slowpath start
518 /* The following parameters are used during protocol-init */
519 u16 half_way_close_timeout;
520 u16 bdq_xoff_threshold[3];
521 u16 bdq_xon_threshold[3];
522 u16 cmdq_xoff_threshold;
523 u16 cmdq_xon_threshold;
526 u8 num_sq_pages_in_ring;
527 u8 num_r2tq_pages_in_ring;
528 u8 num_uhq_pages_in_ring;
540 u8 soc_num_of_blocks_log;
541 u8 bdq_pbl_num_entries[3];
544 struct qed_rdma_pf_params {
545 /* Supplied to QED during resource allocation (may affect the ILT and
548 u32 min_dpis; /* number of requested DPIs */
549 u32 num_qps; /* number of requested Queue Pairs */
550 u32 num_srqs; /* number of requested SRQ */
551 u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */
552 u8 gl_pi; /* protocol index */
554 /* Will allocate rate limiters to be used with QPs */
558 struct qed_pf_params {
559 struct qed_eth_pf_params eth_pf_params;
560 struct qed_fcoe_pf_params fcoe_pf_params;
561 struct qed_iscsi_pf_params iscsi_pf_params;
562 struct qed_rdma_pf_params rdma_pf_params;
573 struct status_block_e4 *sb_virt;
575 u32 sb_ack; /* Last given ack */
577 void __iomem *igu_addr;
579 #define QED_SB_INFO_INIT 0x1
580 #define QED_SB_INFO_SETUP 0x2
582 struct qed_dev *cdev;
585 enum qed_hw_err_type {
587 QED_HW_ERR_MFW_RESP_FAIL,
589 QED_HW_ERR_DMAE_FAIL,
590 QED_HW_ERR_RAMROD_FAIL,
591 QED_HW_ERR_FW_ASSERT,
601 struct qed_dev_info {
602 unsigned long pci_mem_start;
603 unsigned long pci_mem_end;
604 unsigned int pci_irq;
617 #define QED_MFW_VERSION_0_MASK 0x000000FF
618 #define QED_MFW_VERSION_0_OFFSET 0
619 #define QED_MFW_VERSION_1_MASK 0x0000FF00
620 #define QED_MFW_VERSION_1_OFFSET 8
621 #define QED_MFW_VERSION_2_MASK 0x00FF0000
622 #define QED_MFW_VERSION_2_OFFSET 16
623 #define QED_MFW_VERSION_3_MASK 0xFF000000
624 #define QED_MFW_VERSION_3_OFFSET 24
628 bool b_inter_pf_switch;
638 #define QED_MBI_VERSION_0_MASK 0x000000FF
639 #define QED_MBI_VERSION_0_OFFSET 0
640 #define QED_MBI_VERSION_1_MASK 0x0000FF00
641 #define QED_MBI_VERSION_1_OFFSET 8
642 #define QED_MBI_VERSION_2_MASK 0x00FF0000
643 #define QED_MBI_VERSION_2_OFFSET 16
645 enum qed_dev_type dev_type;
647 /* Output parameters for qede */
656 QED_SB_TYPE_L2_QUEUE,
668 QED_FEC_MODE_NONE = BIT(0),
669 QED_FEC_MODE_FIRECODE = BIT(1),
670 QED_FEC_MODE_RS = BIT(2),
671 QED_FEC_MODE_AUTO = BIT(3),
672 QED_FEC_MODE_UNSUPPORTED = BIT(4),
675 struct qed_link_params {
679 #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0)
680 #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1)
681 #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2)
682 #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3)
683 #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4)
684 #define QED_LINK_OVERRIDE_EEE_CONFIG BIT(5)
685 #define QED_LINK_OVERRIDE_FEC_CONFIG BIT(6)
688 __ETHTOOL_DECLARE_LINK_MODE_MASK(adv_speeds);
692 #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0)
693 #define QED_LINK_PAUSE_RX_ENABLE BIT(1)
694 #define QED_LINK_PAUSE_TX_ENABLE BIT(2)
697 #define QED_LINK_LOOPBACK_NONE BIT(0)
698 #define QED_LINK_LOOPBACK_INT_PHY BIT(1)
699 #define QED_LINK_LOOPBACK_EXT_PHY BIT(2)
700 #define QED_LINK_LOOPBACK_EXT BIT(3)
701 #define QED_LINK_LOOPBACK_MAC BIT(4)
702 #define QED_LINK_LOOPBACK_CNIG_AH_ONLY_0123 BIT(5)
703 #define QED_LINK_LOOPBACK_CNIG_AH_ONLY_2301 BIT(6)
704 #define QED_LINK_LOOPBACK_PCS_AH_ONLY BIT(7)
705 #define QED_LINK_LOOPBACK_REVERSE_MAC_AH_ONLY BIT(8)
706 #define QED_LINK_LOOPBACK_INT_PHY_FEA_AH_ONLY BIT(9)
708 struct qed_link_eee_params eee;
712 struct qed_link_output {
715 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported_caps);
716 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised_caps);
717 __ETHTOOL_DECLARE_LINK_MODE_MASK(lp_caps);
719 u32 speed; /* In Mb/s */
720 u8 duplex; /* In DUPLEX defs */
721 u8 port; /* In PORT defs */
725 /* EEE - capability & param */
729 struct qed_link_eee_params eee;
735 struct qed_probe_params {
736 enum qed_protocol protocol;
743 #define QED_DRV_VER_STR_SIZE 12
744 struct qed_slowpath_params {
750 u8 name[QED_DRV_VER_STR_SIZE];
753 #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */
755 struct qed_int_info {
756 struct msix_entry *msix;
759 /* This should be updated by the protocol driver */
763 struct qed_generic_tlvs {
764 #define QED_TLV_IP_CSUM BIT(0)
765 #define QED_TLV_LSO BIT(1)
767 #define QED_TLV_MAC_COUNT 3
768 u8 mac[QED_TLV_MAC_COUNT][ETH_ALEN];
771 #define QED_I2C_DEV_ADDR_A0 0xA0
772 #define QED_I2C_DEV_ADDR_A2 0xA2
774 #define QED_NVM_SIGNATURE 0x12435687
776 enum qed_nvm_flash_cmd {
777 QED_NVM_FLASH_CMD_FILE_DATA = 0x2,
778 QED_NVM_FLASH_CMD_FILE_START = 0x3,
779 QED_NVM_FLASH_CMD_NVM_CHANGE = 0x4,
780 QED_NVM_FLASH_CMD_NVM_CFG_ID = 0x5,
781 QED_NVM_FLASH_CMD_NVM_MAX,
785 struct qed_dev *cdev;
786 struct devlink_health_reporter *fw_reporter;
789 struct qed_common_cb_ops {
790 void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc);
791 void (*link_update)(void *dev, struct qed_link_output *link);
792 void (*schedule_recovery_handler)(void *dev);
793 void (*schedule_hw_err_handler)(void *dev,
794 enum qed_hw_err_type err_type);
795 void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type);
796 void (*get_generic_tlv_data)(void *dev, struct qed_generic_tlvs *data);
797 void (*get_protocol_tlv_data)(void *dev, void *data);
798 void (*bw_update)(void *dev);
801 struct qed_selftest_ops {
803 * @brief selftest_interrupt - Perform interrupt test
807 * @return 0 on success, error otherwise.
809 int (*selftest_interrupt)(struct qed_dev *cdev);
812 * @brief selftest_memory - Perform memory test
816 * @return 0 on success, error otherwise.
818 int (*selftest_memory)(struct qed_dev *cdev);
821 * @brief selftest_register - Perform register test
825 * @return 0 on success, error otherwise.
827 int (*selftest_register)(struct qed_dev *cdev);
830 * @brief selftest_clock - Perform clock test
834 * @return 0 on success, error otherwise.
836 int (*selftest_clock)(struct qed_dev *cdev);
839 * @brief selftest_nvram - Perform nvram test
843 * @return 0 on success, error otherwise.
845 int (*selftest_nvram) (struct qed_dev *cdev);
848 struct qed_common_ops {
849 struct qed_selftest_ops *selftest;
851 struct qed_dev* (*probe)(struct pci_dev *dev,
852 struct qed_probe_params *params);
854 void (*remove)(struct qed_dev *cdev);
856 int (*set_power_state)(struct qed_dev *cdev, pci_power_t state);
858 void (*set_name) (struct qed_dev *cdev, char name[]);
860 /* Client drivers need to make this call before slowpath_start.
861 * PF params required for the call before slowpath_start is
862 * documented within the qed_pf_params structure definition.
864 void (*update_pf_params)(struct qed_dev *cdev,
865 struct qed_pf_params *params);
867 int (*slowpath_start)(struct qed_dev *cdev,
868 struct qed_slowpath_params *params);
870 int (*slowpath_stop)(struct qed_dev *cdev);
872 /* Requests to use `cnt' interrupts for fastpath.
873 * upon success, returns number of interrupts allocated for fastpath.
875 int (*set_fp_int)(struct qed_dev *cdev, u16 cnt);
877 /* Fills `info' with pointers required for utilizing interrupts */
878 int (*get_fp_int)(struct qed_dev *cdev, struct qed_int_info *info);
880 u32 (*sb_init)(struct qed_dev *cdev,
881 struct qed_sb_info *sb_info,
883 dma_addr_t sb_phy_addr,
885 enum qed_sb_type type);
887 u32 (*sb_release)(struct qed_dev *cdev,
888 struct qed_sb_info *sb_info,
890 enum qed_sb_type type);
892 void (*simd_handler_config)(struct qed_dev *cdev,
895 void (*handler)(void *));
897 void (*simd_handler_clean)(struct qed_dev *cdev, int index);
899 int (*dbg_grc)(struct qed_dev *cdev, void *buffer, u32 *num_dumped_bytes);
901 int (*dbg_grc_size)(struct qed_dev *cdev);
903 int (*dbg_all_data)(struct qed_dev *cdev, void *buffer);
905 int (*dbg_all_data_size)(struct qed_dev *cdev);
907 int (*report_fatal_error)(struct devlink *devlink,
908 enum qed_hw_err_type err_type);
911 * @brief can_link_change - can the instance change the link or not
915 * @return true if link-change is allowed, false otherwise.
917 bool (*can_link_change)(struct qed_dev *cdev);
920 * @brief set_link - set links according to params
923 * @param params - values used to override the default link configuration
925 * @return 0 on success, error otherwise.
927 int (*set_link)(struct qed_dev *cdev,
928 struct qed_link_params *params);
931 * @brief get_link - returns the current link state.
934 * @param if_link - structure to be filled with current link configuration.
936 void (*get_link)(struct qed_dev *cdev,
937 struct qed_link_output *if_link);
940 * @brief - drains chip in case Tx completions fail to arrive due to pause.
944 int (*drain)(struct qed_dev *cdev);
947 * @brief update_msglvl - update module debug level
953 void (*update_msglvl)(struct qed_dev *cdev,
957 int (*chain_alloc)(struct qed_dev *cdev,
958 struct qed_chain *chain,
959 struct qed_chain_init_params *params);
961 void (*chain_free)(struct qed_dev *cdev,
962 struct qed_chain *p_chain);
965 * @brief nvm_flash - Flash nvm data.
968 * @param name - file containing the data
970 * @return 0 on success, error otherwise.
972 int (*nvm_flash)(struct qed_dev *cdev, const char *name);
975 * @brief nvm_get_image - reads an entire image from nvram
978 * @param type - type of the request nvram image
979 * @param buf - preallocated buffer to fill with the image
980 * @param len - length of the allocated buffer
982 * @return 0 on success, error otherwise
984 int (*nvm_get_image)(struct qed_dev *cdev,
985 enum qed_nvm_images type, u8 *buf, u16 len);
988 * @brief set_coalesce - Configure Rx coalesce value in usec
991 * @param rx_coal - Rx coalesce value in usec
992 * @param tx_coal - Tx coalesce value in usec
993 * @param qid - Queue index
994 * @param sb_id - Status Block Id
996 * @return 0 on success, error otherwise.
998 int (*set_coalesce)(struct qed_dev *cdev,
999 u16 rx_coal, u16 tx_coal, void *handle);
1002 * @brief set_led - Configure LED mode
1005 * @param mode - LED mode
1007 * @return 0 on success, error otherwise.
1009 int (*set_led)(struct qed_dev *cdev,
1010 enum qed_led_mode mode);
1013 * @brief attn_clr_enable - Prevent attentions from being reasserted
1018 void (*attn_clr_enable)(struct qed_dev *cdev, bool clr_enable);
1021 * @brief db_recovery_add - add doorbell information to the doorbell
1022 * recovery mechanism.
1025 * @param db_addr - doorbell address
1026 * @param db_data - address of where db_data is stored
1027 * @param db_is_32b - doorbell is 32b pr 64b
1028 * @param db_is_user - doorbell recovery addresses are user or kernel space
1030 int (*db_recovery_add)(struct qed_dev *cdev,
1031 void __iomem *db_addr,
1033 enum qed_db_rec_width db_width,
1034 enum qed_db_rec_space db_space);
1037 * @brief db_recovery_del - remove doorbell information from the doorbell
1038 * recovery mechanism. db_data serves as key (db_addr is not unique).
1041 * @param db_addr - doorbell address
1042 * @param db_data - address where db_data is stored. Serves as key for the
1045 int (*db_recovery_del)(struct qed_dev *cdev,
1046 void __iomem *db_addr, void *db_data);
1049 * @brief recovery_process - Trigger a recovery process
1053 * @return 0 on success, error otherwise.
1055 int (*recovery_process)(struct qed_dev *cdev);
1058 * @brief recovery_prolog - Execute the prolog operations of a recovery process
1062 * @return 0 on success, error otherwise.
1064 int (*recovery_prolog)(struct qed_dev *cdev);
1067 * @brief update_drv_state - API to inform the change in the driver state.
1073 int (*update_drv_state)(struct qed_dev *cdev, bool active);
1076 * @brief update_mac - API to inform the change in the mac address
1082 int (*update_mac)(struct qed_dev *cdev, u8 *mac);
1085 * @brief update_mtu - API to inform the change in the mtu
1091 int (*update_mtu)(struct qed_dev *cdev, u16 mtu);
1094 * @brief update_wol - update of changes in the WoL configuration
1097 * @param enabled - true iff WoL should be enabled.
1099 int (*update_wol) (struct qed_dev *cdev, bool enabled);
1102 * @brief read_module_eeprom
1105 * @param buf - buffer
1106 * @param dev_addr - PHY device memory region
1107 * @param offset - offset into eeprom contents to be read
1108 * @param len - buffer length, i.e., max bytes to be read
1110 int (*read_module_eeprom)(struct qed_dev *cdev,
1111 char *buf, u8 dev_addr, u32 offset, u32 len);
1114 * @brief get_affin_hwfn_idx
1118 u8 (*get_affin_hwfn_idx)(struct qed_dev *cdev);
1121 * @brief read_nvm_cfg - Read NVM config attribute value.
1123 * @param buf - buffer
1124 * @param cmd - NVM CFG command id
1125 * @param entity_id - Entity id
1128 int (*read_nvm_cfg)(struct qed_dev *cdev, u8 **buf, u32 cmd,
1131 * @brief read_nvm_cfg - Read NVM config attribute value.
1133 * @param cmd - NVM CFG command id
1135 * @return config id length, 0 on error.
1137 int (*read_nvm_cfg_len)(struct qed_dev *cdev, u32 cmd);
1140 * @brief set_grc_config - Configure value for grc config id.
1142 * @param cfg_id - grc config id
1143 * @param val - grc config value
1146 int (*set_grc_config)(struct qed_dev *cdev, u32 cfg_id, u32 val);
1148 struct devlink* (*devlink_register)(struct qed_dev *cdev);
1150 void (*devlink_unregister)(struct devlink *devlink);
1153 #define MASK_FIELD(_name, _value) \
1154 ((_value) &= (_name ## _MASK))
1156 #define FIELD_VALUE(_name, _value) \
1157 ((_value & _name ## _MASK) << _name ## _SHIFT)
1159 #define SET_FIELD(value, name, flag) \
1161 (value) &= ~(name ## _MASK << name ## _SHIFT); \
1162 (value) |= (((u64)flag) << (name ## _SHIFT)); \
1165 #define GET_FIELD(value, name) \
1166 (((value) >> (name ## _SHIFT)) & name ## _MASK)
1168 #define GET_MFW_FIELD(name, field) \
1169 (((name) & (field ## _MASK)) >> (field ## _OFFSET))
1171 #define SET_MFW_FIELD(name, field, value) \
1173 (name) &= ~(field ## _MASK); \
1174 (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK));\
1177 #define DB_ADDR_SHIFT(addr) ((addr) << DB_PWM_ADDR_OFFSET_SHIFT)
1179 /* Debug print definitions */
1180 #define DP_ERR(cdev, fmt, ...) \
1182 pr_err("[%s:%d(%s)]" fmt, \
1183 __func__, __LINE__, \
1184 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1188 #define DP_NOTICE(cdev, fmt, ...) \
1190 if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
1191 pr_notice("[%s:%d(%s)]" fmt, \
1192 __func__, __LINE__, \
1193 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1199 #define DP_INFO(cdev, fmt, ...) \
1201 if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \
1202 pr_notice("[%s:%d(%s)]" fmt, \
1203 __func__, __LINE__, \
1204 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1209 #define DP_VERBOSE(cdev, module, fmt, ...) \
1211 if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \
1212 ((cdev)->dp_module & module))) { \
1213 pr_notice("[%s:%d(%s)]" fmt, \
1214 __func__, __LINE__, \
1215 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1221 QED_LEVEL_VERBOSE = 0x0,
1222 QED_LEVEL_INFO = 0x1,
1223 QED_LEVEL_NOTICE = 0x2,
1224 QED_LEVEL_ERR = 0x3,
1227 #define QED_LOG_LEVEL_SHIFT (30)
1228 #define QED_LOG_VERBOSE_MASK (0x3fffffff)
1229 #define QED_LOG_INFO_MASK (0x40000000)
1230 #define QED_LOG_NOTICE_MASK (0x80000000)
1233 QED_MSG_SPQ = 0x10000,
1234 QED_MSG_STATS = 0x20000,
1235 QED_MSG_DCB = 0x40000,
1236 QED_MSG_IOV = 0x80000,
1237 QED_MSG_SP = 0x100000,
1238 QED_MSG_STORAGE = 0x200000,
1239 QED_MSG_CXT = 0x800000,
1240 QED_MSG_LL2 = 0x1000000,
1241 QED_MSG_ILT = 0x2000000,
1242 QED_MSG_RDMA = 0x4000000,
1243 QED_MSG_DEBUG = 0x8000000,
1244 /* to be added...up to 0x8000000 */
1253 struct qed_eth_stats_common {
1254 u64 no_buff_discards;
1255 u64 packet_too_big_discard;
1263 u64 mftag_filter_discards;
1264 u64 mac_filter_discards;
1265 u64 gft_filter_drop;
1272 u64 tx_err_drop_pkts;
1273 u64 tpa_coalesced_pkts;
1274 u64 tpa_coalesced_events;
1276 u64 tpa_not_coalesced_pkts;
1277 u64 tpa_coalesced_bytes;
1280 u64 rx_64_byte_packets;
1281 u64 rx_65_to_127_byte_packets;
1282 u64 rx_128_to_255_byte_packets;
1283 u64 rx_256_to_511_byte_packets;
1284 u64 rx_512_to_1023_byte_packets;
1285 u64 rx_1024_to_1518_byte_packets;
1287 u64 rx_mac_crtl_frames;
1288 u64 rx_pause_frames;
1290 u64 rx_align_errors;
1291 u64 rx_carrier_errors;
1292 u64 rx_oversize_packets;
1294 u64 rx_undersize_packets;
1296 u64 tx_64_byte_packets;
1297 u64 tx_65_to_127_byte_packets;
1298 u64 tx_128_to_255_byte_packets;
1299 u64 tx_256_to_511_byte_packets;
1300 u64 tx_512_to_1023_byte_packets;
1301 u64 tx_1024_to_1518_byte_packets;
1302 u64 tx_pause_frames;
1307 u64 rx_mac_uc_packets;
1308 u64 rx_mac_mc_packets;
1309 u64 rx_mac_bc_packets;
1310 u64 rx_mac_frames_ok;
1312 u64 tx_mac_uc_packets;
1313 u64 tx_mac_mc_packets;
1314 u64 tx_mac_bc_packets;
1315 u64 tx_mac_ctrl_frames;
1316 u64 link_change_count;
1319 struct qed_eth_stats_bb {
1320 u64 rx_1519_to_1522_byte_packets;
1321 u64 rx_1519_to_2047_byte_packets;
1322 u64 rx_2048_to_4095_byte_packets;
1323 u64 rx_4096_to_9216_byte_packets;
1324 u64 rx_9217_to_16383_byte_packets;
1325 u64 tx_1519_to_2047_byte_packets;
1326 u64 tx_2048_to_4095_byte_packets;
1327 u64 tx_4096_to_9216_byte_packets;
1328 u64 tx_9217_to_16383_byte_packets;
1329 u64 tx_lpi_entry_count;
1330 u64 tx_total_collisions;
1333 struct qed_eth_stats_ah {
1334 u64 rx_1519_to_max_byte_packets;
1335 u64 tx_1519_to_max_byte_packets;
1338 struct qed_eth_stats {
1339 struct qed_eth_stats_common common;
1342 struct qed_eth_stats_bb bb;
1343 struct qed_eth_stats_ah ah;
1347 #define QED_SB_IDX 0x0002
1350 #define TX_PI(tc) (RX_PI + 1 + tc)
1352 struct qed_sb_cnt_info {
1353 /* Original, current, and free SBs for PF */
1358 /* Original, current and free SBS for child VFs */
1364 static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
1369 prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
1370 STATUS_BLOCK_E4_PROD_INDEX_MASK;
1371 if (sb_info->sb_ack != prod) {
1372 sb_info->sb_ack = prod;
1382 * @brief This function creates an update command for interrupts that is
1383 * written to the IGU.
1385 * @param sb_info - This is the structure allocated and
1386 * initialized per status block. Assumption is
1387 * that it was initialized using qed_sb_init
1388 * @param int_cmd - Enable/Disable/Nop
1389 * @param upd_flg - whether igu consumer should be
1392 * @return inline void
1394 static inline void qed_sb_ack(struct qed_sb_info *sb_info,
1395 enum igu_int_cmd int_cmd,
1400 igu_ack = ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1401 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1402 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1403 (IGU_SEG_ACCESS_REG <<
1404 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1406 DIRECT_REG_WR(sb_info->igu_addr, igu_ack);
1408 /* Both segments (interrupts & acks) are written to same place address;
1409 * Need to guarantee all commands will be received (in-order) by HW.
1414 static inline void __internal_ram_wr(void *p_hwfn,
1422 for (i = 0; i < size / sizeof(*data); i++)
1423 DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
1426 static inline void internal_ram_wr(void __iomem *addr,
1430 __internal_ram_wr(NULL, addr, size, data);
1436 QED_RSS_IPV4_TCP = 0x4,
1437 QED_RSS_IPV6_TCP = 0x8,
1438 QED_RSS_IPV4_UDP = 0x10,
1439 QED_RSS_IPV6_UDP = 0x20,
1442 #define QED_RSS_IND_TABLE_SIZE 128
1443 #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */