2 * Intel Atom SOC Power Management Controller Header File
3 * Copyright (c) 2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 #include <linux/bits.h>
21 /* ValleyView Power Control Unit PCI Device ID */
22 #define PCI_DEVICE_ID_VLV_PMC 0x0F1C
23 /* CherryTrail Power Control Unit PCI Device ID */
24 #define PCI_DEVICE_ID_CHT_PMC 0x229C
26 /* PMC Memory mapped IO registers */
27 #define PMC_BASE_ADDR_OFFSET 0x44
28 #define PMC_BASE_ADDR_MASK 0xFFFFFE00
29 #define PMC_MMIO_REG_LEN 0x100
30 #define PMC_REG_BIT_WIDTH 32
32 /* BIOS uses FUNC_DIS to disable specific function */
33 #define PMC_FUNC_DIS 0x34
34 #define PMC_FUNC_DIS_2 0x38
36 /* CHT specific bits in FUNC_DIS2 register */
37 #define BIT_FD_GMM BIT(3)
38 #define BIT_FD_ISH BIT(4)
40 /* S0ix wake event control */
41 #define PMC_S0IX_WAKE_EN 0x3C
43 #define BIT_LPC_CLOCK_RUN BIT(4)
44 #define BIT_SHARED_IRQ_GPSC BIT(5)
45 #define BIT_ORED_DEDICATED_IRQ_GPSS BIT(18)
46 #define BIT_ORED_DEDICATED_IRQ_GPSC BIT(19)
47 #define BIT_SHARED_IRQ_GPSS BIT(20)
49 #define PMC_WAKE_EN_SETTING ~(BIT_LPC_CLOCK_RUN | \
50 BIT_SHARED_IRQ_GPSC | \
51 BIT_ORED_DEDICATED_IRQ_GPSS | \
52 BIT_ORED_DEDICATED_IRQ_GPSC | \
55 /* The timers accumulate time spent in sleep state */
56 #define PMC_S0IR_TMR 0x80
57 #define PMC_S0I1_TMR 0x84
58 #define PMC_S0I2_TMR 0x88
59 #define PMC_S0I3_TMR 0x8C
60 #define PMC_S0_TMR 0x90
61 /* Sleep state counter is in units of of 32us */
62 #define PMC_TMR_SHIFT 5
64 /* Power status of power islands */
67 #define PMC_PSS_BIT_GBE BIT(0)
68 #define PMC_PSS_BIT_SATA BIT(1)
69 #define PMC_PSS_BIT_HDA BIT(2)
70 #define PMC_PSS_BIT_SEC BIT(3)
71 #define PMC_PSS_BIT_PCIE BIT(4)
72 #define PMC_PSS_BIT_LPSS BIT(5)
73 #define PMC_PSS_BIT_LPE BIT(6)
74 #define PMC_PSS_BIT_DFX BIT(7)
75 #define PMC_PSS_BIT_USH_CTRL BIT(8)
76 #define PMC_PSS_BIT_USH_SUS BIT(9)
77 #define PMC_PSS_BIT_USH_VCCS BIT(10)
78 #define PMC_PSS_BIT_USH_VCCA BIT(11)
79 #define PMC_PSS_BIT_OTG_CTRL BIT(12)
80 #define PMC_PSS_BIT_OTG_VCCS BIT(13)
81 #define PMC_PSS_BIT_OTG_VCCA_CLK BIT(14)
82 #define PMC_PSS_BIT_OTG_VCCA BIT(15)
83 #define PMC_PSS_BIT_USB BIT(16)
84 #define PMC_PSS_BIT_USB_SUS BIT(17)
86 /* CHT specific bits in PSS register */
87 #define PMC_PSS_BIT_CHT_UFS BIT(7)
88 #define PMC_PSS_BIT_CHT_UXD BIT(11)
89 #define PMC_PSS_BIT_CHT_UXD_FD BIT(12)
90 #define PMC_PSS_BIT_CHT_UX_ENG BIT(15)
91 #define PMC_PSS_BIT_CHT_USB_SUS BIT(16)
92 #define PMC_PSS_BIT_CHT_GMM BIT(17)
93 #define PMC_PSS_BIT_CHT_ISH BIT(18)
94 #define PMC_PSS_BIT_CHT_DFX_MASTER BIT(26)
95 #define PMC_PSS_BIT_CHT_DFX_CLUSTER1 BIT(27)
96 #define PMC_PSS_BIT_CHT_DFX_CLUSTER2 BIT(28)
97 #define PMC_PSS_BIT_CHT_DFX_CLUSTER3 BIT(29)
98 #define PMC_PSS_BIT_CHT_DFX_CLUSTER4 BIT(30)
99 #define PMC_PSS_BIT_CHT_DFX_CLUSTER5 BIT(31)
101 /* These registers reflect D3 status of functions */
102 #define PMC_D3_STS_0 0xA0
104 #define BIT_LPSS1_F0_DMA BIT(0)
105 #define BIT_LPSS1_F1_PWM1 BIT(1)
106 #define BIT_LPSS1_F2_PWM2 BIT(2)
107 #define BIT_LPSS1_F3_HSUART1 BIT(3)
108 #define BIT_LPSS1_F4_HSUART2 BIT(4)
109 #define BIT_LPSS1_F5_SPI BIT(5)
110 #define BIT_LPSS1_F6_XXX BIT(6)
111 #define BIT_LPSS1_F7_XXX BIT(7)
112 #define BIT_SCC_EMMC BIT(8)
113 #define BIT_SCC_SDIO BIT(9)
114 #define BIT_SCC_SDCARD BIT(10)
115 #define BIT_SCC_MIPI BIT(11)
116 #define BIT_HDA BIT(12)
117 #define BIT_LPE BIT(13)
118 #define BIT_OTG BIT(14)
119 #define BIT_USH BIT(15)
120 #define BIT_GBE BIT(16)
121 #define BIT_SATA BIT(17)
122 #define BIT_USB_EHCI BIT(18)
123 #define BIT_SEC BIT(19)
124 #define BIT_PCIE_PORT0 BIT(20)
125 #define BIT_PCIE_PORT1 BIT(21)
126 #define BIT_PCIE_PORT2 BIT(22)
127 #define BIT_PCIE_PORT3 BIT(23)
128 #define BIT_LPSS2_F0_DMA BIT(24)
129 #define BIT_LPSS2_F1_I2C1 BIT(25)
130 #define BIT_LPSS2_F2_I2C2 BIT(26)
131 #define BIT_LPSS2_F3_I2C3 BIT(27)
132 #define BIT_LPSS2_F4_I2C4 BIT(28)
133 #define BIT_LPSS2_F5_I2C5 BIT(29)
134 #define BIT_LPSS2_F6_I2C6 BIT(30)
135 #define BIT_LPSS2_F7_I2C7 BIT(31)
137 #define PMC_D3_STS_1 0xA4
138 #define BIT_SMB BIT(0)
139 #define BIT_OTG_SS_PHY BIT(1)
140 #define BIT_USH_SS_PHY BIT(2)
141 #define BIT_DFX BIT(3)
143 /* CHT specific bits in PMC_D3_STS_1 register */
144 #define BIT_STS_GMM BIT(1)
145 #define BIT_STS_ISH BIT(2)
147 /* PMC I/O Registers */
148 #define ACPI_BASE_ADDR_OFFSET 0x40
149 #define ACPI_BASE_ADDR_MASK 0xFFFFFE00
150 #define ACPI_MMIO_REG_LEN 0x100
153 #define SLEEP_TYPE_MASK GENMASK(12, 10)
154 #define SLEEP_TYPE_S5 0x1C00
155 #define SLEEP_ENABLE BIT(13)
157 extern int pmc_atom_read(int offset, u32 *value);
158 extern int pmc_atom_write(int offset, u32 value);
160 #endif /* PMC_ATOM_H */