1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Intel Atom SOC Power Management Controller Header File
4 * Copyright (c) 2014, Intel Corporation.
10 #include <linux/bits.h>
12 /* ValleyView Power Control Unit PCI Device ID */
13 #define PCI_DEVICE_ID_VLV_PMC 0x0F1C
14 /* CherryTrail Power Control Unit PCI Device ID */
15 #define PCI_DEVICE_ID_CHT_PMC 0x229C
17 /* PMC Memory mapped IO registers */
18 #define PMC_BASE_ADDR_OFFSET 0x44
19 #define PMC_BASE_ADDR_MASK 0xFFFFFE00
20 #define PMC_MMIO_REG_LEN 0x100
21 #define PMC_REG_BIT_WIDTH 32
23 /* BIOS uses FUNC_DIS to disable specific function */
24 #define PMC_FUNC_DIS 0x34
25 #define PMC_FUNC_DIS_2 0x38
27 /* CHT specific bits in FUNC_DIS2 register */
28 #define BIT_FD_GMM BIT(3)
29 #define BIT_FD_ISH BIT(4)
31 /* S0ix wake event control */
32 #define PMC_S0IX_WAKE_EN 0x3C
34 #define BIT_LPC_CLOCK_RUN BIT(4)
35 #define BIT_SHARED_IRQ_GPSC BIT(5)
36 #define BIT_ORED_DEDICATED_IRQ_GPSS BIT(18)
37 #define BIT_ORED_DEDICATED_IRQ_GPSC BIT(19)
38 #define BIT_SHARED_IRQ_GPSS BIT(20)
40 #define PMC_WAKE_EN_SETTING ~(BIT_LPC_CLOCK_RUN | \
41 BIT_SHARED_IRQ_GPSC | \
42 BIT_ORED_DEDICATED_IRQ_GPSS | \
43 BIT_ORED_DEDICATED_IRQ_GPSC | \
46 /* The timers accumulate time spent in sleep state */
47 #define PMC_S0IR_TMR 0x80
48 #define PMC_S0I1_TMR 0x84
49 #define PMC_S0I2_TMR 0x88
50 #define PMC_S0I3_TMR 0x8C
51 #define PMC_S0_TMR 0x90
52 /* Sleep state counter is in units of 32us */
53 #define PMC_TMR_SHIFT 5
55 /* Power status of power islands */
58 #define PMC_PSS_BIT_GBE BIT(0)
59 #define PMC_PSS_BIT_SATA BIT(1)
60 #define PMC_PSS_BIT_HDA BIT(2)
61 #define PMC_PSS_BIT_SEC BIT(3)
62 #define PMC_PSS_BIT_PCIE BIT(4)
63 #define PMC_PSS_BIT_LPSS BIT(5)
64 #define PMC_PSS_BIT_LPE BIT(6)
65 #define PMC_PSS_BIT_DFX BIT(7)
66 #define PMC_PSS_BIT_USH_CTRL BIT(8)
67 #define PMC_PSS_BIT_USH_SUS BIT(9)
68 #define PMC_PSS_BIT_USH_VCCS BIT(10)
69 #define PMC_PSS_BIT_USH_VCCA BIT(11)
70 #define PMC_PSS_BIT_OTG_CTRL BIT(12)
71 #define PMC_PSS_BIT_OTG_VCCS BIT(13)
72 #define PMC_PSS_BIT_OTG_VCCA_CLK BIT(14)
73 #define PMC_PSS_BIT_OTG_VCCA BIT(15)
74 #define PMC_PSS_BIT_USB BIT(16)
75 #define PMC_PSS_BIT_USB_SUS BIT(17)
77 /* CHT specific bits in PSS register */
78 #define PMC_PSS_BIT_CHT_UFS BIT(7)
79 #define PMC_PSS_BIT_CHT_UXD BIT(11)
80 #define PMC_PSS_BIT_CHT_UXD_FD BIT(12)
81 #define PMC_PSS_BIT_CHT_UX_ENG BIT(15)
82 #define PMC_PSS_BIT_CHT_USB_SUS BIT(16)
83 #define PMC_PSS_BIT_CHT_GMM BIT(17)
84 #define PMC_PSS_BIT_CHT_ISH BIT(18)
85 #define PMC_PSS_BIT_CHT_DFX_MASTER BIT(26)
86 #define PMC_PSS_BIT_CHT_DFX_CLUSTER1 BIT(27)
87 #define PMC_PSS_BIT_CHT_DFX_CLUSTER2 BIT(28)
88 #define PMC_PSS_BIT_CHT_DFX_CLUSTER3 BIT(29)
89 #define PMC_PSS_BIT_CHT_DFX_CLUSTER4 BIT(30)
90 #define PMC_PSS_BIT_CHT_DFX_CLUSTER5 BIT(31)
92 /* These registers reflect D3 status of functions */
93 #define PMC_D3_STS_0 0xA0
95 #define BIT_LPSS1_F0_DMA BIT(0)
96 #define BIT_LPSS1_F1_PWM1 BIT(1)
97 #define BIT_LPSS1_F2_PWM2 BIT(2)
98 #define BIT_LPSS1_F3_HSUART1 BIT(3)
99 #define BIT_LPSS1_F4_HSUART2 BIT(4)
100 #define BIT_LPSS1_F5_SPI BIT(5)
101 #define BIT_LPSS1_F6_XXX BIT(6)
102 #define BIT_LPSS1_F7_XXX BIT(7)
103 #define BIT_SCC_EMMC BIT(8)
104 #define BIT_SCC_SDIO BIT(9)
105 #define BIT_SCC_SDCARD BIT(10)
106 #define BIT_SCC_MIPI BIT(11)
107 #define BIT_HDA BIT(12)
108 #define BIT_LPE BIT(13)
109 #define BIT_OTG BIT(14)
110 #define BIT_USH BIT(15)
111 #define BIT_GBE BIT(16)
112 #define BIT_SATA BIT(17)
113 #define BIT_USB_EHCI BIT(18)
114 #define BIT_SEC BIT(19)
115 #define BIT_PCIE_PORT0 BIT(20)
116 #define BIT_PCIE_PORT1 BIT(21)
117 #define BIT_PCIE_PORT2 BIT(22)
118 #define BIT_PCIE_PORT3 BIT(23)
119 #define BIT_LPSS2_F0_DMA BIT(24)
120 #define BIT_LPSS2_F1_I2C1 BIT(25)
121 #define BIT_LPSS2_F2_I2C2 BIT(26)
122 #define BIT_LPSS2_F3_I2C3 BIT(27)
123 #define BIT_LPSS2_F4_I2C4 BIT(28)
124 #define BIT_LPSS2_F5_I2C5 BIT(29)
125 #define BIT_LPSS2_F6_I2C6 BIT(30)
126 #define BIT_LPSS2_F7_I2C7 BIT(31)
128 #define PMC_D3_STS_1 0xA4
129 #define BIT_SMB BIT(0)
130 #define BIT_OTG_SS_PHY BIT(1)
131 #define BIT_USH_SS_PHY BIT(2)
132 #define BIT_DFX BIT(3)
134 /* CHT specific bits in PMC_D3_STS_1 register */
135 #define BIT_STS_GMM BIT(1)
136 #define BIT_STS_ISH BIT(2)
138 /* PMC I/O Registers */
139 #define ACPI_BASE_ADDR_OFFSET 0x40
140 #define ACPI_BASE_ADDR_MASK 0xFFFFFE00
141 #define ACPI_MMIO_REG_LEN 0x100
144 #define SLEEP_TYPE_MASK GENMASK(12, 10)
145 #define SLEEP_TYPE_S5 0x1C00
146 #define SLEEP_ENABLE BIT(13)
148 extern int pmc_atom_read(int offset, u32 *value);
150 #endif /* PMC_ATOM_H */