1 /* SPDX-License-Identifier: GPL-2.0 */
3 #ifndef __TI_SYSC_DATA_H__
4 #define __TI_SYSC_DATA_H__
6 enum ti_sysc_module_type {
18 TI_SYSC_OMAP4_USB_HOST_FS,
22 struct ti_sysc_cookie {
28 * struct sysc_regbits - TI OCP_SYSCONFIG register field offsets
29 * @midle_shift: Offset of the midle bit
30 * @clkact_shift: Offset of the clockactivity bit
31 * @sidle_shift: Offset of the sidle bit
32 * @enwkup_shift: Offset of the enawakeup bit
33 * @srst_shift: Offset of the softreset bit
34 * @autoidle_shift: Offset of the autoidle bit
35 * @dmadisable_shift: Offset of the dmadisable bit
36 * @emufree_shift; Offset of the emufree bit
38 * Note that 0 is a valid shift, and for ti-sysc.c -ENODEV can be used if a
39 * feature is not available.
52 #define SYSC_MODULE_QUIRK_RTC_UNLOCK BIT(22)
53 #define SYSC_QUIRK_CLKDM_NOAUTO BIT(21)
54 #define SYSC_QUIRK_FORCE_MSTANDBY BIT(20)
55 #define SYSC_MODULE_QUIRK_AESS BIT(19)
56 #define SYSC_MODULE_QUIRK_SGX BIT(18)
57 #define SYSC_MODULE_QUIRK_HDQ1W BIT(17)
58 #define SYSC_MODULE_QUIRK_I2C BIT(16)
59 #define SYSC_MODULE_QUIRK_WDT BIT(15)
60 #define SYSS_QUIRK_RESETDONE_INVERTED BIT(14)
61 #define SYSC_QUIRK_SWSUP_MSTANDBY BIT(13)
62 #define SYSC_QUIRK_SWSUP_SIDLE_ACT BIT(12)
63 #define SYSC_QUIRK_SWSUP_SIDLE BIT(11)
64 #define SYSC_QUIRK_EXT_OPT_CLOCK BIT(10)
65 #define SYSC_QUIRK_LEGACY_IDLE BIT(9)
66 #define SYSC_QUIRK_RESET_STATUS BIT(8)
67 #define SYSC_QUIRK_NO_IDLE BIT(7)
68 #define SYSC_QUIRK_NO_IDLE_ON_INIT BIT(6)
69 #define SYSC_QUIRK_NO_RESET_ON_INIT BIT(5)
70 #define SYSC_QUIRK_OPT_CLKS_NEEDED BIT(4)
71 #define SYSC_QUIRK_OPT_CLKS_IN_RESET BIT(3)
72 #define SYSC_QUIRK_16BIT BIT(2)
73 #define SYSC_QUIRK_UNCACHED BIT(1)
74 #define SYSC_QUIRK_USE_CLOCKACT BIT(0)
76 #define SYSC_NR_IDLEMODES 4
79 * struct sysc_capabilities - capabilities for an interconnect target module
80 * @type: sysc type identifier for the module
81 * @sysc_mask: bitmask of supported SYSCONFIG register bits
82 * @regbits: bitmask of SYSCONFIG register bits
83 * @mod_quirks: bitmask of module specific quirks
85 struct sysc_capabilities {
86 const enum ti_sysc_module_type type;
88 const struct sysc_regbits *regbits;
93 * struct sysc_config - configuration for an interconnect target module
94 * @sysc_val: configured value for sysc register
95 * @syss_mask: configured mask value for SYSSTATUS register
96 * @midlemodes: bitmask of supported master idle modes
97 * @sidlemodes: bitmask of supported slave idle modes
98 * @srst_udelay: optional delay needed after OCP soft reset
99 * @quirks: bitmask of enabled quirks
110 enum sysc_registers {
118 * struct ti_sysc_module_data - ti-sysc to hwmod translation data for a module
119 * @name: legacy "ti,hwmods" module name
120 * @module_pa: physical address of the interconnect target module
121 * @module_size: size of the interconnect target module
122 * @offsets: array of register offsets as listed in enum sysc_registers
123 * @nr_offsets: number of registers
124 * @cap: interconnect target module capabilities
125 * @cfg: interconnect target module configuration
127 * This data is enough to allocate a new struct omap_hwmod_class_sysconfig
128 * based on device tree data parsed by ti-sysc driver.
130 struct ti_sysc_module_data {
136 const struct sysc_capabilities *cap;
137 struct sysc_config *cfg;
143 struct ti_sysc_platform_data {
144 struct of_dev_auxdata *auxdata;
145 int (*init_clockdomain)(struct device *dev, struct clk *fck,
146 struct clk *ick, struct ti_sysc_cookie *cookie);
147 void (*clkdm_deny_idle)(struct device *dev,
148 const struct ti_sysc_cookie *cookie);
149 void (*clkdm_allow_idle)(struct device *dev,
150 const struct ti_sysc_cookie *cookie);
151 int (*init_module)(struct device *dev,
152 const struct ti_sysc_module_data *data,
153 struct ti_sysc_cookie *cookie);
154 int (*enable_module)(struct device *dev,
155 const struct ti_sysc_cookie *cookie);
156 int (*idle_module)(struct device *dev,
157 const struct ti_sysc_cookie *cookie);
158 int (*shutdown_module)(struct device *dev,
159 const struct ti_sysc_cookie *cookie);
162 #endif /* __TI_SYSC_DATA_H__ */