1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * TI DaVinci Audio Serial Port support
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
8 #ifndef __DAVINCI_ASP_H
9 #define __DAVINCI_ASP_H
11 #include <linux/genalloc.h>
13 struct davinci_mcasp_pdata {
16 int asp_chan_q; /* event queue number for ASP channel */
17 int ram_chan_q; /* event queue number for RAM channel */
19 * Allowing this is more efficient and eliminates left and right swaps
20 * caused by underruns, but will swap the left and right channels
21 * when compared to previous behavior.
23 unsigned enable_channel_combine:1;
24 unsigned sram_size_playback;
25 unsigned sram_size_capture;
26 struct gen_pool *sram_pool;
29 * If McBSP peripheral gets the clock from an external pin,
30 * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR
32 * Depending on different hardware connections it is possible
33 * to use this setting to change the behaviour of McBSP
39 * This flag works when both clock and FS are outputs for the cpu
40 * and makes clock more accurate (FS is not symmetrical and the
42 * The clock becoming faster is named
43 * i2s continuous serial clock (I2S_SCK) and it is an externally
46 * first line : WordSelect
47 * second line : ContinuousSerialClock
48 * third line: SerialData
50 * SYMMETRICAL APPROACH:
51 * _______________________ LEFT
52 * _| RIGHT |______________________|
54 * _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_
56 * _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_
57 * \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
59 * ACCURATE CLOCK APPROACH:
61 * _| RIGHT |_______________________________|
63 * _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| |
64 * _ _ _ _ dummy cycles
65 * _/ \_ ... _/ \_/ \_ ... _/ \__________________
69 bool i2s_accurate_sck;
71 /* McASP specific fields */
83 /* TODO: Fix arch/arm/mach-davinci/ users and remove this define */
84 #define snd_platform_data davinci_mcasp_pdata
87 MCASP_VERSION_1 = 0, /* DM646x */
88 MCASP_VERSION_2, /* DA8xx/OMAPL1x */
89 MCASP_VERSION_3, /* TI81xx/AM33xx */
90 MCASP_VERSION_4, /* DRA7xxx */
91 MCASP_VERSION_OMAP, /* OMAP4/5 */
94 enum mcbsp_clk_input_pin {
95 MCBSP_CLKR = 0, /* as in DM365 */
99 #define INACTIVE_MODE 0
103 #define DAVINCI_MCASP_IIS_MODE 0
104 #define DAVINCI_MCASP_DIT_MODE 1