1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
27 #include <linux/mod_devicetable.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
40 #include <linux/resource_ext.h>
41 #include <uapi/linux/pci.h>
43 #include <linux/pci_ids.h>
45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
46 PCI_STATUS_SIG_SYSTEM_ERROR | \
47 PCI_STATUS_REC_MASTER_ABORT | \
48 PCI_STATUS_REC_TARGET_ABORT | \
49 PCI_STATUS_SIG_TARGET_ABORT | \
52 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */
53 #define PCI_NUM_RESET_METHODS 7
55 #define PCI_RESET_PROBE true
56 #define PCI_RESET_DO_RESET false
59 * The PCI interface treats multi-function devices as independent
60 * devices. The slot/function address of each device is encoded
61 * in a single byte as follows:
66 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
67 * In the interest of not exposing interfaces to user-space unnecessarily,
68 * the following kernel-only defines are being added here.
70 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
71 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
72 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
74 /* pci_slot represents a physical slot */
76 struct pci_bus *bus; /* Bus this slot is on */
77 struct list_head list; /* Node in list of slots */
78 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
79 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
83 static inline const char *pci_slot_name(const struct pci_slot *slot)
85 return kobject_name(&slot->kobj);
88 /* File state for mmap()s on /proc/bus/pci/X/Y */
94 /* For PCI devices, the region numbers are assigned this way: */
96 /* #0-5: standard PCI resources */
98 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
100 /* #6: expansion ROM resource */
103 /* Device-specific resources */
104 #ifdef CONFIG_PCI_IOV
106 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
109 /* PCI-to-PCI (P2P) bridge windows */
110 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
111 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
112 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
114 /* CardBus bridge windows */
115 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
116 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
117 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
118 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
120 /* Total number of bridge resources for P2P and CardBus */
121 #define PCI_BRIDGE_RESOURCE_NUM 4
123 /* Resources assigned to buses behind the bridge */
124 PCI_BRIDGE_RESOURCES,
125 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
126 PCI_BRIDGE_RESOURCE_NUM - 1,
128 /* Total resources associated with a PCI device */
131 /* Preserve this for compatibility */
132 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
136 * enum pci_interrupt_pin - PCI INTx interrupt values
137 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
138 * @PCI_INTERRUPT_INTA: PCI INTA pin
139 * @PCI_INTERRUPT_INTB: PCI INTB pin
140 * @PCI_INTERRUPT_INTC: PCI INTC pin
141 * @PCI_INTERRUPT_INTD: PCI INTD pin
143 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
144 * PCI_INTERRUPT_PIN register.
146 enum pci_interrupt_pin {
147 PCI_INTERRUPT_UNKNOWN,
154 /* The number of legacy PCI INTx interrupts */
155 #define PCI_NUM_INTX 4
158 * pci_power_t values must match the bits in the Capabilities PME_Support
159 * and Control/Status PowerState fields in the Power Management capability.
161 typedef int __bitwise pci_power_t;
163 #define PCI_D0 ((pci_power_t __force) 0)
164 #define PCI_D1 ((pci_power_t __force) 1)
165 #define PCI_D2 ((pci_power_t __force) 2)
166 #define PCI_D3hot ((pci_power_t __force) 3)
167 #define PCI_D3cold ((pci_power_t __force) 4)
168 #define PCI_UNKNOWN ((pci_power_t __force) 5)
169 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
171 /* Remember to update this when the list above changes! */
172 extern const char *pci_power_names[];
174 static inline const char *pci_power_name(pci_power_t state)
176 return pci_power_names[1 + (__force int) state];
180 * typedef pci_channel_state_t
182 * The pci_channel state describes connectivity between the CPU and
183 * the PCI device. If some PCI bus between here and the PCI device
184 * has crashed or locked up, this info is reflected here.
186 typedef unsigned int __bitwise pci_channel_state_t;
189 /* I/O channel is in normal state */
190 pci_channel_io_normal = (__force pci_channel_state_t) 1,
192 /* I/O to channel is blocked */
193 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
195 /* PCI card is dead */
196 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
199 typedef unsigned int __bitwise pcie_reset_state_t;
201 enum pcie_reset_state {
202 /* Reset is NOT asserted (Use to deassert reset) */
203 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
205 /* Use #PERST to reset PCIe device */
206 pcie_warm_reset = (__force pcie_reset_state_t) 2,
208 /* Use PCIe Hot Reset to reset device */
209 pcie_hot_reset = (__force pcie_reset_state_t) 3
212 typedef unsigned short __bitwise pci_dev_flags_t;
214 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
215 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
216 /* Device configuration is irrevocably lost if disabled into D3 */
217 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
218 /* Provide indication device is assigned by a Virtual Machine Manager */
219 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
220 /* Flag for quirk use to store if quirk-specific ACS is enabled */
221 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
222 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
223 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
224 /* Do not use bus resets for device */
225 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
226 /* Do not use PM reset even if device advertises NoSoftRst- */
227 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
228 /* Get VPD from function 0 VPD */
229 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
230 /* A non-root bridge where translation occurs, stop alias search here */
231 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
232 /* Do not use FLR even if device advertises PCI_AF_CAP */
233 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
234 /* Don't use Relaxed Ordering for TLPs directed at this device */
235 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
236 /* Device does honor MSI masking despite saying otherwise */
237 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
240 enum pci_irq_reroute_variant {
241 INTEL_IRQ_REROUTE_VARIANT = 1,
242 MAX_IRQ_REROUTE_VARIANTS = 3
245 typedef unsigned short __bitwise pci_bus_flags_t;
247 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
248 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
249 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
250 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
253 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
254 enum pcie_link_width {
255 PCIE_LNK_WIDTH_RESRV = 0x00,
263 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
266 /* See matching string table in pci_speed_string() */
268 PCI_SPEED_33MHz = 0x00,
269 PCI_SPEED_66MHz = 0x01,
270 PCI_SPEED_66MHz_PCIX = 0x02,
271 PCI_SPEED_100MHz_PCIX = 0x03,
272 PCI_SPEED_133MHz_PCIX = 0x04,
273 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
274 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
275 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
276 PCI_SPEED_66MHz_PCIX_266 = 0x09,
277 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
278 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
284 PCI_SPEED_66MHz_PCIX_533 = 0x11,
285 PCI_SPEED_100MHz_PCIX_533 = 0x12,
286 PCI_SPEED_133MHz_PCIX_533 = 0x13,
287 PCIE_SPEED_2_5GT = 0x14,
288 PCIE_SPEED_5_0GT = 0x15,
289 PCIE_SPEED_8_0GT = 0x16,
290 PCIE_SPEED_16_0GT = 0x17,
291 PCIE_SPEED_32_0GT = 0x18,
292 PCIE_SPEED_64_0GT = 0x19,
293 PCI_SPEED_UNKNOWN = 0xff,
296 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
297 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
306 struct pcie_link_state;
311 /* The pci_dev structure describes PCI devices */
313 struct list_head bus_list; /* Node in per-bus list */
314 struct pci_bus *bus; /* Bus this device is on */
315 struct pci_bus *subordinate; /* Bus this device bridges to */
317 void *sysdata; /* Hook for sys-specific extension */
318 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
319 struct pci_slot *slot; /* Physical slot this device is in */
321 unsigned int devfn; /* Encoded device & function index */
322 unsigned short vendor;
323 unsigned short device;
324 unsigned short subsystem_vendor;
325 unsigned short subsystem_device;
326 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
327 u8 revision; /* PCI revision, low byte of class word */
328 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
329 #ifdef CONFIG_PCIEAER
330 u16 aer_cap; /* AER capability offset */
331 struct aer_stats *aer_stats; /* AER stats for this device */
333 #ifdef CONFIG_PCIEPORTBUS
334 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
335 struct pci_dev *rcec; /* Associated RCEC device */
337 u32 devcap; /* PCIe Device Capabilities */
338 u8 pcie_cap; /* PCIe capability offset */
339 u8 msi_cap; /* MSI capability offset */
340 u8 msix_cap; /* MSI-X capability offset */
341 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
342 u8 rom_base_reg; /* Config register controlling ROM */
343 u8 pin; /* Interrupt pin this device uses */
344 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
345 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
347 struct pci_driver *driver; /* Driver bound to this device */
348 u64 dma_mask; /* Mask of the bits of bus address this
349 device implements. Normally this is
350 0xffffffff. You only need to change
351 this if your device has broken DMA
352 or supports 64-bit transfers. */
354 struct device_dma_parameters dma_parms;
356 pci_power_t current_state; /* Current operating state. In ACPI,
357 this is D0-D3, D0 being fully
358 functional, and D3 being off. */
359 unsigned int imm_ready:1; /* Supports Immediate Readiness */
360 u8 pm_cap; /* PM capability offset */
361 unsigned int pme_support:5; /* Bitmask of states from which PME#
363 unsigned int pme_poll:1; /* Poll device's PME status bit */
364 unsigned int d1_support:1; /* Low power state D1 is supported */
365 unsigned int d2_support:1; /* Low power state D2 is supported */
366 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
367 unsigned int no_d3cold:1; /* D3cold is forbidden */
368 unsigned int bridge_d3:1; /* Allow D3 for bridge */
369 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
370 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
371 decoding during BAR sizing */
372 unsigned int wakeup_prepared:1;
373 unsigned int runtime_d3cold:1; /* Whether go through runtime
374 D3cold, not set for devices
375 powered on/off by the
376 corresponding bridge */
377 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
378 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
379 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
380 controlled exclusively by
382 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
384 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
385 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
387 #ifdef CONFIG_PCIEASPM
388 struct pcie_link_state *link_state; /* ASPM link state */
389 unsigned int ltr_path:1; /* Latency Tolerance Reporting
390 supported from root to here */
391 u16 l1ss; /* L1SS Capability pointer */
393 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
394 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
396 pci_channel_state_t error_state; /* Current connectivity state */
397 struct device dev; /* Generic device interface */
399 int cfg_size; /* Size of config space */
402 * Instead of touching interrupt line and base address registers
403 * directly, use the values stored here. They might be different!
406 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
408 bool match_driver; /* Skip attaching driver */
410 unsigned int transparent:1; /* Subtractive decode bridge */
411 unsigned int io_window:1; /* Bridge has I/O window */
412 unsigned int pref_window:1; /* Bridge has pref mem window */
413 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
414 unsigned int multifunction:1; /* Multi-function device */
416 unsigned int is_busmaster:1; /* Is busmaster */
417 unsigned int no_msi:1; /* May not use MSI */
418 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
419 unsigned int block_cfg_access:1; /* Config space access blocked */
420 unsigned int broken_parity_status:1; /* Generates false positive parity */
421 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
422 unsigned int msi_enabled:1;
423 unsigned int msix_enabled:1;
424 unsigned int ari_enabled:1; /* ARI forwarding */
425 unsigned int ats_enabled:1; /* Address Translation Svc */
426 unsigned int pasid_enabled:1; /* Process Address Space ID */
427 unsigned int pri_enabled:1; /* Page Request Interface */
428 unsigned int is_managed:1;
429 unsigned int needs_freset:1; /* Requires fundamental reset */
430 unsigned int state_saved:1;
431 unsigned int is_physfn:1;
432 unsigned int is_virtfn:1;
433 unsigned int is_hotplug_bridge:1;
434 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
435 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
437 * Devices marked being untrusted are the ones that can potentially
438 * execute DMA attacks and similar. They are typically connected
439 * through external ports such as Thunderbolt but not limited to
440 * that. When an IOMMU is enabled they should be getting full
441 * mappings to make sure they cannot access arbitrary memory.
443 unsigned int untrusted:1;
445 * Info from the platform, e.g., ACPI or device tree, may mark a
446 * device as "external-facing". An external-facing device is
447 * itself internal but devices downstream from it are external.
449 unsigned int external_facing:1;
450 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
451 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
452 unsigned int irq_managed:1;
453 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
454 unsigned int is_probed:1; /* Device probing in progress */
455 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
456 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
457 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
458 pci_dev_flags_t dev_flags;
459 atomic_t enable_cnt; /* pci_enable_device has been called */
461 u32 saved_config_space[16]; /* Config space saved at suspend time */
462 struct hlist_head saved_cap_space;
463 int rom_attr_enabled; /* Display of ROM attribute enabled? */
464 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
465 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
467 #ifdef CONFIG_HOTPLUG_PCI_PCIE
468 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
470 #ifdef CONFIG_PCIE_PTM
471 unsigned int ptm_root:1;
472 unsigned int ptm_enabled:1;
475 #ifdef CONFIG_PCI_MSI
476 const struct attribute_group **msi_irq_groups;
479 #ifdef CONFIG_PCIE_DPC
481 unsigned int dpc_rp_extensions:1;
484 #ifdef CONFIG_PCI_ATS
486 struct pci_sriov *sriov; /* PF: SR-IOV info */
487 struct pci_dev *physfn; /* VF: related PF */
489 u16 ats_cap; /* ATS Capability offset */
490 u8 ats_stu; /* ATS Smallest Translation Unit */
492 #ifdef CONFIG_PCI_PRI
493 u16 pri_cap; /* PRI Capability offset */
494 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
495 unsigned int pasid_required:1; /* PRG Response PASID Required */
497 #ifdef CONFIG_PCI_PASID
498 u16 pasid_cap; /* PASID Capability offset */
501 #ifdef CONFIG_PCI_P2PDMA
502 struct pci_p2pdma __rcu *p2pdma;
504 u16 acs_cap; /* ACS Capability offset */
505 phys_addr_t rom; /* Physical address if not from BAR */
506 size_t romlen; /* Length if not from BAR */
507 char *driver_override; /* Driver name to force a match */
509 unsigned long priv_flags; /* Private flags for the PCI driver */
511 /* These methods index pci_reset_fn_methods[] */
512 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
515 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
517 #ifdef CONFIG_PCI_IOV
524 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
526 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
527 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
529 static inline int pci_channel_offline(struct pci_dev *pdev)
531 return (pdev->error_state != pci_channel_io_normal);
535 * Currently in ACPI spec, for each PCI host bridge, PCI Segment
536 * Group number is limited to a 16-bit value, therefore (int)-1 is
537 * not a valid PCI domain number, and can be used as a sentinel
538 * value indicating ->domain_nr is not set by the driver (and
539 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with
540 * pci_bus_find_domain_nr()).
542 #define PCI_DOMAIN_NR_NOT_SET (-1)
544 struct pci_host_bridge {
546 struct pci_bus *bus; /* Root bus */
548 struct pci_ops *child_ops;
552 struct list_head windows; /* resource_entry */
553 struct list_head dma_ranges; /* dma ranges resource list */
554 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
555 int (*map_irq)(const struct pci_dev *, u8, u8);
556 void (*release_fn)(struct pci_host_bridge *);
558 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
559 unsigned int no_ext_tags:1; /* No Extended Tags */
560 unsigned int native_aer:1; /* OS may use PCIe AER */
561 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
562 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
563 unsigned int native_pme:1; /* OS may use PCIe PME */
564 unsigned int native_ltr:1; /* OS may use PCIe LTR */
565 unsigned int native_dpc:1; /* OS may use PCIe DPC */
566 unsigned int preserve_config:1; /* Preserve FW resource setup */
567 unsigned int size_windows:1; /* Enable root bus sizing */
568 unsigned int msi_domain:1; /* Bridge wants MSI domain */
570 /* Resource alignment requirements */
571 resource_size_t (*align_resource)(struct pci_dev *dev,
572 const struct resource *res,
573 resource_size_t start,
574 resource_size_t size,
575 resource_size_t align);
576 unsigned long private[] ____cacheline_aligned;
579 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
581 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
583 return (void *)bridge->private;
586 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
588 return container_of(priv, struct pci_host_bridge, private);
591 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
592 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
594 void pci_free_host_bridge(struct pci_host_bridge *bridge);
595 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
597 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
598 void (*release_fn)(struct pci_host_bridge *),
601 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
604 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
605 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
606 * buses below host bridges or subtractive decode bridges) go in the list.
607 * Use pci_bus_for_each_resource() to iterate through all the resources.
611 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
612 * and there's no way to program the bridge with the details of the window.
613 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
614 * decode bit set, because they are explicit and can be programmed with _SRS.
616 #define PCI_SUBTRACTIVE_DECODE 0x1
618 struct pci_bus_resource {
619 struct list_head list;
620 struct resource *res;
624 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
627 struct list_head node; /* Node in list of buses */
628 struct pci_bus *parent; /* Parent bus this bridge is on */
629 struct list_head children; /* List of child buses */
630 struct list_head devices; /* List of devices on this bus */
631 struct pci_dev *self; /* Bridge device as seen by parent */
632 struct list_head slots; /* List of slots on this bus;
633 protected by pci_slot_mutex */
634 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
635 struct list_head resources; /* Address space routed to this bus */
636 struct resource busn_res; /* Bus numbers routed to this bus */
638 struct pci_ops *ops; /* Configuration access functions */
639 void *sysdata; /* Hook for sys-specific extension */
640 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
642 unsigned char number; /* Bus number */
643 unsigned char primary; /* Number of primary bridge */
644 unsigned char max_bus_speed; /* enum pci_bus_speed */
645 unsigned char cur_bus_speed; /* enum pci_bus_speed */
646 #ifdef CONFIG_PCI_DOMAINS_GENERIC
652 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
653 pci_bus_flags_t bus_flags; /* Inherited by child buses */
654 struct device *bridge;
656 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
657 struct bin_attribute *legacy_mem; /* Legacy mem */
658 unsigned int is_added:1;
659 unsigned int unsafe_warn:1; /* warned about RW1C config write */
662 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
664 static inline u16 pci_dev_id(struct pci_dev *dev)
666 return PCI_DEVID(dev->bus->number, dev->devfn);
670 * Returns true if the PCI bus is root (behind host-PCI bridge),
673 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
674 * This is incorrect because "virtual" buses added for SR-IOV (via
675 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
677 static inline bool pci_is_root_bus(struct pci_bus *pbus)
679 return !(pbus->parent);
683 * pci_is_bridge - check if the PCI device is a bridge
686 * Return true if the PCI device is bridge whether it has subordinate
689 static inline bool pci_is_bridge(struct pci_dev *dev)
691 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
692 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
695 #define for_each_pci_bridge(dev, bus) \
696 list_for_each_entry(dev, &bus->devices, bus_list) \
697 if (!pci_is_bridge(dev)) {} else
699 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
701 dev = pci_physfn(dev);
702 if (pci_is_root_bus(dev->bus))
705 return dev->bus->self;
708 #ifdef CONFIG_PCI_MSI
709 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
711 return pci_dev->msi_enabled || pci_dev->msix_enabled;
714 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
717 /* Error values that may be returned by PCI functions */
718 #define PCIBIOS_SUCCESSFUL 0x00
719 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
720 #define PCIBIOS_BAD_VENDOR_ID 0x83
721 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
722 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
723 #define PCIBIOS_SET_FAILED 0x88
724 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
726 /* Translate above to generic errno for passing back through non-PCI code */
727 static inline int pcibios_err_to_errno(int err)
729 if (err <= PCIBIOS_SUCCESSFUL)
730 return err; /* Assume already errno */
733 case PCIBIOS_FUNC_NOT_SUPPORTED:
735 case PCIBIOS_BAD_VENDOR_ID:
737 case PCIBIOS_DEVICE_NOT_FOUND:
739 case PCIBIOS_BAD_REGISTER_NUMBER:
741 case PCIBIOS_SET_FAILED:
743 case PCIBIOS_BUFFER_TOO_SMALL:
750 /* Low-level architecture-dependent routines */
753 int (*add_bus)(struct pci_bus *bus);
754 void (*remove_bus)(struct pci_bus *bus);
755 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
756 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
757 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
761 * ACPI needs to be able to access PCI config space before we've done a
762 * PCI bus scan and created pci_bus structures.
764 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
765 int reg, int len, u32 *val);
766 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
767 int reg, int len, u32 val);
769 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
770 typedef u64 pci_bus_addr_t;
772 typedef u32 pci_bus_addr_t;
775 struct pci_bus_region {
776 pci_bus_addr_t start;
781 spinlock_t lock; /* Protects list, index */
782 struct list_head list; /* For IDs added at runtime */
787 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
788 * a set of callbacks in struct pci_error_handlers, that device driver
789 * will be notified of PCI bus errors, and will be driven to recovery
790 * when an error occurs.
793 typedef unsigned int __bitwise pci_ers_result_t;
795 enum pci_ers_result {
796 /* No result/none/not supported in device driver */
797 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
799 /* Device driver can recover without slot reset */
800 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
802 /* Device driver wants slot to be reset */
803 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
805 /* Device has completely failed, is unrecoverable */
806 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
808 /* Device driver is fully recovered and operational */
809 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
811 /* No AER capabilities registered for the driver */
812 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
815 /* PCI bus error event callbacks */
816 struct pci_error_handlers {
817 /* PCI bus error detected on this device */
818 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
819 pci_channel_state_t error);
821 /* MMIO has been re-enabled, but not DMA */
822 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
824 /* PCI slot has been reset */
825 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
827 /* PCI function reset prepare or completed */
828 void (*reset_prepare)(struct pci_dev *dev);
829 void (*reset_done)(struct pci_dev *dev);
831 /* Device driver may resume normal operations */
832 void (*resume)(struct pci_dev *dev);
839 * struct pci_driver - PCI driver structure
840 * @node: List of driver structures.
841 * @name: Driver name.
842 * @id_table: Pointer to table of device IDs the driver is
843 * interested in. Most drivers should export this
844 * table using MODULE_DEVICE_TABLE(pci,...).
845 * @probe: This probing function gets called (during execution
846 * of pci_register_driver() for already existing
847 * devices or later if a new device gets inserted) for
848 * all PCI devices which match the ID table and are not
849 * "owned" by the other drivers yet. This function gets
850 * passed a "struct pci_dev \*" for each device whose
851 * entry in the ID table matches the device. The probe
852 * function returns zero when the driver chooses to
853 * take "ownership" of the device or an error code
854 * (negative number) otherwise.
855 * The probe function always gets called from process
856 * context, so it can sleep.
857 * @remove: The remove() function gets called whenever a device
858 * being handled by this driver is removed (either during
859 * deregistration of the driver or when it's manually
860 * pulled out of a hot-pluggable slot).
861 * The remove function always gets called from process
862 * context, so it can sleep.
863 * @suspend: Put device into low power state.
864 * @resume: Wake device from low power state.
865 * (Please see Documentation/power/pci.rst for descriptions
866 * of PCI Power Management and the related functions.)
867 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
868 * Intended to stop any idling DMA operations.
869 * Useful for enabling wake-on-lan (NIC) or changing
870 * the power state of a device before reboot.
871 * e.g. drivers/net/e100.c.
872 * @sriov_configure: Optional driver callback to allow configuration of
873 * number of VFs to enable via sysfs "sriov_numvfs" file.
874 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X
875 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count".
876 * This will change MSI-X Table Size in the VF Message Control
878 * @sriov_get_vf_total_msix: PF driver callback to get the total number of
879 * MSI-X vectors available for distribution to the VFs.
880 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
881 * @groups: Sysfs attribute groups.
882 * @dev_groups: Attributes attached to the device that will be
883 * created once it is bound to the driver.
884 * @driver: Driver model structure.
885 * @dynids: List of dynamically added device IDs.
888 struct list_head node;
890 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
891 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
892 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
893 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
894 int (*resume)(struct pci_dev *dev); /* Device woken up */
895 void (*shutdown)(struct pci_dev *dev);
896 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
897 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
898 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
899 const struct pci_error_handlers *err_handler;
900 const struct attribute_group **groups;
901 const struct attribute_group **dev_groups;
902 struct device_driver driver;
903 struct pci_dynids dynids;
906 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
909 * PCI_DEVICE - macro used to describe a specific PCI device
910 * @vend: the 16 bit PCI Vendor ID
911 * @dev: the 16 bit PCI Device ID
913 * This macro is used to create a struct pci_device_id that matches a
914 * specific device. The subvendor and subdevice fields will be set to
917 #define PCI_DEVICE(vend,dev) \
918 .vendor = (vend), .device = (dev), \
919 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
922 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with
923 * override_only flags.
924 * @vend: the 16 bit PCI Vendor ID
925 * @dev: the 16 bit PCI Device ID
926 * @driver_override: the 32 bit PCI Device override_only
928 * This macro is used to create a struct pci_device_id that matches only a
929 * driver_override device. The subvendor and subdevice fields will be set to
932 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \
933 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \
934 .subdevice = PCI_ANY_ID, .override_only = (driver_override)
937 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO
938 * "driver_override" PCI device.
939 * @vend: the 16 bit PCI Vendor ID
940 * @dev: the 16 bit PCI Device ID
942 * This macro is used to create a struct pci_device_id that matches a
943 * specific device. The subvendor and subdevice fields will be set to
944 * PCI_ANY_ID and the driver_override will be set to
945 * PCI_ID_F_VFIO_DRIVER_OVERRIDE.
947 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \
948 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE)
951 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
952 * @vend: the 16 bit PCI Vendor ID
953 * @dev: the 16 bit PCI Device ID
954 * @subvend: the 16 bit PCI Subvendor ID
955 * @subdev: the 16 bit PCI Subdevice ID
957 * This macro is used to create a struct pci_device_id that matches a
958 * specific device with subsystem information.
960 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
961 .vendor = (vend), .device = (dev), \
962 .subvendor = (subvend), .subdevice = (subdev)
965 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
966 * @dev_class: the class, subclass, prog-if triple for this device
967 * @dev_class_mask: the class mask for this device
969 * This macro is used to create a struct pci_device_id that matches a
970 * specific PCI class. The vendor, device, subvendor, and subdevice
971 * fields will be set to PCI_ANY_ID.
973 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
974 .class = (dev_class), .class_mask = (dev_class_mask), \
975 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
976 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
979 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
980 * @vend: the vendor name
981 * @dev: the 16 bit PCI Device ID
983 * This macro is used to create a struct pci_device_id that matches a
984 * specific PCI device. The subvendor, and subdevice fields will be set
985 * to PCI_ANY_ID. The macro allows the next field to follow as the device
988 #define PCI_VDEVICE(vend, dev) \
989 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
990 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
993 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
994 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
995 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
996 * @data: the driver data to be filled
998 * This macro is used to create a struct pci_device_id that matches a
999 * specific PCI device. The subvendor, and subdevice fields will be set
1002 #define PCI_DEVICE_DATA(vend, dev, data) \
1003 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
1004 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
1005 .driver_data = (kernel_ulong_t)(data)
1008 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
1009 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
1010 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
1011 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
1012 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
1013 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
1014 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
1017 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1018 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1019 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1020 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1022 /* These external functions are only available when PCI support is enabled */
1025 extern unsigned int pci_flags;
1027 static inline void pci_set_flags(int flags) { pci_flags = flags; }
1028 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
1029 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
1030 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
1032 void pcie_bus_configure_settings(struct pci_bus *bus);
1034 enum pcie_bus_config_types {
1035 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
1036 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
1037 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
1038 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
1039 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
1042 extern enum pcie_bus_config_types pcie_bus_config;
1044 extern struct bus_type pci_bus_type;
1046 /* Do NOT directly access these two variables, unless you are arch-specific PCI
1047 * code, or PCI core code. */
1048 extern struct list_head pci_root_buses; /* List of all known PCI buses */
1049 /* Some device drivers need know if PCI is initiated */
1050 int no_pci_devices(void);
1052 void pcibios_resource_survey_bus(struct pci_bus *bus);
1053 void pcibios_bus_add_device(struct pci_dev *pdev);
1054 void pcibios_add_bus(struct pci_bus *bus);
1055 void pcibios_remove_bus(struct pci_bus *bus);
1056 void pcibios_fixup_bus(struct pci_bus *);
1057 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1058 /* Architecture-specific versions may override this (weak) */
1059 char *pcibios_setup(char *str);
1061 /* Used only when drivers/pci/setup.c is used */
1062 resource_size_t pcibios_align_resource(void *, const struct resource *,
1066 /* Weak but can be overridden by arch */
1067 void pci_fixup_cardbus(struct pci_bus *);
1069 /* Generic PCI functions used internally */
1071 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1072 struct resource *res);
1073 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1074 struct pci_bus_region *region);
1075 void pcibios_scan_specific_bus(int busn);
1076 struct pci_bus *pci_find_bus(int domain, int busnr);
1077 void pci_bus_add_devices(const struct pci_bus *bus);
1078 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1079 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1080 struct pci_ops *ops, void *sysdata,
1081 struct list_head *resources);
1082 int pci_host_probe(struct pci_host_bridge *bridge);
1083 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1084 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1085 void pci_bus_release_busn_res(struct pci_bus *b);
1086 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1087 struct pci_ops *ops, void *sysdata,
1088 struct list_head *resources);
1089 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1090 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1092 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1094 struct hotplug_slot *hotplug);
1095 void pci_destroy_slot(struct pci_slot *slot);
1097 void pci_dev_assign_slot(struct pci_dev *dev);
1099 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1101 int pci_scan_slot(struct pci_bus *bus, int devfn);
1102 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1103 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1104 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1105 void pci_bus_add_device(struct pci_dev *dev);
1106 void pci_read_bridge_bases(struct pci_bus *child);
1107 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1108 struct resource *res);
1109 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1110 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1111 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1112 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1113 void pci_dev_put(struct pci_dev *dev);
1114 void pci_remove_bus(struct pci_bus *b);
1115 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1116 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1117 void pci_stop_root_bus(struct pci_bus *bus);
1118 void pci_remove_root_bus(struct pci_bus *bus);
1119 void pci_setup_cardbus(struct pci_bus *bus);
1120 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1121 void pci_sort_breadthfirst(void);
1122 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1123 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1125 /* Generic PCI functions exported to card drivers */
1127 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1128 u8 pci_find_capability(struct pci_dev *dev, int cap);
1129 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1130 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1131 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1132 u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1133 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1134 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1135 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
1137 u64 pci_get_dsn(struct pci_dev *dev);
1139 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1140 struct pci_dev *from);
1141 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1142 unsigned int ss_vendor, unsigned int ss_device,
1143 struct pci_dev *from);
1144 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1145 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1146 unsigned int devfn);
1147 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1148 int pci_dev_present(const struct pci_device_id *ids);
1150 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1151 int where, u8 *val);
1152 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1153 int where, u16 *val);
1154 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1155 int where, u32 *val);
1156 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1158 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1159 int where, u16 val);
1160 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1161 int where, u32 val);
1163 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1164 int where, int size, u32 *val);
1165 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1166 int where, int size, u32 val);
1167 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1168 int where, int size, u32 *val);
1169 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1170 int where, int size, u32 val);
1172 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1174 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1175 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1176 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1177 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1178 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1179 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1181 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1182 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1183 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1184 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1185 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1186 u16 clear, u16 set);
1187 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1188 u32 clear, u32 set);
1190 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1193 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1196 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1199 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1202 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1205 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1208 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1211 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1214 /* User-space driven config access */
1215 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1216 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1217 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1218 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1219 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1220 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1222 int __must_check pci_enable_device(struct pci_dev *dev);
1223 int __must_check pci_enable_device_io(struct pci_dev *dev);
1224 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1225 int __must_check pci_reenable_device(struct pci_dev *);
1226 int __must_check pcim_enable_device(struct pci_dev *pdev);
1227 void pcim_pin_device(struct pci_dev *pdev);
1229 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1232 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1233 * writable and no quirk has marked the feature broken.
1235 return !pdev->broken_intx_masking;
1238 static inline int pci_is_enabled(struct pci_dev *pdev)
1240 return (atomic_read(&pdev->enable_cnt) > 0);
1243 static inline int pci_is_managed(struct pci_dev *pdev)
1245 return pdev->is_managed;
1248 void pci_disable_device(struct pci_dev *dev);
1250 extern unsigned int pcibios_max_latency;
1251 void pci_set_master(struct pci_dev *dev);
1252 void pci_clear_master(struct pci_dev *dev);
1254 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1255 int pci_set_cacheline_size(struct pci_dev *dev);
1256 int __must_check pci_set_mwi(struct pci_dev *dev);
1257 int __must_check pcim_set_mwi(struct pci_dev *dev);
1258 int pci_try_set_mwi(struct pci_dev *dev);
1259 void pci_clear_mwi(struct pci_dev *dev);
1260 void pci_disable_parity(struct pci_dev *dev);
1261 void pci_intx(struct pci_dev *dev, int enable);
1262 bool pci_check_and_mask_intx(struct pci_dev *dev);
1263 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1264 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1265 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1266 int pcix_get_max_mmrbc(struct pci_dev *dev);
1267 int pcix_get_mmrbc(struct pci_dev *dev);
1268 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1269 int pcie_get_readrq(struct pci_dev *dev);
1270 int pcie_set_readrq(struct pci_dev *dev, int rq);
1271 int pcie_get_mps(struct pci_dev *dev);
1272 int pcie_set_mps(struct pci_dev *dev, int mps);
1273 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1274 enum pci_bus_speed *speed,
1275 enum pcie_link_width *width);
1276 void pcie_print_link_status(struct pci_dev *dev);
1277 int pcie_reset_flr(struct pci_dev *dev, bool probe);
1278 int pcie_flr(struct pci_dev *dev);
1279 int __pci_reset_function_locked(struct pci_dev *dev);
1280 int pci_reset_function(struct pci_dev *dev);
1281 int pci_reset_function_locked(struct pci_dev *dev);
1282 int pci_try_reset_function(struct pci_dev *dev);
1283 int pci_probe_reset_slot(struct pci_slot *slot);
1284 int pci_probe_reset_bus(struct pci_bus *bus);
1285 int pci_reset_bus(struct pci_dev *dev);
1286 void pci_reset_secondary_bus(struct pci_dev *dev);
1287 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1288 void pci_update_resource(struct pci_dev *dev, int resno);
1289 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1290 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1291 void pci_release_resource(struct pci_dev *dev, int resno);
1292 static inline int pci_rebar_bytes_to_size(u64 bytes)
1294 bytes = roundup_pow_of_two(bytes);
1296 /* Return BAR size as defined in the resizable BAR specification */
1297 return max(ilog2(bytes), 20) - 20;
1300 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1301 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1302 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1303 bool pci_device_is_present(struct pci_dev *pdev);
1304 void pci_ignore_hotplug(struct pci_dev *dev);
1305 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1306 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1308 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1309 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1310 const char *fmt, ...);
1311 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1313 /* ROM control related routines */
1314 int pci_enable_rom(struct pci_dev *pdev);
1315 void pci_disable_rom(struct pci_dev *pdev);
1316 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1317 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1319 /* Power management related routines */
1320 int pci_save_state(struct pci_dev *dev);
1321 void pci_restore_state(struct pci_dev *dev);
1322 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1323 int pci_load_saved_state(struct pci_dev *dev,
1324 struct pci_saved_state *state);
1325 int pci_load_and_free_saved_state(struct pci_dev *dev,
1326 struct pci_saved_state **state);
1327 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1328 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1329 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1330 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1331 void pci_pme_active(struct pci_dev *dev, bool enable);
1332 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1333 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1334 int pci_prepare_to_sleep(struct pci_dev *dev);
1335 int pci_back_from_sleep(struct pci_dev *dev);
1336 bool pci_dev_run_wake(struct pci_dev *dev);
1337 void pci_d3cold_enable(struct pci_dev *dev);
1338 void pci_d3cold_disable(struct pci_dev *dev);
1339 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1340 void pci_resume_bus(struct pci_bus *bus);
1341 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1343 /* For use by arch with custom probe code */
1344 void set_pcie_port_type(struct pci_dev *pdev);
1345 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1347 /* Functions for PCI Hotplug drivers to use */
1348 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1349 unsigned int pci_rescan_bus(struct pci_bus *bus);
1350 void pci_lock_rescan_remove(void);
1351 void pci_unlock_rescan_remove(void);
1353 /* Vital Product Data routines */
1354 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1355 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1357 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1358 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1359 void pci_bus_assign_resources(const struct pci_bus *bus);
1360 void pci_bus_claim_resources(struct pci_bus *bus);
1361 void pci_bus_size_bridges(struct pci_bus *bus);
1362 int pci_claim_resource(struct pci_dev *, int);
1363 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1364 void pci_assign_unassigned_resources(void);
1365 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1366 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1367 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1368 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1369 void pdev_enable_device(struct pci_dev *);
1370 int pci_enable_resources(struct pci_dev *, int mask);
1371 void pci_assign_irq(struct pci_dev *dev);
1372 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1373 #define HAVE_PCI_REQ_REGIONS 2
1374 int __must_check pci_request_regions(struct pci_dev *, const char *);
1375 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1376 void pci_release_regions(struct pci_dev *);
1377 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1378 void pci_release_region(struct pci_dev *, int);
1379 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1380 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1381 void pci_release_selected_regions(struct pci_dev *, int);
1383 /* drivers/pci/bus.c */
1384 void pci_add_resource(struct list_head *resources, struct resource *res);
1385 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1386 resource_size_t offset);
1387 void pci_free_resource_list(struct list_head *resources);
1388 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1389 unsigned int flags);
1390 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1391 void pci_bus_remove_resources(struct pci_bus *bus);
1392 int devm_request_pci_bus_resources(struct device *dev,
1393 struct list_head *resources);
1395 /* Temporary until new and working PCI SBR API in place */
1396 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1398 #define pci_bus_for_each_resource(bus, res, i) \
1400 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1403 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1404 struct resource *res, resource_size_t size,
1405 resource_size_t align, resource_size_t min,
1406 unsigned long type_mask,
1407 resource_size_t (*alignf)(void *,
1408 const struct resource *,
1414 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1415 resource_size_t size);
1416 unsigned long pci_address_to_pio(phys_addr_t addr);
1417 phys_addr_t pci_pio_to_address(unsigned long pio);
1418 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1419 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1420 phys_addr_t phys_addr);
1421 void pci_unmap_iospace(struct resource *res);
1422 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1423 resource_size_t offset,
1424 resource_size_t size);
1425 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1426 struct resource *res);
1428 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1430 struct pci_bus_region region;
1432 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1433 return region.start;
1436 /* Proper probing supporting hot-pluggable devices */
1437 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1438 const char *mod_name);
1440 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1441 #define pci_register_driver(driver) \
1442 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1444 void pci_unregister_driver(struct pci_driver *dev);
1447 * module_pci_driver() - Helper macro for registering a PCI driver
1448 * @__pci_driver: pci_driver struct
1450 * Helper macro for PCI drivers which do not do anything special in module
1451 * init/exit. This eliminates a lot of boilerplate. Each module may only
1452 * use this macro once, and calling it replaces module_init() and module_exit()
1454 #define module_pci_driver(__pci_driver) \
1455 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1458 * builtin_pci_driver() - Helper macro for registering a PCI driver
1459 * @__pci_driver: pci_driver struct
1461 * Helper macro for PCI drivers which do not do anything special in their
1462 * init code. This eliminates a lot of boilerplate. Each driver may only
1463 * use this macro once, and calling it replaces device_initcall(...)
1465 #define builtin_pci_driver(__pci_driver) \
1466 builtin_driver(__pci_driver, pci_register_driver)
1468 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1469 int pci_add_dynid(struct pci_driver *drv,
1470 unsigned int vendor, unsigned int device,
1471 unsigned int subvendor, unsigned int subdevice,
1472 unsigned int class, unsigned int class_mask,
1473 unsigned long driver_data);
1474 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1475 struct pci_dev *dev);
1476 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1479 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1481 int pci_cfg_space_size(struct pci_dev *dev);
1482 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1483 void pci_setup_bridge(struct pci_bus *bus);
1484 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1485 unsigned long type);
1487 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1488 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1490 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1491 unsigned int command_bits, u32 flags);
1494 * Virtual interrupts allow for more interrupts to be allocated
1495 * than the device has interrupts for. These are not programmed
1496 * into the device's MSI-X table and must be handled by some
1497 * other driver means.
1499 #define PCI_IRQ_VIRTUAL (1 << 4)
1501 #define PCI_IRQ_ALL_TYPES \
1502 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1504 /* kmem_cache style wrapper around pci_alloc_consistent() */
1506 #include <linux/dmapool.h>
1508 #define pci_pool dma_pool
1509 #define pci_pool_create(name, pdev, size, align, allocation) \
1510 dma_pool_create(name, &pdev->dev, size, align, allocation)
1511 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1512 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1513 #define pci_pool_zalloc(pool, flags, handle) \
1514 dma_pool_zalloc(pool, flags, handle)
1515 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1518 u32 vector; /* Kernel uses to write allocated vector */
1519 u16 entry; /* Driver uses to specify entry, OS writes */
1522 #ifdef CONFIG_PCI_MSI
1523 int pci_msi_vec_count(struct pci_dev *dev);
1524 void pci_disable_msi(struct pci_dev *dev);
1525 int pci_msix_vec_count(struct pci_dev *dev);
1526 void pci_disable_msix(struct pci_dev *dev);
1527 void pci_restore_msi_state(struct pci_dev *dev);
1528 int pci_msi_enabled(void);
1529 int pci_enable_msi(struct pci_dev *dev);
1530 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1531 int minvec, int maxvec);
1532 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1533 struct msix_entry *entries, int nvec)
1535 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1540 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1541 unsigned int max_vecs, unsigned int flags,
1542 struct irq_affinity *affd);
1544 void pci_free_irq_vectors(struct pci_dev *dev);
1545 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1546 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1549 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1550 static inline void pci_disable_msi(struct pci_dev *dev) { }
1551 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1552 static inline void pci_disable_msix(struct pci_dev *dev) { }
1553 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1554 static inline int pci_msi_enabled(void) { return 0; }
1555 static inline int pci_enable_msi(struct pci_dev *dev)
1557 static inline int pci_enable_msix_range(struct pci_dev *dev,
1558 struct msix_entry *entries, int minvec, int maxvec)
1560 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1561 struct msix_entry *entries, int nvec)
1565 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1566 unsigned int max_vecs, unsigned int flags,
1567 struct irq_affinity *aff_desc)
1569 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1574 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1578 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1580 if (WARN_ON_ONCE(nr > 0))
1584 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1587 return cpu_possible_mask;
1592 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1593 * @d: the INTx IRQ domain
1594 * @node: the DT node for the device whose interrupt we're translating
1595 * @intspec: the interrupt specifier data from the DT
1596 * @intsize: the number of entries in @intspec
1597 * @out_hwirq: pointer at which to write the hwirq number
1598 * @out_type: pointer at which to write the interrupt type
1600 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1601 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1602 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1603 * INTx value to obtain the hwirq number.
1605 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1607 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1608 struct device_node *node,
1610 unsigned int intsize,
1611 unsigned long *out_hwirq,
1612 unsigned int *out_type)
1614 const u32 intx = intspec[0];
1616 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1619 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1623 #ifdef CONFIG_PCIEPORTBUS
1624 extern bool pcie_ports_disabled;
1625 extern bool pcie_ports_native;
1627 #define pcie_ports_disabled true
1628 #define pcie_ports_native false
1631 #define PCIE_LINK_STATE_L0S BIT(0)
1632 #define PCIE_LINK_STATE_L1 BIT(1)
1633 #define PCIE_LINK_STATE_CLKPM BIT(2)
1634 #define PCIE_LINK_STATE_L1_1 BIT(3)
1635 #define PCIE_LINK_STATE_L1_2 BIT(4)
1636 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1637 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1639 #ifdef CONFIG_PCIEASPM
1640 int pci_disable_link_state(struct pci_dev *pdev, int state);
1641 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1642 void pcie_no_aspm(void);
1643 bool pcie_aspm_support_enabled(void);
1644 bool pcie_aspm_enabled(struct pci_dev *pdev);
1646 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1648 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1650 static inline void pcie_no_aspm(void) { }
1651 static inline bool pcie_aspm_support_enabled(void) { return false; }
1652 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1655 #ifdef CONFIG_PCIEAER
1656 bool pci_aer_available(void);
1658 static inline bool pci_aer_available(void) { return false; }
1661 bool pci_ats_disabled(void);
1663 #ifdef CONFIG_PCIE_PTM
1664 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1665 bool pcie_ptm_enabled(struct pci_dev *dev);
1667 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1669 static inline bool pcie_ptm_enabled(struct pci_dev *dev)
1673 void pci_cfg_access_lock(struct pci_dev *dev);
1674 bool pci_cfg_access_trylock(struct pci_dev *dev);
1675 void pci_cfg_access_unlock(struct pci_dev *dev);
1677 int pci_dev_trylock(struct pci_dev *dev);
1678 void pci_dev_unlock(struct pci_dev *dev);
1681 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1682 * a PCI domain is defined to be a set of PCI buses which share
1683 * configuration space.
1685 #ifdef CONFIG_PCI_DOMAINS
1686 extern int pci_domains_supported;
1688 enum { pci_domains_supported = 0 };
1689 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1690 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1691 #endif /* CONFIG_PCI_DOMAINS */
1694 * Generic implementation for PCI domain support. If your
1695 * architecture does not need custom management of PCI
1696 * domains then this implementation will be used
1698 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1699 static inline int pci_domain_nr(struct pci_bus *bus)
1701 return bus->domain_nr;
1704 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1706 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1709 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1712 /* Some architectures require additional setup to direct VGA traffic */
1713 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1714 unsigned int command_bits, u32 flags);
1715 void pci_register_set_vga_state(arch_set_vga_state_t func);
1718 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1720 return pci_request_selected_regions(pdev,
1721 pci_select_bars(pdev, IORESOURCE_IO), name);
1725 pci_release_io_regions(struct pci_dev *pdev)
1727 return pci_release_selected_regions(pdev,
1728 pci_select_bars(pdev, IORESOURCE_IO));
1732 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1734 return pci_request_selected_regions(pdev,
1735 pci_select_bars(pdev, IORESOURCE_MEM), name);
1739 pci_release_mem_regions(struct pci_dev *pdev)
1741 return pci_release_selected_regions(pdev,
1742 pci_select_bars(pdev, IORESOURCE_MEM));
1745 #else /* CONFIG_PCI is not enabled */
1747 static inline void pci_set_flags(int flags) { }
1748 static inline void pci_add_flags(int flags) { }
1749 static inline void pci_clear_flags(int flags) { }
1750 static inline int pci_has_flag(int flag) { return 0; }
1753 * If the system does not have PCI, clearly these return errors. Define
1754 * these as simple inline functions to avoid hair in drivers.
1756 #define _PCI_NOP(o, s, t) \
1757 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1759 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1761 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1762 _PCI_NOP(o, word, u16 x) \
1763 _PCI_NOP(o, dword, u32 x)
1764 _PCI_NOP_ALL(read, *)
1765 _PCI_NOP_ALL(write,)
1767 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1768 unsigned int device,
1769 struct pci_dev *from)
1772 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1773 unsigned int device,
1774 unsigned int ss_vendor,
1775 unsigned int ss_device,
1776 struct pci_dev *from)
1779 static inline struct pci_dev *pci_get_class(unsigned int class,
1780 struct pci_dev *from)
1783 #define pci_dev_present(ids) (0)
1784 #define no_pci_devices() (1)
1785 #define pci_dev_put(dev) do { } while (0)
1787 static inline void pci_set_master(struct pci_dev *dev) { }
1788 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1789 static inline void pci_disable_device(struct pci_dev *dev) { }
1790 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
1791 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1793 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1794 struct module *owner,
1795 const char *mod_name)
1797 static inline int pci_register_driver(struct pci_driver *drv)
1799 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1800 static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
1802 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1805 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1808 static inline u64 pci_get_dsn(struct pci_dev *dev)
1811 /* Power management related routines */
1812 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1813 static inline void pci_restore_state(struct pci_dev *dev) { }
1814 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1816 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1818 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1821 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1825 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1826 struct resource *res)
1828 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1830 static inline void pci_release_regions(struct pci_dev *dev) { }
1832 static inline int pci_register_io_range(struct fwnode_handle *fwnode,
1833 phys_addr_t addr, resource_size_t size)
1836 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1838 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1840 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1843 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1844 unsigned int bus, unsigned int devfn)
1847 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1848 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1850 #define dev_is_pci(d) (false)
1851 #define dev_is_pf(d) (false)
1852 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1854 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1855 struct device_node *node,
1857 unsigned int intsize,
1858 unsigned long *out_hwirq,
1859 unsigned int *out_type)
1862 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1863 struct pci_dev *dev)
1865 static inline bool pci_ats_disabled(void) { return true; }
1867 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1873 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1874 unsigned int max_vecs, unsigned int flags,
1875 struct irq_affinity *aff_desc)
1879 #endif /* CONFIG_PCI */
1882 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1883 unsigned int max_vecs, unsigned int flags)
1885 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1889 /* Include architecture-dependent settings and functions */
1891 #include <asm/pci.h>
1893 /* These two functions provide almost identical functionality. Depending
1894 * on the architecture, one will be implemented as a wrapper around the
1895 * other (in drivers/pci/mmap.c).
1897 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1898 * is expected to be an offset within that region.
1900 * pci_mmap_page_range() is the legacy architecture-specific interface,
1901 * which accepts a "user visible" resource address converted by
1902 * pci_resource_to_user(), as used in the legacy mmap() interface in
1905 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1906 struct vm_area_struct *vma,
1907 enum pci_mmap_state mmap_state, int write_combine);
1908 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1909 struct vm_area_struct *vma,
1910 enum pci_mmap_state mmap_state, int write_combine);
1912 #ifndef arch_can_pci_mmap_wc
1913 #define arch_can_pci_mmap_wc() 0
1916 #ifndef arch_can_pci_mmap_io
1917 #define arch_can_pci_mmap_io() 0
1918 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1920 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1923 #ifndef pci_root_bus_fwnode
1924 #define pci_root_bus_fwnode(bus) NULL
1928 * These helpers provide future and backwards compatibility
1929 * for accessing popular PCI BAR info
1931 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1932 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1933 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1934 #define pci_resource_len(dev,bar) \
1935 ((pci_resource_end((dev), (bar)) == 0) ? 0 : \
1937 (pci_resource_end((dev), (bar)) - \
1938 pci_resource_start((dev), (bar)) + 1))
1941 * Similar to the helpers above, these manipulate per-pci_dev
1942 * driver-specific data. They are really just a wrapper around
1943 * the generic device structure functions of these calls.
1945 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1947 return dev_get_drvdata(&pdev->dev);
1950 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1952 dev_set_drvdata(&pdev->dev, data);
1955 static inline const char *pci_name(const struct pci_dev *pdev)
1957 return dev_name(&pdev->dev);
1960 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1961 const struct resource *rsrc,
1962 resource_size_t *start, resource_size_t *end);
1965 * The world is not perfect and supplies us with broken PCI devices.
1966 * For at least a part of these bugs we need a work-around, so both
1967 * generic (drivers/pci/quirks.c) and per-architecture code can define
1968 * fixup hooks to be called for particular buggy devices.
1972 u16 vendor; /* Or PCI_ANY_ID */
1973 u16 device; /* Or PCI_ANY_ID */
1974 u32 class; /* Or PCI_ANY_ID */
1975 unsigned int class_shift; /* should be 0, 8, 16 */
1976 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1979 void (*hook)(struct pci_dev *dev);
1983 enum pci_fixup_pass {
1984 pci_fixup_early, /* Before probing BARs */
1985 pci_fixup_header, /* After reading configuration header */
1986 pci_fixup_final, /* Final phase of device fixups */
1987 pci_fixup_enable, /* pci_enable_device() time */
1988 pci_fixup_resume, /* pci_device_resume() */
1989 pci_fixup_suspend, /* pci_device_suspend() */
1990 pci_fixup_resume_early, /* pci_device_resume_early() */
1991 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1994 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1995 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1996 class_shift, hook) \
1997 __ADDRESSABLE(hook) \
1998 asm(".section " #sec ", \"a\" \n" \
2000 ".short " #vendor ", " #device " \n" \
2001 ".long " #class ", " #class_shift " \n" \
2002 ".long " #hook " - . \n" \
2006 * Clang's LTO may rename static functions in C, but has no way to
2007 * handle such renamings when referenced from inline asm. To work
2008 * around this, create global C stubs for these cases.
2010 #ifdef CONFIG_LTO_CLANG
2011 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2012 class_shift, hook, stub) \
2013 void __cficanonical stub(struct pci_dev *dev); \
2014 void __cficanonical stub(struct pci_dev *dev) \
2018 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2021 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2022 class_shift, hook, stub) \
2023 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2027 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2028 class_shift, hook) \
2029 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2030 class_shift, hook, __UNIQUE_ID(hook))
2032 /* Anonymous variables would be nice... */
2033 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
2034 class_shift, hook) \
2035 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
2036 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
2037 = { vendor, device, class, class_shift, hook };
2040 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
2041 class_shift, hook) \
2042 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2043 hook, vendor, device, class, class_shift, hook)
2044 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
2045 class_shift, hook) \
2046 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2047 hook, vendor, device, class, class_shift, hook)
2048 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2049 class_shift, hook) \
2050 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2051 hook, vendor, device, class, class_shift, hook)
2052 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2053 class_shift, hook) \
2054 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2055 hook, vendor, device, class, class_shift, hook)
2056 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2057 class_shift, hook) \
2058 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2059 resume##hook, vendor, device, class, class_shift, hook)
2060 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2061 class_shift, hook) \
2062 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2063 resume_early##hook, vendor, device, class, class_shift, hook)
2064 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2065 class_shift, hook) \
2066 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2067 suspend##hook, vendor, device, class, class_shift, hook)
2068 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2069 class_shift, hook) \
2070 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2071 suspend_late##hook, vendor, device, class, class_shift, hook)
2073 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2074 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2075 hook, vendor, device, PCI_ANY_ID, 0, hook)
2076 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2077 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2078 hook, vendor, device, PCI_ANY_ID, 0, hook)
2079 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2080 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2081 hook, vendor, device, PCI_ANY_ID, 0, hook)
2082 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2083 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2084 hook, vendor, device, PCI_ANY_ID, 0, hook)
2085 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2086 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2087 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2088 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2089 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2090 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2091 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2092 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2093 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2094 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2095 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2096 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2098 #ifdef CONFIG_PCI_QUIRKS
2099 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2101 static inline void pci_fixup_device(enum pci_fixup_pass pass,
2102 struct pci_dev *dev) { }
2105 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2106 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2107 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2108 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2109 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2111 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2113 extern int pci_pci_problems;
2114 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2115 #define PCIPCI_TRITON 2
2116 #define PCIPCI_NATOMA 4
2117 #define PCIPCI_VIAETBF 8
2118 #define PCIPCI_VSFX 16
2119 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2120 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2122 extern unsigned long pci_cardbus_io_size;
2123 extern unsigned long pci_cardbus_mem_size;
2124 extern u8 pci_dfl_cache_line_size;
2125 extern u8 pci_cache_line_size;
2127 /* Architecture-specific versions may override these (weak) */
2128 void pcibios_disable_device(struct pci_dev *dev);
2129 void pcibios_set_master(struct pci_dev *dev);
2130 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2131 enum pcie_reset_state state);
2132 int pcibios_add_device(struct pci_dev *dev);
2133 void pcibios_release_device(struct pci_dev *dev);
2135 void pcibios_penalize_isa_irq(int irq, int active);
2137 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2139 int pcibios_alloc_irq(struct pci_dev *dev);
2140 void pcibios_free_irq(struct pci_dev *dev);
2141 resource_size_t pcibios_default_alignment(void);
2143 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2144 void __init pci_mmcfg_early_init(void);
2145 void __init pci_mmcfg_late_init(void);
2147 static inline void pci_mmcfg_early_init(void) { }
2148 static inline void pci_mmcfg_late_init(void) { }
2151 int pci_ext_cfg_avail(void);
2153 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2154 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2156 #ifdef CONFIG_PCI_IOV
2157 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2158 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2160 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2161 void pci_disable_sriov(struct pci_dev *dev);
2163 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2164 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2165 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2166 int pci_num_vf(struct pci_dev *dev);
2167 int pci_vfs_assigned(struct pci_dev *dev);
2168 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2169 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2170 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2171 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2172 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2174 /* Arch may override these (weak) */
2175 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2176 int pcibios_sriov_disable(struct pci_dev *pdev);
2177 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2179 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2183 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2187 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2190 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2191 struct pci_dev *virtfn, int id)
2195 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2199 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2201 static inline void pci_disable_sriov(struct pci_dev *dev) { }
2202 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2203 static inline int pci_vfs_assigned(struct pci_dev *dev)
2205 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2207 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2209 #define pci_sriov_configure_simple NULL
2210 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2212 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2215 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2216 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2217 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2221 * pci_pcie_cap - get the saved PCIe capability offset
2224 * PCIe capability offset is calculated at PCI device initialization
2225 * time and saved in the data structure. This function returns saved
2226 * PCIe capability offset. Using this instead of pci_find_capability()
2227 * reduces unnecessary search in the PCI configuration space. If you
2228 * need to calculate PCIe capability offset from raw device for some
2229 * reasons, please use pci_find_capability() instead.
2231 static inline int pci_pcie_cap(struct pci_dev *dev)
2233 return dev->pcie_cap;
2237 * pci_is_pcie - check if the PCI device is PCI Express capable
2240 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2242 static inline bool pci_is_pcie(struct pci_dev *dev)
2244 return pci_pcie_cap(dev);
2248 * pcie_caps_reg - get the PCIe Capabilities Register
2251 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2253 return dev->pcie_flags_reg;
2257 * pci_pcie_type - get the PCIe device/port type
2260 static inline int pci_pcie_type(const struct pci_dev *dev)
2262 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2266 * pcie_find_root_port - Get the PCIe root port device
2269 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2270 * for a given PCI/PCIe Device.
2272 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2275 if (pci_is_pcie(dev) &&
2276 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2278 dev = pci_upstream_bridge(dev);
2284 void pci_request_acs(void);
2285 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2286 bool pci_acs_path_enabled(struct pci_dev *start,
2287 struct pci_dev *end, u16 acs_flags);
2288 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2290 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2291 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2293 /* Large Resource Data Type Tag Item Names */
2294 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2295 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2296 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2298 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2299 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2300 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2302 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2303 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2304 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2305 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2306 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2309 * pci_vpd_alloc - Allocate buffer and read VPD into it
2311 * @size: pointer to field where VPD length is returned
2313 * Returns pointer to allocated buffer or an ERR_PTR in case of failure
2315 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
2318 * pci_vpd_find_id_string - Locate id string in VPD
2319 * @buf: Pointer to buffered VPD data
2320 * @len: The length of the buffer area in which to search
2321 * @size: Pointer to field where length of id string is returned
2323 * Returns the index of the id string or -ENOENT if not found.
2325 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
2328 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section
2329 * @buf: Pointer to buffered VPD data
2330 * @len: The length of the buffer area in which to search
2331 * @kw: The keyword to search for
2332 * @size: Pointer to field where length of found keyword data is returned
2334 * Returns the index of the information field keyword data or -ENOENT if
2337 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
2338 const char *kw, unsigned int *size);
2341 * pci_vpd_check_csum - Check VPD checksum
2342 * @buf: Pointer to buffered VPD data
2345 * Returns 1 if VPD has no checksum, otherwise 0 or an errno
2347 int pci_vpd_check_csum(const void *buf, unsigned int len);
2349 /* PCI <-> OF binding helpers */
2353 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2354 bool pci_host_of_has_msi_map(struct device *dev);
2356 /* Arch may override this (weak) */
2357 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2359 #else /* CONFIG_OF */
2360 static inline struct irq_domain *
2361 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2362 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
2363 #endif /* CONFIG_OF */
2365 static inline struct device_node *
2366 pci_device_to_OF_node(const struct pci_dev *pdev)
2368 return pdev ? pdev->dev.of_node : NULL;
2371 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2373 return bus ? bus->dev.of_node : NULL;
2377 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2380 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2381 bool pci_pr3_present(struct pci_dev *pdev);
2383 static inline struct irq_domain *
2384 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2385 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2389 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2391 return pdev->dev.archdata.edev;
2395 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2396 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2397 int pci_for_each_dma_alias(struct pci_dev *pdev,
2398 int (*fn)(struct pci_dev *pdev,
2399 u16 alias, void *data), void *data);
2401 /* Helper functions for operation of device flag */
2402 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2404 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2406 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2408 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2410 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2412 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2416 * pci_ari_enabled - query ARI forwarding status
2419 * Returns true if ARI forwarding is enabled.
2421 static inline bool pci_ari_enabled(struct pci_bus *bus)
2423 return bus->self && bus->self->ari_enabled;
2427 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2428 * @pdev: PCI device to check
2430 * Walk upwards from @pdev and check for each encountered bridge if it's part
2431 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2432 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2434 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2436 struct pci_dev *parent = pdev;
2438 if (pdev->is_thunderbolt)
2441 while ((parent = pci_upstream_bridge(parent)))
2442 if (parent->is_thunderbolt)
2448 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2449 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2452 /* Provide the legacy pci_dma_* API */
2453 #include <linux/pci-dma-compat.h>
2455 #define pci_printk(level, pdev, fmt, arg...) \
2456 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2458 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2459 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2460 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2461 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2462 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2463 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2464 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2465 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2467 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2468 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2470 #define pci_info_ratelimited(pdev, fmt, arg...) \
2471 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2473 #define pci_WARN(pdev, condition, fmt, arg...) \
2474 WARN(condition, "%s %s: " fmt, \
2475 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2477 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2478 WARN_ONCE(condition, "%s %s: " fmt, \
2479 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2481 #endif /* LINUX_PCI_H */