1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
27 #include <linux/mod_devicetable.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
40 #include <linux/resource_ext.h>
41 #include <uapi/linux/pci.h>
43 #include <linux/pci_ids.h>
46 * The PCI interface treats multi-function devices as independent
47 * devices. The slot/function address of each device is encoded
48 * in a single byte as follows:
53 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
54 * In the interest of not exposing interfaces to user-space unnecessarily,
55 * the following kernel-only defines are being added here.
57 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
58 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
59 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
61 /* pci_slot represents a physical slot */
63 struct pci_bus *bus; /* Bus this slot is on */
64 struct list_head list; /* Node in list of slots */
65 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
66 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
70 static inline const char *pci_slot_name(const struct pci_slot *slot)
72 return kobject_name(&slot->kobj);
75 /* File state for mmap()s on /proc/bus/pci/X/Y */
81 /* For PCI devices, the region numbers are assigned this way: */
83 /* #0-5: standard PCI resources */
85 PCI_STD_RESOURCE_END = 5,
87 /* #6: expansion ROM resource */
90 /* Device-specific resources */
93 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
96 /* Resources assigned to buses behind the bridge */
97 #define PCI_BRIDGE_RESOURCE_NUM 4
100 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
101 PCI_BRIDGE_RESOURCE_NUM - 1,
103 /* Total resources associated with a PCI device */
106 /* Preserve this for compatibility */
107 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
111 * enum pci_interrupt_pin - PCI INTx interrupt values
112 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
113 * @PCI_INTERRUPT_INTA: PCI INTA pin
114 * @PCI_INTERRUPT_INTB: PCI INTB pin
115 * @PCI_INTERRUPT_INTC: PCI INTC pin
116 * @PCI_INTERRUPT_INTD: PCI INTD pin
118 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
119 * PCI_INTERRUPT_PIN register.
121 enum pci_interrupt_pin {
122 PCI_INTERRUPT_UNKNOWN,
129 /* The number of legacy PCI INTx interrupts */
130 #define PCI_NUM_INTX 4
133 * pci_power_t values must match the bits in the Capabilities PME_Support
134 * and Control/Status PowerState fields in the Power Management capability.
136 typedef int __bitwise pci_power_t;
138 #define PCI_D0 ((pci_power_t __force) 0)
139 #define PCI_D1 ((pci_power_t __force) 1)
140 #define PCI_D2 ((pci_power_t __force) 2)
141 #define PCI_D3hot ((pci_power_t __force) 3)
142 #define PCI_D3cold ((pci_power_t __force) 4)
143 #define PCI_UNKNOWN ((pci_power_t __force) 5)
144 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
146 /* Remember to update this when the list above changes! */
147 extern const char *pci_power_names[];
149 static inline const char *pci_power_name(pci_power_t state)
151 return pci_power_names[1 + (__force int) state];
155 * typedef pci_channel_state_t
157 * The pci_channel state describes connectivity between the CPU and
158 * the PCI device. If some PCI bus between here and the PCI device
159 * has crashed or locked up, this info is reflected here.
161 typedef unsigned int __bitwise pci_channel_state_t;
163 enum pci_channel_state {
164 /* I/O channel is in normal state */
165 pci_channel_io_normal = (__force pci_channel_state_t) 1,
167 /* I/O to channel is blocked */
168 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
170 /* PCI card is dead */
171 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
174 typedef unsigned int __bitwise pcie_reset_state_t;
176 enum pcie_reset_state {
177 /* Reset is NOT asserted (Use to deassert reset) */
178 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
180 /* Use #PERST to reset PCIe device */
181 pcie_warm_reset = (__force pcie_reset_state_t) 2,
183 /* Use PCIe Hot Reset to reset device */
184 pcie_hot_reset = (__force pcie_reset_state_t) 3
187 typedef unsigned short __bitwise pci_dev_flags_t;
189 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
190 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
191 /* Device configuration is irrevocably lost if disabled into D3 */
192 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
193 /* Provide indication device is assigned by a Virtual Machine Manager */
194 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
195 /* Flag for quirk use to store if quirk-specific ACS is enabled */
196 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
197 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
198 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
199 /* Do not use bus resets for device */
200 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
201 /* Do not use PM reset even if device advertises NoSoftRst- */
202 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
203 /* Get VPD from function 0 VPD */
204 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
205 /* A non-root bridge where translation occurs, stop alias search here */
206 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
207 /* Do not use FLR even if device advertises PCI_AF_CAP */
208 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
209 /* Don't use Relaxed Ordering for TLPs directed at this device */
210 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
211 /* Device does honor MSI masking despite saying otherwise */
212 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
215 enum pci_irq_reroute_variant {
216 INTEL_IRQ_REROUTE_VARIANT = 1,
217 MAX_IRQ_REROUTE_VARIANTS = 3
220 typedef unsigned short __bitwise pci_bus_flags_t;
222 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
223 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
224 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
225 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
228 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
229 enum pcie_link_width {
230 PCIE_LNK_WIDTH_RESRV = 0x00,
238 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
241 /* Based on the PCI Hotplug Spec, but some values are made up by us */
243 PCI_SPEED_33MHz = 0x00,
244 PCI_SPEED_66MHz = 0x01,
245 PCI_SPEED_66MHz_PCIX = 0x02,
246 PCI_SPEED_100MHz_PCIX = 0x03,
247 PCI_SPEED_133MHz_PCIX = 0x04,
248 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
249 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
250 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
251 PCI_SPEED_66MHz_PCIX_266 = 0x09,
252 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
253 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
259 PCI_SPEED_66MHz_PCIX_533 = 0x11,
260 PCI_SPEED_100MHz_PCIX_533 = 0x12,
261 PCI_SPEED_133MHz_PCIX_533 = 0x13,
262 PCIE_SPEED_2_5GT = 0x14,
263 PCIE_SPEED_5_0GT = 0x15,
264 PCIE_SPEED_8_0GT = 0x16,
265 PCIE_SPEED_16_0GT = 0x17,
266 PCIE_SPEED_32_0GT = 0x18,
267 PCI_SPEED_UNKNOWN = 0xff,
270 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
271 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
273 struct pci_cap_saved_data {
280 struct pci_cap_saved_state {
281 struct hlist_node next;
282 struct pci_cap_saved_data cap;
286 struct pcie_link_state;
292 /* The pci_dev structure describes PCI devices */
294 struct list_head bus_list; /* Node in per-bus list */
295 struct pci_bus *bus; /* Bus this device is on */
296 struct pci_bus *subordinate; /* Bus this device bridges to */
298 void *sysdata; /* Hook for sys-specific extension */
299 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
300 struct pci_slot *slot; /* Physical slot this device is in */
302 unsigned int devfn; /* Encoded device & function index */
303 unsigned short vendor;
304 unsigned short device;
305 unsigned short subsystem_vendor;
306 unsigned short subsystem_device;
307 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
308 u8 revision; /* PCI revision, low byte of class word */
309 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
310 #ifdef CONFIG_PCIEAER
311 u16 aer_cap; /* AER capability offset */
312 struct aer_stats *aer_stats; /* AER stats for this device */
314 u8 pcie_cap; /* PCIe capability offset */
315 u8 msi_cap; /* MSI capability offset */
316 u8 msix_cap; /* MSI-X capability offset */
317 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
318 u8 rom_base_reg; /* Config register controlling ROM */
319 u8 pin; /* Interrupt pin this device uses */
320 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
321 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
323 struct pci_driver *driver; /* Driver bound to this device */
324 u64 dma_mask; /* Mask of the bits of bus address this
325 device implements. Normally this is
326 0xffffffff. You only need to change
327 this if your device has broken DMA
328 or supports 64-bit transfers. */
330 struct device_dma_parameters dma_parms;
332 pci_power_t current_state; /* Current operating state. In ACPI,
333 this is D0-D3, D0 being fully
334 functional, and D3 being off. */
335 unsigned int imm_ready:1; /* Supports Immediate Readiness */
336 u8 pm_cap; /* PM capability offset */
337 unsigned int pme_support:5; /* Bitmask of states from which PME#
339 unsigned int pme_poll:1; /* Poll device's PME status bit */
340 unsigned int d1_support:1; /* Low power state D1 is supported */
341 unsigned int d2_support:1; /* Low power state D2 is supported */
342 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
343 unsigned int no_d3cold:1; /* D3cold is forbidden */
344 unsigned int bridge_d3:1; /* Allow D3 for bridge */
345 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
346 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
347 decoding during BAR sizing */
348 unsigned int wakeup_prepared:1;
349 unsigned int runtime_d3cold:1; /* Whether go through runtime
350 D3cold, not set for devices
351 powered on/off by the
352 corresponding bridge */
353 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
354 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
355 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
356 controlled exclusively by
358 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
360 unsigned int d3_delay; /* D3->D0 transition time in ms */
361 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
363 #ifdef CONFIG_PCIEASPM
364 struct pcie_link_state *link_state; /* ASPM link state */
365 unsigned int ltr_path:1; /* Latency Tolerance Reporting
366 supported from root to here */
368 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
370 pci_channel_state_t error_state; /* Current connectivity state */
371 struct device dev; /* Generic device interface */
373 int cfg_size; /* Size of config space */
376 * Instead of touching interrupt line and base address registers
377 * directly, use the values stored here. They might be different!
380 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
382 bool match_driver; /* Skip attaching driver */
384 unsigned int transparent:1; /* Subtractive decode bridge */
385 unsigned int io_window:1; /* Bridge has I/O window */
386 unsigned int pref_window:1; /* Bridge has pref mem window */
387 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
388 unsigned int multifunction:1; /* Multi-function device */
390 unsigned int is_busmaster:1; /* Is busmaster */
391 unsigned int no_msi:1; /* May not use MSI */
392 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
393 unsigned int block_cfg_access:1; /* Config space access blocked */
394 unsigned int broken_parity_status:1; /* Generates false positive parity */
395 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
396 unsigned int msi_enabled:1;
397 unsigned int msix_enabled:1;
398 unsigned int ari_enabled:1; /* ARI forwarding */
399 unsigned int ats_enabled:1; /* Address Translation Svc */
400 unsigned int pasid_enabled:1; /* Process Address Space ID */
401 unsigned int pri_enabled:1; /* Page Request Interface */
402 unsigned int is_managed:1;
403 unsigned int needs_freset:1; /* Requires fundamental reset */
404 unsigned int state_saved:1;
405 unsigned int is_physfn:1;
406 unsigned int is_virtfn:1;
407 unsigned int reset_fn:1;
408 unsigned int is_hotplug_bridge:1;
409 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
410 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
412 * Devices marked being untrusted are the ones that can potentially
413 * execute DMA attacks and similar. They are typically connected
414 * through external ports such as Thunderbolt but not limited to
415 * that. When an IOMMU is enabled they should be getting full
416 * mappings to make sure they cannot access arbitrary memory.
418 unsigned int untrusted:1;
419 unsigned int __aer_firmware_first_valid:1;
420 unsigned int __aer_firmware_first:1;
421 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
422 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
423 unsigned int irq_managed:1;
424 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
425 unsigned int is_probed:1; /* Device probing in progress */
426 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
427 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
428 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
429 pci_dev_flags_t dev_flags;
430 atomic_t enable_cnt; /* pci_enable_device has been called */
432 u32 saved_config_space[16]; /* Config space saved at suspend time */
433 struct hlist_head saved_cap_space;
434 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
435 int rom_attr_enabled; /* Display of ROM attribute enabled? */
436 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
437 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
439 #ifdef CONFIG_HOTPLUG_PCI_PCIE
440 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
442 #ifdef CONFIG_PCIE_PTM
443 unsigned int ptm_root:1;
444 unsigned int ptm_enabled:1;
447 #ifdef CONFIG_PCI_MSI
448 const struct attribute_group **msi_irq_groups;
451 #ifdef CONFIG_PCI_ATS
453 struct pci_sriov *sriov; /* PF: SR-IOV info */
454 struct pci_dev *physfn; /* VF: related PF */
456 u16 ats_cap; /* ATS Capability offset */
457 u8 ats_stu; /* ATS Smallest Translation Unit */
458 atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */
460 #ifdef CONFIG_PCI_PRI
461 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
463 #ifdef CONFIG_PCI_PASID
466 #ifdef CONFIG_PCI_P2PDMA
467 struct pci_p2pdma *p2pdma;
469 phys_addr_t rom; /* Physical address if not from BAR */
470 size_t romlen; /* Length if not from BAR */
471 char *driver_override; /* Driver name to force a match */
473 unsigned long priv_flags; /* Private flags for the PCI driver */
476 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
478 #ifdef CONFIG_PCI_IOV
485 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
487 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
488 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
490 static inline int pci_channel_offline(struct pci_dev *pdev)
492 return (pdev->error_state != pci_channel_io_normal);
495 struct pci_host_bridge {
497 struct pci_bus *bus; /* Root bus */
501 struct list_head windows; /* resource_entry */
502 struct list_head dma_ranges; /* dma ranges resource list */
503 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
504 int (*map_irq)(const struct pci_dev *, u8, u8);
505 void (*release_fn)(struct pci_host_bridge *);
507 struct msi_controller *msi;
508 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
509 unsigned int no_ext_tags:1; /* No Extended Tags */
510 unsigned int native_aer:1; /* OS may use PCIe AER */
511 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
512 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
513 unsigned int native_pme:1; /* OS may use PCIe PME */
514 unsigned int native_ltr:1; /* OS may use PCIe LTR */
515 unsigned int preserve_config:1; /* Preserve FW resource setup */
517 /* Resource alignment requirements */
518 resource_size_t (*align_resource)(struct pci_dev *dev,
519 const struct resource *res,
520 resource_size_t start,
521 resource_size_t size,
522 resource_size_t align);
523 unsigned long private[0] ____cacheline_aligned;
526 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
528 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
530 return (void *)bridge->private;
533 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
535 return container_of(priv, struct pci_host_bridge, private);
538 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
539 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
541 void pci_free_host_bridge(struct pci_host_bridge *bridge);
542 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
544 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
545 void (*release_fn)(struct pci_host_bridge *),
548 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
551 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
552 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
553 * buses below host bridges or subtractive decode bridges) go in the list.
554 * Use pci_bus_for_each_resource() to iterate through all the resources.
558 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
559 * and there's no way to program the bridge with the details of the window.
560 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
561 * decode bit set, because they are explicit and can be programmed with _SRS.
563 #define PCI_SUBTRACTIVE_DECODE 0x1
565 struct pci_bus_resource {
566 struct list_head list;
567 struct resource *res;
571 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
574 struct list_head node; /* Node in list of buses */
575 struct pci_bus *parent; /* Parent bus this bridge is on */
576 struct list_head children; /* List of child buses */
577 struct list_head devices; /* List of devices on this bus */
578 struct pci_dev *self; /* Bridge device as seen by parent */
579 struct list_head slots; /* List of slots on this bus;
580 protected by pci_slot_mutex */
581 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
582 struct list_head resources; /* Address space routed to this bus */
583 struct resource busn_res; /* Bus numbers routed to this bus */
585 struct pci_ops *ops; /* Configuration access functions */
586 struct msi_controller *msi; /* MSI controller */
587 void *sysdata; /* Hook for sys-specific extension */
588 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
590 unsigned char number; /* Bus number */
591 unsigned char primary; /* Number of primary bridge */
592 unsigned char max_bus_speed; /* enum pci_bus_speed */
593 unsigned char cur_bus_speed; /* enum pci_bus_speed */
594 #ifdef CONFIG_PCI_DOMAINS_GENERIC
600 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
601 pci_bus_flags_t bus_flags; /* Inherited by child buses */
602 struct device *bridge;
604 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
605 struct bin_attribute *legacy_mem; /* Legacy mem */
606 unsigned int is_added:1;
607 unsigned int unsafe_warn:1; /* warned about RW1C config write */
610 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
612 static inline u16 pci_dev_id(struct pci_dev *dev)
614 return PCI_DEVID(dev->bus->number, dev->devfn);
618 * Returns true if the PCI bus is root (behind host-PCI bridge),
621 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
622 * This is incorrect because "virtual" buses added for SR-IOV (via
623 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
625 static inline bool pci_is_root_bus(struct pci_bus *pbus)
627 return !(pbus->parent);
631 * pci_is_bridge - check if the PCI device is a bridge
634 * Return true if the PCI device is bridge whether it has subordinate
637 static inline bool pci_is_bridge(struct pci_dev *dev)
639 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
640 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
643 #define for_each_pci_bridge(dev, bus) \
644 list_for_each_entry(dev, &bus->devices, bus_list) \
645 if (!pci_is_bridge(dev)) {} else
647 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
649 dev = pci_physfn(dev);
650 if (pci_is_root_bus(dev->bus))
653 return dev->bus->self;
656 #ifdef CONFIG_PCI_MSI
657 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
659 return pci_dev->msi_enabled || pci_dev->msix_enabled;
662 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
665 /* Error values that may be returned by PCI functions */
666 #define PCIBIOS_SUCCESSFUL 0x00
667 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
668 #define PCIBIOS_BAD_VENDOR_ID 0x83
669 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
670 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
671 #define PCIBIOS_SET_FAILED 0x88
672 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
674 /* Translate above to generic errno for passing back through non-PCI code */
675 static inline int pcibios_err_to_errno(int err)
677 if (err <= PCIBIOS_SUCCESSFUL)
678 return err; /* Assume already errno */
681 case PCIBIOS_FUNC_NOT_SUPPORTED:
683 case PCIBIOS_BAD_VENDOR_ID:
685 case PCIBIOS_DEVICE_NOT_FOUND:
687 case PCIBIOS_BAD_REGISTER_NUMBER:
689 case PCIBIOS_SET_FAILED:
691 case PCIBIOS_BUFFER_TOO_SMALL:
698 /* Low-level architecture-dependent routines */
701 int (*add_bus)(struct pci_bus *bus);
702 void (*remove_bus)(struct pci_bus *bus);
703 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
704 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
705 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
709 * ACPI needs to be able to access PCI config space before we've done a
710 * PCI bus scan and created pci_bus structures.
712 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
713 int reg, int len, u32 *val);
714 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
715 int reg, int len, u32 val);
717 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
718 typedef u64 pci_bus_addr_t;
720 typedef u32 pci_bus_addr_t;
723 struct pci_bus_region {
724 pci_bus_addr_t start;
729 spinlock_t lock; /* Protects list, index */
730 struct list_head list; /* For IDs added at runtime */
735 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
736 * a set of callbacks in struct pci_error_handlers, that device driver
737 * will be notified of PCI bus errors, and will be driven to recovery
738 * when an error occurs.
741 typedef unsigned int __bitwise pci_ers_result_t;
743 enum pci_ers_result {
744 /* No result/none/not supported in device driver */
745 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
747 /* Device driver can recover without slot reset */
748 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
750 /* Device driver wants slot to be reset */
751 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
753 /* Device has completely failed, is unrecoverable */
754 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
756 /* Device driver is fully recovered and operational */
757 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
759 /* No AER capabilities registered for the driver */
760 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
763 /* PCI bus error event callbacks */
764 struct pci_error_handlers {
765 /* PCI bus error detected on this device */
766 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
767 enum pci_channel_state error);
769 /* MMIO has been re-enabled, but not DMA */
770 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
772 /* PCI slot has been reset */
773 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
775 /* PCI function reset prepare or completed */
776 void (*reset_prepare)(struct pci_dev *dev);
777 void (*reset_done)(struct pci_dev *dev);
779 /* Device driver may resume normal operations */
780 void (*resume)(struct pci_dev *dev);
787 * struct pci_driver - PCI driver structure
788 * @node: List of driver structures.
789 * @name: Driver name.
790 * @id_table: Pointer to table of device IDs the driver is
791 * interested in. Most drivers should export this
792 * table using MODULE_DEVICE_TABLE(pci,...).
793 * @probe: This probing function gets called (during execution
794 * of pci_register_driver() for already existing
795 * devices or later if a new device gets inserted) for
796 * all PCI devices which match the ID table and are not
797 * "owned" by the other drivers yet. This function gets
798 * passed a "struct pci_dev \*" for each device whose
799 * entry in the ID table matches the device. The probe
800 * function returns zero when the driver chooses to
801 * take "ownership" of the device or an error code
802 * (negative number) otherwise.
803 * The probe function always gets called from process
804 * context, so it can sleep.
805 * @remove: The remove() function gets called whenever a device
806 * being handled by this driver is removed (either during
807 * deregistration of the driver or when it's manually
808 * pulled out of a hot-pluggable slot).
809 * The remove function always gets called from process
810 * context, so it can sleep.
811 * @suspend: Put device into low power state.
812 * @suspend_late: Put device into low power state.
813 * @resume_early: Wake device from low power state.
814 * @resume: Wake device from low power state.
815 * (Please see Documentation/power/pci.rst for descriptions
816 * of PCI Power Management and the related functions.)
817 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
818 * Intended to stop any idling DMA operations.
819 * Useful for enabling wake-on-lan (NIC) or changing
820 * the power state of a device before reboot.
821 * e.g. drivers/net/e100.c.
822 * @sriov_configure: Optional driver callback to allow configuration of
823 * number of VFs to enable via sysfs "sriov_numvfs" file.
824 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
825 * @groups: Sysfs attribute groups.
826 * @driver: Driver model structure.
827 * @dynids: List of dynamically added device IDs.
830 struct list_head node;
832 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
833 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
834 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
835 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
836 int (*suspend_late)(struct pci_dev *dev, pm_message_t state);
837 int (*resume_early)(struct pci_dev *dev);
838 int (*resume)(struct pci_dev *dev); /* Device woken up */
839 void (*shutdown)(struct pci_dev *dev);
840 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
841 const struct pci_error_handlers *err_handler;
842 const struct attribute_group **groups;
843 struct device_driver driver;
844 struct pci_dynids dynids;
847 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
850 * PCI_DEVICE - macro used to describe a specific PCI device
851 * @vend: the 16 bit PCI Vendor ID
852 * @dev: the 16 bit PCI Device ID
854 * This macro is used to create a struct pci_device_id that matches a
855 * specific device. The subvendor and subdevice fields will be set to
858 #define PCI_DEVICE(vend,dev) \
859 .vendor = (vend), .device = (dev), \
860 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
863 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
864 * @vend: the 16 bit PCI Vendor ID
865 * @dev: the 16 bit PCI Device ID
866 * @subvend: the 16 bit PCI Subvendor ID
867 * @subdev: the 16 bit PCI Subdevice ID
869 * This macro is used to create a struct pci_device_id that matches a
870 * specific device with subsystem information.
872 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
873 .vendor = (vend), .device = (dev), \
874 .subvendor = (subvend), .subdevice = (subdev)
877 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
878 * @dev_class: the class, subclass, prog-if triple for this device
879 * @dev_class_mask: the class mask for this device
881 * This macro is used to create a struct pci_device_id that matches a
882 * specific PCI class. The vendor, device, subvendor, and subdevice
883 * fields will be set to PCI_ANY_ID.
885 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
886 .class = (dev_class), .class_mask = (dev_class_mask), \
887 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
888 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
891 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
892 * @vend: the vendor name
893 * @dev: the 16 bit PCI Device ID
895 * This macro is used to create a struct pci_device_id that matches a
896 * specific PCI device. The subvendor, and subdevice fields will be set
897 * to PCI_ANY_ID. The macro allows the next field to follow as the device
900 #define PCI_VDEVICE(vend, dev) \
901 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
902 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
905 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
906 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
907 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
908 * @data: the driver data to be filled
910 * This macro is used to create a struct pci_device_id that matches a
911 * specific PCI device. The subvendor, and subdevice fields will be set
914 #define PCI_DEVICE_DATA(vend, dev, data) \
915 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
916 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
917 .driver_data = (kernel_ulong_t)(data)
920 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
921 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
922 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
923 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
924 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
925 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
926 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
929 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
930 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
931 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
932 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
934 /* These external functions are only available when PCI support is enabled */
937 extern unsigned int pci_flags;
939 static inline void pci_set_flags(int flags) { pci_flags = flags; }
940 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
941 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
942 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
944 void pcie_bus_configure_settings(struct pci_bus *bus);
946 enum pcie_bus_config_types {
947 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
948 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
949 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
950 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
951 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
954 extern enum pcie_bus_config_types pcie_bus_config;
956 extern struct bus_type pci_bus_type;
958 /* Do NOT directly access these two variables, unless you are arch-specific PCI
959 * code, or PCI core code. */
960 extern struct list_head pci_root_buses; /* List of all known PCI buses */
961 /* Some device drivers need know if PCI is initiated */
962 int no_pci_devices(void);
964 void pcibios_resource_survey_bus(struct pci_bus *bus);
965 void pcibios_bus_add_device(struct pci_dev *pdev);
966 void pcibios_add_bus(struct pci_bus *bus);
967 void pcibios_remove_bus(struct pci_bus *bus);
968 void pcibios_fixup_bus(struct pci_bus *);
969 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
970 /* Architecture-specific versions may override this (weak) */
971 char *pcibios_setup(char *str);
973 /* Used only when drivers/pci/setup.c is used */
974 resource_size_t pcibios_align_resource(void *, const struct resource *,
978 /* Weak but can be overridden by arch */
979 void pci_fixup_cardbus(struct pci_bus *);
981 /* Generic PCI functions used internally */
983 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
984 struct resource *res);
985 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
986 struct pci_bus_region *region);
987 void pcibios_scan_specific_bus(int busn);
988 struct pci_bus *pci_find_bus(int domain, int busnr);
989 void pci_bus_add_devices(const struct pci_bus *bus);
990 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
991 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
992 struct pci_ops *ops, void *sysdata,
993 struct list_head *resources);
994 int pci_host_probe(struct pci_host_bridge *bridge);
995 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
996 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
997 void pci_bus_release_busn_res(struct pci_bus *b);
998 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
999 struct pci_ops *ops, void *sysdata,
1000 struct list_head *resources);
1001 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1002 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1004 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1006 struct hotplug_slot *hotplug);
1007 void pci_destroy_slot(struct pci_slot *slot);
1009 void pci_dev_assign_slot(struct pci_dev *dev);
1011 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1013 int pci_scan_slot(struct pci_bus *bus, int devfn);
1014 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1015 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1016 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1017 void pci_bus_add_device(struct pci_dev *dev);
1018 void pci_read_bridge_bases(struct pci_bus *child);
1019 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1020 struct resource *res);
1021 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
1022 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1023 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1024 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1025 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1026 void pci_dev_put(struct pci_dev *dev);
1027 void pci_remove_bus(struct pci_bus *b);
1028 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1029 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1030 void pci_stop_root_bus(struct pci_bus *bus);
1031 void pci_remove_root_bus(struct pci_bus *bus);
1032 void pci_setup_cardbus(struct pci_bus *bus);
1033 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1034 void pci_sort_breadthfirst(void);
1035 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1036 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1038 /* Generic PCI functions exported to card drivers */
1040 enum pci_lost_interrupt_reason {
1041 PCI_LOST_IRQ_NO_INFORMATION = 0,
1042 PCI_LOST_IRQ_DISABLE_MSI,
1043 PCI_LOST_IRQ_DISABLE_MSIX,
1044 PCI_LOST_IRQ_DISABLE_ACPI,
1046 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
1047 int pci_find_capability(struct pci_dev *dev, int cap);
1048 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1049 int pci_find_ext_capability(struct pci_dev *dev, int cap);
1050 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
1051 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1052 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
1053 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1055 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1056 struct pci_dev *from);
1057 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1058 unsigned int ss_vendor, unsigned int ss_device,
1059 struct pci_dev *from);
1060 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1061 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1062 unsigned int devfn);
1063 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1064 int pci_dev_present(const struct pci_device_id *ids);
1066 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1067 int where, u8 *val);
1068 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1069 int where, u16 *val);
1070 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1071 int where, u32 *val);
1072 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1074 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1075 int where, u16 val);
1076 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1077 int where, u32 val);
1079 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1080 int where, int size, u32 *val);
1081 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1082 int where, int size, u32 val);
1083 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1084 int where, int size, u32 *val);
1085 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1086 int where, int size, u32 val);
1088 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1090 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1091 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1092 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1093 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1094 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1095 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1097 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1098 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1099 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1100 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1101 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1102 u16 clear, u16 set);
1103 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1104 u32 clear, u32 set);
1106 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1109 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1112 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1115 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1118 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1121 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1124 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1127 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1130 /* User-space driven config access */
1131 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1132 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1133 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1134 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1135 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1136 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1138 int __must_check pci_enable_device(struct pci_dev *dev);
1139 int __must_check pci_enable_device_io(struct pci_dev *dev);
1140 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1141 int __must_check pci_reenable_device(struct pci_dev *);
1142 int __must_check pcim_enable_device(struct pci_dev *pdev);
1143 void pcim_pin_device(struct pci_dev *pdev);
1145 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1148 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1149 * writable and no quirk has marked the feature broken.
1151 return !pdev->broken_intx_masking;
1154 static inline int pci_is_enabled(struct pci_dev *pdev)
1156 return (atomic_read(&pdev->enable_cnt) > 0);
1159 static inline int pci_is_managed(struct pci_dev *pdev)
1161 return pdev->is_managed;
1164 void pci_disable_device(struct pci_dev *dev);
1166 extern unsigned int pcibios_max_latency;
1167 void pci_set_master(struct pci_dev *dev);
1168 void pci_clear_master(struct pci_dev *dev);
1170 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1171 int pci_set_cacheline_size(struct pci_dev *dev);
1172 #define HAVE_PCI_SET_MWI
1173 int __must_check pci_set_mwi(struct pci_dev *dev);
1174 int __must_check pcim_set_mwi(struct pci_dev *dev);
1175 int pci_try_set_mwi(struct pci_dev *dev);
1176 void pci_clear_mwi(struct pci_dev *dev);
1177 void pci_intx(struct pci_dev *dev, int enable);
1178 bool pci_check_and_mask_intx(struct pci_dev *dev);
1179 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1180 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1181 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1182 int pcix_get_max_mmrbc(struct pci_dev *dev);
1183 int pcix_get_mmrbc(struct pci_dev *dev);
1184 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1185 int pcie_get_readrq(struct pci_dev *dev);
1186 int pcie_set_readrq(struct pci_dev *dev, int rq);
1187 int pcie_get_mps(struct pci_dev *dev);
1188 int pcie_set_mps(struct pci_dev *dev, int mps);
1189 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1190 enum pci_bus_speed *speed,
1191 enum pcie_link_width *width);
1192 void pcie_print_link_status(struct pci_dev *dev);
1193 bool pcie_has_flr(struct pci_dev *dev);
1194 int pcie_flr(struct pci_dev *dev);
1195 int __pci_reset_function_locked(struct pci_dev *dev);
1196 int pci_reset_function(struct pci_dev *dev);
1197 int pci_reset_function_locked(struct pci_dev *dev);
1198 int pci_try_reset_function(struct pci_dev *dev);
1199 int pci_probe_reset_slot(struct pci_slot *slot);
1200 int pci_probe_reset_bus(struct pci_bus *bus);
1201 int pci_reset_bus(struct pci_dev *dev);
1202 void pci_reset_secondary_bus(struct pci_dev *dev);
1203 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1204 void pci_update_resource(struct pci_dev *dev, int resno);
1205 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1206 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1207 void pci_release_resource(struct pci_dev *dev, int resno);
1208 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1209 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1210 bool pci_device_is_present(struct pci_dev *pdev);
1211 void pci_ignore_hotplug(struct pci_dev *dev);
1213 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1214 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1215 const char *fmt, ...);
1216 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1218 /* ROM control related routines */
1219 int pci_enable_rom(struct pci_dev *pdev);
1220 void pci_disable_rom(struct pci_dev *pdev);
1221 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1222 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1224 /* Power management related routines */
1225 int pci_save_state(struct pci_dev *dev);
1226 void pci_restore_state(struct pci_dev *dev);
1227 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1228 int pci_load_saved_state(struct pci_dev *dev,
1229 struct pci_saved_state *state);
1230 int pci_load_and_free_saved_state(struct pci_dev *dev,
1231 struct pci_saved_state **state);
1232 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1233 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1235 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1236 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1237 u16 cap, unsigned int size);
1238 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1239 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1240 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1241 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1242 void pci_pme_active(struct pci_dev *dev, bool enable);
1243 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1244 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1245 int pci_prepare_to_sleep(struct pci_dev *dev);
1246 int pci_back_from_sleep(struct pci_dev *dev);
1247 bool pci_dev_run_wake(struct pci_dev *dev);
1248 void pci_d3cold_enable(struct pci_dev *dev);
1249 void pci_d3cold_disable(struct pci_dev *dev);
1250 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1251 void pci_wakeup_bus(struct pci_bus *bus);
1252 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1254 /* For use by arch with custom probe code */
1255 void set_pcie_port_type(struct pci_dev *pdev);
1256 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1258 /* Functions for PCI Hotplug drivers to use */
1259 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1260 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1261 unsigned int pci_rescan_bus(struct pci_bus *bus);
1262 void pci_lock_rescan_remove(void);
1263 void pci_unlock_rescan_remove(void);
1265 /* Vital Product Data routines */
1266 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1267 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1268 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1270 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1271 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1272 void pci_bus_assign_resources(const struct pci_bus *bus);
1273 void pci_bus_claim_resources(struct pci_bus *bus);
1274 void pci_bus_size_bridges(struct pci_bus *bus);
1275 int pci_claim_resource(struct pci_dev *, int);
1276 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1277 void pci_assign_unassigned_resources(void);
1278 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1279 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1280 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1281 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1282 void pdev_enable_device(struct pci_dev *);
1283 int pci_enable_resources(struct pci_dev *, int mask);
1284 void pci_assign_irq(struct pci_dev *dev);
1285 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1286 #define HAVE_PCI_REQ_REGIONS 2
1287 int __must_check pci_request_regions(struct pci_dev *, const char *);
1288 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1289 void pci_release_regions(struct pci_dev *);
1290 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1291 void pci_release_region(struct pci_dev *, int);
1292 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1293 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1294 void pci_release_selected_regions(struct pci_dev *, int);
1296 /* drivers/pci/bus.c */
1297 void pci_add_resource(struct list_head *resources, struct resource *res);
1298 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1299 resource_size_t offset);
1300 void pci_free_resource_list(struct list_head *resources);
1301 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1302 unsigned int flags);
1303 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1304 void pci_bus_remove_resources(struct pci_bus *bus);
1305 int devm_request_pci_bus_resources(struct device *dev,
1306 struct list_head *resources);
1308 /* Temporary until new and working PCI SBR API in place */
1309 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1311 #define pci_bus_for_each_resource(bus, res, i) \
1313 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1316 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1317 struct resource *res, resource_size_t size,
1318 resource_size_t align, resource_size_t min,
1319 unsigned long type_mask,
1320 resource_size_t (*alignf)(void *,
1321 const struct resource *,
1327 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1328 resource_size_t size);
1329 unsigned long pci_address_to_pio(phys_addr_t addr);
1330 phys_addr_t pci_pio_to_address(unsigned long pio);
1331 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1332 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1333 phys_addr_t phys_addr);
1334 void pci_unmap_iospace(struct resource *res);
1335 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1336 resource_size_t offset,
1337 resource_size_t size);
1338 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1339 struct resource *res);
1341 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1343 struct pci_bus_region region;
1345 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1346 return region.start;
1349 /* Proper probing supporting hot-pluggable devices */
1350 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1351 const char *mod_name);
1353 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1354 #define pci_register_driver(driver) \
1355 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1357 void pci_unregister_driver(struct pci_driver *dev);
1360 * module_pci_driver() - Helper macro for registering a PCI driver
1361 * @__pci_driver: pci_driver struct
1363 * Helper macro for PCI drivers which do not do anything special in module
1364 * init/exit. This eliminates a lot of boilerplate. Each module may only
1365 * use this macro once, and calling it replaces module_init() and module_exit()
1367 #define module_pci_driver(__pci_driver) \
1368 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1371 * builtin_pci_driver() - Helper macro for registering a PCI driver
1372 * @__pci_driver: pci_driver struct
1374 * Helper macro for PCI drivers which do not do anything special in their
1375 * init code. This eliminates a lot of boilerplate. Each driver may only
1376 * use this macro once, and calling it replaces device_initcall(...)
1378 #define builtin_pci_driver(__pci_driver) \
1379 builtin_driver(__pci_driver, pci_register_driver)
1381 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1382 int pci_add_dynid(struct pci_driver *drv,
1383 unsigned int vendor, unsigned int device,
1384 unsigned int subvendor, unsigned int subdevice,
1385 unsigned int class, unsigned int class_mask,
1386 unsigned long driver_data);
1387 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1388 struct pci_dev *dev);
1389 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1392 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1394 int pci_cfg_space_size(struct pci_dev *dev);
1395 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1396 void pci_setup_bridge(struct pci_bus *bus);
1397 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1398 unsigned long type);
1400 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1401 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1403 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1404 unsigned int command_bits, u32 flags);
1407 * Virtual interrupts allow for more interrupts to be allocated
1408 * than the device has interrupts for. These are not programmed
1409 * into the device's MSI-X table and must be handled by some
1410 * other driver means.
1412 #define PCI_IRQ_VIRTUAL (1 << 4)
1414 #define PCI_IRQ_ALL_TYPES \
1415 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1417 /* kmem_cache style wrapper around pci_alloc_consistent() */
1419 #include <linux/dmapool.h>
1421 #define pci_pool dma_pool
1422 #define pci_pool_create(name, pdev, size, align, allocation) \
1423 dma_pool_create(name, &pdev->dev, size, align, allocation)
1424 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1425 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1426 #define pci_pool_zalloc(pool, flags, handle) \
1427 dma_pool_zalloc(pool, flags, handle)
1428 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1431 u32 vector; /* Kernel uses to write allocated vector */
1432 u16 entry; /* Driver uses to specify entry, OS writes */
1435 #ifdef CONFIG_PCI_MSI
1436 int pci_msi_vec_count(struct pci_dev *dev);
1437 void pci_disable_msi(struct pci_dev *dev);
1438 int pci_msix_vec_count(struct pci_dev *dev);
1439 void pci_disable_msix(struct pci_dev *dev);
1440 void pci_restore_msi_state(struct pci_dev *dev);
1441 int pci_msi_enabled(void);
1442 int pci_enable_msi(struct pci_dev *dev);
1443 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1444 int minvec, int maxvec);
1445 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1446 struct msix_entry *entries, int nvec)
1448 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1453 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1454 unsigned int max_vecs, unsigned int flags,
1455 struct irq_affinity *affd);
1457 void pci_free_irq_vectors(struct pci_dev *dev);
1458 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1459 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1460 int pci_irq_get_node(struct pci_dev *pdev, int vec);
1463 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1464 static inline void pci_disable_msi(struct pci_dev *dev) { }
1465 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1466 static inline void pci_disable_msix(struct pci_dev *dev) { }
1467 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1468 static inline int pci_msi_enabled(void) { return 0; }
1469 static inline int pci_enable_msi(struct pci_dev *dev)
1471 static inline int pci_enable_msix_range(struct pci_dev *dev,
1472 struct msix_entry *entries, int minvec, int maxvec)
1474 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1475 struct msix_entry *entries, int nvec)
1479 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1480 unsigned int max_vecs, unsigned int flags,
1481 struct irq_affinity *aff_desc)
1483 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1488 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1492 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1494 if (WARN_ON_ONCE(nr > 0))
1498 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1501 return cpu_possible_mask;
1504 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1506 return first_online_node;
1511 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1512 * @d: the INTx IRQ domain
1513 * @node: the DT node for the device whose interrupt we're translating
1514 * @intspec: the interrupt specifier data from the DT
1515 * @intsize: the number of entries in @intspec
1516 * @out_hwirq: pointer at which to write the hwirq number
1517 * @out_type: pointer at which to write the interrupt type
1519 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1520 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1521 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1522 * INTx value to obtain the hwirq number.
1524 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1526 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1527 struct device_node *node,
1529 unsigned int intsize,
1530 unsigned long *out_hwirq,
1531 unsigned int *out_type)
1533 const u32 intx = intspec[0];
1535 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1538 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1542 #ifdef CONFIG_PCIEPORTBUS
1543 extern bool pcie_ports_disabled;
1544 extern bool pcie_ports_native;
1546 #define pcie_ports_disabled true
1547 #define pcie_ports_native false
1550 #define PCIE_LINK_STATE_L0S 1
1551 #define PCIE_LINK_STATE_L1 2
1552 #define PCIE_LINK_STATE_CLKPM 4
1554 #ifdef CONFIG_PCIEASPM
1555 int pci_disable_link_state(struct pci_dev *pdev, int state);
1556 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1557 void pcie_no_aspm(void);
1558 bool pcie_aspm_support_enabled(void);
1559 bool pcie_aspm_enabled(struct pci_dev *pdev);
1561 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1563 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1565 static inline void pcie_no_aspm(void) { }
1566 static inline bool pcie_aspm_support_enabled(void) { return false; }
1567 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1570 #ifdef CONFIG_PCIEAER
1571 bool pci_aer_available(void);
1573 static inline bool pci_aer_available(void) { return false; }
1576 bool pci_ats_disabled(void);
1578 void pci_cfg_access_lock(struct pci_dev *dev);
1579 bool pci_cfg_access_trylock(struct pci_dev *dev);
1580 void pci_cfg_access_unlock(struct pci_dev *dev);
1583 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1584 * a PCI domain is defined to be a set of PCI buses which share
1585 * configuration space.
1587 #ifdef CONFIG_PCI_DOMAINS
1588 extern int pci_domains_supported;
1590 enum { pci_domains_supported = 0 };
1591 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1592 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1593 #endif /* CONFIG_PCI_DOMAINS */
1596 * Generic implementation for PCI domain support. If your
1597 * architecture does not need custom management of PCI
1598 * domains then this implementation will be used
1600 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1601 static inline int pci_domain_nr(struct pci_bus *bus)
1603 return bus->domain_nr;
1606 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1608 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1611 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1614 /* Some architectures require additional setup to direct VGA traffic */
1615 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1616 unsigned int command_bits, u32 flags);
1617 void pci_register_set_vga_state(arch_set_vga_state_t func);
1620 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1622 return pci_request_selected_regions(pdev,
1623 pci_select_bars(pdev, IORESOURCE_IO), name);
1627 pci_release_io_regions(struct pci_dev *pdev)
1629 return pci_release_selected_regions(pdev,
1630 pci_select_bars(pdev, IORESOURCE_IO));
1634 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1636 return pci_request_selected_regions(pdev,
1637 pci_select_bars(pdev, IORESOURCE_MEM), name);
1641 pci_release_mem_regions(struct pci_dev *pdev)
1643 return pci_release_selected_regions(pdev,
1644 pci_select_bars(pdev, IORESOURCE_MEM));
1647 #else /* CONFIG_PCI is not enabled */
1649 static inline void pci_set_flags(int flags) { }
1650 static inline void pci_add_flags(int flags) { }
1651 static inline void pci_clear_flags(int flags) { }
1652 static inline int pci_has_flag(int flag) { return 0; }
1655 * If the system does not have PCI, clearly these return errors. Define
1656 * these as simple inline functions to avoid hair in drivers.
1658 #define _PCI_NOP(o, s, t) \
1659 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1661 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1663 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1664 _PCI_NOP(o, word, u16 x) \
1665 _PCI_NOP(o, dword, u32 x)
1666 _PCI_NOP_ALL(read, *)
1667 _PCI_NOP_ALL(write,)
1669 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1670 unsigned int device,
1671 struct pci_dev *from)
1674 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1675 unsigned int device,
1676 unsigned int ss_vendor,
1677 unsigned int ss_device,
1678 struct pci_dev *from)
1681 static inline struct pci_dev *pci_get_class(unsigned int class,
1682 struct pci_dev *from)
1685 #define pci_dev_present(ids) (0)
1686 #define no_pci_devices() (1)
1687 #define pci_dev_put(dev) do { } while (0)
1689 static inline void pci_set_master(struct pci_dev *dev) { }
1690 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1691 static inline void pci_disable_device(struct pci_dev *dev) { }
1692 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1694 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1695 struct module *owner,
1696 const char *mod_name)
1698 static inline int pci_register_driver(struct pci_driver *drv)
1700 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1701 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1703 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1706 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1709 /* Power management related routines */
1710 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1711 static inline void pci_restore_state(struct pci_dev *dev) { }
1712 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1714 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1716 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1719 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1723 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1724 struct resource *res)
1726 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1728 static inline void pci_release_regions(struct pci_dev *dev) { }
1730 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1732 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1734 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1737 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1738 unsigned int bus, unsigned int devfn)
1741 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1742 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1744 #define dev_is_pci(d) (false)
1745 #define dev_is_pf(d) (false)
1746 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1748 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1749 struct device_node *node,
1751 unsigned int intsize,
1752 unsigned long *out_hwirq,
1753 unsigned int *out_type)
1756 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1757 struct pci_dev *dev)
1759 static inline bool pci_ats_disabled(void) { return true; }
1761 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1767 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1768 unsigned int max_vecs, unsigned int flags,
1769 struct irq_affinity *aff_desc)
1773 #endif /* CONFIG_PCI */
1776 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1777 unsigned int max_vecs, unsigned int flags)
1779 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1783 #ifdef CONFIG_PCI_ATS
1784 /* Address Translation Service */
1785 int pci_enable_ats(struct pci_dev *dev, int ps);
1786 void pci_disable_ats(struct pci_dev *dev);
1787 int pci_ats_queue_depth(struct pci_dev *dev);
1788 int pci_ats_page_aligned(struct pci_dev *dev);
1790 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1791 static inline void pci_disable_ats(struct pci_dev *d) { }
1792 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1793 static inline int pci_ats_page_aligned(struct pci_dev *dev) { return 0; }
1796 /* Include architecture-dependent settings and functions */
1798 #include <asm/pci.h>
1800 /* These two functions provide almost identical functionality. Depending
1801 * on the architecture, one will be implemented as a wrapper around the
1802 * other (in drivers/pci/mmap.c).
1804 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1805 * is expected to be an offset within that region.
1807 * pci_mmap_page_range() is the legacy architecture-specific interface,
1808 * which accepts a "user visible" resource address converted by
1809 * pci_resource_to_user(), as used in the legacy mmap() interface in
1812 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1813 struct vm_area_struct *vma,
1814 enum pci_mmap_state mmap_state, int write_combine);
1815 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1816 struct vm_area_struct *vma,
1817 enum pci_mmap_state mmap_state, int write_combine);
1819 #ifndef arch_can_pci_mmap_wc
1820 #define arch_can_pci_mmap_wc() 0
1823 #ifndef arch_can_pci_mmap_io
1824 #define arch_can_pci_mmap_io() 0
1825 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1827 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1830 #ifndef pci_root_bus_fwnode
1831 #define pci_root_bus_fwnode(bus) NULL
1835 * These helpers provide future and backwards compatibility
1836 * for accessing popular PCI BAR info
1838 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1839 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1840 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1841 #define pci_resource_len(dev,bar) \
1842 ((pci_resource_start((dev), (bar)) == 0 && \
1843 pci_resource_end((dev), (bar)) == \
1844 pci_resource_start((dev), (bar))) ? 0 : \
1846 (pci_resource_end((dev), (bar)) - \
1847 pci_resource_start((dev), (bar)) + 1))
1850 * Similar to the helpers above, these manipulate per-pci_dev
1851 * driver-specific data. They are really just a wrapper around
1852 * the generic device structure functions of these calls.
1854 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1856 return dev_get_drvdata(&pdev->dev);
1859 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1861 dev_set_drvdata(&pdev->dev, data);
1864 static inline const char *pci_name(const struct pci_dev *pdev)
1866 return dev_name(&pdev->dev);
1869 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1870 const struct resource *rsrc,
1871 resource_size_t *start, resource_size_t *end);
1874 * The world is not perfect and supplies us with broken PCI devices.
1875 * For at least a part of these bugs we need a work-around, so both
1876 * generic (drivers/pci/quirks.c) and per-architecture code can define
1877 * fixup hooks to be called for particular buggy devices.
1881 u16 vendor; /* Or PCI_ANY_ID */
1882 u16 device; /* Or PCI_ANY_ID */
1883 u32 class; /* Or PCI_ANY_ID */
1884 unsigned int class_shift; /* should be 0, 8, 16 */
1885 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1888 void (*hook)(struct pci_dev *dev);
1892 enum pci_fixup_pass {
1893 pci_fixup_early, /* Before probing BARs */
1894 pci_fixup_header, /* After reading configuration header */
1895 pci_fixup_final, /* Final phase of device fixups */
1896 pci_fixup_enable, /* pci_enable_device() time */
1897 pci_fixup_resume, /* pci_device_resume() */
1898 pci_fixup_suspend, /* pci_device_suspend() */
1899 pci_fixup_resume_early, /* pci_device_resume_early() */
1900 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1903 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1904 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1905 class_shift, hook) \
1906 __ADDRESSABLE(hook) \
1907 asm(".section " #sec ", \"a\" \n" \
1909 ".short " #vendor ", " #device " \n" \
1910 ".long " #class ", " #class_shift " \n" \
1911 ".long " #hook " - . \n" \
1913 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1914 class_shift, hook) \
1915 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1918 /* Anonymous variables would be nice... */
1919 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1920 class_shift, hook) \
1921 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1922 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1923 = { vendor, device, class, class_shift, hook };
1926 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1927 class_shift, hook) \
1928 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1929 hook, vendor, device, class, class_shift, hook)
1930 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1931 class_shift, hook) \
1932 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1933 hook, vendor, device, class, class_shift, hook)
1934 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1935 class_shift, hook) \
1936 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1937 hook, vendor, device, class, class_shift, hook)
1938 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1939 class_shift, hook) \
1940 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1941 hook, vendor, device, class, class_shift, hook)
1942 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1943 class_shift, hook) \
1944 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1945 resume##hook, vendor, device, class, class_shift, hook)
1946 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1947 class_shift, hook) \
1948 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1949 resume_early##hook, vendor, device, class, class_shift, hook)
1950 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1951 class_shift, hook) \
1952 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1953 suspend##hook, vendor, device, class, class_shift, hook)
1954 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1955 class_shift, hook) \
1956 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1957 suspend_late##hook, vendor, device, class, class_shift, hook)
1959 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1960 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1961 hook, vendor, device, PCI_ANY_ID, 0, hook)
1962 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1963 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1964 hook, vendor, device, PCI_ANY_ID, 0, hook)
1965 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1966 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1967 hook, vendor, device, PCI_ANY_ID, 0, hook)
1968 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1969 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1970 hook, vendor, device, PCI_ANY_ID, 0, hook)
1971 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1972 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1973 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1974 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1975 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1976 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1977 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1978 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1979 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
1980 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1981 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1982 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1984 #ifdef CONFIG_PCI_QUIRKS
1985 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1987 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1988 struct pci_dev *dev) { }
1991 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1992 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1993 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1994 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1995 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1997 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1999 extern int pci_pci_problems;
2000 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2001 #define PCIPCI_TRITON 2
2002 #define PCIPCI_NATOMA 4
2003 #define PCIPCI_VIAETBF 8
2004 #define PCIPCI_VSFX 16
2005 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2006 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2008 extern unsigned long pci_cardbus_io_size;
2009 extern unsigned long pci_cardbus_mem_size;
2010 extern u8 pci_dfl_cache_line_size;
2011 extern u8 pci_cache_line_size;
2013 /* Architecture-specific versions may override these (weak) */
2014 void pcibios_disable_device(struct pci_dev *dev);
2015 void pcibios_set_master(struct pci_dev *dev);
2016 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2017 enum pcie_reset_state state);
2018 int pcibios_add_device(struct pci_dev *dev);
2019 void pcibios_release_device(struct pci_dev *dev);
2021 void pcibios_penalize_isa_irq(int irq, int active);
2023 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2025 int pcibios_alloc_irq(struct pci_dev *dev);
2026 void pcibios_free_irq(struct pci_dev *dev);
2027 resource_size_t pcibios_default_alignment(void);
2029 #ifdef CONFIG_HIBERNATE_CALLBACKS
2030 extern struct dev_pm_ops pcibios_pm_ops;
2033 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2034 void __init pci_mmcfg_early_init(void);
2035 void __init pci_mmcfg_late_init(void);
2037 static inline void pci_mmcfg_early_init(void) { }
2038 static inline void pci_mmcfg_late_init(void) { }
2041 int pci_ext_cfg_avail(void);
2043 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2044 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2046 #ifdef CONFIG_PCI_IOV
2047 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2048 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2050 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2051 void pci_disable_sriov(struct pci_dev *dev);
2052 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2053 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2054 int pci_num_vf(struct pci_dev *dev);
2055 int pci_vfs_assigned(struct pci_dev *dev);
2056 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2057 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2058 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2059 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2060 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2062 /* Arch may override these (weak) */
2063 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2064 int pcibios_sriov_disable(struct pci_dev *pdev);
2065 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2067 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2071 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2075 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2077 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2081 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2083 static inline void pci_disable_sriov(struct pci_dev *dev) { }
2084 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2085 static inline int pci_vfs_assigned(struct pci_dev *dev)
2087 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2089 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2091 #define pci_sriov_configure_simple NULL
2092 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2094 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2097 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2098 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2099 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2103 * pci_pcie_cap - get the saved PCIe capability offset
2106 * PCIe capability offset is calculated at PCI device initialization
2107 * time and saved in the data structure. This function returns saved
2108 * PCIe capability offset. Using this instead of pci_find_capability()
2109 * reduces unnecessary search in the PCI configuration space. If you
2110 * need to calculate PCIe capability offset from raw device for some
2111 * reasons, please use pci_find_capability() instead.
2113 static inline int pci_pcie_cap(struct pci_dev *dev)
2115 return dev->pcie_cap;
2119 * pci_is_pcie - check if the PCI device is PCI Express capable
2122 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2124 static inline bool pci_is_pcie(struct pci_dev *dev)
2126 return pci_pcie_cap(dev);
2130 * pcie_caps_reg - get the PCIe Capabilities Register
2133 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2135 return dev->pcie_flags_reg;
2139 * pci_pcie_type - get the PCIe device/port type
2142 static inline int pci_pcie_type(const struct pci_dev *dev)
2144 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2147 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2150 if (!pci_is_pcie(dev))
2152 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2154 if (!dev->bus->self)
2156 dev = dev->bus->self;
2161 void pci_request_acs(void);
2162 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2163 bool pci_acs_path_enabled(struct pci_dev *start,
2164 struct pci_dev *end, u16 acs_flags);
2165 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2167 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2168 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2170 /* Large Resource Data Type Tag Item Names */
2171 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2172 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2173 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2175 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2176 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2177 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2179 /* Small Resource Data Type Tag Item Names */
2180 #define PCI_VPD_STIN_END 0x0f /* End */
2182 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2184 #define PCI_VPD_SRDT_TIN_MASK 0x78
2185 #define PCI_VPD_SRDT_LEN_MASK 0x07
2186 #define PCI_VPD_LRDT_TIN_MASK 0x7f
2188 #define PCI_VPD_LRDT_TAG_SIZE 3
2189 #define PCI_VPD_SRDT_TAG_SIZE 1
2191 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2193 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2194 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2195 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2196 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2199 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2200 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2202 * Returns the extracted Large Resource Data Type length.
2204 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2206 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2210 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2211 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2213 * Returns the extracted Large Resource Data Type Tag item.
2215 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2217 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2221 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2222 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2224 * Returns the extracted Small Resource Data Type length.
2226 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2228 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2232 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2233 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2235 * Returns the extracted Small Resource Data Type Tag Item.
2237 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2239 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2243 * pci_vpd_info_field_size - Extracts the information field length
2244 * @info_field: Pointer to the beginning of an information field header
2246 * Returns the extracted information field length.
2248 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2250 return info_field[2];
2254 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2255 * @buf: Pointer to buffered vpd data
2256 * @off: The offset into the buffer at which to begin the search
2257 * @len: The length of the vpd buffer
2258 * @rdt: The Resource Data Type to search for
2260 * Returns the index where the Resource Data Type was found or
2261 * -ENOENT otherwise.
2263 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2266 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2267 * @buf: Pointer to buffered vpd data
2268 * @off: The offset into the buffer at which to begin the search
2269 * @len: The length of the buffer area, relative to off, in which to search
2270 * @kw: The keyword to search for
2272 * Returns the index where the information field keyword was found or
2273 * -ENOENT otherwise.
2275 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2276 unsigned int len, const char *kw);
2278 /* PCI <-> OF binding helpers */
2282 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2283 int pci_parse_request_of_pci_ranges(struct device *dev,
2284 struct list_head *resources,
2285 struct resource **bus_range);
2287 /* Arch may override this (weak) */
2288 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2290 #else /* CONFIG_OF */
2291 static inline struct irq_domain *
2292 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2293 static inline int pci_parse_request_of_pci_ranges(struct device *dev,
2294 struct list_head *resources,
2295 struct resource **bus_range)
2299 #endif /* CONFIG_OF */
2301 static inline struct device_node *
2302 pci_device_to_OF_node(const struct pci_dev *pdev)
2304 return pdev ? pdev->dev.of_node : NULL;
2307 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2309 return bus ? bus->dev.of_node : NULL;
2313 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2316 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2317 bool pci_pr3_present(struct pci_dev *pdev);
2319 static inline struct irq_domain *
2320 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2321 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2325 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2327 return pdev->dev.archdata.edev;
2331 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2332 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2333 int pci_for_each_dma_alias(struct pci_dev *pdev,
2334 int (*fn)(struct pci_dev *pdev,
2335 u16 alias, void *data), void *data);
2337 /* Helper functions for operation of device flag */
2338 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2340 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2342 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2344 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2346 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2348 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2352 * pci_ari_enabled - query ARI forwarding status
2355 * Returns true if ARI forwarding is enabled.
2357 static inline bool pci_ari_enabled(struct pci_bus *bus)
2359 return bus->self && bus->self->ari_enabled;
2363 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2364 * @pdev: PCI device to check
2366 * Walk upwards from @pdev and check for each encountered bridge if it's part
2367 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2368 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2370 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2372 struct pci_dev *parent = pdev;
2374 if (pdev->is_thunderbolt)
2377 while ((parent = pci_upstream_bridge(parent)))
2378 if (parent->is_thunderbolt)
2384 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2385 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2388 /* Provide the legacy pci_dma_* API */
2389 #include <linux/pci-dma-compat.h>
2391 #define pci_printk(level, pdev, fmt, arg...) \
2392 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2394 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2395 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2396 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2397 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2398 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2399 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2400 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2401 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2403 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2404 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2406 #define pci_info_ratelimited(pdev, fmt, arg...) \
2407 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2409 #endif /* LINUX_PCI_H */