1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
27 #include <linux/mod_devicetable.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
40 #include <linux/resource_ext.h>
41 #include <uapi/linux/pci.h>
43 #include <linux/pci_ids.h>
45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
46 PCI_STATUS_SIG_SYSTEM_ERROR | \
47 PCI_STATUS_REC_MASTER_ABORT | \
48 PCI_STATUS_REC_TARGET_ABORT | \
49 PCI_STATUS_SIG_TARGET_ABORT | \
52 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */
53 #define PCI_NUM_RESET_METHODS 7
55 #define PCI_RESET_PROBE true
56 #define PCI_RESET_DO_RESET false
59 * The PCI interface treats multi-function devices as independent
60 * devices. The slot/function address of each device is encoded
61 * in a single byte as follows:
66 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
67 * In the interest of not exposing interfaces to user-space unnecessarily,
68 * the following kernel-only defines are being added here.
70 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
71 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
72 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
74 /* pci_slot represents a physical slot */
76 struct pci_bus *bus; /* Bus this slot is on */
77 struct list_head list; /* Node in list of slots */
78 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
79 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
83 static inline const char *pci_slot_name(const struct pci_slot *slot)
85 return kobject_name(&slot->kobj);
88 /* File state for mmap()s on /proc/bus/pci/X/Y */
94 /* For PCI devices, the region numbers are assigned this way: */
96 /* #0-5: standard PCI resources */
98 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
100 /* #6: expansion ROM resource */
103 /* Device-specific resources */
104 #ifdef CONFIG_PCI_IOV
106 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
109 /* PCI-to-PCI (P2P) bridge windows */
110 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
111 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
112 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
114 /* CardBus bridge windows */
115 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
116 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
117 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
118 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
120 /* Total number of bridge resources for P2P and CardBus */
121 #define PCI_BRIDGE_RESOURCE_NUM 4
123 /* Resources assigned to buses behind the bridge */
124 PCI_BRIDGE_RESOURCES,
125 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
126 PCI_BRIDGE_RESOURCE_NUM - 1,
128 /* Total resources associated with a PCI device */
131 /* Preserve this for compatibility */
132 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
136 * enum pci_interrupt_pin - PCI INTx interrupt values
137 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
138 * @PCI_INTERRUPT_INTA: PCI INTA pin
139 * @PCI_INTERRUPT_INTB: PCI INTB pin
140 * @PCI_INTERRUPT_INTC: PCI INTC pin
141 * @PCI_INTERRUPT_INTD: PCI INTD pin
143 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
144 * PCI_INTERRUPT_PIN register.
146 enum pci_interrupt_pin {
147 PCI_INTERRUPT_UNKNOWN,
154 /* The number of legacy PCI INTx interrupts */
155 #define PCI_NUM_INTX 4
158 * pci_power_t values must match the bits in the Capabilities PME_Support
159 * and Control/Status PowerState fields in the Power Management capability.
161 typedef int __bitwise pci_power_t;
163 #define PCI_D0 ((pci_power_t __force) 0)
164 #define PCI_D1 ((pci_power_t __force) 1)
165 #define PCI_D2 ((pci_power_t __force) 2)
166 #define PCI_D3hot ((pci_power_t __force) 3)
167 #define PCI_D3cold ((pci_power_t __force) 4)
168 #define PCI_UNKNOWN ((pci_power_t __force) 5)
169 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
171 /* Remember to update this when the list above changes! */
172 extern const char *pci_power_names[];
174 static inline const char *pci_power_name(pci_power_t state)
176 return pci_power_names[1 + (__force int) state];
180 * typedef pci_channel_state_t
182 * The pci_channel state describes connectivity between the CPU and
183 * the PCI device. If some PCI bus between here and the PCI device
184 * has crashed or locked up, this info is reflected here.
186 typedef unsigned int __bitwise pci_channel_state_t;
189 /* I/O channel is in normal state */
190 pci_channel_io_normal = (__force pci_channel_state_t) 1,
192 /* I/O to channel is blocked */
193 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
195 /* PCI card is dead */
196 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
199 typedef unsigned int __bitwise pcie_reset_state_t;
201 enum pcie_reset_state {
202 /* Reset is NOT asserted (Use to deassert reset) */
203 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
205 /* Use #PERST to reset PCIe device */
206 pcie_warm_reset = (__force pcie_reset_state_t) 2,
208 /* Use PCIe Hot Reset to reset device */
209 pcie_hot_reset = (__force pcie_reset_state_t) 3
212 typedef unsigned short __bitwise pci_dev_flags_t;
214 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
215 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
216 /* Device configuration is irrevocably lost if disabled into D3 */
217 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
218 /* Provide indication device is assigned by a Virtual Machine Manager */
219 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
220 /* Flag for quirk use to store if quirk-specific ACS is enabled */
221 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
222 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
223 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
224 /* Do not use bus resets for device */
225 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
226 /* Do not use PM reset even if device advertises NoSoftRst- */
227 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
228 /* Get VPD from function 0 VPD */
229 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
230 /* A non-root bridge where translation occurs, stop alias search here */
231 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
232 /* Do not use FLR even if device advertises PCI_AF_CAP */
233 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
234 /* Don't use Relaxed Ordering for TLPs directed at this device */
235 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
236 /* Device does honor MSI masking despite saying otherwise */
237 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
240 enum pci_irq_reroute_variant {
241 INTEL_IRQ_REROUTE_VARIANT = 1,
242 MAX_IRQ_REROUTE_VARIANTS = 3
245 typedef unsigned short __bitwise pci_bus_flags_t;
247 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
248 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
249 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
250 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
253 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
254 enum pcie_link_width {
255 PCIE_LNK_WIDTH_RESRV = 0x00,
263 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
266 /* See matching string table in pci_speed_string() */
268 PCI_SPEED_33MHz = 0x00,
269 PCI_SPEED_66MHz = 0x01,
270 PCI_SPEED_66MHz_PCIX = 0x02,
271 PCI_SPEED_100MHz_PCIX = 0x03,
272 PCI_SPEED_133MHz_PCIX = 0x04,
273 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
274 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
275 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
276 PCI_SPEED_66MHz_PCIX_266 = 0x09,
277 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
278 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
284 PCI_SPEED_66MHz_PCIX_533 = 0x11,
285 PCI_SPEED_100MHz_PCIX_533 = 0x12,
286 PCI_SPEED_133MHz_PCIX_533 = 0x13,
287 PCIE_SPEED_2_5GT = 0x14,
288 PCIE_SPEED_5_0GT = 0x15,
289 PCIE_SPEED_8_0GT = 0x16,
290 PCIE_SPEED_16_0GT = 0x17,
291 PCIE_SPEED_32_0GT = 0x18,
292 PCIE_SPEED_64_0GT = 0x19,
293 PCI_SPEED_UNKNOWN = 0xff,
296 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
297 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
306 struct pcie_link_state;
311 /* The pci_dev structure describes PCI devices */
313 struct list_head bus_list; /* Node in per-bus list */
314 struct pci_bus *bus; /* Bus this device is on */
315 struct pci_bus *subordinate; /* Bus this device bridges to */
317 void *sysdata; /* Hook for sys-specific extension */
318 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
319 struct pci_slot *slot; /* Physical slot this device is in */
321 unsigned int devfn; /* Encoded device & function index */
322 unsigned short vendor;
323 unsigned short device;
324 unsigned short subsystem_vendor;
325 unsigned short subsystem_device;
326 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
327 u8 revision; /* PCI revision, low byte of class word */
328 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
329 #ifdef CONFIG_PCIEAER
330 u16 aer_cap; /* AER capability offset */
331 struct aer_stats *aer_stats; /* AER stats for this device */
333 #ifdef CONFIG_PCIEPORTBUS
334 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
335 struct pci_dev *rcec; /* Associated RCEC device */
337 u32 devcap; /* PCIe Device Capabilities */
338 u8 pcie_cap; /* PCIe capability offset */
339 u8 msi_cap; /* MSI capability offset */
340 u8 msix_cap; /* MSI-X capability offset */
341 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
342 u8 rom_base_reg; /* Config register controlling ROM */
343 u8 pin; /* Interrupt pin this device uses */
344 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
345 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
347 struct pci_driver *driver; /* Driver bound to this device */
348 u64 dma_mask; /* Mask of the bits of bus address this
349 device implements. Normally this is
350 0xffffffff. You only need to change
351 this if your device has broken DMA
352 or supports 64-bit transfers. */
354 struct device_dma_parameters dma_parms;
356 pci_power_t current_state; /* Current operating state. In ACPI,
357 this is D0-D3, D0 being fully
358 functional, and D3 being off. */
359 unsigned int imm_ready:1; /* Supports Immediate Readiness */
360 u8 pm_cap; /* PM capability offset */
361 unsigned int pme_support:5; /* Bitmask of states from which PME#
363 unsigned int pme_poll:1; /* Poll device's PME status bit */
364 unsigned int d1_support:1; /* Low power state D1 is supported */
365 unsigned int d2_support:1; /* Low power state D2 is supported */
366 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
367 unsigned int no_d3cold:1; /* D3cold is forbidden */
368 unsigned int bridge_d3:1; /* Allow D3 for bridge */
369 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
370 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
371 decoding during BAR sizing */
372 unsigned int wakeup_prepared:1;
373 unsigned int runtime_d3cold:1; /* Whether go through runtime
374 D3cold, not set for devices
375 powered on/off by the
376 corresponding bridge */
377 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
378 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
379 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
380 controlled exclusively by
382 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
384 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
385 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
387 #ifdef CONFIG_PCIEASPM
388 struct pcie_link_state *link_state; /* ASPM link state */
389 unsigned int ltr_path:1; /* Latency Tolerance Reporting
390 supported from root to here */
391 u16 l1ss; /* L1SS Capability pointer */
393 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
394 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
396 pci_channel_state_t error_state; /* Current connectivity state */
397 struct device dev; /* Generic device interface */
399 int cfg_size; /* Size of config space */
402 * Instead of touching interrupt line and base address registers
403 * directly, use the values stored here. They might be different!
406 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
408 bool match_driver; /* Skip attaching driver */
410 unsigned int transparent:1; /* Subtractive decode bridge */
411 unsigned int io_window:1; /* Bridge has I/O window */
412 unsigned int pref_window:1; /* Bridge has pref mem window */
413 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
414 unsigned int multifunction:1; /* Multi-function device */
416 unsigned int is_busmaster:1; /* Is busmaster */
417 unsigned int no_msi:1; /* May not use MSI */
418 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
419 unsigned int block_cfg_access:1; /* Config space access blocked */
420 unsigned int broken_parity_status:1; /* Generates false positive parity */
421 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
422 unsigned int msi_enabled:1;
423 unsigned int msix_enabled:1;
424 unsigned int ari_enabled:1; /* ARI forwarding */
425 unsigned int ats_enabled:1; /* Address Translation Svc */
426 unsigned int pasid_enabled:1; /* Process Address Space ID */
427 unsigned int pri_enabled:1; /* Page Request Interface */
428 unsigned int is_managed:1;
429 unsigned int needs_freset:1; /* Requires fundamental reset */
430 unsigned int state_saved:1;
431 unsigned int is_physfn:1;
432 unsigned int is_virtfn:1;
433 unsigned int is_hotplug_bridge:1;
434 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
435 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
437 * Devices marked being untrusted are the ones that can potentially
438 * execute DMA attacks and similar. They are typically connected
439 * through external ports such as Thunderbolt but not limited to
440 * that. When an IOMMU is enabled they should be getting full
441 * mappings to make sure they cannot access arbitrary memory.
443 unsigned int untrusted:1;
445 * Info from the platform, e.g., ACPI or device tree, may mark a
446 * device as "external-facing". An external-facing device is
447 * itself internal but devices downstream from it are external.
449 unsigned int external_facing:1;
450 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
451 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
452 unsigned int irq_managed:1;
453 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
454 unsigned int is_probed:1; /* Device probing in progress */
455 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
456 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
457 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
458 pci_dev_flags_t dev_flags;
459 atomic_t enable_cnt; /* pci_enable_device has been called */
461 u32 saved_config_space[16]; /* Config space saved at suspend time */
462 struct hlist_head saved_cap_space;
463 int rom_attr_enabled; /* Display of ROM attribute enabled? */
464 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
465 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
467 #ifdef CONFIG_HOTPLUG_PCI_PCIE
468 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
470 #ifdef CONFIG_PCIE_PTM
471 unsigned int ptm_root:1;
472 unsigned int ptm_enabled:1;
475 #ifdef CONFIG_PCI_MSI
476 const struct attribute_group **msi_irq_groups;
479 #ifdef CONFIG_PCIE_DPC
481 unsigned int dpc_rp_extensions:1;
484 #ifdef CONFIG_PCI_ATS
486 struct pci_sriov *sriov; /* PF: SR-IOV info */
487 struct pci_dev *physfn; /* VF: related PF */
489 u16 ats_cap; /* ATS Capability offset */
490 u8 ats_stu; /* ATS Smallest Translation Unit */
492 #ifdef CONFIG_PCI_PRI
493 u16 pri_cap; /* PRI Capability offset */
494 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
495 unsigned int pasid_required:1; /* PRG Response PASID Required */
497 #ifdef CONFIG_PCI_PASID
498 u16 pasid_cap; /* PASID Capability offset */
501 #ifdef CONFIG_PCI_P2PDMA
502 struct pci_p2pdma __rcu *p2pdma;
504 u16 acs_cap; /* ACS Capability offset */
505 phys_addr_t rom; /* Physical address if not from BAR */
506 size_t romlen; /* Length if not from BAR */
507 char *driver_override; /* Driver name to force a match */
509 unsigned long priv_flags; /* Private flags for the PCI driver */
511 /* These methods index pci_reset_fn_methods[] */
512 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
515 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
517 #ifdef CONFIG_PCI_IOV
524 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
526 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
527 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
529 static inline int pci_channel_offline(struct pci_dev *pdev)
531 return (pdev->error_state != pci_channel_io_normal);
535 * Currently in ACPI spec, for each PCI host bridge, PCI Segment
536 * Group number is limited to a 16-bit value, therefore (int)-1 is
537 * not a valid PCI domain number, and can be used as a sentinel
538 * value indicating ->domain_nr is not set by the driver (and
539 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with
540 * pci_bus_find_domain_nr()).
542 #define PCI_DOMAIN_NR_NOT_SET (-1)
544 struct pci_host_bridge {
546 struct pci_bus *bus; /* Root bus */
548 struct pci_ops *child_ops;
552 struct list_head windows; /* resource_entry */
553 struct list_head dma_ranges; /* dma ranges resource list */
554 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
555 int (*map_irq)(const struct pci_dev *, u8, u8);
556 void (*release_fn)(struct pci_host_bridge *);
558 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
559 unsigned int no_ext_tags:1; /* No Extended Tags */
560 unsigned int no_inc_mrrs:1; /* No Increase MRRS */
561 unsigned int native_aer:1; /* OS may use PCIe AER */
562 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
563 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
564 unsigned int native_pme:1; /* OS may use PCIe PME */
565 unsigned int native_ltr:1; /* OS may use PCIe LTR */
566 unsigned int native_dpc:1; /* OS may use PCIe DPC */
567 unsigned int preserve_config:1; /* Preserve FW resource setup */
568 unsigned int size_windows:1; /* Enable root bus sizing */
569 unsigned int msi_domain:1; /* Bridge wants MSI domain */
571 /* Resource alignment requirements */
572 resource_size_t (*align_resource)(struct pci_dev *dev,
573 const struct resource *res,
574 resource_size_t start,
575 resource_size_t size,
576 resource_size_t align);
577 unsigned long private[] ____cacheline_aligned;
580 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
582 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
584 return (void *)bridge->private;
587 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
589 return container_of(priv, struct pci_host_bridge, private);
592 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
593 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
595 void pci_free_host_bridge(struct pci_host_bridge *bridge);
596 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
598 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
599 void (*release_fn)(struct pci_host_bridge *),
602 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
605 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
606 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
607 * buses below host bridges or subtractive decode bridges) go in the list.
608 * Use pci_bus_for_each_resource() to iterate through all the resources.
612 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
613 * and there's no way to program the bridge with the details of the window.
614 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
615 * decode bit set, because they are explicit and can be programmed with _SRS.
617 #define PCI_SUBTRACTIVE_DECODE 0x1
619 struct pci_bus_resource {
620 struct list_head list;
621 struct resource *res;
625 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
628 struct list_head node; /* Node in list of buses */
629 struct pci_bus *parent; /* Parent bus this bridge is on */
630 struct list_head children; /* List of child buses */
631 struct list_head devices; /* List of devices on this bus */
632 struct pci_dev *self; /* Bridge device as seen by parent */
633 struct list_head slots; /* List of slots on this bus;
634 protected by pci_slot_mutex */
635 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
636 struct list_head resources; /* Address space routed to this bus */
637 struct resource busn_res; /* Bus numbers routed to this bus */
639 struct pci_ops *ops; /* Configuration access functions */
640 void *sysdata; /* Hook for sys-specific extension */
641 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
643 unsigned char number; /* Bus number */
644 unsigned char primary; /* Number of primary bridge */
645 unsigned char max_bus_speed; /* enum pci_bus_speed */
646 unsigned char cur_bus_speed; /* enum pci_bus_speed */
647 #ifdef CONFIG_PCI_DOMAINS_GENERIC
653 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
654 pci_bus_flags_t bus_flags; /* Inherited by child buses */
655 struct device *bridge;
657 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
658 struct bin_attribute *legacy_mem; /* Legacy mem */
659 unsigned int is_added:1;
660 unsigned int unsafe_warn:1; /* warned about RW1C config write */
663 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
665 static inline u16 pci_dev_id(struct pci_dev *dev)
667 return PCI_DEVID(dev->bus->number, dev->devfn);
671 * Returns true if the PCI bus is root (behind host-PCI bridge),
674 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
675 * This is incorrect because "virtual" buses added for SR-IOV (via
676 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
678 static inline bool pci_is_root_bus(struct pci_bus *pbus)
680 return !(pbus->parent);
684 * pci_is_bridge - check if the PCI device is a bridge
687 * Return true if the PCI device is bridge whether it has subordinate
690 static inline bool pci_is_bridge(struct pci_dev *dev)
692 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
693 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
696 #define for_each_pci_bridge(dev, bus) \
697 list_for_each_entry(dev, &bus->devices, bus_list) \
698 if (!pci_is_bridge(dev)) {} else
700 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
702 dev = pci_physfn(dev);
703 if (pci_is_root_bus(dev->bus))
706 return dev->bus->self;
709 #ifdef CONFIG_PCI_MSI
710 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
712 return pci_dev->msi_enabled || pci_dev->msix_enabled;
715 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
718 /* Error values that may be returned by PCI functions */
719 #define PCIBIOS_SUCCESSFUL 0x00
720 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
721 #define PCIBIOS_BAD_VENDOR_ID 0x83
722 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
723 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
724 #define PCIBIOS_SET_FAILED 0x88
725 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
727 /* Translate above to generic errno for passing back through non-PCI code */
728 static inline int pcibios_err_to_errno(int err)
730 if (err <= PCIBIOS_SUCCESSFUL)
731 return err; /* Assume already errno */
734 case PCIBIOS_FUNC_NOT_SUPPORTED:
736 case PCIBIOS_BAD_VENDOR_ID:
738 case PCIBIOS_DEVICE_NOT_FOUND:
740 case PCIBIOS_BAD_REGISTER_NUMBER:
742 case PCIBIOS_SET_FAILED:
744 case PCIBIOS_BUFFER_TOO_SMALL:
751 /* Low-level architecture-dependent routines */
754 int (*add_bus)(struct pci_bus *bus);
755 void (*remove_bus)(struct pci_bus *bus);
756 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
757 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
758 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
762 * ACPI needs to be able to access PCI config space before we've done a
763 * PCI bus scan and created pci_bus structures.
765 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
766 int reg, int len, u32 *val);
767 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
768 int reg, int len, u32 val);
770 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
771 typedef u64 pci_bus_addr_t;
773 typedef u32 pci_bus_addr_t;
776 struct pci_bus_region {
777 pci_bus_addr_t start;
782 spinlock_t lock; /* Protects list, index */
783 struct list_head list; /* For IDs added at runtime */
788 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
789 * a set of callbacks in struct pci_error_handlers, that device driver
790 * will be notified of PCI bus errors, and will be driven to recovery
791 * when an error occurs.
794 typedef unsigned int __bitwise pci_ers_result_t;
796 enum pci_ers_result {
797 /* No result/none/not supported in device driver */
798 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
800 /* Device driver can recover without slot reset */
801 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
803 /* Device driver wants slot to be reset */
804 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
806 /* Device has completely failed, is unrecoverable */
807 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
809 /* Device driver is fully recovered and operational */
810 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
812 /* No AER capabilities registered for the driver */
813 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
816 /* PCI bus error event callbacks */
817 struct pci_error_handlers {
818 /* PCI bus error detected on this device */
819 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
820 pci_channel_state_t error);
822 /* MMIO has been re-enabled, but not DMA */
823 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
825 /* PCI slot has been reset */
826 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
828 /* PCI function reset prepare or completed */
829 void (*reset_prepare)(struct pci_dev *dev);
830 void (*reset_done)(struct pci_dev *dev);
832 /* Device driver may resume normal operations */
833 void (*resume)(struct pci_dev *dev);
840 * struct pci_driver - PCI driver structure
841 * @node: List of driver structures.
842 * @name: Driver name.
843 * @id_table: Pointer to table of device IDs the driver is
844 * interested in. Most drivers should export this
845 * table using MODULE_DEVICE_TABLE(pci,...).
846 * @probe: This probing function gets called (during execution
847 * of pci_register_driver() for already existing
848 * devices or later if a new device gets inserted) for
849 * all PCI devices which match the ID table and are not
850 * "owned" by the other drivers yet. This function gets
851 * passed a "struct pci_dev \*" for each device whose
852 * entry in the ID table matches the device. The probe
853 * function returns zero when the driver chooses to
854 * take "ownership" of the device or an error code
855 * (negative number) otherwise.
856 * The probe function always gets called from process
857 * context, so it can sleep.
858 * @remove: The remove() function gets called whenever a device
859 * being handled by this driver is removed (either during
860 * deregistration of the driver or when it's manually
861 * pulled out of a hot-pluggable slot).
862 * The remove function always gets called from process
863 * context, so it can sleep.
864 * @suspend: Put device into low power state.
865 * @resume: Wake device from low power state.
866 * (Please see Documentation/power/pci.rst for descriptions
867 * of PCI Power Management and the related functions.)
868 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
869 * Intended to stop any idling DMA operations.
870 * Useful for enabling wake-on-lan (NIC) or changing
871 * the power state of a device before reboot.
872 * e.g. drivers/net/e100.c.
873 * @sriov_configure: Optional driver callback to allow configuration of
874 * number of VFs to enable via sysfs "sriov_numvfs" file.
875 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X
876 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count".
877 * This will change MSI-X Table Size in the VF Message Control
879 * @sriov_get_vf_total_msix: PF driver callback to get the total number of
880 * MSI-X vectors available for distribution to the VFs.
881 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
882 * @groups: Sysfs attribute groups.
883 * @dev_groups: Attributes attached to the device that will be
884 * created once it is bound to the driver.
885 * @driver: Driver model structure.
886 * @dynids: List of dynamically added device IDs.
889 struct list_head node;
891 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
892 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
893 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
894 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
895 int (*resume)(struct pci_dev *dev); /* Device woken up */
896 void (*shutdown)(struct pci_dev *dev);
897 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
898 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
899 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
900 const struct pci_error_handlers *err_handler;
901 const struct attribute_group **groups;
902 const struct attribute_group **dev_groups;
903 struct device_driver driver;
904 struct pci_dynids dynids;
907 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
910 * PCI_DEVICE - macro used to describe a specific PCI device
911 * @vend: the 16 bit PCI Vendor ID
912 * @dev: the 16 bit PCI Device ID
914 * This macro is used to create a struct pci_device_id that matches a
915 * specific device. The subvendor and subdevice fields will be set to
918 #define PCI_DEVICE(vend,dev) \
919 .vendor = (vend), .device = (dev), \
920 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
923 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with
924 * override_only flags.
925 * @vend: the 16 bit PCI Vendor ID
926 * @dev: the 16 bit PCI Device ID
927 * @driver_override: the 32 bit PCI Device override_only
929 * This macro is used to create a struct pci_device_id that matches only a
930 * driver_override device. The subvendor and subdevice fields will be set to
933 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \
934 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \
935 .subdevice = PCI_ANY_ID, .override_only = (driver_override)
938 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO
939 * "driver_override" PCI device.
940 * @vend: the 16 bit PCI Vendor ID
941 * @dev: the 16 bit PCI Device ID
943 * This macro is used to create a struct pci_device_id that matches a
944 * specific device. The subvendor and subdevice fields will be set to
945 * PCI_ANY_ID and the driver_override will be set to
946 * PCI_ID_F_VFIO_DRIVER_OVERRIDE.
948 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \
949 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE)
952 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
953 * @vend: the 16 bit PCI Vendor ID
954 * @dev: the 16 bit PCI Device ID
955 * @subvend: the 16 bit PCI Subvendor ID
956 * @subdev: the 16 bit PCI Subdevice ID
958 * This macro is used to create a struct pci_device_id that matches a
959 * specific device with subsystem information.
961 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
962 .vendor = (vend), .device = (dev), \
963 .subvendor = (subvend), .subdevice = (subdev)
966 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
967 * @dev_class: the class, subclass, prog-if triple for this device
968 * @dev_class_mask: the class mask for this device
970 * This macro is used to create a struct pci_device_id that matches a
971 * specific PCI class. The vendor, device, subvendor, and subdevice
972 * fields will be set to PCI_ANY_ID.
974 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
975 .class = (dev_class), .class_mask = (dev_class_mask), \
976 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
977 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
980 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
981 * @vend: the vendor name
982 * @dev: the 16 bit PCI Device ID
984 * This macro is used to create a struct pci_device_id that matches a
985 * specific PCI device. The subvendor, and subdevice fields will be set
986 * to PCI_ANY_ID. The macro allows the next field to follow as the device
989 #define PCI_VDEVICE(vend, dev) \
990 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
991 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
994 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
995 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
996 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
997 * @data: the driver data to be filled
999 * This macro is used to create a struct pci_device_id that matches a
1000 * specific PCI device. The subvendor, and subdevice fields will be set
1003 #define PCI_DEVICE_DATA(vend, dev, data) \
1004 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
1005 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
1006 .driver_data = (kernel_ulong_t)(data)
1009 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
1010 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
1011 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
1012 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
1013 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
1014 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
1015 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
1018 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1019 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1020 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1021 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1023 /* These external functions are only available when PCI support is enabled */
1026 extern unsigned int pci_flags;
1028 static inline void pci_set_flags(int flags) { pci_flags = flags; }
1029 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
1030 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
1031 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
1033 void pcie_bus_configure_settings(struct pci_bus *bus);
1035 enum pcie_bus_config_types {
1036 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
1037 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
1038 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
1039 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
1040 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
1043 extern enum pcie_bus_config_types pcie_bus_config;
1045 extern struct bus_type pci_bus_type;
1047 /* Do NOT directly access these two variables, unless you are arch-specific PCI
1048 * code, or PCI core code. */
1049 extern struct list_head pci_root_buses; /* List of all known PCI buses */
1050 /* Some device drivers need know if PCI is initiated */
1051 int no_pci_devices(void);
1053 void pcibios_resource_survey_bus(struct pci_bus *bus);
1054 void pcibios_bus_add_device(struct pci_dev *pdev);
1055 void pcibios_add_bus(struct pci_bus *bus);
1056 void pcibios_remove_bus(struct pci_bus *bus);
1057 void pcibios_fixup_bus(struct pci_bus *);
1058 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1059 /* Architecture-specific versions may override this (weak) */
1060 char *pcibios_setup(char *str);
1062 /* Used only when drivers/pci/setup.c is used */
1063 resource_size_t pcibios_align_resource(void *, const struct resource *,
1067 /* Weak but can be overridden by arch */
1068 void pci_fixup_cardbus(struct pci_bus *);
1070 /* Generic PCI functions used internally */
1072 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1073 struct resource *res);
1074 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1075 struct pci_bus_region *region);
1076 void pcibios_scan_specific_bus(int busn);
1077 struct pci_bus *pci_find_bus(int domain, int busnr);
1078 void pci_bus_add_devices(const struct pci_bus *bus);
1079 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1080 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1081 struct pci_ops *ops, void *sysdata,
1082 struct list_head *resources);
1083 int pci_host_probe(struct pci_host_bridge *bridge);
1084 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1085 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1086 void pci_bus_release_busn_res(struct pci_bus *b);
1087 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1088 struct pci_ops *ops, void *sysdata,
1089 struct list_head *resources);
1090 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1091 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1093 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1095 struct hotplug_slot *hotplug);
1096 void pci_destroy_slot(struct pci_slot *slot);
1098 void pci_dev_assign_slot(struct pci_dev *dev);
1100 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1102 int pci_scan_slot(struct pci_bus *bus, int devfn);
1103 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1104 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1105 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1106 void pci_bus_add_device(struct pci_dev *dev);
1107 void pci_read_bridge_bases(struct pci_bus *child);
1108 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1109 struct resource *res);
1110 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1111 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1112 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1113 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1114 void pci_dev_put(struct pci_dev *dev);
1115 void pci_remove_bus(struct pci_bus *b);
1116 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1117 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1118 void pci_stop_root_bus(struct pci_bus *bus);
1119 void pci_remove_root_bus(struct pci_bus *bus);
1120 void pci_setup_cardbus(struct pci_bus *bus);
1121 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1122 void pci_sort_breadthfirst(void);
1123 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1124 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1126 /* Generic PCI functions exported to card drivers */
1128 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1129 u8 pci_find_capability(struct pci_dev *dev, int cap);
1130 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1131 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1132 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1133 u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1134 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1135 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1136 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
1138 u64 pci_get_dsn(struct pci_dev *dev);
1140 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1141 struct pci_dev *from);
1142 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1143 unsigned int ss_vendor, unsigned int ss_device,
1144 struct pci_dev *from);
1145 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1146 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1147 unsigned int devfn);
1148 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1149 int pci_dev_present(const struct pci_device_id *ids);
1151 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1152 int where, u8 *val);
1153 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1154 int where, u16 *val);
1155 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1156 int where, u32 *val);
1157 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1159 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1160 int where, u16 val);
1161 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1162 int where, u32 val);
1164 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1165 int where, int size, u32 *val);
1166 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1167 int where, int size, u32 val);
1168 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1169 int where, int size, u32 *val);
1170 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1171 int where, int size, u32 val);
1173 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1175 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1176 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1177 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1178 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1179 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1180 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1182 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1183 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1184 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1185 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1186 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1187 u16 clear, u16 set);
1188 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1189 u32 clear, u32 set);
1191 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1194 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1197 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1200 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1203 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1206 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1209 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1212 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1215 /* User-space driven config access */
1216 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1217 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1218 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1219 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1220 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1221 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1223 int __must_check pci_enable_device(struct pci_dev *dev);
1224 int __must_check pci_enable_device_io(struct pci_dev *dev);
1225 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1226 int __must_check pci_reenable_device(struct pci_dev *);
1227 int __must_check pcim_enable_device(struct pci_dev *pdev);
1228 void pcim_pin_device(struct pci_dev *pdev);
1230 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1233 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1234 * writable and no quirk has marked the feature broken.
1236 return !pdev->broken_intx_masking;
1239 static inline int pci_is_enabled(struct pci_dev *pdev)
1241 return (atomic_read(&pdev->enable_cnt) > 0);
1244 static inline int pci_is_managed(struct pci_dev *pdev)
1246 return pdev->is_managed;
1249 void pci_disable_device(struct pci_dev *dev);
1251 extern unsigned int pcibios_max_latency;
1252 void pci_set_master(struct pci_dev *dev);
1253 void pci_clear_master(struct pci_dev *dev);
1255 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1256 int pci_set_cacheline_size(struct pci_dev *dev);
1257 int __must_check pci_set_mwi(struct pci_dev *dev);
1258 int __must_check pcim_set_mwi(struct pci_dev *dev);
1259 int pci_try_set_mwi(struct pci_dev *dev);
1260 void pci_clear_mwi(struct pci_dev *dev);
1261 void pci_disable_parity(struct pci_dev *dev);
1262 void pci_intx(struct pci_dev *dev, int enable);
1263 bool pci_check_and_mask_intx(struct pci_dev *dev);
1264 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1265 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1266 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1267 int pcix_get_max_mmrbc(struct pci_dev *dev);
1268 int pcix_get_mmrbc(struct pci_dev *dev);
1269 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1270 int pcie_get_readrq(struct pci_dev *dev);
1271 int pcie_set_readrq(struct pci_dev *dev, int rq);
1272 int pcie_get_mps(struct pci_dev *dev);
1273 int pcie_set_mps(struct pci_dev *dev, int mps);
1274 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1275 enum pci_bus_speed *speed,
1276 enum pcie_link_width *width);
1277 void pcie_print_link_status(struct pci_dev *dev);
1278 int pcie_reset_flr(struct pci_dev *dev, bool probe);
1279 int pcie_flr(struct pci_dev *dev);
1280 int __pci_reset_function_locked(struct pci_dev *dev);
1281 int pci_reset_function(struct pci_dev *dev);
1282 int pci_reset_function_locked(struct pci_dev *dev);
1283 int pci_try_reset_function(struct pci_dev *dev);
1284 int pci_probe_reset_slot(struct pci_slot *slot);
1285 int pci_probe_reset_bus(struct pci_bus *bus);
1286 int pci_reset_bus(struct pci_dev *dev);
1287 void pci_reset_secondary_bus(struct pci_dev *dev);
1288 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1289 void pci_update_resource(struct pci_dev *dev, int resno);
1290 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1291 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1292 void pci_release_resource(struct pci_dev *dev, int resno);
1293 static inline int pci_rebar_bytes_to_size(u64 bytes)
1295 bytes = roundup_pow_of_two(bytes);
1297 /* Return BAR size as defined in the resizable BAR specification */
1298 return max(ilog2(bytes), 20) - 20;
1301 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1302 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1303 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1304 bool pci_device_is_present(struct pci_dev *pdev);
1305 void pci_ignore_hotplug(struct pci_dev *dev);
1306 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1307 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1309 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1310 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1311 const char *fmt, ...);
1312 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1314 /* ROM control related routines */
1315 int pci_enable_rom(struct pci_dev *pdev);
1316 void pci_disable_rom(struct pci_dev *pdev);
1317 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1318 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1320 /* Power management related routines */
1321 int pci_save_state(struct pci_dev *dev);
1322 void pci_restore_state(struct pci_dev *dev);
1323 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1324 int pci_load_saved_state(struct pci_dev *dev,
1325 struct pci_saved_state *state);
1326 int pci_load_and_free_saved_state(struct pci_dev *dev,
1327 struct pci_saved_state **state);
1328 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1329 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1330 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1331 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1332 void pci_pme_active(struct pci_dev *dev, bool enable);
1333 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1334 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1335 int pci_prepare_to_sleep(struct pci_dev *dev);
1336 int pci_back_from_sleep(struct pci_dev *dev);
1337 bool pci_dev_run_wake(struct pci_dev *dev);
1338 void pci_d3cold_enable(struct pci_dev *dev);
1339 void pci_d3cold_disable(struct pci_dev *dev);
1340 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1341 void pci_resume_bus(struct pci_bus *bus);
1342 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1344 /* For use by arch with custom probe code */
1345 void set_pcie_port_type(struct pci_dev *pdev);
1346 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1348 /* Functions for PCI Hotplug drivers to use */
1349 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1350 unsigned int pci_rescan_bus(struct pci_bus *bus);
1351 void pci_lock_rescan_remove(void);
1352 void pci_unlock_rescan_remove(void);
1354 /* Vital Product Data routines */
1355 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1356 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1358 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1359 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1360 void pci_bus_assign_resources(const struct pci_bus *bus);
1361 void pci_bus_claim_resources(struct pci_bus *bus);
1362 void pci_bus_size_bridges(struct pci_bus *bus);
1363 int pci_claim_resource(struct pci_dev *, int);
1364 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1365 void pci_assign_unassigned_resources(void);
1366 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1367 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1368 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1369 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1370 void pdev_enable_device(struct pci_dev *);
1371 int pci_enable_resources(struct pci_dev *, int mask);
1372 void pci_assign_irq(struct pci_dev *dev);
1373 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1374 #define HAVE_PCI_REQ_REGIONS 2
1375 int __must_check pci_request_regions(struct pci_dev *, const char *);
1376 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1377 void pci_release_regions(struct pci_dev *);
1378 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1379 void pci_release_region(struct pci_dev *, int);
1380 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1381 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1382 void pci_release_selected_regions(struct pci_dev *, int);
1384 /* drivers/pci/bus.c */
1385 void pci_add_resource(struct list_head *resources, struct resource *res);
1386 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1387 resource_size_t offset);
1388 void pci_free_resource_list(struct list_head *resources);
1389 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1390 unsigned int flags);
1391 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1392 void pci_bus_remove_resources(struct pci_bus *bus);
1393 void pci_bus_remove_resource(struct pci_bus *bus, struct resource *res);
1394 int devm_request_pci_bus_resources(struct device *dev,
1395 struct list_head *resources);
1397 /* Temporary until new and working PCI SBR API in place */
1398 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1400 #define pci_bus_for_each_resource(bus, res, i) \
1402 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1405 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1406 struct resource *res, resource_size_t size,
1407 resource_size_t align, resource_size_t min,
1408 unsigned long type_mask,
1409 resource_size_t (*alignf)(void *,
1410 const struct resource *,
1416 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1417 resource_size_t size);
1418 unsigned long pci_address_to_pio(phys_addr_t addr);
1419 phys_addr_t pci_pio_to_address(unsigned long pio);
1420 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1421 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1422 phys_addr_t phys_addr);
1423 void pci_unmap_iospace(struct resource *res);
1424 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1425 resource_size_t offset,
1426 resource_size_t size);
1427 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1428 struct resource *res);
1430 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1432 struct pci_bus_region region;
1434 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1435 return region.start;
1438 /* Proper probing supporting hot-pluggable devices */
1439 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1440 const char *mod_name);
1442 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1443 #define pci_register_driver(driver) \
1444 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1446 void pci_unregister_driver(struct pci_driver *dev);
1449 * module_pci_driver() - Helper macro for registering a PCI driver
1450 * @__pci_driver: pci_driver struct
1452 * Helper macro for PCI drivers which do not do anything special in module
1453 * init/exit. This eliminates a lot of boilerplate. Each module may only
1454 * use this macro once, and calling it replaces module_init() and module_exit()
1456 #define module_pci_driver(__pci_driver) \
1457 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1460 * builtin_pci_driver() - Helper macro for registering a PCI driver
1461 * @__pci_driver: pci_driver struct
1463 * Helper macro for PCI drivers which do not do anything special in their
1464 * init code. This eliminates a lot of boilerplate. Each driver may only
1465 * use this macro once, and calling it replaces device_initcall(...)
1467 #define builtin_pci_driver(__pci_driver) \
1468 builtin_driver(__pci_driver, pci_register_driver)
1470 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1471 int pci_add_dynid(struct pci_driver *drv,
1472 unsigned int vendor, unsigned int device,
1473 unsigned int subvendor, unsigned int subdevice,
1474 unsigned int class, unsigned int class_mask,
1475 unsigned long driver_data);
1476 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1477 struct pci_dev *dev);
1478 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1481 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1483 int pci_cfg_space_size(struct pci_dev *dev);
1484 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1485 void pci_setup_bridge(struct pci_bus *bus);
1486 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1487 unsigned long type);
1489 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1490 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1492 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1493 unsigned int command_bits, u32 flags);
1496 * Virtual interrupts allow for more interrupts to be allocated
1497 * than the device has interrupts for. These are not programmed
1498 * into the device's MSI-X table and must be handled by some
1499 * other driver means.
1501 #define PCI_IRQ_VIRTUAL (1 << 4)
1503 #define PCI_IRQ_ALL_TYPES \
1504 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1506 /* kmem_cache style wrapper around pci_alloc_consistent() */
1508 #include <linux/dmapool.h>
1510 #define pci_pool dma_pool
1511 #define pci_pool_create(name, pdev, size, align, allocation) \
1512 dma_pool_create(name, &pdev->dev, size, align, allocation)
1513 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1514 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1515 #define pci_pool_zalloc(pool, flags, handle) \
1516 dma_pool_zalloc(pool, flags, handle)
1517 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1520 u32 vector; /* Kernel uses to write allocated vector */
1521 u16 entry; /* Driver uses to specify entry, OS writes */
1524 #ifdef CONFIG_PCI_MSI
1525 int pci_msi_vec_count(struct pci_dev *dev);
1526 void pci_disable_msi(struct pci_dev *dev);
1527 int pci_msix_vec_count(struct pci_dev *dev);
1528 void pci_disable_msix(struct pci_dev *dev);
1529 void pci_restore_msi_state(struct pci_dev *dev);
1530 int pci_msi_enabled(void);
1531 int pci_enable_msi(struct pci_dev *dev);
1532 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1533 int minvec, int maxvec);
1534 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1535 struct msix_entry *entries, int nvec)
1537 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1542 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1543 unsigned int max_vecs, unsigned int flags,
1544 struct irq_affinity *affd);
1546 void pci_free_irq_vectors(struct pci_dev *dev);
1547 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1548 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1551 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1552 static inline void pci_disable_msi(struct pci_dev *dev) { }
1553 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1554 static inline void pci_disable_msix(struct pci_dev *dev) { }
1555 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1556 static inline int pci_msi_enabled(void) { return 0; }
1557 static inline int pci_enable_msi(struct pci_dev *dev)
1559 static inline int pci_enable_msix_range(struct pci_dev *dev,
1560 struct msix_entry *entries, int minvec, int maxvec)
1562 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1563 struct msix_entry *entries, int nvec)
1567 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1568 unsigned int max_vecs, unsigned int flags,
1569 struct irq_affinity *aff_desc)
1571 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1576 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1580 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1582 if (WARN_ON_ONCE(nr > 0))
1586 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1589 return cpu_possible_mask;
1594 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1595 * @d: the INTx IRQ domain
1596 * @node: the DT node for the device whose interrupt we're translating
1597 * @intspec: the interrupt specifier data from the DT
1598 * @intsize: the number of entries in @intspec
1599 * @out_hwirq: pointer at which to write the hwirq number
1600 * @out_type: pointer at which to write the interrupt type
1602 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1603 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1604 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1605 * INTx value to obtain the hwirq number.
1607 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1609 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1610 struct device_node *node,
1612 unsigned int intsize,
1613 unsigned long *out_hwirq,
1614 unsigned int *out_type)
1616 const u32 intx = intspec[0];
1618 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1621 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1625 #ifdef CONFIG_PCIEPORTBUS
1626 extern bool pcie_ports_disabled;
1627 extern bool pcie_ports_native;
1629 #define pcie_ports_disabled true
1630 #define pcie_ports_native false
1633 #define PCIE_LINK_STATE_L0S BIT(0)
1634 #define PCIE_LINK_STATE_L1 BIT(1)
1635 #define PCIE_LINK_STATE_CLKPM BIT(2)
1636 #define PCIE_LINK_STATE_L1_1 BIT(3)
1637 #define PCIE_LINK_STATE_L1_2 BIT(4)
1638 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1639 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1641 #ifdef CONFIG_PCIEASPM
1642 int pci_disable_link_state(struct pci_dev *pdev, int state);
1643 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1644 void pcie_no_aspm(void);
1645 bool pcie_aspm_support_enabled(void);
1646 bool pcie_aspm_enabled(struct pci_dev *pdev);
1648 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1650 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1652 static inline void pcie_no_aspm(void) { }
1653 static inline bool pcie_aspm_support_enabled(void) { return false; }
1654 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1657 #ifdef CONFIG_PCIEAER
1658 bool pci_aer_available(void);
1660 static inline bool pci_aer_available(void) { return false; }
1663 bool pci_ats_disabled(void);
1665 #ifdef CONFIG_PCIE_PTM
1666 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1667 bool pcie_ptm_enabled(struct pci_dev *dev);
1669 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1671 static inline bool pcie_ptm_enabled(struct pci_dev *dev)
1675 void pci_cfg_access_lock(struct pci_dev *dev);
1676 bool pci_cfg_access_trylock(struct pci_dev *dev);
1677 void pci_cfg_access_unlock(struct pci_dev *dev);
1679 int pci_dev_trylock(struct pci_dev *dev);
1680 void pci_dev_unlock(struct pci_dev *dev);
1683 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1684 * a PCI domain is defined to be a set of PCI buses which share
1685 * configuration space.
1687 #ifdef CONFIG_PCI_DOMAINS
1688 extern int pci_domains_supported;
1690 enum { pci_domains_supported = 0 };
1691 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1692 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1693 #endif /* CONFIG_PCI_DOMAINS */
1696 * Generic implementation for PCI domain support. If your
1697 * architecture does not need custom management of PCI
1698 * domains then this implementation will be used
1700 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1701 static inline int pci_domain_nr(struct pci_bus *bus)
1703 return bus->domain_nr;
1706 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1708 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1711 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1714 /* Some architectures require additional setup to direct VGA traffic */
1715 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1716 unsigned int command_bits, u32 flags);
1717 void pci_register_set_vga_state(arch_set_vga_state_t func);
1720 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1722 return pci_request_selected_regions(pdev,
1723 pci_select_bars(pdev, IORESOURCE_IO), name);
1727 pci_release_io_regions(struct pci_dev *pdev)
1729 return pci_release_selected_regions(pdev,
1730 pci_select_bars(pdev, IORESOURCE_IO));
1734 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1736 return pci_request_selected_regions(pdev,
1737 pci_select_bars(pdev, IORESOURCE_MEM), name);
1741 pci_release_mem_regions(struct pci_dev *pdev)
1743 return pci_release_selected_regions(pdev,
1744 pci_select_bars(pdev, IORESOURCE_MEM));
1747 #else /* CONFIG_PCI is not enabled */
1749 static inline void pci_set_flags(int flags) { }
1750 static inline void pci_add_flags(int flags) { }
1751 static inline void pci_clear_flags(int flags) { }
1752 static inline int pci_has_flag(int flag) { return 0; }
1755 * If the system does not have PCI, clearly these return errors. Define
1756 * these as simple inline functions to avoid hair in drivers.
1758 #define _PCI_NOP(o, s, t) \
1759 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1761 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1763 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1764 _PCI_NOP(o, word, u16 x) \
1765 _PCI_NOP(o, dword, u32 x)
1766 _PCI_NOP_ALL(read, *)
1767 _PCI_NOP_ALL(write,)
1769 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1770 unsigned int device,
1771 struct pci_dev *from)
1774 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1775 unsigned int device,
1776 unsigned int ss_vendor,
1777 unsigned int ss_device,
1778 struct pci_dev *from)
1781 static inline struct pci_dev *pci_get_class(unsigned int class,
1782 struct pci_dev *from)
1785 #define pci_dev_present(ids) (0)
1786 #define no_pci_devices() (1)
1787 #define pci_dev_put(dev) do { } while (0)
1789 static inline void pci_set_master(struct pci_dev *dev) { }
1790 static inline void pci_clear_master(struct pci_dev *dev) { }
1791 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1792 static inline void pci_disable_device(struct pci_dev *dev) { }
1793 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
1794 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1796 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1797 struct module *owner,
1798 const char *mod_name)
1800 static inline int pci_register_driver(struct pci_driver *drv)
1802 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1803 static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
1805 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1808 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1811 static inline u64 pci_get_dsn(struct pci_dev *dev)
1814 /* Power management related routines */
1815 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1816 static inline void pci_restore_state(struct pci_dev *dev) { }
1817 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1819 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1821 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1824 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1828 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1829 struct resource *res)
1831 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1833 static inline void pci_release_regions(struct pci_dev *dev) { }
1835 static inline int pci_register_io_range(struct fwnode_handle *fwnode,
1836 phys_addr_t addr, resource_size_t size)
1839 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1841 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1843 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1846 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1847 unsigned int bus, unsigned int devfn)
1850 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1851 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1853 #define dev_is_pci(d) (false)
1854 #define dev_is_pf(d) (false)
1855 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1857 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1858 struct device_node *node,
1860 unsigned int intsize,
1861 unsigned long *out_hwirq,
1862 unsigned int *out_type)
1865 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1866 struct pci_dev *dev)
1868 static inline bool pci_ats_disabled(void) { return true; }
1870 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1876 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1877 unsigned int max_vecs, unsigned int flags,
1878 struct irq_affinity *aff_desc)
1882 #endif /* CONFIG_PCI */
1885 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1886 unsigned int max_vecs, unsigned int flags)
1888 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1892 /* Include architecture-dependent settings and functions */
1894 #include <asm/pci.h>
1896 /* These two functions provide almost identical functionality. Depending
1897 * on the architecture, one will be implemented as a wrapper around the
1898 * other (in drivers/pci/mmap.c).
1900 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1901 * is expected to be an offset within that region.
1903 * pci_mmap_page_range() is the legacy architecture-specific interface,
1904 * which accepts a "user visible" resource address converted by
1905 * pci_resource_to_user(), as used in the legacy mmap() interface in
1908 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1909 struct vm_area_struct *vma,
1910 enum pci_mmap_state mmap_state, int write_combine);
1911 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1912 struct vm_area_struct *vma,
1913 enum pci_mmap_state mmap_state, int write_combine);
1915 #ifndef arch_can_pci_mmap_wc
1916 #define arch_can_pci_mmap_wc() 0
1919 #ifndef arch_can_pci_mmap_io
1920 #define arch_can_pci_mmap_io() 0
1921 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1923 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1926 #ifndef pci_root_bus_fwnode
1927 #define pci_root_bus_fwnode(bus) NULL
1931 * These helpers provide future and backwards compatibility
1932 * for accessing popular PCI BAR info
1934 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1935 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1936 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1937 #define pci_resource_len(dev,bar) \
1938 ((pci_resource_end((dev), (bar)) == 0) ? 0 : \
1940 (pci_resource_end((dev), (bar)) - \
1941 pci_resource_start((dev), (bar)) + 1))
1944 * Similar to the helpers above, these manipulate per-pci_dev
1945 * driver-specific data. They are really just a wrapper around
1946 * the generic device structure functions of these calls.
1948 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1950 return dev_get_drvdata(&pdev->dev);
1953 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1955 dev_set_drvdata(&pdev->dev, data);
1958 static inline const char *pci_name(const struct pci_dev *pdev)
1960 return dev_name(&pdev->dev);
1963 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1964 const struct resource *rsrc,
1965 resource_size_t *start, resource_size_t *end);
1968 * The world is not perfect and supplies us with broken PCI devices.
1969 * For at least a part of these bugs we need a work-around, so both
1970 * generic (drivers/pci/quirks.c) and per-architecture code can define
1971 * fixup hooks to be called for particular buggy devices.
1975 u16 vendor; /* Or PCI_ANY_ID */
1976 u16 device; /* Or PCI_ANY_ID */
1977 u32 class; /* Or PCI_ANY_ID */
1978 unsigned int class_shift; /* should be 0, 8, 16 */
1979 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1982 void (*hook)(struct pci_dev *dev);
1986 enum pci_fixup_pass {
1987 pci_fixup_early, /* Before probing BARs */
1988 pci_fixup_header, /* After reading configuration header */
1989 pci_fixup_final, /* Final phase of device fixups */
1990 pci_fixup_enable, /* pci_enable_device() time */
1991 pci_fixup_resume, /* pci_device_resume() */
1992 pci_fixup_suspend, /* pci_device_suspend() */
1993 pci_fixup_resume_early, /* pci_device_resume_early() */
1994 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1997 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1998 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1999 class_shift, hook) \
2000 __ADDRESSABLE(hook) \
2001 asm(".section " #sec ", \"a\" \n" \
2003 ".short " #vendor ", " #device " \n" \
2004 ".long " #class ", " #class_shift " \n" \
2005 ".long " #hook " - . \n" \
2009 * Clang's LTO may rename static functions in C, but has no way to
2010 * handle such renamings when referenced from inline asm. To work
2011 * around this, create global C stubs for these cases.
2013 #ifdef CONFIG_LTO_CLANG
2014 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2015 class_shift, hook, stub) \
2016 void __cficanonical stub(struct pci_dev *dev); \
2017 void __cficanonical stub(struct pci_dev *dev) \
2021 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2024 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2025 class_shift, hook, stub) \
2026 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2030 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2031 class_shift, hook) \
2032 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2033 class_shift, hook, __UNIQUE_ID(hook))
2035 /* Anonymous variables would be nice... */
2036 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
2037 class_shift, hook) \
2038 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
2039 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
2040 = { vendor, device, class, class_shift, hook };
2043 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
2044 class_shift, hook) \
2045 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2046 hook, vendor, device, class, class_shift, hook)
2047 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
2048 class_shift, hook) \
2049 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2050 hook, vendor, device, class, class_shift, hook)
2051 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2052 class_shift, hook) \
2053 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2054 hook, vendor, device, class, class_shift, hook)
2055 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2056 class_shift, hook) \
2057 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2058 hook, vendor, device, class, class_shift, hook)
2059 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2060 class_shift, hook) \
2061 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2062 resume##hook, vendor, device, class, class_shift, hook)
2063 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2064 class_shift, hook) \
2065 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2066 resume_early##hook, vendor, device, class, class_shift, hook)
2067 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2068 class_shift, hook) \
2069 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2070 suspend##hook, vendor, device, class, class_shift, hook)
2071 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2072 class_shift, hook) \
2073 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2074 suspend_late##hook, vendor, device, class, class_shift, hook)
2076 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2077 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2078 hook, vendor, device, PCI_ANY_ID, 0, hook)
2079 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2080 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2081 hook, vendor, device, PCI_ANY_ID, 0, hook)
2082 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2083 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2084 hook, vendor, device, PCI_ANY_ID, 0, hook)
2085 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2086 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2087 hook, vendor, device, PCI_ANY_ID, 0, hook)
2088 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2089 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2090 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2091 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2092 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2093 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2094 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2095 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2096 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2097 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2098 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2099 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2101 #ifdef CONFIG_PCI_QUIRKS
2102 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2104 static inline void pci_fixup_device(enum pci_fixup_pass pass,
2105 struct pci_dev *dev) { }
2108 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2109 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2110 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2111 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2112 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2114 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2116 extern int pci_pci_problems;
2117 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2118 #define PCIPCI_TRITON 2
2119 #define PCIPCI_NATOMA 4
2120 #define PCIPCI_VIAETBF 8
2121 #define PCIPCI_VSFX 16
2122 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2123 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2125 extern unsigned long pci_cardbus_io_size;
2126 extern unsigned long pci_cardbus_mem_size;
2127 extern u8 pci_dfl_cache_line_size;
2128 extern u8 pci_cache_line_size;
2130 /* Architecture-specific versions may override these (weak) */
2131 void pcibios_disable_device(struct pci_dev *dev);
2132 void pcibios_set_master(struct pci_dev *dev);
2133 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2134 enum pcie_reset_state state);
2135 int pcibios_add_device(struct pci_dev *dev);
2136 void pcibios_release_device(struct pci_dev *dev);
2138 void pcibios_penalize_isa_irq(int irq, int active);
2140 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2142 int pcibios_alloc_irq(struct pci_dev *dev);
2143 void pcibios_free_irq(struct pci_dev *dev);
2144 resource_size_t pcibios_default_alignment(void);
2146 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2147 void __init pci_mmcfg_early_init(void);
2148 void __init pci_mmcfg_late_init(void);
2150 static inline void pci_mmcfg_early_init(void) { }
2151 static inline void pci_mmcfg_late_init(void) { }
2154 int pci_ext_cfg_avail(void);
2156 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2157 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2159 #ifdef CONFIG_PCI_IOV
2160 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2161 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2163 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2164 void pci_disable_sriov(struct pci_dev *dev);
2166 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2167 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2168 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2169 int pci_num_vf(struct pci_dev *dev);
2170 int pci_vfs_assigned(struct pci_dev *dev);
2171 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2172 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2173 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2174 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2175 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2177 /* Arch may override these (weak) */
2178 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2179 int pcibios_sriov_disable(struct pci_dev *pdev);
2180 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2182 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2186 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2190 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2193 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2194 struct pci_dev *virtfn, int id)
2198 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2202 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2204 static inline void pci_disable_sriov(struct pci_dev *dev) { }
2205 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2206 static inline int pci_vfs_assigned(struct pci_dev *dev)
2208 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2210 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2212 #define pci_sriov_configure_simple NULL
2213 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2215 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2218 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2219 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2220 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2224 * pci_pcie_cap - get the saved PCIe capability offset
2227 * PCIe capability offset is calculated at PCI device initialization
2228 * time and saved in the data structure. This function returns saved
2229 * PCIe capability offset. Using this instead of pci_find_capability()
2230 * reduces unnecessary search in the PCI configuration space. If you
2231 * need to calculate PCIe capability offset from raw device for some
2232 * reasons, please use pci_find_capability() instead.
2234 static inline int pci_pcie_cap(struct pci_dev *dev)
2236 return dev->pcie_cap;
2240 * pci_is_pcie - check if the PCI device is PCI Express capable
2243 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2245 static inline bool pci_is_pcie(struct pci_dev *dev)
2247 return pci_pcie_cap(dev);
2251 * pcie_caps_reg - get the PCIe Capabilities Register
2254 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2256 return dev->pcie_flags_reg;
2260 * pci_pcie_type - get the PCIe device/port type
2263 static inline int pci_pcie_type(const struct pci_dev *dev)
2265 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2269 * pcie_find_root_port - Get the PCIe root port device
2272 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2273 * for a given PCI/PCIe Device.
2275 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2278 if (pci_is_pcie(dev) &&
2279 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2281 dev = pci_upstream_bridge(dev);
2287 void pci_request_acs(void);
2288 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2289 bool pci_acs_path_enabled(struct pci_dev *start,
2290 struct pci_dev *end, u16 acs_flags);
2291 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2293 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2294 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2296 /* Large Resource Data Type Tag Item Names */
2297 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2298 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2299 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2301 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2302 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2303 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2305 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2306 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2307 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2308 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2309 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2312 * pci_vpd_alloc - Allocate buffer and read VPD into it
2314 * @size: pointer to field where VPD length is returned
2316 * Returns pointer to allocated buffer or an ERR_PTR in case of failure
2318 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
2321 * pci_vpd_find_id_string - Locate id string in VPD
2322 * @buf: Pointer to buffered VPD data
2323 * @len: The length of the buffer area in which to search
2324 * @size: Pointer to field where length of id string is returned
2326 * Returns the index of the id string or -ENOENT if not found.
2328 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
2331 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section
2332 * @buf: Pointer to buffered VPD data
2333 * @len: The length of the buffer area in which to search
2334 * @kw: The keyword to search for
2335 * @size: Pointer to field where length of found keyword data is returned
2337 * Returns the index of the information field keyword data or -ENOENT if
2340 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
2341 const char *kw, unsigned int *size);
2344 * pci_vpd_check_csum - Check VPD checksum
2345 * @buf: Pointer to buffered VPD data
2348 * Returns 1 if VPD has no checksum, otherwise 0 or an errno
2350 int pci_vpd_check_csum(const void *buf, unsigned int len);
2352 /* PCI <-> OF binding helpers */
2356 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2357 bool pci_host_of_has_msi_map(struct device *dev);
2359 /* Arch may override this (weak) */
2360 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2362 #else /* CONFIG_OF */
2363 static inline struct irq_domain *
2364 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2365 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
2366 #endif /* CONFIG_OF */
2368 static inline struct device_node *
2369 pci_device_to_OF_node(const struct pci_dev *pdev)
2371 return pdev ? pdev->dev.of_node : NULL;
2374 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2376 return bus ? bus->dev.of_node : NULL;
2380 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2383 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2384 bool pci_pr3_present(struct pci_dev *pdev);
2386 static inline struct irq_domain *
2387 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2388 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2392 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2394 return pdev->dev.archdata.edev;
2398 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2399 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2400 int pci_for_each_dma_alias(struct pci_dev *pdev,
2401 int (*fn)(struct pci_dev *pdev,
2402 u16 alias, void *data), void *data);
2404 /* Helper functions for operation of device flag */
2405 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2407 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2409 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2411 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2413 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2415 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2419 * pci_ari_enabled - query ARI forwarding status
2422 * Returns true if ARI forwarding is enabled.
2424 static inline bool pci_ari_enabled(struct pci_bus *bus)
2426 return bus->self && bus->self->ari_enabled;
2430 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2431 * @pdev: PCI device to check
2433 * Walk upwards from @pdev and check for each encountered bridge if it's part
2434 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2435 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2437 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2439 struct pci_dev *parent = pdev;
2441 if (pdev->is_thunderbolt)
2444 while ((parent = pci_upstream_bridge(parent)))
2445 if (parent->is_thunderbolt)
2451 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2452 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2455 /* Provide the legacy pci_dma_* API */
2456 #include <linux/pci-dma-compat.h>
2458 #define pci_printk(level, pdev, fmt, arg...) \
2459 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2461 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2462 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2463 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2464 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2465 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2466 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2467 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2468 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2470 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2471 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2473 #define pci_info_ratelimited(pdev, fmt, arg...) \
2474 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2476 #define pci_WARN(pdev, condition, fmt, arg...) \
2477 WARN(condition, "%s %s: " fmt, \
2478 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2480 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2481 WARN_ONCE(condition, "%s %s: " fmt, \
2482 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2484 #endif /* LINUX_PCI_H */