4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/mod_devicetable.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
32 #include <linux/resource_ext.h>
33 #include <uapi/linux/pci.h>
35 #include <linux/pci_ids.h>
38 * The PCI interface treats multi-function devices as independent
39 * devices. The slot/function address of each device is encoded
40 * in a single byte as follows:
45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
46 * In the interest of not exposing interfaces to user-space unnecessarily,
47 * the following kernel-only defines are being added here.
49 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
53 /* pci_slot represents a physical slot */
55 struct pci_bus *bus; /* The bus this slot is on */
56 struct list_head list; /* node in list of slots on this bus */
57 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
58 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
62 static inline const char *pci_slot_name(const struct pci_slot *slot)
64 return kobject_name(&slot->kobj);
67 /* File state for mmap()s on /proc/bus/pci/X/Y */
74 * For PCI devices, the region numbers are assigned this way:
77 /* #0-5: standard PCI resources */
79 PCI_STD_RESOURCE_END = 5,
81 /* #6: expansion ROM resource */
84 /* device specific resources */
87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
90 /* resources assigned to buses behind the bridge */
91 #define PCI_BRIDGE_RESOURCE_NUM 4
94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
95 PCI_BRIDGE_RESOURCE_NUM - 1,
97 /* total resources associated with a PCI device */
100 /* preserve this for compatibility */
101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
105 * pci_power_t values must match the bits in the Capabilities PME_Support
106 * and Control/Status PowerState fields in the Power Management capability.
108 typedef int __bitwise pci_power_t;
110 #define PCI_D0 ((pci_power_t __force) 0)
111 #define PCI_D1 ((pci_power_t __force) 1)
112 #define PCI_D2 ((pci_power_t __force) 2)
113 #define PCI_D3hot ((pci_power_t __force) 3)
114 #define PCI_D3cold ((pci_power_t __force) 4)
115 #define PCI_UNKNOWN ((pci_power_t __force) 5)
116 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
118 /* Remember to update this when the list above changes! */
119 extern const char *pci_power_names[];
121 static inline const char *pci_power_name(pci_power_t state)
123 return pci_power_names[1 + (__force int) state];
126 #define PCI_PM_D2_DELAY 200
127 #define PCI_PM_D3_WAIT 10
128 #define PCI_PM_D3COLD_WAIT 100
129 #define PCI_PM_BUS_WAIT 50
131 /** The pci_channel state describes connectivity between the CPU and
132 * the pci device. If some PCI bus between here and the pci device
133 * has crashed or locked up, this info is reflected here.
135 typedef unsigned int __bitwise pci_channel_state_t;
137 enum pci_channel_state {
138 /* I/O channel is in normal state */
139 pci_channel_io_normal = (__force pci_channel_state_t) 1,
141 /* I/O to channel is blocked */
142 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
144 /* PCI card is dead */
145 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
148 typedef unsigned int __bitwise pcie_reset_state_t;
150 enum pcie_reset_state {
151 /* Reset is NOT asserted (Use to deassert reset) */
152 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
154 /* Use #PERST to reset PCIe device */
155 pcie_warm_reset = (__force pcie_reset_state_t) 2,
157 /* Use PCIe Hot Reset to reset device */
158 pcie_hot_reset = (__force pcie_reset_state_t) 3
161 typedef unsigned short __bitwise pci_dev_flags_t;
163 /* INTX_DISABLE in PCI_COMMAND register disables MSI
166 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
167 /* Device configuration is irrevocably lost if disabled into D3 */
168 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
169 /* Provide indication device is assigned by a Virtual Machine Manager */
170 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
171 /* Flag for quirk use to store if quirk-specific ACS is enabled */
172 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
173 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
174 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
175 /* Do not use bus resets for device */
176 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
177 /* Do not use PM reset even if device advertises NoSoftRst- */
178 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
179 /* Get VPD from function 0 VPD */
180 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
182 * Resume before calling the driver's system suspend hooks, disabling
183 * the direct_complete optimization.
185 PCI_DEV_FLAGS_NEEDS_RESUME = (__force pci_dev_flags_t) (1 << 11),
188 enum pci_irq_reroute_variant {
189 INTEL_IRQ_REROUTE_VARIANT = 1,
190 MAX_IRQ_REROUTE_VARIANTS = 3
193 typedef unsigned short __bitwise pci_bus_flags_t;
195 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
196 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
197 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
200 /* These values come from the PCI Express Spec */
201 enum pcie_link_width {
202 PCIE_LNK_WIDTH_RESRV = 0x00,
210 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
213 /* Based on the PCI Hotplug Spec, but some values are made up by us */
215 PCI_SPEED_33MHz = 0x00,
216 PCI_SPEED_66MHz = 0x01,
217 PCI_SPEED_66MHz_PCIX = 0x02,
218 PCI_SPEED_100MHz_PCIX = 0x03,
219 PCI_SPEED_133MHz_PCIX = 0x04,
220 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
221 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
222 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
223 PCI_SPEED_66MHz_PCIX_266 = 0x09,
224 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
225 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
231 PCI_SPEED_66MHz_PCIX_533 = 0x11,
232 PCI_SPEED_100MHz_PCIX_533 = 0x12,
233 PCI_SPEED_133MHz_PCIX_533 = 0x13,
234 PCIE_SPEED_2_5GT = 0x14,
235 PCIE_SPEED_5_0GT = 0x15,
236 PCIE_SPEED_8_0GT = 0x16,
237 PCI_SPEED_UNKNOWN = 0xff,
240 struct pci_cap_saved_data {
247 struct pci_cap_saved_state {
248 struct hlist_node next;
249 struct pci_cap_saved_data cap;
252 struct pcie_link_state;
258 * The pci_dev structure is used to describe PCI devices.
261 struct list_head bus_list; /* node in per-bus list */
262 struct pci_bus *bus; /* bus this device is on */
263 struct pci_bus *subordinate; /* bus this device bridges to */
265 void *sysdata; /* hook for sys-specific extension */
266 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
267 struct pci_slot *slot; /* Physical slot this device is in */
269 unsigned int devfn; /* encoded device & function index */
270 unsigned short vendor;
271 unsigned short device;
272 unsigned short subsystem_vendor;
273 unsigned short subsystem_device;
274 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
275 u8 revision; /* PCI revision, low byte of class word */
276 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
277 #ifdef CONFIG_PCIEAER
278 u16 aer_cap; /* AER capability offset */
280 u8 pcie_cap; /* PCIe capability offset */
281 u8 msi_cap; /* MSI capability offset */
282 u8 msix_cap; /* MSI-X capability offset */
283 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
284 u8 rom_base_reg; /* which config register controls the ROM */
285 u8 pin; /* which interrupt pin this device uses */
286 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
287 unsigned long *dma_alias_mask;/* mask of enabled devfn aliases */
289 struct pci_driver *driver; /* which driver has allocated this device */
290 u64 dma_mask; /* Mask of the bits of bus address this
291 device implements. Normally this is
292 0xffffffff. You only need to change
293 this if your device has broken DMA
294 or supports 64-bit transfers. */
296 struct device_dma_parameters dma_parms;
298 pci_power_t current_state; /* Current operating state. In ACPI-speak,
299 this is D0-D3, D0 being fully functional,
301 u8 pm_cap; /* PM capability offset */
302 unsigned int pme_support:5; /* Bitmask of states from which PME#
304 unsigned int pme_interrupt:1;
305 unsigned int pme_poll:1; /* Poll device's PME status bit */
306 unsigned int d1_support:1; /* Low power state D1 is supported */
307 unsigned int d2_support:1; /* Low power state D2 is supported */
308 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
309 unsigned int no_d3cold:1; /* D3cold is forbidden */
310 unsigned int bridge_d3:1; /* Allow D3 for bridge */
311 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
312 unsigned int mmio_always_on:1; /* disallow turning off io/mem
313 decoding during bar sizing */
314 unsigned int wakeup_prepared:1;
315 unsigned int runtime_d3cold:1; /* whether go through runtime
316 D3cold, not set for devices
317 powered on/off by the
318 corresponding bridge */
319 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
320 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
321 controlled exclusively by
323 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
325 unsigned int d3_delay; /* D3->D0 transition time in ms */
326 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
328 #ifdef CONFIG_PCIEASPM
329 struct pcie_link_state *link_state; /* ASPM link state */
332 pci_channel_state_t error_state; /* current connectivity state */
333 struct device dev; /* Generic device interface */
335 int cfg_size; /* Size of configuration space */
338 * Instead of touching interrupt line and base address registers
339 * directly, use the values stored here. They might be different!
342 struct cpumask *irq_affinity;
343 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
345 bool match_driver; /* Skip attaching driver */
346 /* These fields are used by common fixups */
347 unsigned int transparent:1; /* Subtractive decode PCI bridge */
348 unsigned int multifunction:1;/* Part of multi-function device */
349 /* keep track of device state */
350 unsigned int is_added:1;
351 unsigned int is_busmaster:1; /* device is busmaster */
352 unsigned int no_msi:1; /* device may not use msi */
353 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */
354 unsigned int block_cfg_access:1; /* config space access is blocked */
355 unsigned int broken_parity_status:1; /* Device generates false positive parity */
356 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
357 unsigned int msi_enabled:1;
358 unsigned int msix_enabled:1;
359 unsigned int ari_enabled:1; /* ARI forwarding */
360 unsigned int ats_enabled:1; /* Address Translation Service */
361 unsigned int is_managed:1;
362 unsigned int needs_freset:1; /* Dev requires fundamental reset */
363 unsigned int state_saved:1;
364 unsigned int is_physfn:1;
365 unsigned int is_virtfn:1;
366 unsigned int reset_fn:1;
367 unsigned int is_hotplug_bridge:1;
368 unsigned int __aer_firmware_first_valid:1;
369 unsigned int __aer_firmware_first:1;
370 unsigned int broken_intx_masking:1;
371 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
372 unsigned int irq_managed:1;
373 unsigned int has_secondary_link:1;
374 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */
375 pci_dev_flags_t dev_flags;
376 atomic_t enable_cnt; /* pci_enable_device has been called */
378 u32 saved_config_space[16]; /* config space saved at suspend time */
379 struct hlist_head saved_cap_space;
380 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
381 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
382 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
383 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
385 #ifdef CONFIG_PCIE_PTM
386 unsigned int ptm_root:1;
387 unsigned int ptm_enabled:1;
390 #ifdef CONFIG_PCI_MSI
391 const struct attribute_group **msi_irq_groups;
394 #ifdef CONFIG_PCI_ATS
396 struct pci_sriov *sriov; /* SR-IOV capability related */
397 struct pci_dev *physfn; /* the PF this VF is associated with */
399 u16 ats_cap; /* ATS Capability offset */
400 u8 ats_stu; /* ATS Smallest Translation Unit */
401 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */
403 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
404 size_t romlen; /* Length of ROM if it's not from the BAR */
405 char *driver_override; /* Driver name to force a match */
408 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
410 #ifdef CONFIG_PCI_IOV
417 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
419 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
420 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
422 static inline int pci_channel_offline(struct pci_dev *pdev)
424 return (pdev->error_state != pci_channel_io_normal);
427 struct pci_host_bridge {
429 struct pci_bus *bus; /* root bus */
430 struct list_head windows; /* resource_entry */
431 void (*release_fn)(struct pci_host_bridge *);
433 unsigned int ignore_reset_delay:1; /* for entire hierarchy */
434 /* Resource alignment requirements */
435 resource_size_t (*align_resource)(struct pci_dev *dev,
436 const struct resource *res,
437 resource_size_t start,
438 resource_size_t size,
439 resource_size_t align);
442 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
444 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
446 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
447 void (*release_fn)(struct pci_host_bridge *),
450 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
453 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
454 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
455 * buses below host bridges or subtractive decode bridges) go in the list.
456 * Use pci_bus_for_each_resource() to iterate through all the resources.
460 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
461 * and there's no way to program the bridge with the details of the window.
462 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
463 * decode bit set, because they are explicit and can be programmed with _SRS.
465 #define PCI_SUBTRACTIVE_DECODE 0x1
467 struct pci_bus_resource {
468 struct list_head list;
469 struct resource *res;
473 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
476 struct list_head node; /* node in list of buses */
477 struct pci_bus *parent; /* parent bus this bridge is on */
478 struct list_head children; /* list of child buses */
479 struct list_head devices; /* list of devices on this bus */
480 struct pci_dev *self; /* bridge device as seen by parent */
481 struct list_head slots; /* list of slots on this bus;
482 protected by pci_slot_mutex */
483 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
484 struct list_head resources; /* address space routed to this bus */
485 struct resource busn_res; /* bus numbers routed to this bus */
487 struct pci_ops *ops; /* configuration access functions */
488 struct msi_controller *msi; /* MSI controller */
489 void *sysdata; /* hook for sys-specific extension */
490 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
492 unsigned char number; /* bus number */
493 unsigned char primary; /* number of primary bridge */
494 unsigned char max_bus_speed; /* enum pci_bus_speed */
495 unsigned char cur_bus_speed; /* enum pci_bus_speed */
496 #ifdef CONFIG_PCI_DOMAINS_GENERIC
502 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
503 pci_bus_flags_t bus_flags; /* inherited by child buses */
504 struct device *bridge;
506 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
507 struct bin_attribute *legacy_mem; /* legacy mem */
508 unsigned int is_added:1;
511 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
514 * Returns true if the PCI bus is root (behind host-PCI bridge),
517 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
518 * This is incorrect because "virtual" buses added for SR-IOV (via
519 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
521 static inline bool pci_is_root_bus(struct pci_bus *pbus)
523 return !(pbus->parent);
527 * pci_is_bridge - check if the PCI device is a bridge
530 * Return true if the PCI device is bridge whether it has subordinate
533 static inline bool pci_is_bridge(struct pci_dev *dev)
535 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
536 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
539 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
541 dev = pci_physfn(dev);
542 if (pci_is_root_bus(dev->bus))
545 return dev->bus->self;
548 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
549 void pci_put_host_bridge_device(struct device *dev);
551 #ifdef CONFIG_PCI_MSI
552 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
554 return pci_dev->msi_enabled || pci_dev->msix_enabled;
557 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
561 * Error values that may be returned by PCI functions.
563 #define PCIBIOS_SUCCESSFUL 0x00
564 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
565 #define PCIBIOS_BAD_VENDOR_ID 0x83
566 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
567 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
568 #define PCIBIOS_SET_FAILED 0x88
569 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
572 * Translate above to generic errno for passing back through non-PCI code.
574 static inline int pcibios_err_to_errno(int err)
576 if (err <= PCIBIOS_SUCCESSFUL)
577 return err; /* Assume already errno */
580 case PCIBIOS_FUNC_NOT_SUPPORTED:
582 case PCIBIOS_BAD_VENDOR_ID:
584 case PCIBIOS_DEVICE_NOT_FOUND:
586 case PCIBIOS_BAD_REGISTER_NUMBER:
588 case PCIBIOS_SET_FAILED:
590 case PCIBIOS_BUFFER_TOO_SMALL:
597 /* Low-level architecture-dependent routines */
600 int (*add_bus)(struct pci_bus *bus);
601 void (*remove_bus)(struct pci_bus *bus);
602 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
603 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
604 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
608 * ACPI needs to be able to access PCI config space before we've done a
609 * PCI bus scan and created pci_bus structures.
611 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
612 int reg, int len, u32 *val);
613 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
614 int reg, int len, u32 val);
616 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
617 typedef u64 pci_bus_addr_t;
619 typedef u32 pci_bus_addr_t;
622 struct pci_bus_region {
623 pci_bus_addr_t start;
628 spinlock_t lock; /* protects list, index */
629 struct list_head list; /* for IDs added at runtime */
634 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
635 * a set of callbacks in struct pci_error_handlers, that device driver
636 * will be notified of PCI bus errors, and will be driven to recovery
637 * when an error occurs.
640 typedef unsigned int __bitwise pci_ers_result_t;
642 enum pci_ers_result {
643 /* no result/none/not supported in device driver */
644 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
646 /* Device driver can recover without slot reset */
647 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
649 /* Device driver wants slot to be reset. */
650 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
652 /* Device has completely failed, is unrecoverable */
653 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
655 /* Device driver is fully recovered and operational */
656 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
658 /* No AER capabilities registered for the driver */
659 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
662 /* PCI bus error event callbacks */
663 struct pci_error_handlers {
664 /* PCI bus error detected on this device */
665 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
666 enum pci_channel_state error);
668 /* MMIO has been re-enabled, but not DMA */
669 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
671 /* PCI Express link has been reset */
672 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
674 /* PCI slot has been reset */
675 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
677 /* PCI function reset prepare or completed */
678 void (*reset_notify)(struct pci_dev *dev, bool prepare);
680 /* Device driver may resume normal operations */
681 void (*resume)(struct pci_dev *dev);
687 struct list_head node;
689 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
690 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
691 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
692 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
693 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
694 int (*resume_early) (struct pci_dev *dev);
695 int (*resume) (struct pci_dev *dev); /* Device woken up */
696 void (*shutdown) (struct pci_dev *dev);
697 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
698 const struct pci_error_handlers *err_handler;
699 struct device_driver driver;
700 struct pci_dynids dynids;
703 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
706 * PCI_DEVICE - macro used to describe a specific pci device
707 * @vend: the 16 bit PCI Vendor ID
708 * @dev: the 16 bit PCI Device ID
710 * This macro is used to create a struct pci_device_id that matches a
711 * specific device. The subvendor and subdevice fields will be set to
714 #define PCI_DEVICE(vend,dev) \
715 .vendor = (vend), .device = (dev), \
716 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
719 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
720 * @vend: the 16 bit PCI Vendor ID
721 * @dev: the 16 bit PCI Device ID
722 * @subvend: the 16 bit PCI Subvendor ID
723 * @subdev: the 16 bit PCI Subdevice ID
725 * This macro is used to create a struct pci_device_id that matches a
726 * specific device with subsystem information.
728 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
729 .vendor = (vend), .device = (dev), \
730 .subvendor = (subvend), .subdevice = (subdev)
733 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
734 * @dev_class: the class, subclass, prog-if triple for this device
735 * @dev_class_mask: the class mask for this device
737 * This macro is used to create a struct pci_device_id that matches a
738 * specific PCI class. The vendor, device, subvendor, and subdevice
739 * fields will be set to PCI_ANY_ID.
741 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
742 .class = (dev_class), .class_mask = (dev_class_mask), \
743 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
744 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
747 * PCI_VDEVICE - macro used to describe a specific pci device in short form
748 * @vend: the vendor name
749 * @dev: the 16 bit PCI Device ID
751 * This macro is used to create a struct pci_device_id that matches a
752 * specific PCI device. The subvendor, and subdevice fields will be set
753 * to PCI_ANY_ID. The macro allows the next field to follow as the device
757 #define PCI_VDEVICE(vend, dev) \
758 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
759 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
762 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */
763 PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */
764 PCI_PROBE_ONLY = 0x00000004, /* use existing setup */
765 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */
766 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */
767 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
768 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */
771 /* these external functions are only available when PCI support is enabled */
774 extern unsigned int pci_flags;
776 static inline void pci_set_flags(int flags) { pci_flags = flags; }
777 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
778 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
779 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
781 void pcie_bus_configure_settings(struct pci_bus *bus);
783 enum pcie_bus_config_types {
784 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */
785 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */
786 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */
787 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */
788 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */
791 extern enum pcie_bus_config_types pcie_bus_config;
793 extern struct bus_type pci_bus_type;
795 /* Do NOT directly access these two variables, unless you are arch-specific PCI
796 * code, or PCI core code. */
797 extern struct list_head pci_root_buses; /* list of all known PCI buses */
798 /* Some device drivers need know if PCI is initiated */
799 int no_pci_devices(void);
801 void pcibios_resource_survey_bus(struct pci_bus *bus);
802 void pcibios_bus_add_device(struct pci_dev *pdev);
803 void pcibios_add_bus(struct pci_bus *bus);
804 void pcibios_remove_bus(struct pci_bus *bus);
805 void pcibios_fixup_bus(struct pci_bus *);
806 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
807 /* Architecture-specific versions may override this (weak) */
808 char *pcibios_setup(char *str);
810 /* Used only when drivers/pci/setup.c is used */
811 resource_size_t pcibios_align_resource(void *, const struct resource *,
814 void pcibios_update_irq(struct pci_dev *, int irq);
816 /* Weak but can be overriden by arch */
817 void pci_fixup_cardbus(struct pci_bus *);
819 /* Generic PCI functions used internally */
821 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
822 struct resource *res);
823 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
824 struct pci_bus_region *region);
825 void pcibios_scan_specific_bus(int busn);
826 struct pci_bus *pci_find_bus(int domain, int busnr);
827 void pci_bus_add_devices(const struct pci_bus *bus);
828 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
829 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
830 struct pci_ops *ops, void *sysdata,
831 struct list_head *resources);
832 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
833 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
834 void pci_bus_release_busn_res(struct pci_bus *b);
835 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
836 struct pci_ops *ops, void *sysdata,
837 struct list_head *resources,
838 struct msi_controller *msi);
839 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
840 struct pci_ops *ops, void *sysdata,
841 struct list_head *resources);
842 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
844 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
845 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
847 struct hotplug_slot *hotplug);
848 void pci_destroy_slot(struct pci_slot *slot);
850 void pci_dev_assign_slot(struct pci_dev *dev);
852 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
854 int pci_scan_slot(struct pci_bus *bus, int devfn);
855 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
856 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
857 unsigned int pci_scan_child_bus(struct pci_bus *bus);
858 void pci_bus_add_device(struct pci_dev *dev);
859 void pci_read_bridge_bases(struct pci_bus *child);
860 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
861 struct resource *res);
862 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
863 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
864 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
865 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
866 struct pci_dev *pci_dev_get(struct pci_dev *dev);
867 void pci_dev_put(struct pci_dev *dev);
868 void pci_remove_bus(struct pci_bus *b);
869 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
870 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
871 void pci_stop_root_bus(struct pci_bus *bus);
872 void pci_remove_root_bus(struct pci_bus *bus);
873 void pci_setup_cardbus(struct pci_bus *bus);
874 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
875 void pci_sort_breadthfirst(void);
876 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
877 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
878 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
880 /* Generic PCI functions exported to card drivers */
882 enum pci_lost_interrupt_reason {
883 PCI_LOST_IRQ_NO_INFORMATION = 0,
884 PCI_LOST_IRQ_DISABLE_MSI,
885 PCI_LOST_IRQ_DISABLE_MSIX,
886 PCI_LOST_IRQ_DISABLE_ACPI,
888 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
889 int pci_find_capability(struct pci_dev *dev, int cap);
890 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
891 int pci_find_ext_capability(struct pci_dev *dev, int cap);
892 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
893 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
894 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
895 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
897 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
898 struct pci_dev *from);
899 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
900 unsigned int ss_vendor, unsigned int ss_device,
901 struct pci_dev *from);
902 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
903 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
905 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
908 return pci_get_domain_bus_and_slot(0, bus, devfn);
910 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
911 int pci_dev_present(const struct pci_device_id *ids);
913 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
915 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
916 int where, u16 *val);
917 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
918 int where, u32 *val);
919 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
921 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
923 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
926 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
927 int where, int size, u32 *val);
928 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
929 int where, int size, u32 val);
930 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
931 int where, int size, u32 *val);
932 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
933 int where, int size, u32 val);
935 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
937 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
939 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
941 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
943 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
945 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
948 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
950 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
952 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
954 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
956 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
958 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
961 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
964 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
965 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
966 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
967 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
968 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
970 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
973 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
976 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
979 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
982 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
985 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
988 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
991 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
994 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
997 /* user-space driven config access */
998 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
999 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1000 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1001 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1002 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1003 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1005 int __must_check pci_enable_device(struct pci_dev *dev);
1006 int __must_check pci_enable_device_io(struct pci_dev *dev);
1007 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1008 int __must_check pci_reenable_device(struct pci_dev *);
1009 int __must_check pcim_enable_device(struct pci_dev *pdev);
1010 void pcim_pin_device(struct pci_dev *pdev);
1012 static inline int pci_is_enabled(struct pci_dev *pdev)
1014 return (atomic_read(&pdev->enable_cnt) > 0);
1017 static inline int pci_is_managed(struct pci_dev *pdev)
1019 return pdev->is_managed;
1022 void pci_disable_device(struct pci_dev *dev);
1024 extern unsigned int pcibios_max_latency;
1025 void pci_set_master(struct pci_dev *dev);
1026 void pci_clear_master(struct pci_dev *dev);
1028 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1029 int pci_set_cacheline_size(struct pci_dev *dev);
1030 #define HAVE_PCI_SET_MWI
1031 int __must_check pci_set_mwi(struct pci_dev *dev);
1032 int pci_try_set_mwi(struct pci_dev *dev);
1033 void pci_clear_mwi(struct pci_dev *dev);
1034 void pci_intx(struct pci_dev *dev, int enable);
1035 bool pci_intx_mask_supported(struct pci_dev *dev);
1036 bool pci_check_and_mask_intx(struct pci_dev *dev);
1037 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1038 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1039 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1040 int pcix_get_max_mmrbc(struct pci_dev *dev);
1041 int pcix_get_mmrbc(struct pci_dev *dev);
1042 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1043 int pcie_get_readrq(struct pci_dev *dev);
1044 int pcie_set_readrq(struct pci_dev *dev, int rq);
1045 int pcie_get_mps(struct pci_dev *dev);
1046 int pcie_set_mps(struct pci_dev *dev, int mps);
1047 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1048 enum pcie_link_width *width);
1049 int __pci_reset_function(struct pci_dev *dev);
1050 int __pci_reset_function_locked(struct pci_dev *dev);
1051 int pci_reset_function(struct pci_dev *dev);
1052 int pci_try_reset_function(struct pci_dev *dev);
1053 int pci_probe_reset_slot(struct pci_slot *slot);
1054 int pci_reset_slot(struct pci_slot *slot);
1055 int pci_try_reset_slot(struct pci_slot *slot);
1056 int pci_probe_reset_bus(struct pci_bus *bus);
1057 int pci_reset_bus(struct pci_bus *bus);
1058 int pci_try_reset_bus(struct pci_bus *bus);
1059 void pci_reset_secondary_bus(struct pci_dev *dev);
1060 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1061 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1062 void pci_update_resource(struct pci_dev *dev, int resno);
1063 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1064 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1065 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1066 bool pci_device_is_present(struct pci_dev *pdev);
1067 void pci_ignore_hotplug(struct pci_dev *dev);
1069 /* ROM control related routines */
1070 int pci_enable_rom(struct pci_dev *pdev);
1071 void pci_disable_rom(struct pci_dev *pdev);
1072 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1073 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1074 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1075 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1077 /* Power management related routines */
1078 int pci_save_state(struct pci_dev *dev);
1079 void pci_restore_state(struct pci_dev *dev);
1080 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1081 int pci_load_saved_state(struct pci_dev *dev,
1082 struct pci_saved_state *state);
1083 int pci_load_and_free_saved_state(struct pci_dev *dev,
1084 struct pci_saved_state **state);
1085 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1086 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1088 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1089 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1090 u16 cap, unsigned int size);
1091 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1092 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1093 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1094 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1095 void pci_pme_active(struct pci_dev *dev, bool enable);
1096 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1097 bool runtime, bool enable);
1098 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1099 int pci_prepare_to_sleep(struct pci_dev *dev);
1100 int pci_back_from_sleep(struct pci_dev *dev);
1101 bool pci_dev_run_wake(struct pci_dev *dev);
1102 bool pci_check_pme_status(struct pci_dev *dev);
1103 void pci_pme_wakeup_bus(struct pci_bus *bus);
1104 void pci_d3cold_enable(struct pci_dev *dev);
1105 void pci_d3cold_disable(struct pci_dev *dev);
1107 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1110 return __pci_enable_wake(dev, state, false, enable);
1113 /* PCI Virtual Channel */
1114 int pci_save_vc_state(struct pci_dev *dev);
1115 void pci_restore_vc_state(struct pci_dev *dev);
1116 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1118 /* For use by arch with custom probe code */
1119 void set_pcie_port_type(struct pci_dev *pdev);
1120 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1122 /* Functions for PCI Hotplug drivers to use */
1123 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1124 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1125 unsigned int pci_rescan_bus(struct pci_bus *bus);
1126 void pci_lock_rescan_remove(void);
1127 void pci_unlock_rescan_remove(void);
1129 /* Vital product data routines */
1130 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1131 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1132 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1134 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1135 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1136 void pci_bus_assign_resources(const struct pci_bus *bus);
1137 void pci_bus_claim_resources(struct pci_bus *bus);
1138 void pci_bus_size_bridges(struct pci_bus *bus);
1139 int pci_claim_resource(struct pci_dev *, int);
1140 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1141 void pci_assign_unassigned_resources(void);
1142 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1143 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1144 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1145 void pdev_enable_device(struct pci_dev *);
1146 int pci_enable_resources(struct pci_dev *, int mask);
1147 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1148 int (*)(const struct pci_dev *, u8, u8));
1149 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1150 #define HAVE_PCI_REQ_REGIONS 2
1151 int __must_check pci_request_regions(struct pci_dev *, const char *);
1152 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1153 void pci_release_regions(struct pci_dev *);
1154 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1155 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1156 void pci_release_region(struct pci_dev *, int);
1157 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1158 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1159 void pci_release_selected_regions(struct pci_dev *, int);
1161 /* drivers/pci/bus.c */
1162 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1163 void pci_bus_put(struct pci_bus *bus);
1164 void pci_add_resource(struct list_head *resources, struct resource *res);
1165 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1166 resource_size_t offset);
1167 void pci_free_resource_list(struct list_head *resources);
1168 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1169 unsigned int flags);
1170 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1171 void pci_bus_remove_resources(struct pci_bus *bus);
1172 int devm_request_pci_bus_resources(struct device *dev,
1173 struct list_head *resources);
1175 #define pci_bus_for_each_resource(bus, res, i) \
1177 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1180 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1181 struct resource *res, resource_size_t size,
1182 resource_size_t align, resource_size_t min,
1183 unsigned long type_mask,
1184 resource_size_t (*alignf)(void *,
1185 const struct resource *,
1191 int pci_register_io_range(phys_addr_t addr, resource_size_t size);
1192 unsigned long pci_address_to_pio(phys_addr_t addr);
1193 phys_addr_t pci_pio_to_address(unsigned long pio);
1194 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1195 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1196 phys_addr_t phys_addr);
1197 void pci_unmap_iospace(struct resource *res);
1199 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1201 struct pci_bus_region region;
1203 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1204 return region.start;
1207 /* Proper probing supporting hot-pluggable devices */
1208 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1209 const char *mod_name);
1212 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1214 #define pci_register_driver(driver) \
1215 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1217 void pci_unregister_driver(struct pci_driver *dev);
1220 * module_pci_driver() - Helper macro for registering a PCI driver
1221 * @__pci_driver: pci_driver struct
1223 * Helper macro for PCI drivers which do not do anything special in module
1224 * init/exit. This eliminates a lot of boilerplate. Each module may only
1225 * use this macro once, and calling it replaces module_init() and module_exit()
1227 #define module_pci_driver(__pci_driver) \
1228 module_driver(__pci_driver, pci_register_driver, \
1229 pci_unregister_driver)
1232 * builtin_pci_driver() - Helper macro for registering a PCI driver
1233 * @__pci_driver: pci_driver struct
1235 * Helper macro for PCI drivers which do not do anything special in their
1236 * init code. This eliminates a lot of boilerplate. Each driver may only
1237 * use this macro once, and calling it replaces device_initcall(...)
1239 #define builtin_pci_driver(__pci_driver) \
1240 builtin_driver(__pci_driver, pci_register_driver)
1242 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1243 int pci_add_dynid(struct pci_driver *drv,
1244 unsigned int vendor, unsigned int device,
1245 unsigned int subvendor, unsigned int subdevice,
1246 unsigned int class, unsigned int class_mask,
1247 unsigned long driver_data);
1248 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1249 struct pci_dev *dev);
1250 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1253 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1255 int pci_cfg_space_size(struct pci_dev *dev);
1256 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1257 void pci_setup_bridge(struct pci_bus *bus);
1258 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1259 unsigned long type);
1260 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1262 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1263 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1265 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1266 unsigned int command_bits, u32 flags);
1268 #define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */
1269 #define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */
1270 #define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */
1271 #define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */
1272 #define PCI_IRQ_ALL_TYPES \
1273 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1275 /* kmem_cache style wrapper around pci_alloc_consistent() */
1277 #include <linux/pci-dma.h>
1278 #include <linux/dmapool.h>
1280 #define pci_pool dma_pool
1281 #define pci_pool_create(name, pdev, size, align, allocation) \
1282 dma_pool_create(name, &pdev->dev, size, align, allocation)
1283 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1284 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1285 #define pci_pool_zalloc(pool, flags, handle) \
1286 dma_pool_zalloc(pool, flags, handle)
1287 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1290 u32 vector; /* kernel uses to write allocated vector */
1291 u16 entry; /* driver uses to specify entry, OS writes */
1294 #ifdef CONFIG_PCI_MSI
1295 int pci_msi_vec_count(struct pci_dev *dev);
1296 void pci_msi_shutdown(struct pci_dev *dev);
1297 void pci_disable_msi(struct pci_dev *dev);
1298 int pci_msix_vec_count(struct pci_dev *dev);
1299 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1300 void pci_msix_shutdown(struct pci_dev *dev);
1301 void pci_disable_msix(struct pci_dev *dev);
1302 void pci_restore_msi_state(struct pci_dev *dev);
1303 int pci_msi_enabled(void);
1304 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec);
1305 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1307 int rc = pci_enable_msi_range(dev, nvec, nvec);
1312 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1313 int minvec, int maxvec);
1314 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1315 struct msix_entry *entries, int nvec)
1317 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1322 int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1323 unsigned int max_vecs, unsigned int flags);
1324 void pci_free_irq_vectors(struct pci_dev *dev);
1325 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1326 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1329 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1330 static inline void pci_msi_shutdown(struct pci_dev *dev) { }
1331 static inline void pci_disable_msi(struct pci_dev *dev) { }
1332 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1333 static inline int pci_enable_msix(struct pci_dev *dev,
1334 struct msix_entry *entries, int nvec)
1336 static inline void pci_msix_shutdown(struct pci_dev *dev) { }
1337 static inline void pci_disable_msix(struct pci_dev *dev) { }
1338 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1339 static inline int pci_msi_enabled(void) { return 0; }
1340 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec,
1343 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1345 static inline int pci_enable_msix_range(struct pci_dev *dev,
1346 struct msix_entry *entries, int minvec, int maxvec)
1348 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1349 struct msix_entry *entries, int nvec)
1351 static inline int pci_alloc_irq_vectors(struct pci_dev *dev,
1352 unsigned int min_vecs, unsigned int max_vecs,
1355 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1359 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1363 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1365 if (WARN_ON_ONCE(nr > 0))
1369 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1372 return cpu_possible_mask;
1376 #ifdef CONFIG_PCIEPORTBUS
1377 extern bool pcie_ports_disabled;
1378 extern bool pcie_ports_auto;
1380 #define pcie_ports_disabled true
1381 #define pcie_ports_auto false
1384 #ifdef CONFIG_PCIEASPM
1385 bool pcie_aspm_support_enabled(void);
1387 static inline bool pcie_aspm_support_enabled(void) { return false; }
1390 #ifdef CONFIG_PCIEAER
1391 void pci_no_aer(void);
1392 bool pci_aer_available(void);
1393 int pci_aer_init(struct pci_dev *dev);
1395 static inline void pci_no_aer(void) { }
1396 static inline bool pci_aer_available(void) { return false; }
1397 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
1400 #ifdef CONFIG_PCIE_ECRC
1401 void pcie_set_ecrc_checking(struct pci_dev *dev);
1402 void pcie_ecrc_get_policy(char *str);
1404 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1405 static inline void pcie_ecrc_get_policy(char *str) { }
1408 #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1)
1410 #ifdef CONFIG_HT_IRQ
1411 /* The functions a driver should call */
1412 int ht_create_irq(struct pci_dev *dev, int idx);
1413 void ht_destroy_irq(unsigned int irq);
1414 #endif /* CONFIG_HT_IRQ */
1416 #ifdef CONFIG_PCI_ATS
1417 /* Address Translation Service */
1418 void pci_ats_init(struct pci_dev *dev);
1419 int pci_enable_ats(struct pci_dev *dev, int ps);
1420 void pci_disable_ats(struct pci_dev *dev);
1421 int pci_ats_queue_depth(struct pci_dev *dev);
1423 static inline void pci_ats_init(struct pci_dev *d) { }
1424 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1425 static inline void pci_disable_ats(struct pci_dev *d) { }
1426 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1429 #ifdef CONFIG_PCIE_PTM
1430 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1432 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1436 void pci_cfg_access_lock(struct pci_dev *dev);
1437 bool pci_cfg_access_trylock(struct pci_dev *dev);
1438 void pci_cfg_access_unlock(struct pci_dev *dev);
1441 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1442 * a PCI domain is defined to be a set of PCI buses which share
1443 * configuration space.
1445 #ifdef CONFIG_PCI_DOMAINS
1446 extern int pci_domains_supported;
1447 int pci_get_new_domain_nr(void);
1449 enum { pci_domains_supported = 0 };
1450 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1451 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1452 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1453 #endif /* CONFIG_PCI_DOMAINS */
1456 * Generic implementation for PCI domain support. If your
1457 * architecture does not need custom management of PCI
1458 * domains then this implementation will be used
1460 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1461 static inline int pci_domain_nr(struct pci_bus *bus)
1463 return bus->domain_nr;
1466 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1468 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1471 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1474 /* some architectures require additional setup to direct VGA traffic */
1475 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1476 unsigned int command_bits, u32 flags);
1477 void pci_register_set_vga_state(arch_set_vga_state_t func);
1480 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1482 return pci_request_selected_regions(pdev,
1483 pci_select_bars(pdev, IORESOURCE_IO), name);
1487 pci_release_io_regions(struct pci_dev *pdev)
1489 return pci_release_selected_regions(pdev,
1490 pci_select_bars(pdev, IORESOURCE_IO));
1494 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1496 return pci_request_selected_regions(pdev,
1497 pci_select_bars(pdev, IORESOURCE_MEM), name);
1501 pci_release_mem_regions(struct pci_dev *pdev)
1503 return pci_release_selected_regions(pdev,
1504 pci_select_bars(pdev, IORESOURCE_MEM));
1507 #else /* CONFIG_PCI is not enabled */
1509 static inline void pci_set_flags(int flags) { }
1510 static inline void pci_add_flags(int flags) { }
1511 static inline void pci_clear_flags(int flags) { }
1512 static inline int pci_has_flag(int flag) { return 0; }
1515 * If the system does not have PCI, clearly these return errors. Define
1516 * these as simple inline functions to avoid hair in drivers.
1519 #define _PCI_NOP(o, s, t) \
1520 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1522 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1524 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1525 _PCI_NOP(o, word, u16 x) \
1526 _PCI_NOP(o, dword, u32 x)
1527 _PCI_NOP_ALL(read, *)
1528 _PCI_NOP_ALL(write,)
1530 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1531 unsigned int device,
1532 struct pci_dev *from)
1535 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1536 unsigned int device,
1537 unsigned int ss_vendor,
1538 unsigned int ss_device,
1539 struct pci_dev *from)
1542 static inline struct pci_dev *pci_get_class(unsigned int class,
1543 struct pci_dev *from)
1546 #define pci_dev_present(ids) (0)
1547 #define no_pci_devices() (1)
1548 #define pci_dev_put(dev) do { } while (0)
1550 static inline void pci_set_master(struct pci_dev *dev) { }
1551 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1552 static inline void pci_disable_device(struct pci_dev *dev) { }
1553 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1555 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1556 struct module *owner,
1557 const char *mod_name)
1559 static inline int pci_register_driver(struct pci_driver *drv)
1561 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1562 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1564 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1567 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1570 /* Power management related routines */
1571 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1572 static inline void pci_restore_state(struct pci_dev *dev) { }
1573 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1575 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1577 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1580 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1584 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1585 struct resource *res)
1587 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1589 static inline void pci_release_regions(struct pci_dev *dev) { }
1591 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1593 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1594 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1596 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1598 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1600 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1603 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1607 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1608 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1609 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1611 #define dev_is_pci(d) (false)
1612 #define dev_is_pf(d) (false)
1613 #define dev_num_vf(d) (0)
1614 #endif /* CONFIG_PCI */
1616 /* Include architecture-dependent settings and functions */
1618 #include <asm/pci.h>
1620 #ifndef pci_root_bus_fwnode
1621 #define pci_root_bus_fwnode(bus) NULL
1624 /* these helpers provide future and backwards compatibility
1625 * for accessing popular PCI BAR info */
1626 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1627 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1628 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1629 #define pci_resource_len(dev,bar) \
1630 ((pci_resource_start((dev), (bar)) == 0 && \
1631 pci_resource_end((dev), (bar)) == \
1632 pci_resource_start((dev), (bar))) ? 0 : \
1634 (pci_resource_end((dev), (bar)) - \
1635 pci_resource_start((dev), (bar)) + 1))
1637 /* Similar to the helpers above, these manipulate per-pci_dev
1638 * driver-specific data. They are really just a wrapper around
1639 * the generic device structure functions of these calls.
1641 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1643 return dev_get_drvdata(&pdev->dev);
1646 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1648 dev_set_drvdata(&pdev->dev, data);
1651 /* If you want to know what to call your pci_dev, ask this function.
1652 * Again, it's a wrapper around the generic device.
1654 static inline const char *pci_name(const struct pci_dev *pdev)
1656 return dev_name(&pdev->dev);
1660 /* Some archs don't want to expose struct resource to userland as-is
1661 * in sysfs and /proc
1663 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1664 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1665 const struct resource *rsrc,
1666 resource_size_t *start, resource_size_t *end);
1668 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1669 const struct resource *rsrc, resource_size_t *start,
1670 resource_size_t *end)
1672 *start = rsrc->start;
1675 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1679 * The world is not perfect and supplies us with broken PCI devices.
1680 * For at least a part of these bugs we need a work-around, so both
1681 * generic (drivers/pci/quirks.c) and per-architecture code can define
1682 * fixup hooks to be called for particular buggy devices.
1686 u16 vendor; /* You can use PCI_ANY_ID here of course */
1687 u16 device; /* You can use PCI_ANY_ID here of course */
1688 u32 class; /* You can use PCI_ANY_ID here too */
1689 unsigned int class_shift; /* should be 0, 8, 16 */
1690 void (*hook)(struct pci_dev *dev);
1693 enum pci_fixup_pass {
1694 pci_fixup_early, /* Before probing BARs */
1695 pci_fixup_header, /* After reading configuration header */
1696 pci_fixup_final, /* Final phase of device fixups */
1697 pci_fixup_enable, /* pci_enable_device() time */
1698 pci_fixup_resume, /* pci_device_resume() */
1699 pci_fixup_suspend, /* pci_device_suspend() */
1700 pci_fixup_resume_early, /* pci_device_resume_early() */
1701 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1704 /* Anonymous variables would be nice... */
1705 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1706 class_shift, hook) \
1707 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1708 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1709 = { vendor, device, class, class_shift, hook };
1711 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1712 class_shift, hook) \
1713 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1714 hook, vendor, device, class, class_shift, hook)
1715 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1716 class_shift, hook) \
1717 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1718 hook, vendor, device, class, class_shift, hook)
1719 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1720 class_shift, hook) \
1721 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1722 hook, vendor, device, class, class_shift, hook)
1723 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1724 class_shift, hook) \
1725 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1726 hook, vendor, device, class, class_shift, hook)
1727 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1728 class_shift, hook) \
1729 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1730 resume##hook, vendor, device, class, \
1732 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1733 class_shift, hook) \
1734 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1735 resume_early##hook, vendor, device, \
1736 class, class_shift, hook)
1737 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1738 class_shift, hook) \
1739 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1740 suspend##hook, vendor, device, class, \
1742 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1743 class_shift, hook) \
1744 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1745 suspend_late##hook, vendor, device, \
1746 class, class_shift, hook)
1748 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1749 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1750 hook, vendor, device, PCI_ANY_ID, 0, hook)
1751 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1752 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1753 hook, vendor, device, PCI_ANY_ID, 0, hook)
1754 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1755 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1756 hook, vendor, device, PCI_ANY_ID, 0, hook)
1757 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1758 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1759 hook, vendor, device, PCI_ANY_ID, 0, hook)
1760 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1761 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1762 resume##hook, vendor, device, \
1763 PCI_ANY_ID, 0, hook)
1764 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1765 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1766 resume_early##hook, vendor, device, \
1767 PCI_ANY_ID, 0, hook)
1768 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1769 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1770 suspend##hook, vendor, device, \
1771 PCI_ANY_ID, 0, hook)
1772 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1773 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1774 suspend_late##hook, vendor, device, \
1775 PCI_ANY_ID, 0, hook)
1777 #ifdef CONFIG_PCI_QUIRKS
1778 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1779 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1780 int pci_dev_specific_enable_acs(struct pci_dev *dev);
1782 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1783 struct pci_dev *dev) { }
1784 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1789 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1795 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1796 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1797 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1798 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1799 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1801 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1803 extern int pci_pci_problems;
1804 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1805 #define PCIPCI_TRITON 2
1806 #define PCIPCI_NATOMA 4
1807 #define PCIPCI_VIAETBF 8
1808 #define PCIPCI_VSFX 16
1809 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1810 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1812 extern unsigned long pci_cardbus_io_size;
1813 extern unsigned long pci_cardbus_mem_size;
1814 extern u8 pci_dfl_cache_line_size;
1815 extern u8 pci_cache_line_size;
1817 extern unsigned long pci_hotplug_io_size;
1818 extern unsigned long pci_hotplug_mem_size;
1819 extern unsigned long pci_hotplug_bus_size;
1821 /* Architecture-specific versions may override these (weak) */
1822 void pcibios_disable_device(struct pci_dev *dev);
1823 void pcibios_set_master(struct pci_dev *dev);
1824 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1825 enum pcie_reset_state state);
1826 int pcibios_add_device(struct pci_dev *dev);
1827 void pcibios_release_device(struct pci_dev *dev);
1828 void pcibios_penalize_isa_irq(int irq, int active);
1829 int pcibios_alloc_irq(struct pci_dev *dev);
1830 void pcibios_free_irq(struct pci_dev *dev);
1832 #ifdef CONFIG_HIBERNATE_CALLBACKS
1833 extern struct dev_pm_ops pcibios_pm_ops;
1836 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1837 void __init pci_mmcfg_early_init(void);
1838 void __init pci_mmcfg_late_init(void);
1840 static inline void pci_mmcfg_early_init(void) { }
1841 static inline void pci_mmcfg_late_init(void) { }
1844 int pci_ext_cfg_avail(void);
1846 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1847 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1849 #ifdef CONFIG_PCI_IOV
1850 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1851 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1853 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1854 void pci_disable_sriov(struct pci_dev *dev);
1855 int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset);
1856 void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset);
1857 int pci_num_vf(struct pci_dev *dev);
1858 int pci_vfs_assigned(struct pci_dev *dev);
1859 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1860 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1861 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1863 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1867 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1871 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1873 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset)
1877 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
1878 int id, int reset) { }
1879 static inline void pci_disable_sriov(struct pci_dev *dev) { }
1880 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1881 static inline int pci_vfs_assigned(struct pci_dev *dev)
1883 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1885 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1887 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1891 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1892 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1893 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1897 * pci_pcie_cap - get the saved PCIe capability offset
1900 * PCIe capability offset is calculated at PCI device initialization
1901 * time and saved in the data structure. This function returns saved
1902 * PCIe capability offset. Using this instead of pci_find_capability()
1903 * reduces unnecessary search in the PCI configuration space. If you
1904 * need to calculate PCIe capability offset from raw device for some
1905 * reasons, please use pci_find_capability() instead.
1907 static inline int pci_pcie_cap(struct pci_dev *dev)
1909 return dev->pcie_cap;
1913 * pci_is_pcie - check if the PCI device is PCI Express capable
1916 * Returns: true if the PCI device is PCI Express capable, false otherwise.
1918 static inline bool pci_is_pcie(struct pci_dev *dev)
1920 return pci_pcie_cap(dev);
1924 * pcie_caps_reg - get the PCIe Capabilities Register
1927 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1929 return dev->pcie_flags_reg;
1933 * pci_pcie_type - get the PCIe device/port type
1936 static inline int pci_pcie_type(const struct pci_dev *dev)
1938 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1941 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
1944 if (!pci_is_pcie(dev))
1946 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
1948 if (!dev->bus->self)
1950 dev = dev->bus->self;
1955 void pci_request_acs(void);
1956 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1957 bool pci_acs_path_enabled(struct pci_dev *start,
1958 struct pci_dev *end, u16 acs_flags);
1960 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1961 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
1963 /* Large Resource Data Type Tag Item Names */
1964 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1965 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1966 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1968 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1969 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1970 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1972 /* Small Resource Data Type Tag Item Names */
1973 #define PCI_VPD_STIN_END 0x0f /* End */
1975 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
1977 #define PCI_VPD_SRDT_TIN_MASK 0x78
1978 #define PCI_VPD_SRDT_LEN_MASK 0x07
1979 #define PCI_VPD_LRDT_TIN_MASK 0x7f
1981 #define PCI_VPD_LRDT_TAG_SIZE 3
1982 #define PCI_VPD_SRDT_TAG_SIZE 1
1984 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1986 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1987 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1988 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1989 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1992 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1993 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1995 * Returns the extracted Large Resource Data Type length.
1997 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1999 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2003 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2004 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2006 * Returns the extracted Large Resource Data Type Tag item.
2008 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2010 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2014 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2015 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
2017 * Returns the extracted Small Resource Data Type length.
2019 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2021 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2025 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2026 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
2028 * Returns the extracted Small Resource Data Type Tag Item.
2030 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2032 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2036 * pci_vpd_info_field_size - Extracts the information field length
2037 * @lrdt: Pointer to the beginning of an information field header
2039 * Returns the extracted information field length.
2041 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2043 return info_field[2];
2047 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2048 * @buf: Pointer to buffered vpd data
2049 * @off: The offset into the buffer at which to begin the search
2050 * @len: The length of the vpd buffer
2051 * @rdt: The Resource Data Type to search for
2053 * Returns the index where the Resource Data Type was found or
2054 * -ENOENT otherwise.
2056 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2059 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2060 * @buf: Pointer to buffered vpd data
2061 * @off: The offset into the buffer at which to begin the search
2062 * @len: The length of the buffer area, relative to off, in which to search
2063 * @kw: The keyword to search for
2065 * Returns the index where the information field keyword was found or
2066 * -ENOENT otherwise.
2068 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2069 unsigned int len, const char *kw);
2071 /* PCI <-> OF binding helpers */
2075 void pci_set_of_node(struct pci_dev *dev);
2076 void pci_release_of_node(struct pci_dev *dev);
2077 void pci_set_bus_of_node(struct pci_bus *bus);
2078 void pci_release_bus_of_node(struct pci_bus *bus);
2079 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2081 /* Arch may override this (weak) */
2082 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2084 static inline struct device_node *
2085 pci_device_to_OF_node(const struct pci_dev *pdev)
2087 return pdev ? pdev->dev.of_node : NULL;
2090 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2092 return bus ? bus->dev.of_node : NULL;
2095 #else /* CONFIG_OF */
2096 static inline void pci_set_of_node(struct pci_dev *dev) { }
2097 static inline void pci_release_of_node(struct pci_dev *dev) { }
2098 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2099 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2100 static inline struct device_node *
2101 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
2102 static inline struct irq_domain *
2103 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2104 #endif /* CONFIG_OF */
2107 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2110 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2112 static inline struct irq_domain *
2113 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2117 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2119 return pdev->dev.archdata.edev;
2123 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2124 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2125 int pci_for_each_dma_alias(struct pci_dev *pdev,
2126 int (*fn)(struct pci_dev *pdev,
2127 u16 alias, void *data), void *data);
2129 /* helper functions for operation of device flag */
2130 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2132 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2134 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2136 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2138 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2140 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2144 * pci_ari_enabled - query ARI forwarding status
2147 * Returns true if ARI forwarding is enabled.
2149 static inline bool pci_ari_enabled(struct pci_bus *bus)
2151 return bus->self && bus->self->ari_enabled;
2154 /* provide the legacy pci_dma_* API */
2155 #include <linux/pci-dma-compat.h>
2157 #define pci_printk(level, pdev, fmt, arg...) \
2158 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2160 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2161 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2162 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2163 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2164 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2165 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2166 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2167 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2169 #endif /* LINUX_PCI_H */