1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * For more information, please consult the following manuals (look at
10 * http://www.pcisig.com/ for how to get them):
12 * PCI BIOS Specification
13 * PCI Local Bus Specification
14 * PCI to PCI Bridge Specification
15 * PCI System Design Guide
21 #include <linux/mod_devicetable.h>
23 #include <linux/types.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/list.h>
27 #include <linux/compiler.h>
28 #include <linux/errno.h>
29 #include <linux/kobject.h>
30 #include <linux/atomic.h>
31 #include <linux/device.h>
32 #include <linux/interrupt.h>
34 #include <linux/resource_ext.h>
35 #include <uapi/linux/pci.h>
37 #include <linux/pci_ids.h>
40 * The PCI interface treats multi-function devices as independent
41 * devices. The slot/function address of each device is encoded
42 * in a single byte as follows:
47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
48 * In the interest of not exposing interfaces to user-space unnecessarily,
49 * the following kernel-only defines are being added here.
51 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
52 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
53 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
55 /* pci_slot represents a physical slot */
57 struct pci_bus *bus; /* The bus this slot is on */
58 struct list_head list; /* node in list of slots on this bus */
59 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
64 static inline const char *pci_slot_name(const struct pci_slot *slot)
66 return kobject_name(&slot->kobj);
69 /* File state for mmap()s on /proc/bus/pci/X/Y */
76 * For PCI devices, the region numbers are assigned this way:
79 /* #0-5: standard PCI resources */
81 PCI_STD_RESOURCE_END = 5,
83 /* #6: expansion ROM resource */
86 /* device specific resources */
89 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
92 /* resources assigned to buses behind the bridge */
93 #define PCI_BRIDGE_RESOURCE_NUM 4
96 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
97 PCI_BRIDGE_RESOURCE_NUM - 1,
99 /* total resources associated with a PCI device */
102 /* preserve this for compatibility */
103 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
107 * enum pci_interrupt_pin - PCI INTx interrupt values
108 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
109 * @PCI_INTERRUPT_INTA: PCI INTA pin
110 * @PCI_INTERRUPT_INTB: PCI INTB pin
111 * @PCI_INTERRUPT_INTC: PCI INTC pin
112 * @PCI_INTERRUPT_INTD: PCI INTD pin
114 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
115 * PCI_INTERRUPT_PIN register.
117 enum pci_interrupt_pin {
118 PCI_INTERRUPT_UNKNOWN,
125 /* The number of legacy PCI INTx interrupts */
126 #define PCI_NUM_INTX 4
129 * pci_power_t values must match the bits in the Capabilities PME_Support
130 * and Control/Status PowerState fields in the Power Management capability.
132 typedef int __bitwise pci_power_t;
134 #define PCI_D0 ((pci_power_t __force) 0)
135 #define PCI_D1 ((pci_power_t __force) 1)
136 #define PCI_D2 ((pci_power_t __force) 2)
137 #define PCI_D3hot ((pci_power_t __force) 3)
138 #define PCI_D3cold ((pci_power_t __force) 4)
139 #define PCI_UNKNOWN ((pci_power_t __force) 5)
140 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
142 /* Remember to update this when the list above changes! */
143 extern const char *pci_power_names[];
145 static inline const char *pci_power_name(pci_power_t state)
147 return pci_power_names[1 + (__force int) state];
150 #define PCI_PM_D2_DELAY 200
151 #define PCI_PM_D3_WAIT 10
152 #define PCI_PM_D3COLD_WAIT 100
153 #define PCI_PM_BUS_WAIT 50
155 /** The pci_channel state describes connectivity between the CPU and
156 * the pci device. If some PCI bus between here and the pci device
157 * has crashed or locked up, this info is reflected here.
159 typedef unsigned int __bitwise pci_channel_state_t;
161 enum pci_channel_state {
162 /* I/O channel is in normal state */
163 pci_channel_io_normal = (__force pci_channel_state_t) 1,
165 /* I/O to channel is blocked */
166 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
168 /* PCI card is dead */
169 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
172 typedef unsigned int __bitwise pcie_reset_state_t;
174 enum pcie_reset_state {
175 /* Reset is NOT asserted (Use to deassert reset) */
176 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
178 /* Use #PERST to reset PCIe device */
179 pcie_warm_reset = (__force pcie_reset_state_t) 2,
181 /* Use PCIe Hot Reset to reset device */
182 pcie_hot_reset = (__force pcie_reset_state_t) 3
185 typedef unsigned short __bitwise pci_dev_flags_t;
187 /* INTX_DISABLE in PCI_COMMAND register disables MSI
190 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
191 /* Device configuration is irrevocably lost if disabled into D3 */
192 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
193 /* Provide indication device is assigned by a Virtual Machine Manager */
194 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
195 /* Flag for quirk use to store if quirk-specific ACS is enabled */
196 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
197 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
198 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
199 /* Do not use bus resets for device */
200 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
201 /* Do not use PM reset even if device advertises NoSoftRst- */
202 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
203 /* Get VPD from function 0 VPD */
204 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
205 /* a non-root bridge where translation occurs, stop alias search here */
206 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
207 /* Do not use FLR even if device advertises PCI_AF_CAP */
208 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
210 * Resume before calling the driver's system suspend hooks, disabling
211 * the direct_complete optimization.
213 PCI_DEV_FLAGS_NEEDS_RESUME = (__force pci_dev_flags_t) (1 << 11),
214 /* Don't use Relaxed Ordering for TLPs directed at this device */
215 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 12),
218 enum pci_irq_reroute_variant {
219 INTEL_IRQ_REROUTE_VARIANT = 1,
220 MAX_IRQ_REROUTE_VARIANTS = 3
223 typedef unsigned short __bitwise pci_bus_flags_t;
225 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
226 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
227 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
230 /* These values come from the PCI Express Spec */
231 enum pcie_link_width {
232 PCIE_LNK_WIDTH_RESRV = 0x00,
240 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
243 /* Based on the PCI Hotplug Spec, but some values are made up by us */
245 PCI_SPEED_33MHz = 0x00,
246 PCI_SPEED_66MHz = 0x01,
247 PCI_SPEED_66MHz_PCIX = 0x02,
248 PCI_SPEED_100MHz_PCIX = 0x03,
249 PCI_SPEED_133MHz_PCIX = 0x04,
250 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
251 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
252 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
253 PCI_SPEED_66MHz_PCIX_266 = 0x09,
254 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
255 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
261 PCI_SPEED_66MHz_PCIX_533 = 0x11,
262 PCI_SPEED_100MHz_PCIX_533 = 0x12,
263 PCI_SPEED_133MHz_PCIX_533 = 0x13,
264 PCIE_SPEED_2_5GT = 0x14,
265 PCIE_SPEED_5_0GT = 0x15,
266 PCIE_SPEED_8_0GT = 0x16,
267 PCI_SPEED_UNKNOWN = 0xff,
270 struct pci_cap_saved_data {
277 struct pci_cap_saved_state {
278 struct hlist_node next;
279 struct pci_cap_saved_data cap;
283 struct pcie_link_state;
289 * The pci_dev structure is used to describe PCI devices.
292 struct list_head bus_list; /* node in per-bus list */
293 struct pci_bus *bus; /* bus this device is on */
294 struct pci_bus *subordinate; /* bus this device bridges to */
296 void *sysdata; /* hook for sys-specific extension */
297 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
298 struct pci_slot *slot; /* Physical slot this device is in */
300 unsigned int devfn; /* encoded device & function index */
301 unsigned short vendor;
302 unsigned short device;
303 unsigned short subsystem_vendor;
304 unsigned short subsystem_device;
305 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
306 u8 revision; /* PCI revision, low byte of class word */
307 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
308 #ifdef CONFIG_PCIEAER
309 u16 aer_cap; /* AER capability offset */
311 u8 pcie_cap; /* PCIe capability offset */
312 u8 msi_cap; /* MSI capability offset */
313 u8 msix_cap; /* MSI-X capability offset */
314 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
315 u8 rom_base_reg; /* which config register controls the ROM */
316 u8 pin; /* which interrupt pin this device uses */
317 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
318 unsigned long *dma_alias_mask;/* mask of enabled devfn aliases */
320 struct pci_driver *driver; /* which driver has allocated this device */
321 u64 dma_mask; /* Mask of the bits of bus address this
322 device implements. Normally this is
323 0xffffffff. You only need to change
324 this if your device has broken DMA
325 or supports 64-bit transfers. */
327 struct device_dma_parameters dma_parms;
329 pci_power_t current_state; /* Current operating state. In ACPI-speak,
330 this is D0-D3, D0 being fully functional,
332 u8 pm_cap; /* PM capability offset */
333 unsigned int pme_support:5; /* Bitmask of states from which PME#
335 unsigned int pme_poll:1; /* Poll device's PME status bit */
336 unsigned int d1_support:1; /* Low power state D1 is supported */
337 unsigned int d2_support:1; /* Low power state D2 is supported */
338 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
339 unsigned int no_d3cold:1; /* D3cold is forbidden */
340 unsigned int bridge_d3:1; /* Allow D3 for bridge */
341 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
342 unsigned int mmio_always_on:1; /* disallow turning off io/mem
343 decoding during bar sizing */
344 unsigned int wakeup_prepared:1;
345 unsigned int runtime_d3cold:1; /* whether go through runtime
346 D3cold, not set for devices
347 powered on/off by the
348 corresponding bridge */
349 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
350 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
351 controlled exclusively by
353 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
355 unsigned int d3_delay; /* D3->D0 transition time in ms */
356 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
358 #ifdef CONFIG_PCIEASPM
359 struct pcie_link_state *link_state; /* ASPM link state */
362 pci_channel_state_t error_state; /* current connectivity state */
363 struct device dev; /* Generic device interface */
365 int cfg_size; /* Size of configuration space */
368 * Instead of touching interrupt line and base address registers
369 * directly, use the values stored here. They might be different!
372 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
374 bool match_driver; /* Skip attaching driver */
375 /* These fields are used by common fixups */
376 unsigned int transparent:1; /* Subtractive decode PCI bridge */
377 unsigned int multifunction:1;/* Part of multi-function device */
378 /* keep track of device state */
379 unsigned int is_added:1;
380 unsigned int is_busmaster:1; /* device is busmaster */
381 unsigned int no_msi:1; /* device may not use msi */
382 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */
383 unsigned int block_cfg_access:1; /* config space access is blocked */
384 unsigned int broken_parity_status:1; /* Device generates false positive parity */
385 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
386 unsigned int msi_enabled:1;
387 unsigned int msix_enabled:1;
388 unsigned int ari_enabled:1; /* ARI forwarding */
389 unsigned int ats_enabled:1; /* Address Translation Service */
390 unsigned int pasid_enabled:1; /* Process Address Space ID */
391 unsigned int pri_enabled:1; /* Page Request Interface */
392 unsigned int is_managed:1;
393 unsigned int needs_freset:1; /* Dev requires fundamental reset */
394 unsigned int state_saved:1;
395 unsigned int is_physfn:1;
396 unsigned int is_virtfn:1;
397 unsigned int reset_fn:1;
398 unsigned int is_hotplug_bridge:1;
399 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
400 unsigned int __aer_firmware_first_valid:1;
401 unsigned int __aer_firmware_first:1;
402 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
403 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
404 unsigned int irq_managed:1;
405 unsigned int has_secondary_link:1;
406 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */
407 unsigned int is_probed:1; /* device probing in progress */
408 pci_dev_flags_t dev_flags;
409 atomic_t enable_cnt; /* pci_enable_device has been called */
411 u32 saved_config_space[16]; /* config space saved at suspend time */
412 struct hlist_head saved_cap_space;
413 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
414 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
415 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
416 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
418 #ifdef CONFIG_PCIE_PTM
419 unsigned int ptm_root:1;
420 unsigned int ptm_enabled:1;
423 #ifdef CONFIG_PCI_MSI
424 const struct attribute_group **msi_irq_groups;
427 #ifdef CONFIG_PCI_ATS
429 struct pci_sriov *sriov; /* SR-IOV capability related */
430 struct pci_dev *physfn; /* the PF this VF is associated with */
432 u16 ats_cap; /* ATS Capability offset */
433 u8 ats_stu; /* ATS Smallest Translation Unit */
434 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */
436 #ifdef CONFIG_PCI_PRI
437 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
439 #ifdef CONFIG_PCI_PASID
442 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
443 size_t romlen; /* Length of ROM if it's not from the BAR */
444 char *driver_override; /* Driver name to force a match */
446 unsigned long priv_flags; /* Private flags for the pci driver */
449 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
451 #ifdef CONFIG_PCI_IOV
458 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
460 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
461 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
463 static inline int pci_channel_offline(struct pci_dev *pdev)
465 return (pdev->error_state != pci_channel_io_normal);
468 struct pci_host_bridge {
470 struct pci_bus *bus; /* root bus */
474 struct list_head windows; /* resource_entry */
475 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* platform IRQ swizzler */
476 int (*map_irq)(const struct pci_dev *, u8, u8);
477 void (*release_fn)(struct pci_host_bridge *);
479 struct msi_controller *msi;
480 unsigned int ignore_reset_delay:1; /* for entire hierarchy */
481 unsigned int no_ext_tags:1; /* no Extended Tags */
482 /* Resource alignment requirements */
483 resource_size_t (*align_resource)(struct pci_dev *dev,
484 const struct resource *res,
485 resource_size_t start,
486 resource_size_t size,
487 resource_size_t align);
488 unsigned long private[0] ____cacheline_aligned;
491 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
493 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
495 return (void *)bridge->private;
498 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
500 return container_of(priv, struct pci_host_bridge, private);
503 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
504 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
506 void pci_free_host_bridge(struct pci_host_bridge *bridge);
507 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
509 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
510 void (*release_fn)(struct pci_host_bridge *),
513 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
516 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
517 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
518 * buses below host bridges or subtractive decode bridges) go in the list.
519 * Use pci_bus_for_each_resource() to iterate through all the resources.
523 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
524 * and there's no way to program the bridge with the details of the window.
525 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
526 * decode bit set, because they are explicit and can be programmed with _SRS.
528 #define PCI_SUBTRACTIVE_DECODE 0x1
530 struct pci_bus_resource {
531 struct list_head list;
532 struct resource *res;
536 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
539 struct list_head node; /* node in list of buses */
540 struct pci_bus *parent; /* parent bus this bridge is on */
541 struct list_head children; /* list of child buses */
542 struct list_head devices; /* list of devices on this bus */
543 struct pci_dev *self; /* bridge device as seen by parent */
544 struct list_head slots; /* list of slots on this bus;
545 protected by pci_slot_mutex */
546 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
547 struct list_head resources; /* address space routed to this bus */
548 struct resource busn_res; /* bus numbers routed to this bus */
550 struct pci_ops *ops; /* configuration access functions */
551 struct msi_controller *msi; /* MSI controller */
552 void *sysdata; /* hook for sys-specific extension */
553 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
555 unsigned char number; /* bus number */
556 unsigned char primary; /* number of primary bridge */
557 unsigned char max_bus_speed; /* enum pci_bus_speed */
558 unsigned char cur_bus_speed; /* enum pci_bus_speed */
559 #ifdef CONFIG_PCI_DOMAINS_GENERIC
565 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
566 pci_bus_flags_t bus_flags; /* inherited by child buses */
567 struct device *bridge;
569 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
570 struct bin_attribute *legacy_mem; /* legacy mem */
571 unsigned int is_added:1;
574 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
577 * Returns true if the PCI bus is root (behind host-PCI bridge),
580 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
581 * This is incorrect because "virtual" buses added for SR-IOV (via
582 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
584 static inline bool pci_is_root_bus(struct pci_bus *pbus)
586 return !(pbus->parent);
590 * pci_is_bridge - check if the PCI device is a bridge
593 * Return true if the PCI device is bridge whether it has subordinate
596 static inline bool pci_is_bridge(struct pci_dev *dev)
598 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
599 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
602 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
604 dev = pci_physfn(dev);
605 if (pci_is_root_bus(dev->bus))
608 return dev->bus->self;
611 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
612 void pci_put_host_bridge_device(struct device *dev);
614 #ifdef CONFIG_PCI_MSI
615 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
617 return pci_dev->msi_enabled || pci_dev->msix_enabled;
620 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
624 * Error values that may be returned by PCI functions.
626 #define PCIBIOS_SUCCESSFUL 0x00
627 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
628 #define PCIBIOS_BAD_VENDOR_ID 0x83
629 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
630 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
631 #define PCIBIOS_SET_FAILED 0x88
632 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
635 * Translate above to generic errno for passing back through non-PCI code.
637 static inline int pcibios_err_to_errno(int err)
639 if (err <= PCIBIOS_SUCCESSFUL)
640 return err; /* Assume already errno */
643 case PCIBIOS_FUNC_NOT_SUPPORTED:
645 case PCIBIOS_BAD_VENDOR_ID:
647 case PCIBIOS_DEVICE_NOT_FOUND:
649 case PCIBIOS_BAD_REGISTER_NUMBER:
651 case PCIBIOS_SET_FAILED:
653 case PCIBIOS_BUFFER_TOO_SMALL:
660 /* Low-level architecture-dependent routines */
663 int (*add_bus)(struct pci_bus *bus);
664 void (*remove_bus)(struct pci_bus *bus);
665 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
666 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
667 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
671 * ACPI needs to be able to access PCI config space before we've done a
672 * PCI bus scan and created pci_bus structures.
674 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
675 int reg, int len, u32 *val);
676 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
677 int reg, int len, u32 val);
679 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
680 typedef u64 pci_bus_addr_t;
682 typedef u32 pci_bus_addr_t;
685 struct pci_bus_region {
686 pci_bus_addr_t start;
691 spinlock_t lock; /* protects list, index */
692 struct list_head list; /* for IDs added at runtime */
697 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
698 * a set of callbacks in struct pci_error_handlers, that device driver
699 * will be notified of PCI bus errors, and will be driven to recovery
700 * when an error occurs.
703 typedef unsigned int __bitwise pci_ers_result_t;
705 enum pci_ers_result {
706 /* no result/none/not supported in device driver */
707 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
709 /* Device driver can recover without slot reset */
710 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
712 /* Device driver wants slot to be reset. */
713 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
715 /* Device has completely failed, is unrecoverable */
716 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
718 /* Device driver is fully recovered and operational */
719 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
721 /* No AER capabilities registered for the driver */
722 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
725 /* PCI bus error event callbacks */
726 struct pci_error_handlers {
727 /* PCI bus error detected on this device */
728 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
729 enum pci_channel_state error);
731 /* MMIO has been re-enabled, but not DMA */
732 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
734 /* PCI slot has been reset */
735 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
737 /* PCI function reset prepare or completed */
738 void (*reset_prepare)(struct pci_dev *dev);
739 void (*reset_done)(struct pci_dev *dev);
741 /* Device driver may resume normal operations */
742 void (*resume)(struct pci_dev *dev);
748 struct list_head node;
750 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
751 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
752 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
753 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
754 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
755 int (*resume_early) (struct pci_dev *dev);
756 int (*resume) (struct pci_dev *dev); /* Device woken up */
757 void (*shutdown) (struct pci_dev *dev);
758 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
759 const struct pci_error_handlers *err_handler;
760 const struct attribute_group **groups;
761 struct device_driver driver;
762 struct pci_dynids dynids;
765 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
768 * PCI_DEVICE - macro used to describe a specific pci device
769 * @vend: the 16 bit PCI Vendor ID
770 * @dev: the 16 bit PCI Device ID
772 * This macro is used to create a struct pci_device_id that matches a
773 * specific device. The subvendor and subdevice fields will be set to
776 #define PCI_DEVICE(vend,dev) \
777 .vendor = (vend), .device = (dev), \
778 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
781 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
782 * @vend: the 16 bit PCI Vendor ID
783 * @dev: the 16 bit PCI Device ID
784 * @subvend: the 16 bit PCI Subvendor ID
785 * @subdev: the 16 bit PCI Subdevice ID
787 * This macro is used to create a struct pci_device_id that matches a
788 * specific device with subsystem information.
790 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
791 .vendor = (vend), .device = (dev), \
792 .subvendor = (subvend), .subdevice = (subdev)
795 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
796 * @dev_class: the class, subclass, prog-if triple for this device
797 * @dev_class_mask: the class mask for this device
799 * This macro is used to create a struct pci_device_id that matches a
800 * specific PCI class. The vendor, device, subvendor, and subdevice
801 * fields will be set to PCI_ANY_ID.
803 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
804 .class = (dev_class), .class_mask = (dev_class_mask), \
805 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
806 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
809 * PCI_VDEVICE - macro used to describe a specific pci device in short form
810 * @vend: the vendor name
811 * @dev: the 16 bit PCI Device ID
813 * This macro is used to create a struct pci_device_id that matches a
814 * specific PCI device. The subvendor, and subdevice fields will be set
815 * to PCI_ANY_ID. The macro allows the next field to follow as the device
819 #define PCI_VDEVICE(vend, dev) \
820 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
821 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
824 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */
825 PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */
826 PCI_PROBE_ONLY = 0x00000004, /* use existing setup */
827 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */
828 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */
829 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
830 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */
833 /* these external functions are only available when PCI support is enabled */
836 extern unsigned int pci_flags;
838 static inline void pci_set_flags(int flags) { pci_flags = flags; }
839 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
840 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
841 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
843 void pcie_bus_configure_settings(struct pci_bus *bus);
845 enum pcie_bus_config_types {
846 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */
847 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */
848 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */
849 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */
850 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */
853 extern enum pcie_bus_config_types pcie_bus_config;
855 extern struct bus_type pci_bus_type;
857 /* Do NOT directly access these two variables, unless you are arch-specific PCI
858 * code, or PCI core code. */
859 extern struct list_head pci_root_buses; /* list of all known PCI buses */
860 /* Some device drivers need know if PCI is initiated */
861 int no_pci_devices(void);
863 void pcibios_resource_survey_bus(struct pci_bus *bus);
864 void pcibios_bus_add_device(struct pci_dev *pdev);
865 void pcibios_add_bus(struct pci_bus *bus);
866 void pcibios_remove_bus(struct pci_bus *bus);
867 void pcibios_fixup_bus(struct pci_bus *);
868 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
869 /* Architecture-specific versions may override this (weak) */
870 char *pcibios_setup(char *str);
872 /* Used only when drivers/pci/setup.c is used */
873 resource_size_t pcibios_align_resource(void *, const struct resource *,
877 /* Weak but can be overriden by arch */
878 void pci_fixup_cardbus(struct pci_bus *);
880 /* Generic PCI functions used internally */
882 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
883 struct resource *res);
884 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
885 struct pci_bus_region *region);
886 void pcibios_scan_specific_bus(int busn);
887 struct pci_bus *pci_find_bus(int domain, int busnr);
888 void pci_bus_add_devices(const struct pci_bus *bus);
889 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
890 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
891 struct pci_ops *ops, void *sysdata,
892 struct list_head *resources);
893 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
894 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
895 void pci_bus_release_busn_res(struct pci_bus *b);
896 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
897 struct pci_ops *ops, void *sysdata,
898 struct list_head *resources);
899 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
900 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
902 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
903 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
905 struct hotplug_slot *hotplug);
906 void pci_destroy_slot(struct pci_slot *slot);
908 void pci_dev_assign_slot(struct pci_dev *dev);
910 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
912 int pci_scan_slot(struct pci_bus *bus, int devfn);
913 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
914 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
915 unsigned int pci_scan_child_bus(struct pci_bus *bus);
916 void pci_bus_add_device(struct pci_dev *dev);
917 void pci_read_bridge_bases(struct pci_bus *child);
918 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
919 struct resource *res);
920 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
921 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
922 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
923 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
924 struct pci_dev *pci_dev_get(struct pci_dev *dev);
925 void pci_dev_put(struct pci_dev *dev);
926 void pci_remove_bus(struct pci_bus *b);
927 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
928 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
929 void pci_stop_root_bus(struct pci_bus *bus);
930 void pci_remove_root_bus(struct pci_bus *bus);
931 void pci_setup_cardbus(struct pci_bus *bus);
932 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
933 void pci_sort_breadthfirst(void);
934 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
935 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
937 /* Generic PCI functions exported to card drivers */
939 enum pci_lost_interrupt_reason {
940 PCI_LOST_IRQ_NO_INFORMATION = 0,
941 PCI_LOST_IRQ_DISABLE_MSI,
942 PCI_LOST_IRQ_DISABLE_MSIX,
943 PCI_LOST_IRQ_DISABLE_ACPI,
945 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
946 int pci_find_capability(struct pci_dev *dev, int cap);
947 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
948 int pci_find_ext_capability(struct pci_dev *dev, int cap);
949 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
950 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
951 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
952 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
954 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
955 struct pci_dev *from);
956 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
957 unsigned int ss_vendor, unsigned int ss_device,
958 struct pci_dev *from);
959 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
960 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
962 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
965 return pci_get_domain_bus_and_slot(0, bus, devfn);
967 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
968 int pci_dev_present(const struct pci_device_id *ids);
970 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
972 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
973 int where, u16 *val);
974 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
975 int where, u32 *val);
976 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
978 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
980 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
983 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
984 int where, int size, u32 *val);
985 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
986 int where, int size, u32 val);
987 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
988 int where, int size, u32 *val);
989 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
990 int where, int size, u32 val);
992 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
994 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
995 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
996 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
997 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
998 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
999 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1001 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1002 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1003 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1004 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1005 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1006 u16 clear, u16 set);
1007 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1008 u32 clear, u32 set);
1010 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1013 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1016 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1019 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1022 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1025 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1028 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1031 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1034 /* user-space driven config access */
1035 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1036 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1037 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1038 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1039 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1040 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1042 int __must_check pci_enable_device(struct pci_dev *dev);
1043 int __must_check pci_enable_device_io(struct pci_dev *dev);
1044 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1045 int __must_check pci_reenable_device(struct pci_dev *);
1046 int __must_check pcim_enable_device(struct pci_dev *pdev);
1047 void pcim_pin_device(struct pci_dev *pdev);
1049 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1052 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1053 * writable and no quirk has marked the feature broken.
1055 return !pdev->broken_intx_masking;
1058 static inline int pci_is_enabled(struct pci_dev *pdev)
1060 return (atomic_read(&pdev->enable_cnt) > 0);
1063 static inline int pci_is_managed(struct pci_dev *pdev)
1065 return pdev->is_managed;
1068 void pci_disable_device(struct pci_dev *dev);
1070 extern unsigned int pcibios_max_latency;
1071 void pci_set_master(struct pci_dev *dev);
1072 void pci_clear_master(struct pci_dev *dev);
1074 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1075 int pci_set_cacheline_size(struct pci_dev *dev);
1076 #define HAVE_PCI_SET_MWI
1077 int __must_check pci_set_mwi(struct pci_dev *dev);
1078 int pci_try_set_mwi(struct pci_dev *dev);
1079 void pci_clear_mwi(struct pci_dev *dev);
1080 void pci_intx(struct pci_dev *dev, int enable);
1081 bool pci_check_and_mask_intx(struct pci_dev *dev);
1082 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1083 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1084 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1085 int pcix_get_max_mmrbc(struct pci_dev *dev);
1086 int pcix_get_mmrbc(struct pci_dev *dev);
1087 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1088 int pcie_get_readrq(struct pci_dev *dev);
1089 int pcie_set_readrq(struct pci_dev *dev, int rq);
1090 int pcie_get_mps(struct pci_dev *dev);
1091 int pcie_set_mps(struct pci_dev *dev, int mps);
1092 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1093 enum pcie_link_width *width);
1094 void pcie_flr(struct pci_dev *dev);
1095 int __pci_reset_function(struct pci_dev *dev);
1096 int __pci_reset_function_locked(struct pci_dev *dev);
1097 int pci_reset_function(struct pci_dev *dev);
1098 int pci_reset_function_locked(struct pci_dev *dev);
1099 int pci_try_reset_function(struct pci_dev *dev);
1100 int pci_probe_reset_slot(struct pci_slot *slot);
1101 int pci_reset_slot(struct pci_slot *slot);
1102 int pci_try_reset_slot(struct pci_slot *slot);
1103 int pci_probe_reset_bus(struct pci_bus *bus);
1104 int pci_reset_bus(struct pci_bus *bus);
1105 int pci_try_reset_bus(struct pci_bus *bus);
1106 void pci_reset_secondary_bus(struct pci_dev *dev);
1107 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1108 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1109 void pci_update_resource(struct pci_dev *dev, int resno);
1110 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1111 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1112 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1113 bool pci_device_is_present(struct pci_dev *pdev);
1114 void pci_ignore_hotplug(struct pci_dev *dev);
1116 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1117 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1118 const char *fmt, ...);
1119 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1121 /* ROM control related routines */
1122 int pci_enable_rom(struct pci_dev *pdev);
1123 void pci_disable_rom(struct pci_dev *pdev);
1124 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1125 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1126 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1127 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1129 /* Power management related routines */
1130 int pci_save_state(struct pci_dev *dev);
1131 void pci_restore_state(struct pci_dev *dev);
1132 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1133 int pci_load_saved_state(struct pci_dev *dev,
1134 struct pci_saved_state *state);
1135 int pci_load_and_free_saved_state(struct pci_dev *dev,
1136 struct pci_saved_state **state);
1137 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1138 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1140 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1141 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1142 u16 cap, unsigned int size);
1143 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1144 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1145 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1146 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1147 void pci_pme_active(struct pci_dev *dev, bool enable);
1148 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1149 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1150 int pci_prepare_to_sleep(struct pci_dev *dev);
1151 int pci_back_from_sleep(struct pci_dev *dev);
1152 bool pci_dev_run_wake(struct pci_dev *dev);
1153 bool pci_check_pme_status(struct pci_dev *dev);
1154 void pci_pme_wakeup_bus(struct pci_bus *bus);
1155 void pci_d3cold_enable(struct pci_dev *dev);
1156 void pci_d3cold_disable(struct pci_dev *dev);
1157 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1159 /* PCI Virtual Channel */
1160 int pci_save_vc_state(struct pci_dev *dev);
1161 void pci_restore_vc_state(struct pci_dev *dev);
1162 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1164 /* For use by arch with custom probe code */
1165 void set_pcie_port_type(struct pci_dev *pdev);
1166 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1168 /* Functions for PCI Hotplug drivers to use */
1169 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1170 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1171 unsigned int pci_rescan_bus(struct pci_bus *bus);
1172 void pci_lock_rescan_remove(void);
1173 void pci_unlock_rescan_remove(void);
1175 /* Vital product data routines */
1176 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1177 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1178 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1180 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1181 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1182 void pci_bus_assign_resources(const struct pci_bus *bus);
1183 void pci_bus_claim_resources(struct pci_bus *bus);
1184 void pci_bus_size_bridges(struct pci_bus *bus);
1185 int pci_claim_resource(struct pci_dev *, int);
1186 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1187 void pci_assign_unassigned_resources(void);
1188 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1189 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1190 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1191 void pdev_enable_device(struct pci_dev *);
1192 int pci_enable_resources(struct pci_dev *, int mask);
1193 void pci_assign_irq(struct pci_dev *dev);
1194 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1195 #define HAVE_PCI_REQ_REGIONS 2
1196 int __must_check pci_request_regions(struct pci_dev *, const char *);
1197 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1198 void pci_release_regions(struct pci_dev *);
1199 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1200 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1201 void pci_release_region(struct pci_dev *, int);
1202 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1203 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1204 void pci_release_selected_regions(struct pci_dev *, int);
1206 /* drivers/pci/bus.c */
1207 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1208 void pci_bus_put(struct pci_bus *bus);
1209 void pci_add_resource(struct list_head *resources, struct resource *res);
1210 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1211 resource_size_t offset);
1212 void pci_free_resource_list(struct list_head *resources);
1213 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1214 unsigned int flags);
1215 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1216 void pci_bus_remove_resources(struct pci_bus *bus);
1217 int devm_request_pci_bus_resources(struct device *dev,
1218 struct list_head *resources);
1220 #define pci_bus_for_each_resource(bus, res, i) \
1222 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1225 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1226 struct resource *res, resource_size_t size,
1227 resource_size_t align, resource_size_t min,
1228 unsigned long type_mask,
1229 resource_size_t (*alignf)(void *,
1230 const struct resource *,
1236 int pci_register_io_range(phys_addr_t addr, resource_size_t size);
1237 unsigned long pci_address_to_pio(phys_addr_t addr);
1238 phys_addr_t pci_pio_to_address(unsigned long pio);
1239 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1240 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1241 phys_addr_t phys_addr);
1242 void pci_unmap_iospace(struct resource *res);
1243 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1244 resource_size_t offset,
1245 resource_size_t size);
1246 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1247 struct resource *res);
1249 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1251 struct pci_bus_region region;
1253 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1254 return region.start;
1257 /* Proper probing supporting hot-pluggable devices */
1258 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1259 const char *mod_name);
1262 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1264 #define pci_register_driver(driver) \
1265 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1267 void pci_unregister_driver(struct pci_driver *dev);
1270 * module_pci_driver() - Helper macro for registering a PCI driver
1271 * @__pci_driver: pci_driver struct
1273 * Helper macro for PCI drivers which do not do anything special in module
1274 * init/exit. This eliminates a lot of boilerplate. Each module may only
1275 * use this macro once, and calling it replaces module_init() and module_exit()
1277 #define module_pci_driver(__pci_driver) \
1278 module_driver(__pci_driver, pci_register_driver, \
1279 pci_unregister_driver)
1282 * builtin_pci_driver() - Helper macro for registering a PCI driver
1283 * @__pci_driver: pci_driver struct
1285 * Helper macro for PCI drivers which do not do anything special in their
1286 * init code. This eliminates a lot of boilerplate. Each driver may only
1287 * use this macro once, and calling it replaces device_initcall(...)
1289 #define builtin_pci_driver(__pci_driver) \
1290 builtin_driver(__pci_driver, pci_register_driver)
1292 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1293 int pci_add_dynid(struct pci_driver *drv,
1294 unsigned int vendor, unsigned int device,
1295 unsigned int subvendor, unsigned int subdevice,
1296 unsigned int class, unsigned int class_mask,
1297 unsigned long driver_data);
1298 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1299 struct pci_dev *dev);
1300 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1303 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1305 int pci_cfg_space_size(struct pci_dev *dev);
1306 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1307 void pci_setup_bridge(struct pci_bus *bus);
1308 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1309 unsigned long type);
1310 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1312 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1313 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1315 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1316 unsigned int command_bits, u32 flags);
1318 #define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */
1319 #define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */
1320 #define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */
1321 #define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */
1322 #define PCI_IRQ_ALL_TYPES \
1323 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1325 /* kmem_cache style wrapper around pci_alloc_consistent() */
1327 #include <linux/pci-dma.h>
1328 #include <linux/dmapool.h>
1330 #define pci_pool dma_pool
1331 #define pci_pool_create(name, pdev, size, align, allocation) \
1332 dma_pool_create(name, &pdev->dev, size, align, allocation)
1333 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1334 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1335 #define pci_pool_zalloc(pool, flags, handle) \
1336 dma_pool_zalloc(pool, flags, handle)
1337 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1340 u32 vector; /* kernel uses to write allocated vector */
1341 u16 entry; /* driver uses to specify entry, OS writes */
1344 #ifdef CONFIG_PCI_MSI
1345 int pci_msi_vec_count(struct pci_dev *dev);
1346 void pci_disable_msi(struct pci_dev *dev);
1347 int pci_msix_vec_count(struct pci_dev *dev);
1348 void pci_disable_msix(struct pci_dev *dev);
1349 void pci_restore_msi_state(struct pci_dev *dev);
1350 int pci_msi_enabled(void);
1351 int pci_enable_msi(struct pci_dev *dev);
1352 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1353 int minvec, int maxvec);
1354 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1355 struct msix_entry *entries, int nvec)
1357 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1362 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1363 unsigned int max_vecs, unsigned int flags,
1364 const struct irq_affinity *affd);
1366 void pci_free_irq_vectors(struct pci_dev *dev);
1367 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1368 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1369 int pci_irq_get_node(struct pci_dev *pdev, int vec);
1372 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1373 static inline void pci_disable_msi(struct pci_dev *dev) { }
1374 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1375 static inline void pci_disable_msix(struct pci_dev *dev) { }
1376 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1377 static inline int pci_msi_enabled(void) { return 0; }
1378 static inline int pci_enable_msi(struct pci_dev *dev)
1380 static inline int pci_enable_msix_range(struct pci_dev *dev,
1381 struct msix_entry *entries, int minvec, int maxvec)
1383 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1384 struct msix_entry *entries, int nvec)
1388 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1389 unsigned int max_vecs, unsigned int flags,
1390 const struct irq_affinity *aff_desc)
1392 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1397 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1401 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1403 if (WARN_ON_ONCE(nr > 0))
1407 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1410 return cpu_possible_mask;
1413 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1415 return first_online_node;
1420 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1421 unsigned int max_vecs, unsigned int flags)
1423 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1428 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1429 * @d: the INTx IRQ domain
1430 * @node: the DT node for the device whose interrupt we're translating
1431 * @intspec: the interrupt specifier data from the DT
1432 * @intsize: the number of entries in @intspec
1433 * @out_hwirq: pointer at which to write the hwirq number
1434 * @out_type: pointer at which to write the interrupt type
1436 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1437 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1438 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1439 * INTx value to obtain the hwirq number.
1441 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1443 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1444 struct device_node *node,
1446 unsigned int intsize,
1447 unsigned long *out_hwirq,
1448 unsigned int *out_type)
1450 const u32 intx = intspec[0];
1452 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1455 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1459 #ifdef CONFIG_PCIEPORTBUS
1460 extern bool pcie_ports_disabled;
1461 extern bool pcie_ports_auto;
1463 #define pcie_ports_disabled true
1464 #define pcie_ports_auto false
1467 #ifdef CONFIG_PCIEASPM
1468 bool pcie_aspm_support_enabled(void);
1470 static inline bool pcie_aspm_support_enabled(void) { return false; }
1473 #ifdef CONFIG_PCIEAER
1474 void pci_no_aer(void);
1475 bool pci_aer_available(void);
1476 int pci_aer_init(struct pci_dev *dev);
1478 static inline void pci_no_aer(void) { }
1479 static inline bool pci_aer_available(void) { return false; }
1480 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
1483 #ifdef CONFIG_PCIE_ECRC
1484 void pcie_set_ecrc_checking(struct pci_dev *dev);
1485 void pcie_ecrc_get_policy(char *str);
1487 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1488 static inline void pcie_ecrc_get_policy(char *str) { }
1491 #ifdef CONFIG_HT_IRQ
1492 /* The functions a driver should call */
1493 int ht_create_irq(struct pci_dev *dev, int idx);
1494 void ht_destroy_irq(unsigned int irq);
1495 #endif /* CONFIG_HT_IRQ */
1497 #ifdef CONFIG_PCI_ATS
1498 /* Address Translation Service */
1499 void pci_ats_init(struct pci_dev *dev);
1500 int pci_enable_ats(struct pci_dev *dev, int ps);
1501 void pci_disable_ats(struct pci_dev *dev);
1502 int pci_ats_queue_depth(struct pci_dev *dev);
1504 static inline void pci_ats_init(struct pci_dev *d) { }
1505 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1506 static inline void pci_disable_ats(struct pci_dev *d) { }
1507 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1510 #ifdef CONFIG_PCIE_PTM
1511 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1513 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1517 void pci_cfg_access_lock(struct pci_dev *dev);
1518 bool pci_cfg_access_trylock(struct pci_dev *dev);
1519 void pci_cfg_access_unlock(struct pci_dev *dev);
1522 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1523 * a PCI domain is defined to be a set of PCI buses which share
1524 * configuration space.
1526 #ifdef CONFIG_PCI_DOMAINS
1527 extern int pci_domains_supported;
1528 int pci_get_new_domain_nr(void);
1530 enum { pci_domains_supported = 0 };
1531 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1532 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1533 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1534 #endif /* CONFIG_PCI_DOMAINS */
1537 * Generic implementation for PCI domain support. If your
1538 * architecture does not need custom management of PCI
1539 * domains then this implementation will be used
1541 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1542 static inline int pci_domain_nr(struct pci_bus *bus)
1544 return bus->domain_nr;
1547 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1549 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1552 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1555 /* some architectures require additional setup to direct VGA traffic */
1556 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1557 unsigned int command_bits, u32 flags);
1558 void pci_register_set_vga_state(arch_set_vga_state_t func);
1561 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1563 return pci_request_selected_regions(pdev,
1564 pci_select_bars(pdev, IORESOURCE_IO), name);
1568 pci_release_io_regions(struct pci_dev *pdev)
1570 return pci_release_selected_regions(pdev,
1571 pci_select_bars(pdev, IORESOURCE_IO));
1575 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1577 return pci_request_selected_regions(pdev,
1578 pci_select_bars(pdev, IORESOURCE_MEM), name);
1582 pci_release_mem_regions(struct pci_dev *pdev)
1584 return pci_release_selected_regions(pdev,
1585 pci_select_bars(pdev, IORESOURCE_MEM));
1588 #else /* CONFIG_PCI is not enabled */
1590 static inline void pci_set_flags(int flags) { }
1591 static inline void pci_add_flags(int flags) { }
1592 static inline void pci_clear_flags(int flags) { }
1593 static inline int pci_has_flag(int flag) { return 0; }
1596 * If the system does not have PCI, clearly these return errors. Define
1597 * these as simple inline functions to avoid hair in drivers.
1600 #define _PCI_NOP(o, s, t) \
1601 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1603 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1605 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1606 _PCI_NOP(o, word, u16 x) \
1607 _PCI_NOP(o, dword, u32 x)
1608 _PCI_NOP_ALL(read, *)
1609 _PCI_NOP_ALL(write,)
1611 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1612 unsigned int device,
1613 struct pci_dev *from)
1616 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1617 unsigned int device,
1618 unsigned int ss_vendor,
1619 unsigned int ss_device,
1620 struct pci_dev *from)
1623 static inline struct pci_dev *pci_get_class(unsigned int class,
1624 struct pci_dev *from)
1627 #define pci_dev_present(ids) (0)
1628 #define no_pci_devices() (1)
1629 #define pci_dev_put(dev) do { } while (0)
1631 static inline void pci_set_master(struct pci_dev *dev) { }
1632 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1633 static inline void pci_disable_device(struct pci_dev *dev) { }
1634 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1636 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1637 struct module *owner,
1638 const char *mod_name)
1640 static inline int pci_register_driver(struct pci_driver *drv)
1642 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1643 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1645 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1648 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1651 /* Power management related routines */
1652 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1653 static inline void pci_restore_state(struct pci_dev *dev) { }
1654 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1656 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1658 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1661 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1665 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1666 struct resource *res)
1668 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1670 static inline void pci_release_regions(struct pci_dev *dev) { }
1672 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1674 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1675 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1677 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1679 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1681 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1684 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1688 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1689 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1690 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1692 #define dev_is_pci(d) (false)
1693 #define dev_is_pf(d) (false)
1694 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1696 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1697 struct device_node *node,
1699 unsigned int intsize,
1700 unsigned long *out_hwirq,
1701 unsigned int *out_type)
1703 #endif /* CONFIG_PCI */
1705 /* Include architecture-dependent settings and functions */
1707 #include <asm/pci.h>
1709 /* These two functions provide almost identical functionality. Depennding
1710 * on the architecture, one will be implemented as a wrapper around the
1711 * other (in drivers/pci/mmap.c).
1713 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1714 * is expected to be an offset within that region.
1716 * pci_mmap_page_range() is the legacy architecture-specific interface,
1717 * which accepts a "user visible" resource address converted by
1718 * pci_resource_to_user(), as used in the legacy mmap() interface in
1721 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1722 struct vm_area_struct *vma,
1723 enum pci_mmap_state mmap_state, int write_combine);
1724 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1725 struct vm_area_struct *vma,
1726 enum pci_mmap_state mmap_state, int write_combine);
1728 #ifndef arch_can_pci_mmap_wc
1729 #define arch_can_pci_mmap_wc() 0
1732 #ifndef arch_can_pci_mmap_io
1733 #define arch_can_pci_mmap_io() 0
1734 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1736 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1739 #ifndef pci_root_bus_fwnode
1740 #define pci_root_bus_fwnode(bus) NULL
1743 /* these helpers provide future and backwards compatibility
1744 * for accessing popular PCI BAR info */
1745 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1746 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1747 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1748 #define pci_resource_len(dev,bar) \
1749 ((pci_resource_start((dev), (bar)) == 0 && \
1750 pci_resource_end((dev), (bar)) == \
1751 pci_resource_start((dev), (bar))) ? 0 : \
1753 (pci_resource_end((dev), (bar)) - \
1754 pci_resource_start((dev), (bar)) + 1))
1756 /* Similar to the helpers above, these manipulate per-pci_dev
1757 * driver-specific data. They are really just a wrapper around
1758 * the generic device structure functions of these calls.
1760 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1762 return dev_get_drvdata(&pdev->dev);
1765 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1767 dev_set_drvdata(&pdev->dev, data);
1770 /* If you want to know what to call your pci_dev, ask this function.
1771 * Again, it's a wrapper around the generic device.
1773 static inline const char *pci_name(const struct pci_dev *pdev)
1775 return dev_name(&pdev->dev);
1779 /* Some archs don't want to expose struct resource to userland as-is
1780 * in sysfs and /proc
1782 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1783 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1784 const struct resource *rsrc,
1785 resource_size_t *start, resource_size_t *end);
1787 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1788 const struct resource *rsrc, resource_size_t *start,
1789 resource_size_t *end)
1791 *start = rsrc->start;
1794 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1798 * The world is not perfect and supplies us with broken PCI devices.
1799 * For at least a part of these bugs we need a work-around, so both
1800 * generic (drivers/pci/quirks.c) and per-architecture code can define
1801 * fixup hooks to be called for particular buggy devices.
1805 u16 vendor; /* You can use PCI_ANY_ID here of course */
1806 u16 device; /* You can use PCI_ANY_ID here of course */
1807 u32 class; /* You can use PCI_ANY_ID here too */
1808 unsigned int class_shift; /* should be 0, 8, 16 */
1809 void (*hook)(struct pci_dev *dev);
1812 enum pci_fixup_pass {
1813 pci_fixup_early, /* Before probing BARs */
1814 pci_fixup_header, /* After reading configuration header */
1815 pci_fixup_final, /* Final phase of device fixups */
1816 pci_fixup_enable, /* pci_enable_device() time */
1817 pci_fixup_resume, /* pci_device_resume() */
1818 pci_fixup_suspend, /* pci_device_suspend() */
1819 pci_fixup_resume_early, /* pci_device_resume_early() */
1820 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1823 /* Anonymous variables would be nice... */
1824 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1825 class_shift, hook) \
1826 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1827 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1828 = { vendor, device, class, class_shift, hook };
1830 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1831 class_shift, hook) \
1832 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1833 hook, vendor, device, class, class_shift, hook)
1834 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1835 class_shift, hook) \
1836 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1837 hook, vendor, device, class, class_shift, hook)
1838 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1839 class_shift, hook) \
1840 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1841 hook, vendor, device, class, class_shift, hook)
1842 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1843 class_shift, hook) \
1844 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1845 hook, vendor, device, class, class_shift, hook)
1846 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1847 class_shift, hook) \
1848 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1849 resume##hook, vendor, device, class, \
1851 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1852 class_shift, hook) \
1853 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1854 resume_early##hook, vendor, device, \
1855 class, class_shift, hook)
1856 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1857 class_shift, hook) \
1858 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1859 suspend##hook, vendor, device, class, \
1861 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1862 class_shift, hook) \
1863 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1864 suspend_late##hook, vendor, device, \
1865 class, class_shift, hook)
1867 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1868 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1869 hook, vendor, device, PCI_ANY_ID, 0, hook)
1870 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1871 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1872 hook, vendor, device, PCI_ANY_ID, 0, hook)
1873 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1874 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1875 hook, vendor, device, PCI_ANY_ID, 0, hook)
1876 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1877 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1878 hook, vendor, device, PCI_ANY_ID, 0, hook)
1879 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1880 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1881 resume##hook, vendor, device, \
1882 PCI_ANY_ID, 0, hook)
1883 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1884 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1885 resume_early##hook, vendor, device, \
1886 PCI_ANY_ID, 0, hook)
1887 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1888 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1889 suspend##hook, vendor, device, \
1890 PCI_ANY_ID, 0, hook)
1891 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1892 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1893 suspend_late##hook, vendor, device, \
1894 PCI_ANY_ID, 0, hook)
1896 #ifdef CONFIG_PCI_QUIRKS
1897 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1898 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1899 int pci_dev_specific_enable_acs(struct pci_dev *dev);
1901 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1902 struct pci_dev *dev) { }
1903 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1908 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1914 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1915 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1916 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1917 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1918 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1920 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1922 extern int pci_pci_problems;
1923 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1924 #define PCIPCI_TRITON 2
1925 #define PCIPCI_NATOMA 4
1926 #define PCIPCI_VIAETBF 8
1927 #define PCIPCI_VSFX 16
1928 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1929 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1931 extern unsigned long pci_cardbus_io_size;
1932 extern unsigned long pci_cardbus_mem_size;
1933 extern u8 pci_dfl_cache_line_size;
1934 extern u8 pci_cache_line_size;
1936 extern unsigned long pci_hotplug_io_size;
1937 extern unsigned long pci_hotplug_mem_size;
1938 extern unsigned long pci_hotplug_bus_size;
1940 /* Architecture-specific versions may override these (weak) */
1941 void pcibios_disable_device(struct pci_dev *dev);
1942 void pcibios_set_master(struct pci_dev *dev);
1943 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1944 enum pcie_reset_state state);
1945 int pcibios_add_device(struct pci_dev *dev);
1946 void pcibios_release_device(struct pci_dev *dev);
1947 void pcibios_penalize_isa_irq(int irq, int active);
1948 int pcibios_alloc_irq(struct pci_dev *dev);
1949 void pcibios_free_irq(struct pci_dev *dev);
1951 #ifdef CONFIG_HIBERNATE_CALLBACKS
1952 extern struct dev_pm_ops pcibios_pm_ops;
1955 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1956 void __init pci_mmcfg_early_init(void);
1957 void __init pci_mmcfg_late_init(void);
1959 static inline void pci_mmcfg_early_init(void) { }
1960 static inline void pci_mmcfg_late_init(void) { }
1963 int pci_ext_cfg_avail(void);
1965 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1966 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1968 #ifdef CONFIG_PCI_IOV
1969 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1970 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1972 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1973 void pci_disable_sriov(struct pci_dev *dev);
1974 int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset);
1975 void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset);
1976 int pci_num_vf(struct pci_dev *dev);
1977 int pci_vfs_assigned(struct pci_dev *dev);
1978 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1979 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1980 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1982 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1986 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1990 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1992 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset)
1996 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
1997 int id, int reset) { }
1998 static inline void pci_disable_sriov(struct pci_dev *dev) { }
1999 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2000 static inline int pci_vfs_assigned(struct pci_dev *dev)
2002 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2004 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2006 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2010 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2011 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2012 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2016 * pci_pcie_cap - get the saved PCIe capability offset
2019 * PCIe capability offset is calculated at PCI device initialization
2020 * time and saved in the data structure. This function returns saved
2021 * PCIe capability offset. Using this instead of pci_find_capability()
2022 * reduces unnecessary search in the PCI configuration space. If you
2023 * need to calculate PCIe capability offset from raw device for some
2024 * reasons, please use pci_find_capability() instead.
2026 static inline int pci_pcie_cap(struct pci_dev *dev)
2028 return dev->pcie_cap;
2032 * pci_is_pcie - check if the PCI device is PCI Express capable
2035 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2037 static inline bool pci_is_pcie(struct pci_dev *dev)
2039 return pci_pcie_cap(dev);
2043 * pcie_caps_reg - get the PCIe Capabilities Register
2046 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2048 return dev->pcie_flags_reg;
2052 * pci_pcie_type - get the PCIe device/port type
2055 static inline int pci_pcie_type(const struct pci_dev *dev)
2057 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2060 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2063 if (!pci_is_pcie(dev))
2065 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2067 if (!dev->bus->self)
2069 dev = dev->bus->self;
2074 void pci_request_acs(void);
2075 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2076 bool pci_acs_path_enabled(struct pci_dev *start,
2077 struct pci_dev *end, u16 acs_flags);
2079 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2080 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2082 /* Large Resource Data Type Tag Item Names */
2083 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2084 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2085 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2087 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2088 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2089 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2091 /* Small Resource Data Type Tag Item Names */
2092 #define PCI_VPD_STIN_END 0x0f /* End */
2094 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2096 #define PCI_VPD_SRDT_TIN_MASK 0x78
2097 #define PCI_VPD_SRDT_LEN_MASK 0x07
2098 #define PCI_VPD_LRDT_TIN_MASK 0x7f
2100 #define PCI_VPD_LRDT_TAG_SIZE 3
2101 #define PCI_VPD_SRDT_TAG_SIZE 1
2103 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2105 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2106 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2107 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2108 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2111 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2112 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2114 * Returns the extracted Large Resource Data Type length.
2116 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2118 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2122 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2123 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2125 * Returns the extracted Large Resource Data Type Tag item.
2127 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2129 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2133 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2134 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2136 * Returns the extracted Small Resource Data Type length.
2138 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2140 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2144 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2145 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2147 * Returns the extracted Small Resource Data Type Tag Item.
2149 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2151 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2155 * pci_vpd_info_field_size - Extracts the information field length
2156 * @lrdt: Pointer to the beginning of an information field header
2158 * Returns the extracted information field length.
2160 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2162 return info_field[2];
2166 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2167 * @buf: Pointer to buffered vpd data
2168 * @off: The offset into the buffer at which to begin the search
2169 * @len: The length of the vpd buffer
2170 * @rdt: The Resource Data Type to search for
2172 * Returns the index where the Resource Data Type was found or
2173 * -ENOENT otherwise.
2175 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2178 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2179 * @buf: Pointer to buffered vpd data
2180 * @off: The offset into the buffer at which to begin the search
2181 * @len: The length of the buffer area, relative to off, in which to search
2182 * @kw: The keyword to search for
2184 * Returns the index where the information field keyword was found or
2185 * -ENOENT otherwise.
2187 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2188 unsigned int len, const char *kw);
2190 /* PCI <-> OF binding helpers */
2194 void pci_set_of_node(struct pci_dev *dev);
2195 void pci_release_of_node(struct pci_dev *dev);
2196 void pci_set_bus_of_node(struct pci_bus *bus);
2197 void pci_release_bus_of_node(struct pci_bus *bus);
2198 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2200 /* Arch may override this (weak) */
2201 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2203 static inline struct device_node *
2204 pci_device_to_OF_node(const struct pci_dev *pdev)
2206 return pdev ? pdev->dev.of_node : NULL;
2209 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2211 return bus ? bus->dev.of_node : NULL;
2214 #else /* CONFIG_OF */
2215 static inline void pci_set_of_node(struct pci_dev *dev) { }
2216 static inline void pci_release_of_node(struct pci_dev *dev) { }
2217 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2218 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2219 static inline struct device_node *
2220 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
2221 static inline struct irq_domain *
2222 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2223 #endif /* CONFIG_OF */
2226 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2229 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2231 static inline struct irq_domain *
2232 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2236 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2238 return pdev->dev.archdata.edev;
2242 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2243 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2244 int pci_for_each_dma_alias(struct pci_dev *pdev,
2245 int (*fn)(struct pci_dev *pdev,
2246 u16 alias, void *data), void *data);
2248 /* helper functions for operation of device flag */
2249 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2251 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2253 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2255 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2257 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2259 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2263 * pci_ari_enabled - query ARI forwarding status
2266 * Returns true if ARI forwarding is enabled.
2268 static inline bool pci_ari_enabled(struct pci_bus *bus)
2270 return bus->self && bus->self->ari_enabled;
2274 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2275 * @pdev: PCI device to check
2277 * Walk upwards from @pdev and check for each encountered bridge if it's part
2278 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2279 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2281 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2283 struct pci_dev *parent = pdev;
2285 if (pdev->is_thunderbolt)
2288 while ((parent = pci_upstream_bridge(parent)))
2289 if (parent->is_thunderbolt)
2295 /* provide the legacy pci_dma_* API */
2296 #include <linux/pci-dma-compat.h>
2298 #define pci_printk(level, pdev, fmt, arg...) \
2299 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2301 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2302 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2303 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2304 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2305 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2306 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2307 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2308 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2310 #endif /* LINUX_PCI_H */