1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
27 #include <linux/mod_devicetable.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
40 #include <linux/resource_ext.h>
41 #include <uapi/linux/pci.h>
43 #include <linux/pci_ids.h>
45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
46 PCI_STATUS_SIG_SYSTEM_ERROR | \
47 PCI_STATUS_REC_MASTER_ABORT | \
48 PCI_STATUS_REC_TARGET_ABORT | \
49 PCI_STATUS_SIG_TARGET_ABORT | \
53 * The PCI interface treats multi-function devices as independent
54 * devices. The slot/function address of each device is encoded
55 * in a single byte as follows:
60 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
61 * In the interest of not exposing interfaces to user-space unnecessarily,
62 * the following kernel-only defines are being added here.
64 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
65 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
66 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
68 /* pci_slot represents a physical slot */
70 struct pci_bus *bus; /* Bus this slot is on */
71 struct list_head list; /* Node in list of slots */
72 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
73 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
77 static inline const char *pci_slot_name(const struct pci_slot *slot)
79 return kobject_name(&slot->kobj);
82 /* File state for mmap()s on /proc/bus/pci/X/Y */
88 /* For PCI devices, the region numbers are assigned this way: */
90 /* #0-5: standard PCI resources */
92 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
94 /* #6: expansion ROM resource */
97 /* Device-specific resources */
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
103 /* PCI-to-PCI (P2P) bridge windows */
104 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
105 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
106 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
108 /* CardBus bridge windows */
109 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
110 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
111 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
112 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
114 /* Total number of bridge resources for P2P and CardBus */
115 #define PCI_BRIDGE_RESOURCE_NUM 4
117 /* Resources assigned to buses behind the bridge */
118 PCI_BRIDGE_RESOURCES,
119 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
120 PCI_BRIDGE_RESOURCE_NUM - 1,
122 /* Total resources associated with a PCI device */
125 /* Preserve this for compatibility */
126 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
130 * enum pci_interrupt_pin - PCI INTx interrupt values
131 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
132 * @PCI_INTERRUPT_INTA: PCI INTA pin
133 * @PCI_INTERRUPT_INTB: PCI INTB pin
134 * @PCI_INTERRUPT_INTC: PCI INTC pin
135 * @PCI_INTERRUPT_INTD: PCI INTD pin
137 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
138 * PCI_INTERRUPT_PIN register.
140 enum pci_interrupt_pin {
141 PCI_INTERRUPT_UNKNOWN,
148 /* The number of legacy PCI INTx interrupts */
149 #define PCI_NUM_INTX 4
152 * pci_power_t values must match the bits in the Capabilities PME_Support
153 * and Control/Status PowerState fields in the Power Management capability.
155 typedef int __bitwise pci_power_t;
157 #define PCI_D0 ((pci_power_t __force) 0)
158 #define PCI_D1 ((pci_power_t __force) 1)
159 #define PCI_D2 ((pci_power_t __force) 2)
160 #define PCI_D3hot ((pci_power_t __force) 3)
161 #define PCI_D3cold ((pci_power_t __force) 4)
162 #define PCI_UNKNOWN ((pci_power_t __force) 5)
163 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
165 /* Remember to update this when the list above changes! */
166 extern const char *pci_power_names[];
168 static inline const char *pci_power_name(pci_power_t state)
170 return pci_power_names[1 + (__force int) state];
174 * typedef pci_channel_state_t
176 * The pci_channel state describes connectivity between the CPU and
177 * the PCI device. If some PCI bus between here and the PCI device
178 * has crashed or locked up, this info is reflected here.
180 typedef unsigned int __bitwise pci_channel_state_t;
183 /* I/O channel is in normal state */
184 pci_channel_io_normal = (__force pci_channel_state_t) 1,
186 /* I/O to channel is blocked */
187 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
189 /* PCI card is dead */
190 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
193 typedef unsigned int __bitwise pcie_reset_state_t;
195 enum pcie_reset_state {
196 /* Reset is NOT asserted (Use to deassert reset) */
197 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
199 /* Use #PERST to reset PCIe device */
200 pcie_warm_reset = (__force pcie_reset_state_t) 2,
202 /* Use PCIe Hot Reset to reset device */
203 pcie_hot_reset = (__force pcie_reset_state_t) 3
206 typedef unsigned short __bitwise pci_dev_flags_t;
208 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
209 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
210 /* Device configuration is irrevocably lost if disabled into D3 */
211 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
212 /* Provide indication device is assigned by a Virtual Machine Manager */
213 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
214 /* Flag for quirk use to store if quirk-specific ACS is enabled */
215 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
216 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
217 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
218 /* Do not use bus resets for device */
219 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
220 /* Do not use PM reset even if device advertises NoSoftRst- */
221 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
222 /* Get VPD from function 0 VPD */
223 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
224 /* A non-root bridge where translation occurs, stop alias search here */
225 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
226 /* Do not use FLR even if device advertises PCI_AF_CAP */
227 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
228 /* Don't use Relaxed Ordering for TLPs directed at this device */
229 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
230 /* Device does honor MSI masking despite saying otherwise */
231 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
234 enum pci_irq_reroute_variant {
235 INTEL_IRQ_REROUTE_VARIANT = 1,
236 MAX_IRQ_REROUTE_VARIANTS = 3
239 typedef unsigned short __bitwise pci_bus_flags_t;
241 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
242 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
243 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
244 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
247 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
248 enum pcie_link_width {
249 PCIE_LNK_WIDTH_RESRV = 0x00,
257 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
260 /* See matching string table in pci_speed_string() */
262 PCI_SPEED_33MHz = 0x00,
263 PCI_SPEED_66MHz = 0x01,
264 PCI_SPEED_66MHz_PCIX = 0x02,
265 PCI_SPEED_100MHz_PCIX = 0x03,
266 PCI_SPEED_133MHz_PCIX = 0x04,
267 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
268 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
269 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
270 PCI_SPEED_66MHz_PCIX_266 = 0x09,
271 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
272 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
278 PCI_SPEED_66MHz_PCIX_533 = 0x11,
279 PCI_SPEED_100MHz_PCIX_533 = 0x12,
280 PCI_SPEED_133MHz_PCIX_533 = 0x13,
281 PCIE_SPEED_2_5GT = 0x14,
282 PCIE_SPEED_5_0GT = 0x15,
283 PCIE_SPEED_8_0GT = 0x16,
284 PCIE_SPEED_16_0GT = 0x17,
285 PCIE_SPEED_32_0GT = 0x18,
286 PCI_SPEED_UNKNOWN = 0xff,
289 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
290 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
292 struct pci_cap_saved_data {
299 struct pci_cap_saved_state {
300 struct hlist_node next;
301 struct pci_cap_saved_data cap;
305 struct pcie_link_state;
311 /* The pci_dev structure describes PCI devices */
313 struct list_head bus_list; /* Node in per-bus list */
314 struct pci_bus *bus; /* Bus this device is on */
315 struct pci_bus *subordinate; /* Bus this device bridges to */
317 void *sysdata; /* Hook for sys-specific extension */
318 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
319 struct pci_slot *slot; /* Physical slot this device is in */
321 unsigned int devfn; /* Encoded device & function index */
322 unsigned short vendor;
323 unsigned short device;
324 unsigned short subsystem_vendor;
325 unsigned short subsystem_device;
326 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
327 u8 revision; /* PCI revision, low byte of class word */
328 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
329 #ifdef CONFIG_PCIEAER
330 u16 aer_cap; /* AER capability offset */
331 struct aer_stats *aer_stats; /* AER stats for this device */
333 #ifdef CONFIG_PCIEPORTBUS
334 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
336 u32 devcap; /* PCIe Device Capabilities */
337 u8 pcie_cap; /* PCIe capability offset */
338 u8 msi_cap; /* MSI capability offset */
339 u8 msix_cap; /* MSI-X capability offset */
340 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
341 u8 rom_base_reg; /* Config register controlling ROM */
342 u8 pin; /* Interrupt pin this device uses */
343 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
344 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
346 struct pci_driver *driver; /* Driver bound to this device */
347 u64 dma_mask; /* Mask of the bits of bus address this
348 device implements. Normally this is
349 0xffffffff. You only need to change
350 this if your device has broken DMA
351 or supports 64-bit transfers. */
353 struct device_dma_parameters dma_parms;
355 pci_power_t current_state; /* Current operating state. In ACPI,
356 this is D0-D3, D0 being fully
357 functional, and D3 being off. */
358 unsigned int imm_ready:1; /* Supports Immediate Readiness */
359 u8 pm_cap; /* PM capability offset */
360 unsigned int pme_support:5; /* Bitmask of states from which PME#
362 unsigned int pme_poll:1; /* Poll device's PME status bit */
363 unsigned int d1_support:1; /* Low power state D1 is supported */
364 unsigned int d2_support:1; /* Low power state D2 is supported */
365 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
366 unsigned int no_d3cold:1; /* D3cold is forbidden */
367 unsigned int bridge_d3:1; /* Allow D3 for bridge */
368 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
369 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
370 decoding during BAR sizing */
371 unsigned int wakeup_prepared:1;
372 unsigned int runtime_d3cold:1; /* Whether go through runtime
373 D3cold, not set for devices
374 powered on/off by the
375 corresponding bridge */
376 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
377 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
378 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
379 controlled exclusively by
381 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
383 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
384 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
386 #ifdef CONFIG_PCIEASPM
387 struct pcie_link_state *link_state; /* ASPM link state */
388 unsigned int ltr_path:1; /* Latency Tolerance Reporting
389 supported from root to here */
390 int l1ss; /* L1SS Capability pointer */
392 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
394 pci_channel_state_t error_state; /* Current connectivity state */
395 struct device dev; /* Generic device interface */
397 int cfg_size; /* Size of config space */
400 * Instead of touching interrupt line and base address registers
401 * directly, use the values stored here. They might be different!
404 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
406 bool match_driver; /* Skip attaching driver */
408 unsigned int transparent:1; /* Subtractive decode bridge */
409 unsigned int io_window:1; /* Bridge has I/O window */
410 unsigned int pref_window:1; /* Bridge has pref mem window */
411 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
412 unsigned int multifunction:1; /* Multi-function device */
414 unsigned int is_busmaster:1; /* Is busmaster */
415 unsigned int no_msi:1; /* May not use MSI */
416 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
417 unsigned int block_cfg_access:1; /* Config space access blocked */
418 unsigned int broken_parity_status:1; /* Generates false positive parity */
419 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
420 unsigned int msi_enabled:1;
421 unsigned int msix_enabled:1;
422 unsigned int ari_enabled:1; /* ARI forwarding */
423 unsigned int ats_enabled:1; /* Address Translation Svc */
424 unsigned int pasid_enabled:1; /* Process Address Space ID */
425 unsigned int pri_enabled:1; /* Page Request Interface */
426 unsigned int is_managed:1;
427 unsigned int needs_freset:1; /* Requires fundamental reset */
428 unsigned int state_saved:1;
429 unsigned int is_physfn:1;
430 unsigned int is_virtfn:1;
431 unsigned int reset_fn:1;
432 unsigned int is_hotplug_bridge:1;
433 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
434 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
436 * Devices marked being untrusted are the ones that can potentially
437 * execute DMA attacks and similar. They are typically connected
438 * through external ports such as Thunderbolt but not limited to
439 * that. When an IOMMU is enabled they should be getting full
440 * mappings to make sure they cannot access arbitrary memory.
442 unsigned int untrusted:1;
444 * Info from the platform, e.g., ACPI or device tree, may mark a
445 * device as "external-facing". An external-facing device is
446 * itself internal but devices downstream from it are external.
448 unsigned int external_facing:1;
449 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
450 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
451 unsigned int irq_managed:1;
452 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
453 unsigned int is_probed:1; /* Device probing in progress */
454 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
455 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
456 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
457 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */
458 pci_dev_flags_t dev_flags;
459 atomic_t enable_cnt; /* pci_enable_device has been called */
461 u32 saved_config_space[16]; /* Config space saved at suspend time */
462 struct hlist_head saved_cap_space;
463 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
464 int rom_attr_enabled; /* Display of ROM attribute enabled? */
465 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
466 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
468 #ifdef CONFIG_HOTPLUG_PCI_PCIE
469 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
471 #ifdef CONFIG_PCIE_PTM
472 unsigned int ptm_root:1;
473 unsigned int ptm_enabled:1;
476 #ifdef CONFIG_PCI_MSI
477 const struct attribute_group **msi_irq_groups;
480 #ifdef CONFIG_PCIE_DPC
482 unsigned int dpc_rp_extensions:1;
485 #ifdef CONFIG_PCI_ATS
487 struct pci_sriov *sriov; /* PF: SR-IOV info */
488 struct pci_dev *physfn; /* VF: related PF */
490 u16 ats_cap; /* ATS Capability offset */
491 u8 ats_stu; /* ATS Smallest Translation Unit */
493 #ifdef CONFIG_PCI_PRI
494 u16 pri_cap; /* PRI Capability offset */
495 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
496 unsigned int pasid_required:1; /* PRG Response PASID Required */
498 #ifdef CONFIG_PCI_PASID
499 u16 pasid_cap; /* PASID Capability offset */
502 #ifdef CONFIG_PCI_P2PDMA
503 struct pci_p2pdma *p2pdma;
505 u16 acs_cap; /* ACS Capability offset */
506 phys_addr_t rom; /* Physical address if not from BAR */
507 size_t romlen; /* Length if not from BAR */
508 char *driver_override; /* Driver name to force a match */
510 unsigned long priv_flags; /* Private flags for the PCI driver */
513 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
515 #ifdef CONFIG_PCI_IOV
522 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
524 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
525 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
527 static inline int pci_channel_offline(struct pci_dev *pdev)
529 return (pdev->error_state != pci_channel_io_normal);
532 struct pci_host_bridge {
534 struct pci_bus *bus; /* Root bus */
536 struct pci_ops *child_ops;
539 struct list_head windows; /* resource_entry */
540 struct list_head dma_ranges; /* dma ranges resource list */
541 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
542 int (*map_irq)(const struct pci_dev *, u8, u8);
543 void (*release_fn)(struct pci_host_bridge *);
545 struct msi_controller *msi;
546 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
547 unsigned int no_ext_tags:1; /* No Extended Tags */
548 unsigned int no_inc_mrrs:1; /* No Increase MRRS */
549 unsigned int native_aer:1; /* OS may use PCIe AER */
550 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
551 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
552 unsigned int native_pme:1; /* OS may use PCIe PME */
553 unsigned int native_ltr:1; /* OS may use PCIe LTR */
554 unsigned int native_dpc:1; /* OS may use PCIe DPC */
555 unsigned int preserve_config:1; /* Preserve FW resource setup */
556 unsigned int size_windows:1; /* Enable root bus sizing */
558 /* Resource alignment requirements */
559 resource_size_t (*align_resource)(struct pci_dev *dev,
560 const struct resource *res,
561 resource_size_t start,
562 resource_size_t size,
563 resource_size_t align);
564 unsigned long private[] ____cacheline_aligned;
567 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
569 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
571 return (void *)bridge->private;
574 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
576 return container_of(priv, struct pci_host_bridge, private);
579 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
580 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
582 void pci_free_host_bridge(struct pci_host_bridge *bridge);
583 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
585 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
586 void (*release_fn)(struct pci_host_bridge *),
589 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
592 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
593 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
594 * buses below host bridges or subtractive decode bridges) go in the list.
595 * Use pci_bus_for_each_resource() to iterate through all the resources.
599 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
600 * and there's no way to program the bridge with the details of the window.
601 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
602 * decode bit set, because they are explicit and can be programmed with _SRS.
604 #define PCI_SUBTRACTIVE_DECODE 0x1
606 struct pci_bus_resource {
607 struct list_head list;
608 struct resource *res;
612 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
615 struct list_head node; /* Node in list of buses */
616 struct pci_bus *parent; /* Parent bus this bridge is on */
617 struct list_head children; /* List of child buses */
618 struct list_head devices; /* List of devices on this bus */
619 struct pci_dev *self; /* Bridge device as seen by parent */
620 struct list_head slots; /* List of slots on this bus;
621 protected by pci_slot_mutex */
622 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
623 struct list_head resources; /* Address space routed to this bus */
624 struct resource busn_res; /* Bus numbers routed to this bus */
626 struct pci_ops *ops; /* Configuration access functions */
627 struct msi_controller *msi; /* MSI controller */
628 void *sysdata; /* Hook for sys-specific extension */
629 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
631 unsigned char number; /* Bus number */
632 unsigned char primary; /* Number of primary bridge */
633 unsigned char max_bus_speed; /* enum pci_bus_speed */
634 unsigned char cur_bus_speed; /* enum pci_bus_speed */
635 #ifdef CONFIG_PCI_DOMAINS_GENERIC
641 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
642 pci_bus_flags_t bus_flags; /* Inherited by child buses */
643 struct device *bridge;
645 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
646 struct bin_attribute *legacy_mem; /* Legacy mem */
647 unsigned int is_added:1;
648 unsigned int unsafe_warn:1; /* warned about RW1C config write */
651 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
653 static inline u16 pci_dev_id(struct pci_dev *dev)
655 return PCI_DEVID(dev->bus->number, dev->devfn);
659 * Returns true if the PCI bus is root (behind host-PCI bridge),
662 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
663 * This is incorrect because "virtual" buses added for SR-IOV (via
664 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
666 static inline bool pci_is_root_bus(struct pci_bus *pbus)
668 return !(pbus->parent);
672 * pci_is_bridge - check if the PCI device is a bridge
675 * Return true if the PCI device is bridge whether it has subordinate
678 static inline bool pci_is_bridge(struct pci_dev *dev)
680 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
681 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
684 #define for_each_pci_bridge(dev, bus) \
685 list_for_each_entry(dev, &bus->devices, bus_list) \
686 if (!pci_is_bridge(dev)) {} else
688 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
690 dev = pci_physfn(dev);
691 if (pci_is_root_bus(dev->bus))
694 return dev->bus->self;
697 #ifdef CONFIG_PCI_MSI
698 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
700 return pci_dev->msi_enabled || pci_dev->msix_enabled;
703 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
706 /* Error values that may be returned by PCI functions */
707 #define PCIBIOS_SUCCESSFUL 0x00
708 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
709 #define PCIBIOS_BAD_VENDOR_ID 0x83
710 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
711 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
712 #define PCIBIOS_SET_FAILED 0x88
713 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
715 /* Translate above to generic errno for passing back through non-PCI code */
716 static inline int pcibios_err_to_errno(int err)
718 if (err <= PCIBIOS_SUCCESSFUL)
719 return err; /* Assume already errno */
722 case PCIBIOS_FUNC_NOT_SUPPORTED:
724 case PCIBIOS_BAD_VENDOR_ID:
726 case PCIBIOS_DEVICE_NOT_FOUND:
728 case PCIBIOS_BAD_REGISTER_NUMBER:
730 case PCIBIOS_SET_FAILED:
732 case PCIBIOS_BUFFER_TOO_SMALL:
739 /* Low-level architecture-dependent routines */
742 int (*add_bus)(struct pci_bus *bus);
743 void (*remove_bus)(struct pci_bus *bus);
744 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
745 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
746 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
750 * ACPI needs to be able to access PCI config space before we've done a
751 * PCI bus scan and created pci_bus structures.
753 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
754 int reg, int len, u32 *val);
755 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
756 int reg, int len, u32 val);
758 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
759 typedef u64 pci_bus_addr_t;
761 typedef u32 pci_bus_addr_t;
764 struct pci_bus_region {
765 pci_bus_addr_t start;
770 spinlock_t lock; /* Protects list, index */
771 struct list_head list; /* For IDs added at runtime */
776 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
777 * a set of callbacks in struct pci_error_handlers, that device driver
778 * will be notified of PCI bus errors, and will be driven to recovery
779 * when an error occurs.
782 typedef unsigned int __bitwise pci_ers_result_t;
784 enum pci_ers_result {
785 /* No result/none/not supported in device driver */
786 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
788 /* Device driver can recover without slot reset */
789 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
791 /* Device driver wants slot to be reset */
792 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
794 /* Device has completely failed, is unrecoverable */
795 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
797 /* Device driver is fully recovered and operational */
798 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
800 /* No AER capabilities registered for the driver */
801 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
804 /* PCI bus error event callbacks */
805 struct pci_error_handlers {
806 /* PCI bus error detected on this device */
807 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
808 pci_channel_state_t error);
810 /* MMIO has been re-enabled, but not DMA */
811 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
813 /* PCI slot has been reset */
814 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
816 /* PCI function reset prepare or completed */
817 void (*reset_prepare)(struct pci_dev *dev);
818 void (*reset_done)(struct pci_dev *dev);
820 /* Device driver may resume normal operations */
821 void (*resume)(struct pci_dev *dev);
828 * struct pci_driver - PCI driver structure
829 * @node: List of driver structures.
830 * @name: Driver name.
831 * @id_table: Pointer to table of device IDs the driver is
832 * interested in. Most drivers should export this
833 * table using MODULE_DEVICE_TABLE(pci,...).
834 * @probe: This probing function gets called (during execution
835 * of pci_register_driver() for already existing
836 * devices or later if a new device gets inserted) for
837 * all PCI devices which match the ID table and are not
838 * "owned" by the other drivers yet. This function gets
839 * passed a "struct pci_dev \*" for each device whose
840 * entry in the ID table matches the device. The probe
841 * function returns zero when the driver chooses to
842 * take "ownership" of the device or an error code
843 * (negative number) otherwise.
844 * The probe function always gets called from process
845 * context, so it can sleep.
846 * @remove: The remove() function gets called whenever a device
847 * being handled by this driver is removed (either during
848 * deregistration of the driver or when it's manually
849 * pulled out of a hot-pluggable slot).
850 * The remove function always gets called from process
851 * context, so it can sleep.
852 * @suspend: Put device into low power state.
853 * @resume: Wake device from low power state.
854 * (Please see Documentation/power/pci.rst for descriptions
855 * of PCI Power Management and the related functions.)
856 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
857 * Intended to stop any idling DMA operations.
858 * Useful for enabling wake-on-lan (NIC) or changing
859 * the power state of a device before reboot.
860 * e.g. drivers/net/e100.c.
861 * @sriov_configure: Optional driver callback to allow configuration of
862 * number of VFs to enable via sysfs "sriov_numvfs" file.
863 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
864 * @groups: Sysfs attribute groups.
865 * @driver: Driver model structure.
866 * @dynids: List of dynamically added device IDs.
869 struct list_head node;
871 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
872 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
873 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
874 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
875 int (*resume)(struct pci_dev *dev); /* Device woken up */
876 void (*shutdown)(struct pci_dev *dev);
877 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
878 const struct pci_error_handlers *err_handler;
879 const struct attribute_group **groups;
880 struct device_driver driver;
881 struct pci_dynids dynids;
884 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
887 * PCI_DEVICE - macro used to describe a specific PCI device
888 * @vend: the 16 bit PCI Vendor ID
889 * @dev: the 16 bit PCI Device ID
891 * This macro is used to create a struct pci_device_id that matches a
892 * specific device. The subvendor and subdevice fields will be set to
895 #define PCI_DEVICE(vend,dev) \
896 .vendor = (vend), .device = (dev), \
897 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
900 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
901 * @vend: the 16 bit PCI Vendor ID
902 * @dev: the 16 bit PCI Device ID
903 * @subvend: the 16 bit PCI Subvendor ID
904 * @subdev: the 16 bit PCI Subdevice ID
906 * This macro is used to create a struct pci_device_id that matches a
907 * specific device with subsystem information.
909 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
910 .vendor = (vend), .device = (dev), \
911 .subvendor = (subvend), .subdevice = (subdev)
914 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
915 * @dev_class: the class, subclass, prog-if triple for this device
916 * @dev_class_mask: the class mask for this device
918 * This macro is used to create a struct pci_device_id that matches a
919 * specific PCI class. The vendor, device, subvendor, and subdevice
920 * fields will be set to PCI_ANY_ID.
922 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
923 .class = (dev_class), .class_mask = (dev_class_mask), \
924 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
925 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
928 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
929 * @vend: the vendor name
930 * @dev: the 16 bit PCI Device ID
932 * This macro is used to create a struct pci_device_id that matches a
933 * specific PCI device. The subvendor, and subdevice fields will be set
934 * to PCI_ANY_ID. The macro allows the next field to follow as the device
937 #define PCI_VDEVICE(vend, dev) \
938 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
939 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
942 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
943 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
944 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
945 * @data: the driver data to be filled
947 * This macro is used to create a struct pci_device_id that matches a
948 * specific PCI device. The subvendor, and subdevice fields will be set
951 #define PCI_DEVICE_DATA(vend, dev, data) \
952 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
953 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
954 .driver_data = (kernel_ulong_t)(data)
957 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
958 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
959 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
960 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
961 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
962 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
963 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
966 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
967 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
968 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
969 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
971 /* These external functions are only available when PCI support is enabled */
974 extern unsigned int pci_flags;
976 static inline void pci_set_flags(int flags) { pci_flags = flags; }
977 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
978 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
979 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
981 void pcie_bus_configure_settings(struct pci_bus *bus);
983 enum pcie_bus_config_types {
984 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
985 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
986 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
987 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
988 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
991 extern enum pcie_bus_config_types pcie_bus_config;
993 extern struct bus_type pci_bus_type;
995 /* Do NOT directly access these two variables, unless you are arch-specific PCI
996 * code, or PCI core code. */
997 extern struct list_head pci_root_buses; /* List of all known PCI buses */
998 /* Some device drivers need know if PCI is initiated */
999 int no_pci_devices(void);
1001 void pcibios_resource_survey_bus(struct pci_bus *bus);
1002 void pcibios_bus_add_device(struct pci_dev *pdev);
1003 void pcibios_add_bus(struct pci_bus *bus);
1004 void pcibios_remove_bus(struct pci_bus *bus);
1005 void pcibios_fixup_bus(struct pci_bus *);
1006 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1007 /* Architecture-specific versions may override this (weak) */
1008 char *pcibios_setup(char *str);
1010 /* Used only when drivers/pci/setup.c is used */
1011 resource_size_t pcibios_align_resource(void *, const struct resource *,
1015 /* Weak but can be overridden by arch */
1016 void pci_fixup_cardbus(struct pci_bus *);
1018 /* Generic PCI functions used internally */
1020 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1021 struct resource *res);
1022 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1023 struct pci_bus_region *region);
1024 void pcibios_scan_specific_bus(int busn);
1025 struct pci_bus *pci_find_bus(int domain, int busnr);
1026 void pci_bus_add_devices(const struct pci_bus *bus);
1027 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1028 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1029 struct pci_ops *ops, void *sysdata,
1030 struct list_head *resources);
1031 int pci_host_probe(struct pci_host_bridge *bridge);
1032 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1033 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1034 void pci_bus_release_busn_res(struct pci_bus *b);
1035 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1036 struct pci_ops *ops, void *sysdata,
1037 struct list_head *resources);
1038 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1039 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1041 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1043 struct hotplug_slot *hotplug);
1044 void pci_destroy_slot(struct pci_slot *slot);
1046 void pci_dev_assign_slot(struct pci_dev *dev);
1048 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1050 int pci_scan_slot(struct pci_bus *bus, int devfn);
1051 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1052 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1053 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1054 void pci_bus_add_device(struct pci_dev *dev);
1055 void pci_read_bridge_bases(struct pci_bus *child);
1056 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1057 struct resource *res);
1058 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1059 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1060 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1061 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1062 void pci_dev_put(struct pci_dev *dev);
1063 void pci_remove_bus(struct pci_bus *b);
1064 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1065 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1066 void pci_stop_root_bus(struct pci_bus *bus);
1067 void pci_remove_root_bus(struct pci_bus *bus);
1068 void pci_setup_cardbus(struct pci_bus *bus);
1069 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1070 void pci_sort_breadthfirst(void);
1071 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1072 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1074 /* Generic PCI functions exported to card drivers */
1076 int pci_find_capability(struct pci_dev *dev, int cap);
1077 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1078 int pci_find_ext_capability(struct pci_dev *dev, int cap);
1079 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
1080 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1081 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
1082 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1084 u64 pci_get_dsn(struct pci_dev *dev);
1086 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1087 struct pci_dev *from);
1088 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1089 unsigned int ss_vendor, unsigned int ss_device,
1090 struct pci_dev *from);
1091 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1092 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1093 unsigned int devfn);
1094 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1095 int pci_dev_present(const struct pci_device_id *ids);
1097 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1098 int where, u8 *val);
1099 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1100 int where, u16 *val);
1101 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1102 int where, u32 *val);
1103 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1105 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1106 int where, u16 val);
1107 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1108 int where, u32 val);
1110 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1111 int where, int size, u32 *val);
1112 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1113 int where, int size, u32 val);
1114 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1115 int where, int size, u32 *val);
1116 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1117 int where, int size, u32 val);
1119 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1121 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1122 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1123 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1124 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1125 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1126 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1128 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1129 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1130 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1131 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1132 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1133 u16 clear, u16 set);
1134 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1135 u32 clear, u32 set);
1137 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1140 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1143 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1146 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1149 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1152 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1155 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1158 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1161 /* User-space driven config access */
1162 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1163 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1164 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1165 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1166 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1167 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1169 int __must_check pci_enable_device(struct pci_dev *dev);
1170 int __must_check pci_enable_device_io(struct pci_dev *dev);
1171 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1172 int __must_check pci_reenable_device(struct pci_dev *);
1173 int __must_check pcim_enable_device(struct pci_dev *pdev);
1174 void pcim_pin_device(struct pci_dev *pdev);
1176 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1179 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1180 * writable and no quirk has marked the feature broken.
1182 return !pdev->broken_intx_masking;
1185 static inline int pci_is_enabled(struct pci_dev *pdev)
1187 return (atomic_read(&pdev->enable_cnt) > 0);
1190 static inline int pci_is_managed(struct pci_dev *pdev)
1192 return pdev->is_managed;
1195 void pci_disable_device(struct pci_dev *dev);
1197 extern unsigned int pcibios_max_latency;
1198 void pci_set_master(struct pci_dev *dev);
1199 void pci_clear_master(struct pci_dev *dev);
1201 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1202 int pci_set_cacheline_size(struct pci_dev *dev);
1203 #define HAVE_PCI_SET_MWI
1204 int __must_check pci_set_mwi(struct pci_dev *dev);
1205 int __must_check pcim_set_mwi(struct pci_dev *dev);
1206 int pci_try_set_mwi(struct pci_dev *dev);
1207 void pci_clear_mwi(struct pci_dev *dev);
1208 void pci_intx(struct pci_dev *dev, int enable);
1209 bool pci_check_and_mask_intx(struct pci_dev *dev);
1210 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1211 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1212 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1213 int pcix_get_max_mmrbc(struct pci_dev *dev);
1214 int pcix_get_mmrbc(struct pci_dev *dev);
1215 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1216 int pcie_get_readrq(struct pci_dev *dev);
1217 int pcie_set_readrq(struct pci_dev *dev, int rq);
1218 int pcie_get_mps(struct pci_dev *dev);
1219 int pcie_set_mps(struct pci_dev *dev, int mps);
1220 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1221 enum pci_bus_speed *speed,
1222 enum pcie_link_width *width);
1223 void pcie_print_link_status(struct pci_dev *dev);
1224 bool pcie_has_flr(struct pci_dev *dev);
1225 int pcie_flr(struct pci_dev *dev);
1226 int __pci_reset_function_locked(struct pci_dev *dev);
1227 int pci_reset_function(struct pci_dev *dev);
1228 int pci_reset_function_locked(struct pci_dev *dev);
1229 int pci_try_reset_function(struct pci_dev *dev);
1230 int pci_probe_reset_slot(struct pci_slot *slot);
1231 int pci_probe_reset_bus(struct pci_bus *bus);
1232 int pci_reset_bus(struct pci_dev *dev);
1233 void pci_reset_secondary_bus(struct pci_dev *dev);
1234 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1235 void pci_update_resource(struct pci_dev *dev, int resno);
1236 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1237 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1238 void pci_release_resource(struct pci_dev *dev, int resno);
1239 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1240 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1241 bool pci_device_is_present(struct pci_dev *pdev);
1242 void pci_ignore_hotplug(struct pci_dev *dev);
1243 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1244 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1246 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1247 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1248 const char *fmt, ...);
1249 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1251 /* ROM control related routines */
1252 int pci_enable_rom(struct pci_dev *pdev);
1253 void pci_disable_rom(struct pci_dev *pdev);
1254 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1255 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1257 /* Power management related routines */
1258 int pci_save_state(struct pci_dev *dev);
1259 void pci_restore_state(struct pci_dev *dev);
1260 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1261 int pci_load_saved_state(struct pci_dev *dev,
1262 struct pci_saved_state *state);
1263 int pci_load_and_free_saved_state(struct pci_dev *dev,
1264 struct pci_saved_state **state);
1265 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1266 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1268 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1269 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1270 u16 cap, unsigned int size);
1271 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1272 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1273 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1274 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1275 void pci_pme_active(struct pci_dev *dev, bool enable);
1276 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1277 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1278 int pci_prepare_to_sleep(struct pci_dev *dev);
1279 int pci_back_from_sleep(struct pci_dev *dev);
1280 bool pci_dev_run_wake(struct pci_dev *dev);
1281 void pci_d3cold_enable(struct pci_dev *dev);
1282 void pci_d3cold_disable(struct pci_dev *dev);
1283 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1284 void pci_wakeup_bus(struct pci_bus *bus);
1285 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1287 /* For use by arch with custom probe code */
1288 void set_pcie_port_type(struct pci_dev *pdev);
1289 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1291 /* Functions for PCI Hotplug drivers to use */
1292 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1293 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1294 unsigned int pci_rescan_bus(struct pci_bus *bus);
1295 void pci_lock_rescan_remove(void);
1296 void pci_unlock_rescan_remove(void);
1298 /* Vital Product Data routines */
1299 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1300 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1301 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1303 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1304 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1305 void pci_bus_assign_resources(const struct pci_bus *bus);
1306 void pci_bus_claim_resources(struct pci_bus *bus);
1307 void pci_bus_size_bridges(struct pci_bus *bus);
1308 int pci_claim_resource(struct pci_dev *, int);
1309 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1310 void pci_assign_unassigned_resources(void);
1311 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1312 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1313 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1314 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1315 void pdev_enable_device(struct pci_dev *);
1316 int pci_enable_resources(struct pci_dev *, int mask);
1317 void pci_assign_irq(struct pci_dev *dev);
1318 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1319 #define HAVE_PCI_REQ_REGIONS 2
1320 int __must_check pci_request_regions(struct pci_dev *, const char *);
1321 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1322 void pci_release_regions(struct pci_dev *);
1323 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1324 void pci_release_region(struct pci_dev *, int);
1325 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1326 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1327 void pci_release_selected_regions(struct pci_dev *, int);
1329 /* drivers/pci/bus.c */
1330 void pci_add_resource(struct list_head *resources, struct resource *res);
1331 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1332 resource_size_t offset);
1333 void pci_free_resource_list(struct list_head *resources);
1334 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1335 unsigned int flags);
1336 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1337 void pci_bus_remove_resources(struct pci_bus *bus);
1338 int devm_request_pci_bus_resources(struct device *dev,
1339 struct list_head *resources);
1341 /* Temporary until new and working PCI SBR API in place */
1342 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1344 #define pci_bus_for_each_resource(bus, res, i) \
1346 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1349 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1350 struct resource *res, resource_size_t size,
1351 resource_size_t align, resource_size_t min,
1352 unsigned long type_mask,
1353 resource_size_t (*alignf)(void *,
1354 const struct resource *,
1360 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1361 resource_size_t size);
1362 unsigned long pci_address_to_pio(phys_addr_t addr);
1363 phys_addr_t pci_pio_to_address(unsigned long pio);
1364 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1365 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1366 phys_addr_t phys_addr);
1367 void pci_unmap_iospace(struct resource *res);
1368 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1369 resource_size_t offset,
1370 resource_size_t size);
1371 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1372 struct resource *res);
1374 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1376 struct pci_bus_region region;
1378 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1379 return region.start;
1382 /* Proper probing supporting hot-pluggable devices */
1383 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1384 const char *mod_name);
1386 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1387 #define pci_register_driver(driver) \
1388 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1390 void pci_unregister_driver(struct pci_driver *dev);
1393 * module_pci_driver() - Helper macro for registering a PCI driver
1394 * @__pci_driver: pci_driver struct
1396 * Helper macro for PCI drivers which do not do anything special in module
1397 * init/exit. This eliminates a lot of boilerplate. Each module may only
1398 * use this macro once, and calling it replaces module_init() and module_exit()
1400 #define module_pci_driver(__pci_driver) \
1401 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1404 * builtin_pci_driver() - Helper macro for registering a PCI driver
1405 * @__pci_driver: pci_driver struct
1407 * Helper macro for PCI drivers which do not do anything special in their
1408 * init code. This eliminates a lot of boilerplate. Each driver may only
1409 * use this macro once, and calling it replaces device_initcall(...)
1411 #define builtin_pci_driver(__pci_driver) \
1412 builtin_driver(__pci_driver, pci_register_driver)
1414 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1415 int pci_add_dynid(struct pci_driver *drv,
1416 unsigned int vendor, unsigned int device,
1417 unsigned int subvendor, unsigned int subdevice,
1418 unsigned int class, unsigned int class_mask,
1419 unsigned long driver_data);
1420 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1421 struct pci_dev *dev);
1422 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1425 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1427 int pci_cfg_space_size(struct pci_dev *dev);
1428 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1429 void pci_setup_bridge(struct pci_bus *bus);
1430 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1431 unsigned long type);
1433 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1434 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1436 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1437 unsigned int command_bits, u32 flags);
1440 * Virtual interrupts allow for more interrupts to be allocated
1441 * than the device has interrupts for. These are not programmed
1442 * into the device's MSI-X table and must be handled by some
1443 * other driver means.
1445 #define PCI_IRQ_VIRTUAL (1 << 4)
1447 #define PCI_IRQ_ALL_TYPES \
1448 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1450 /* kmem_cache style wrapper around pci_alloc_consistent() */
1452 #include <linux/dmapool.h>
1454 #define pci_pool dma_pool
1455 #define pci_pool_create(name, pdev, size, align, allocation) \
1456 dma_pool_create(name, &pdev->dev, size, align, allocation)
1457 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1458 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1459 #define pci_pool_zalloc(pool, flags, handle) \
1460 dma_pool_zalloc(pool, flags, handle)
1461 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1464 u32 vector; /* Kernel uses to write allocated vector */
1465 u16 entry; /* Driver uses to specify entry, OS writes */
1468 #ifdef CONFIG_PCI_MSI
1469 int pci_msi_vec_count(struct pci_dev *dev);
1470 void pci_disable_msi(struct pci_dev *dev);
1471 int pci_msix_vec_count(struct pci_dev *dev);
1472 void pci_disable_msix(struct pci_dev *dev);
1473 void pci_restore_msi_state(struct pci_dev *dev);
1474 int pci_msi_enabled(void);
1475 int pci_enable_msi(struct pci_dev *dev);
1476 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1477 int minvec, int maxvec);
1478 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1479 struct msix_entry *entries, int nvec)
1481 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1486 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1487 unsigned int max_vecs, unsigned int flags,
1488 struct irq_affinity *affd);
1490 void pci_free_irq_vectors(struct pci_dev *dev);
1491 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1492 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1495 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1496 static inline void pci_disable_msi(struct pci_dev *dev) { }
1497 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1498 static inline void pci_disable_msix(struct pci_dev *dev) { }
1499 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1500 static inline int pci_msi_enabled(void) { return 0; }
1501 static inline int pci_enable_msi(struct pci_dev *dev)
1503 static inline int pci_enable_msix_range(struct pci_dev *dev,
1504 struct msix_entry *entries, int minvec, int maxvec)
1506 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1507 struct msix_entry *entries, int nvec)
1511 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1512 unsigned int max_vecs, unsigned int flags,
1513 struct irq_affinity *aff_desc)
1515 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1520 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1524 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1526 if (WARN_ON_ONCE(nr > 0))
1530 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1533 return cpu_possible_mask;
1538 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1539 * @d: the INTx IRQ domain
1540 * @node: the DT node for the device whose interrupt we're translating
1541 * @intspec: the interrupt specifier data from the DT
1542 * @intsize: the number of entries in @intspec
1543 * @out_hwirq: pointer at which to write the hwirq number
1544 * @out_type: pointer at which to write the interrupt type
1546 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1547 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1548 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1549 * INTx value to obtain the hwirq number.
1551 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1553 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1554 struct device_node *node,
1556 unsigned int intsize,
1557 unsigned long *out_hwirq,
1558 unsigned int *out_type)
1560 const u32 intx = intspec[0];
1562 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1565 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1569 #ifdef CONFIG_PCIEPORTBUS
1570 extern bool pcie_ports_disabled;
1571 extern bool pcie_ports_native;
1573 #define pcie_ports_disabled true
1574 #define pcie_ports_native false
1577 #define PCIE_LINK_STATE_L0S BIT(0)
1578 #define PCIE_LINK_STATE_L1 BIT(1)
1579 #define PCIE_LINK_STATE_CLKPM BIT(2)
1580 #define PCIE_LINK_STATE_L1_1 BIT(3)
1581 #define PCIE_LINK_STATE_L1_2 BIT(4)
1582 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1583 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1585 #ifdef CONFIG_PCIEASPM
1586 int pci_disable_link_state(struct pci_dev *pdev, int state);
1587 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1588 void pcie_no_aspm(void);
1589 bool pcie_aspm_support_enabled(void);
1590 bool pcie_aspm_enabled(struct pci_dev *pdev);
1592 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1594 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1596 static inline void pcie_no_aspm(void) { }
1597 static inline bool pcie_aspm_support_enabled(void) { return false; }
1598 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1601 #ifdef CONFIG_PCIEAER
1602 bool pci_aer_available(void);
1604 static inline bool pci_aer_available(void) { return false; }
1607 bool pci_ats_disabled(void);
1609 #ifdef CONFIG_PCIE_PTM
1610 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1612 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1616 void pci_cfg_access_lock(struct pci_dev *dev);
1617 bool pci_cfg_access_trylock(struct pci_dev *dev);
1618 void pci_cfg_access_unlock(struct pci_dev *dev);
1621 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1622 * a PCI domain is defined to be a set of PCI buses which share
1623 * configuration space.
1625 #ifdef CONFIG_PCI_DOMAINS
1626 extern int pci_domains_supported;
1628 enum { pci_domains_supported = 0 };
1629 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1630 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1631 #endif /* CONFIG_PCI_DOMAINS */
1634 * Generic implementation for PCI domain support. If your
1635 * architecture does not need custom management of PCI
1636 * domains then this implementation will be used
1638 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1639 static inline int pci_domain_nr(struct pci_bus *bus)
1641 return bus->domain_nr;
1644 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1646 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1649 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1652 /* Some architectures require additional setup to direct VGA traffic */
1653 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1654 unsigned int command_bits, u32 flags);
1655 void pci_register_set_vga_state(arch_set_vga_state_t func);
1658 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1660 return pci_request_selected_regions(pdev,
1661 pci_select_bars(pdev, IORESOURCE_IO), name);
1665 pci_release_io_regions(struct pci_dev *pdev)
1667 return pci_release_selected_regions(pdev,
1668 pci_select_bars(pdev, IORESOURCE_IO));
1672 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1674 return pci_request_selected_regions(pdev,
1675 pci_select_bars(pdev, IORESOURCE_MEM), name);
1679 pci_release_mem_regions(struct pci_dev *pdev)
1681 return pci_release_selected_regions(pdev,
1682 pci_select_bars(pdev, IORESOURCE_MEM));
1685 #else /* CONFIG_PCI is not enabled */
1687 static inline void pci_set_flags(int flags) { }
1688 static inline void pci_add_flags(int flags) { }
1689 static inline void pci_clear_flags(int flags) { }
1690 static inline int pci_has_flag(int flag) { return 0; }
1693 * If the system does not have PCI, clearly these return errors. Define
1694 * these as simple inline functions to avoid hair in drivers.
1696 #define _PCI_NOP(o, s, t) \
1697 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1699 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1701 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1702 _PCI_NOP(o, word, u16 x) \
1703 _PCI_NOP(o, dword, u32 x)
1704 _PCI_NOP_ALL(read, *)
1705 _PCI_NOP_ALL(write,)
1707 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1708 unsigned int device,
1709 struct pci_dev *from)
1712 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1713 unsigned int device,
1714 unsigned int ss_vendor,
1715 unsigned int ss_device,
1716 struct pci_dev *from)
1719 static inline struct pci_dev *pci_get_class(unsigned int class,
1720 struct pci_dev *from)
1723 #define pci_dev_present(ids) (0)
1724 #define no_pci_devices() (1)
1725 #define pci_dev_put(dev) do { } while (0)
1727 static inline void pci_set_master(struct pci_dev *dev) { }
1728 static inline void pci_clear_master(struct pci_dev *dev) { }
1729 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1730 static inline void pci_disable_device(struct pci_dev *dev) { }
1731 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
1732 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1734 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1735 struct module *owner,
1736 const char *mod_name)
1738 static inline int pci_register_driver(struct pci_driver *drv)
1740 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1741 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1743 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1746 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1749 static inline u64 pci_get_dsn(struct pci_dev *dev)
1752 /* Power management related routines */
1753 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1754 static inline void pci_restore_state(struct pci_dev *dev) { }
1755 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1757 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1759 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1762 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1766 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1767 struct resource *res)
1769 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1771 static inline void pci_release_regions(struct pci_dev *dev) { }
1773 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1775 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1777 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1780 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1781 unsigned int bus, unsigned int devfn)
1784 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1785 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1787 #define dev_is_pci(d) (false)
1788 #define dev_is_pf(d) (false)
1789 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1791 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1792 struct device_node *node,
1794 unsigned int intsize,
1795 unsigned long *out_hwirq,
1796 unsigned int *out_type)
1799 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1800 struct pci_dev *dev)
1802 static inline bool pci_ats_disabled(void) { return true; }
1804 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1810 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1811 unsigned int max_vecs, unsigned int flags,
1812 struct irq_affinity *aff_desc)
1816 #endif /* CONFIG_PCI */
1819 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1820 unsigned int max_vecs, unsigned int flags)
1822 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1826 /* Include architecture-dependent settings and functions */
1828 #include <asm/pci.h>
1830 /* These two functions provide almost identical functionality. Depending
1831 * on the architecture, one will be implemented as a wrapper around the
1832 * other (in drivers/pci/mmap.c).
1834 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1835 * is expected to be an offset within that region.
1837 * pci_mmap_page_range() is the legacy architecture-specific interface,
1838 * which accepts a "user visible" resource address converted by
1839 * pci_resource_to_user(), as used in the legacy mmap() interface in
1842 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1843 struct vm_area_struct *vma,
1844 enum pci_mmap_state mmap_state, int write_combine);
1845 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1846 struct vm_area_struct *vma,
1847 enum pci_mmap_state mmap_state, int write_combine);
1849 #ifndef arch_can_pci_mmap_wc
1850 #define arch_can_pci_mmap_wc() 0
1853 #ifndef arch_can_pci_mmap_io
1854 #define arch_can_pci_mmap_io() 0
1855 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1857 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1860 #ifndef pci_root_bus_fwnode
1861 #define pci_root_bus_fwnode(bus) NULL
1865 * These helpers provide future and backwards compatibility
1866 * for accessing popular PCI BAR info
1868 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1869 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1870 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1871 #define pci_resource_len(dev,bar) \
1872 ((pci_resource_start((dev), (bar)) == 0 && \
1873 pci_resource_end((dev), (bar)) == \
1874 pci_resource_start((dev), (bar))) ? 0 : \
1876 (pci_resource_end((dev), (bar)) - \
1877 pci_resource_start((dev), (bar)) + 1))
1880 * Similar to the helpers above, these manipulate per-pci_dev
1881 * driver-specific data. They are really just a wrapper around
1882 * the generic device structure functions of these calls.
1884 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1886 return dev_get_drvdata(&pdev->dev);
1889 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1891 dev_set_drvdata(&pdev->dev, data);
1894 static inline const char *pci_name(const struct pci_dev *pdev)
1896 return dev_name(&pdev->dev);
1899 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1900 const struct resource *rsrc,
1901 resource_size_t *start, resource_size_t *end);
1904 * The world is not perfect and supplies us with broken PCI devices.
1905 * For at least a part of these bugs we need a work-around, so both
1906 * generic (drivers/pci/quirks.c) and per-architecture code can define
1907 * fixup hooks to be called for particular buggy devices.
1911 u16 vendor; /* Or PCI_ANY_ID */
1912 u16 device; /* Or PCI_ANY_ID */
1913 u32 class; /* Or PCI_ANY_ID */
1914 unsigned int class_shift; /* should be 0, 8, 16 */
1915 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1918 void (*hook)(struct pci_dev *dev);
1922 enum pci_fixup_pass {
1923 pci_fixup_early, /* Before probing BARs */
1924 pci_fixup_header, /* After reading configuration header */
1925 pci_fixup_final, /* Final phase of device fixups */
1926 pci_fixup_enable, /* pci_enable_device() time */
1927 pci_fixup_resume, /* pci_device_resume() */
1928 pci_fixup_suspend, /* pci_device_suspend() */
1929 pci_fixup_resume_early, /* pci_device_resume_early() */
1930 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1933 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1934 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1935 class_shift, hook) \
1936 __ADDRESSABLE(hook) \
1937 asm(".section " #sec ", \"a\" \n" \
1939 ".short " #vendor ", " #device " \n" \
1940 ".long " #class ", " #class_shift " \n" \
1941 ".long " #hook " - . \n" \
1943 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1944 class_shift, hook) \
1945 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1948 /* Anonymous variables would be nice... */
1949 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1950 class_shift, hook) \
1951 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1952 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1953 = { vendor, device, class, class_shift, hook };
1956 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1957 class_shift, hook) \
1958 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1959 hook, vendor, device, class, class_shift, hook)
1960 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1961 class_shift, hook) \
1962 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1963 hook, vendor, device, class, class_shift, hook)
1964 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1965 class_shift, hook) \
1966 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1967 hook, vendor, device, class, class_shift, hook)
1968 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1969 class_shift, hook) \
1970 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1971 hook, vendor, device, class, class_shift, hook)
1972 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1973 class_shift, hook) \
1974 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1975 resume##hook, vendor, device, class, class_shift, hook)
1976 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1977 class_shift, hook) \
1978 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1979 resume_early##hook, vendor, device, class, class_shift, hook)
1980 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1981 class_shift, hook) \
1982 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1983 suspend##hook, vendor, device, class, class_shift, hook)
1984 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1985 class_shift, hook) \
1986 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1987 suspend_late##hook, vendor, device, class, class_shift, hook)
1989 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1990 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1991 hook, vendor, device, PCI_ANY_ID, 0, hook)
1992 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1993 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1994 hook, vendor, device, PCI_ANY_ID, 0, hook)
1995 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1996 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1997 hook, vendor, device, PCI_ANY_ID, 0, hook)
1998 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1999 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2000 hook, vendor, device, PCI_ANY_ID, 0, hook)
2001 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2002 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2003 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2004 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2005 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2006 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2007 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2008 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2009 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2010 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2011 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2012 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2014 #ifdef CONFIG_PCI_QUIRKS
2015 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2017 static inline void pci_fixup_device(enum pci_fixup_pass pass,
2018 struct pci_dev *dev) { }
2021 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2022 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2023 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2024 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2025 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2027 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2029 extern int pci_pci_problems;
2030 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2031 #define PCIPCI_TRITON 2
2032 #define PCIPCI_NATOMA 4
2033 #define PCIPCI_VIAETBF 8
2034 #define PCIPCI_VSFX 16
2035 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2036 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2038 extern unsigned long pci_cardbus_io_size;
2039 extern unsigned long pci_cardbus_mem_size;
2040 extern u8 pci_dfl_cache_line_size;
2041 extern u8 pci_cache_line_size;
2043 /* Architecture-specific versions may override these (weak) */
2044 void pcibios_disable_device(struct pci_dev *dev);
2045 void pcibios_set_master(struct pci_dev *dev);
2046 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2047 enum pcie_reset_state state);
2048 int pcibios_add_device(struct pci_dev *dev);
2049 void pcibios_release_device(struct pci_dev *dev);
2051 void pcibios_penalize_isa_irq(int irq, int active);
2053 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2055 int pcibios_alloc_irq(struct pci_dev *dev);
2056 void pcibios_free_irq(struct pci_dev *dev);
2057 resource_size_t pcibios_default_alignment(void);
2059 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2060 void __init pci_mmcfg_early_init(void);
2061 void __init pci_mmcfg_late_init(void);
2063 static inline void pci_mmcfg_early_init(void) { }
2064 static inline void pci_mmcfg_late_init(void) { }
2067 int pci_ext_cfg_avail(void);
2069 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2070 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2072 #ifdef CONFIG_PCI_IOV
2073 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2074 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2076 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2077 void pci_disable_sriov(struct pci_dev *dev);
2079 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2080 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2081 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2082 int pci_num_vf(struct pci_dev *dev);
2083 int pci_vfs_assigned(struct pci_dev *dev);
2084 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2085 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2086 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2087 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2088 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2090 /* Arch may override these (weak) */
2091 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2092 int pcibios_sriov_disable(struct pci_dev *pdev);
2093 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2095 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2099 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2103 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2106 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2107 struct pci_dev *virtfn, int id)
2111 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2115 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2117 static inline void pci_disable_sriov(struct pci_dev *dev) { }
2118 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2119 static inline int pci_vfs_assigned(struct pci_dev *dev)
2121 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2123 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2125 #define pci_sriov_configure_simple NULL
2126 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2128 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2131 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2132 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2133 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2137 * pci_pcie_cap - get the saved PCIe capability offset
2140 * PCIe capability offset is calculated at PCI device initialization
2141 * time and saved in the data structure. This function returns saved
2142 * PCIe capability offset. Using this instead of pci_find_capability()
2143 * reduces unnecessary search in the PCI configuration space. If you
2144 * need to calculate PCIe capability offset from raw device for some
2145 * reasons, please use pci_find_capability() instead.
2147 static inline int pci_pcie_cap(struct pci_dev *dev)
2149 return dev->pcie_cap;
2153 * pci_is_pcie - check if the PCI device is PCI Express capable
2156 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2158 static inline bool pci_is_pcie(struct pci_dev *dev)
2160 return pci_pcie_cap(dev);
2164 * pcie_caps_reg - get the PCIe Capabilities Register
2167 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2169 return dev->pcie_flags_reg;
2173 * pci_pcie_type - get the PCIe device/port type
2176 static inline int pci_pcie_type(const struct pci_dev *dev)
2178 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2182 * pcie_find_root_port - Get the PCIe root port device
2185 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2186 * for a given PCI/PCIe Device.
2188 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2191 if (pci_is_pcie(dev) &&
2192 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2194 dev = pci_upstream_bridge(dev);
2200 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
2202 return dev->error_state == pci_channel_io_perm_failure;
2205 void pci_request_acs(void);
2206 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2207 bool pci_acs_path_enabled(struct pci_dev *start,
2208 struct pci_dev *end, u16 acs_flags);
2209 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2211 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2212 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2214 /* Large Resource Data Type Tag Item Names */
2215 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2216 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2217 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2219 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2220 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2221 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2223 /* Small Resource Data Type Tag Item Names */
2224 #define PCI_VPD_STIN_END 0x0f /* End */
2226 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2228 #define PCI_VPD_SRDT_TIN_MASK 0x78
2229 #define PCI_VPD_SRDT_LEN_MASK 0x07
2230 #define PCI_VPD_LRDT_TIN_MASK 0x7f
2232 #define PCI_VPD_LRDT_TAG_SIZE 3
2233 #define PCI_VPD_SRDT_TAG_SIZE 1
2235 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2237 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2238 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2239 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2240 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2241 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2244 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2245 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2247 * Returns the extracted Large Resource Data Type length.
2249 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2251 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2255 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2256 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2258 * Returns the extracted Large Resource Data Type Tag item.
2260 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2262 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2266 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2267 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2269 * Returns the extracted Small Resource Data Type length.
2271 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2273 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2277 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2278 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2280 * Returns the extracted Small Resource Data Type Tag Item.
2282 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2284 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2288 * pci_vpd_info_field_size - Extracts the information field length
2289 * @info_field: Pointer to the beginning of an information field header
2291 * Returns the extracted information field length.
2293 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2295 return info_field[2];
2299 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2300 * @buf: Pointer to buffered vpd data
2301 * @off: The offset into the buffer at which to begin the search
2302 * @len: The length of the vpd buffer
2303 * @rdt: The Resource Data Type to search for
2305 * Returns the index where the Resource Data Type was found or
2306 * -ENOENT otherwise.
2308 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2311 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2312 * @buf: Pointer to buffered vpd data
2313 * @off: The offset into the buffer at which to begin the search
2314 * @len: The length of the buffer area, relative to off, in which to search
2315 * @kw: The keyword to search for
2317 * Returns the index where the information field keyword was found or
2318 * -ENOENT otherwise.
2320 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2321 unsigned int len, const char *kw);
2323 /* PCI <-> OF binding helpers */
2327 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2329 /* Arch may override this (weak) */
2330 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2332 #else /* CONFIG_OF */
2333 static inline struct irq_domain *
2334 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2335 #endif /* CONFIG_OF */
2337 static inline struct device_node *
2338 pci_device_to_OF_node(const struct pci_dev *pdev)
2340 return pdev ? pdev->dev.of_node : NULL;
2343 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2345 return bus ? bus->dev.of_node : NULL;
2349 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2352 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2353 bool pci_pr3_present(struct pci_dev *pdev);
2355 static inline struct irq_domain *
2356 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2357 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2361 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2363 return pdev->dev.archdata.edev;
2367 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2368 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2369 int pci_for_each_dma_alias(struct pci_dev *pdev,
2370 int (*fn)(struct pci_dev *pdev,
2371 u16 alias, void *data), void *data);
2373 /* Helper functions for operation of device flag */
2374 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2376 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2378 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2380 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2382 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2384 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2388 * pci_ari_enabled - query ARI forwarding status
2391 * Returns true if ARI forwarding is enabled.
2393 static inline bool pci_ari_enabled(struct pci_bus *bus)
2395 return bus->self && bus->self->ari_enabled;
2399 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2400 * @pdev: PCI device to check
2402 * Walk upwards from @pdev and check for each encountered bridge if it's part
2403 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2404 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2406 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2408 struct pci_dev *parent = pdev;
2410 if (pdev->is_thunderbolt)
2413 while ((parent = pci_upstream_bridge(parent)))
2414 if (parent->is_thunderbolt)
2420 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2421 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2424 /* Provide the legacy pci_dma_* API */
2425 #include <linux/pci-dma-compat.h>
2427 #define pci_printk(level, pdev, fmt, arg...) \
2428 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2430 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2431 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2432 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2433 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2434 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2435 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2436 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2437 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2439 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2440 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2442 #define pci_info_ratelimited(pdev, fmt, arg...) \
2443 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2445 #define pci_WARN(pdev, condition, fmt, arg...) \
2446 WARN(condition, "%s %s: " fmt, \
2447 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2449 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2450 WARN_ONCE(condition, "%s %s: " fmt, \
2451 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2453 #endif /* LINUX_PCI_H */