1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * For more information, please consult the following manuals (look at
10 * http://www.pcisig.com/ for how to get them):
12 * PCI BIOS Specification
13 * PCI Local Bus Specification
14 * PCI to PCI Bridge Specification
15 * PCI System Design Guide
21 #include <linux/mod_devicetable.h>
23 #include <linux/types.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/list.h>
27 #include <linux/compiler.h>
28 #include <linux/errno.h>
29 #include <linux/kobject.h>
30 #include <linux/atomic.h>
31 #include <linux/device.h>
32 #include <linux/interrupt.h>
34 #include <linux/resource_ext.h>
35 #include <uapi/linux/pci.h>
37 #include <linux/pci_ids.h>
40 * The PCI interface treats multi-function devices as independent
41 * devices. The slot/function address of each device is encoded
42 * in a single byte as follows:
47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
48 * In the interest of not exposing interfaces to user-space unnecessarily,
49 * the following kernel-only defines are being added here.
51 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
52 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
53 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
55 /* pci_slot represents a physical slot */
57 struct pci_bus *bus; /* Bus this slot is on */
58 struct list_head list; /* Node in list of slots */
59 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
64 static inline const char *pci_slot_name(const struct pci_slot *slot)
66 return kobject_name(&slot->kobj);
69 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 /* For PCI devices, the region numbers are assigned this way: */
77 /* #0-5: standard PCI resources */
79 PCI_STD_RESOURCE_END = 5,
81 /* #6: expansion ROM resource */
84 /* Device-specific resources */
87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
90 /* Resources assigned to buses behind the bridge */
91 #define PCI_BRIDGE_RESOURCE_NUM 4
94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
95 PCI_BRIDGE_RESOURCE_NUM - 1,
97 /* Total resources associated with a PCI device */
100 /* Preserve this for compatibility */
101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
105 * enum pci_interrupt_pin - PCI INTx interrupt values
106 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
107 * @PCI_INTERRUPT_INTA: PCI INTA pin
108 * @PCI_INTERRUPT_INTB: PCI INTB pin
109 * @PCI_INTERRUPT_INTC: PCI INTC pin
110 * @PCI_INTERRUPT_INTD: PCI INTD pin
112 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
113 * PCI_INTERRUPT_PIN register.
115 enum pci_interrupt_pin {
116 PCI_INTERRUPT_UNKNOWN,
123 /* The number of legacy PCI INTx interrupts */
124 #define PCI_NUM_INTX 4
127 * pci_power_t values must match the bits in the Capabilities PME_Support
128 * and Control/Status PowerState fields in the Power Management capability.
130 typedef int __bitwise pci_power_t;
132 #define PCI_D0 ((pci_power_t __force) 0)
133 #define PCI_D1 ((pci_power_t __force) 1)
134 #define PCI_D2 ((pci_power_t __force) 2)
135 #define PCI_D3hot ((pci_power_t __force) 3)
136 #define PCI_D3cold ((pci_power_t __force) 4)
137 #define PCI_UNKNOWN ((pci_power_t __force) 5)
138 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
140 /* Remember to update this when the list above changes! */
141 extern const char *pci_power_names[];
143 static inline const char *pci_power_name(pci_power_t state)
145 return pci_power_names[1 + (__force int) state];
148 #define PCI_PM_D2_DELAY 200
149 #define PCI_PM_D3_WAIT 10
150 #define PCI_PM_D3COLD_WAIT 100
151 #define PCI_PM_BUS_WAIT 50
154 * The pci_channel state describes connectivity between the CPU and
155 * the PCI device. If some PCI bus between here and the PCI device
156 * has crashed or locked up, this info is reflected here.
158 typedef unsigned int __bitwise pci_channel_state_t;
160 enum pci_channel_state {
161 /* I/O channel is in normal state */
162 pci_channel_io_normal = (__force pci_channel_state_t) 1,
164 /* I/O to channel is blocked */
165 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
167 /* PCI card is dead */
168 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
171 typedef unsigned int __bitwise pcie_reset_state_t;
173 enum pcie_reset_state {
174 /* Reset is NOT asserted (Use to deassert reset) */
175 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
177 /* Use #PERST to reset PCIe device */
178 pcie_warm_reset = (__force pcie_reset_state_t) 2,
180 /* Use PCIe Hot Reset to reset device */
181 pcie_hot_reset = (__force pcie_reset_state_t) 3
184 typedef unsigned short __bitwise pci_dev_flags_t;
186 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
187 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
188 /* Device configuration is irrevocably lost if disabled into D3 */
189 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
190 /* Provide indication device is assigned by a Virtual Machine Manager */
191 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
192 /* Flag for quirk use to store if quirk-specific ACS is enabled */
193 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
194 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
195 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
196 /* Do not use bus resets for device */
197 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
198 /* Do not use PM reset even if device advertises NoSoftRst- */
199 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
200 /* Get VPD from function 0 VPD */
201 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
202 /* A non-root bridge where translation occurs, stop alias search here */
203 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
204 /* Do not use FLR even if device advertises PCI_AF_CAP */
205 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
206 /* Don't use Relaxed Ordering for TLPs directed at this device */
207 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
208 /* Device does honor MSI masking despite saying otherwise */
209 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
212 enum pci_irq_reroute_variant {
213 INTEL_IRQ_REROUTE_VARIANT = 1,
214 MAX_IRQ_REROUTE_VARIANTS = 3
217 typedef unsigned short __bitwise pci_bus_flags_t;
219 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
220 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
221 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
222 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
225 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
226 enum pcie_link_width {
227 PCIE_LNK_WIDTH_RESRV = 0x00,
235 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
238 /* Based on the PCI Hotplug Spec, but some values are made up by us */
240 PCI_SPEED_33MHz = 0x00,
241 PCI_SPEED_66MHz = 0x01,
242 PCI_SPEED_66MHz_PCIX = 0x02,
243 PCI_SPEED_100MHz_PCIX = 0x03,
244 PCI_SPEED_133MHz_PCIX = 0x04,
245 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
246 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
247 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
248 PCI_SPEED_66MHz_PCIX_266 = 0x09,
249 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
250 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
256 PCI_SPEED_66MHz_PCIX_533 = 0x11,
257 PCI_SPEED_100MHz_PCIX_533 = 0x12,
258 PCI_SPEED_133MHz_PCIX_533 = 0x13,
259 PCIE_SPEED_2_5GT = 0x14,
260 PCIE_SPEED_5_0GT = 0x15,
261 PCIE_SPEED_8_0GT = 0x16,
262 PCIE_SPEED_16_0GT = 0x17,
263 PCI_SPEED_UNKNOWN = 0xff,
266 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
267 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
269 struct pci_cap_saved_data {
276 struct pci_cap_saved_state {
277 struct hlist_node next;
278 struct pci_cap_saved_data cap;
282 struct pcie_link_state;
287 /* The pci_dev structure describes PCI devices */
289 struct list_head bus_list; /* Node in per-bus list */
290 struct pci_bus *bus; /* Bus this device is on */
291 struct pci_bus *subordinate; /* Bus this device bridges to */
293 void *sysdata; /* Hook for sys-specific extension */
294 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
295 struct pci_slot *slot; /* Physical slot this device is in */
297 unsigned int devfn; /* Encoded device & function index */
298 unsigned short vendor;
299 unsigned short device;
300 unsigned short subsystem_vendor;
301 unsigned short subsystem_device;
302 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
303 u8 revision; /* PCI revision, low byte of class word */
304 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
305 #ifdef CONFIG_PCIEAER
306 u16 aer_cap; /* AER capability offset */
307 struct aer_stats *aer_stats; /* AER stats for this device */
309 u8 pcie_cap; /* PCIe capability offset */
310 u8 msi_cap; /* MSI capability offset */
311 u8 msix_cap; /* MSI-X capability offset */
312 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
313 u8 rom_base_reg; /* Config register controlling ROM */
314 u8 pin; /* Interrupt pin this device uses */
315 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
316 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
318 struct pci_driver *driver; /* Driver bound to this device */
319 u64 dma_mask; /* Mask of the bits of bus address this
320 device implements. Normally this is
321 0xffffffff. You only need to change
322 this if your device has broken DMA
323 or supports 64-bit transfers. */
325 struct device_dma_parameters dma_parms;
327 pci_power_t current_state; /* Current operating state. In ACPI,
328 this is D0-D3, D0 being fully
329 functional, and D3 being off. */
330 u8 pm_cap; /* PM capability offset */
331 unsigned int pme_support:5; /* Bitmask of states from which PME#
333 unsigned int pme_poll:1; /* Poll device's PME status bit */
334 unsigned int d1_support:1; /* Low power state D1 is supported */
335 unsigned int d2_support:1; /* Low power state D2 is supported */
336 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
337 unsigned int no_d3cold:1; /* D3cold is forbidden */
338 unsigned int bridge_d3:1; /* Allow D3 for bridge */
339 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
340 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
341 decoding during BAR sizing */
342 unsigned int wakeup_prepared:1;
343 unsigned int runtime_d3cold:1; /* Whether go through runtime
344 D3cold, not set for devices
345 powered on/off by the
346 corresponding bridge */
347 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
348 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
349 controlled exclusively by
351 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
353 unsigned int d3_delay; /* D3->D0 transition time in ms */
354 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
356 #ifdef CONFIG_PCIEASPM
357 struct pcie_link_state *link_state; /* ASPM link state */
358 unsigned int ltr_path:1; /* Latency Tolerance Reporting
359 supported from root to here */
361 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
363 pci_channel_state_t error_state; /* Current connectivity state */
364 struct device dev; /* Generic device interface */
366 int cfg_size; /* Size of config space */
369 * Instead of touching interrupt line and base address registers
370 * directly, use the values stored here. They might be different!
373 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
375 bool match_driver; /* Skip attaching driver */
377 unsigned int transparent:1; /* Subtractive decode bridge */
378 unsigned int io_window:1; /* Bridge has I/O window */
379 unsigned int pref_window:1; /* Bridge has pref mem window */
380 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
381 unsigned int multifunction:1; /* Multi-function device */
383 unsigned int is_busmaster:1; /* Is busmaster */
384 unsigned int no_msi:1; /* May not use MSI */
385 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
386 unsigned int block_cfg_access:1; /* Config space access blocked */
387 unsigned int broken_parity_status:1; /* Generates false positive parity */
388 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
389 unsigned int msi_enabled:1;
390 unsigned int msix_enabled:1;
391 unsigned int ari_enabled:1; /* ARI forwarding */
392 unsigned int ats_enabled:1; /* Address Translation Svc */
393 unsigned int pasid_enabled:1; /* Process Address Space ID */
394 unsigned int pri_enabled:1; /* Page Request Interface */
395 unsigned int is_managed:1;
396 unsigned int needs_freset:1; /* Requires fundamental reset */
397 unsigned int state_saved:1;
398 unsigned int is_physfn:1;
399 unsigned int is_virtfn:1;
400 unsigned int reset_fn:1;
401 unsigned int is_hotplug_bridge:1;
402 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
403 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
404 unsigned int __aer_firmware_first_valid:1;
405 unsigned int __aer_firmware_first:1;
406 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
407 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
408 unsigned int irq_managed:1;
409 unsigned int has_secondary_link:1;
410 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
411 unsigned int is_probed:1; /* Device probing in progress */
412 pci_dev_flags_t dev_flags;
413 atomic_t enable_cnt; /* pci_enable_device has been called */
415 u32 saved_config_space[16]; /* Config space saved at suspend time */
416 struct hlist_head saved_cap_space;
417 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
418 int rom_attr_enabled; /* Display of ROM attribute enabled? */
419 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
420 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
422 #ifdef CONFIG_HOTPLUG_PCI_PCIE
423 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
425 #ifdef CONFIG_PCIE_PTM
426 unsigned int ptm_root:1;
427 unsigned int ptm_enabled:1;
430 #ifdef CONFIG_PCI_MSI
431 const struct attribute_group **msi_irq_groups;
434 #ifdef CONFIG_PCI_ATS
436 struct pci_sriov *sriov; /* PF: SR-IOV info */
437 struct pci_dev *physfn; /* VF: related PF */
439 u16 ats_cap; /* ATS Capability offset */
440 u8 ats_stu; /* ATS Smallest Translation Unit */
441 atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */
443 #ifdef CONFIG_PCI_PRI
444 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
446 #ifdef CONFIG_PCI_PASID
449 phys_addr_t rom; /* Physical address if not from BAR */
450 size_t romlen; /* Length if not from BAR */
451 char *driver_override; /* Driver name to force a match */
453 unsigned long priv_flags; /* Private flags for the PCI driver */
456 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
458 #ifdef CONFIG_PCI_IOV
465 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
467 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
468 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
470 static inline int pci_channel_offline(struct pci_dev *pdev)
472 return (pdev->error_state != pci_channel_io_normal);
475 struct pci_host_bridge {
477 struct pci_bus *bus; /* Root bus */
481 struct list_head windows; /* resource_entry */
482 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
483 int (*map_irq)(const struct pci_dev *, u8, u8);
484 void (*release_fn)(struct pci_host_bridge *);
486 struct msi_controller *msi;
487 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
488 unsigned int no_ext_tags:1; /* No Extended Tags */
489 unsigned int native_aer:1; /* OS may use PCIe AER */
490 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
491 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
492 unsigned int native_pme:1; /* OS may use PCIe PME */
493 unsigned int native_ltr:1; /* OS may use PCIe LTR */
494 /* Resource alignment requirements */
495 resource_size_t (*align_resource)(struct pci_dev *dev,
496 const struct resource *res,
497 resource_size_t start,
498 resource_size_t size,
499 resource_size_t align);
500 unsigned long private[0] ____cacheline_aligned;
503 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
505 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
507 return (void *)bridge->private;
510 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
512 return container_of(priv, struct pci_host_bridge, private);
515 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
516 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
518 void pci_free_host_bridge(struct pci_host_bridge *bridge);
519 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
521 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
522 void (*release_fn)(struct pci_host_bridge *),
525 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
528 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
529 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
530 * buses below host bridges or subtractive decode bridges) go in the list.
531 * Use pci_bus_for_each_resource() to iterate through all the resources.
535 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
536 * and there's no way to program the bridge with the details of the window.
537 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
538 * decode bit set, because they are explicit and can be programmed with _SRS.
540 #define PCI_SUBTRACTIVE_DECODE 0x1
542 struct pci_bus_resource {
543 struct list_head list;
544 struct resource *res;
548 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
551 struct list_head node; /* Node in list of buses */
552 struct pci_bus *parent; /* Parent bus this bridge is on */
553 struct list_head children; /* List of child buses */
554 struct list_head devices; /* List of devices on this bus */
555 struct pci_dev *self; /* Bridge device as seen by parent */
556 struct list_head slots; /* List of slots on this bus;
557 protected by pci_slot_mutex */
558 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
559 struct list_head resources; /* Address space routed to this bus */
560 struct resource busn_res; /* Bus numbers routed to this bus */
562 struct pci_ops *ops; /* Configuration access functions */
563 struct msi_controller *msi; /* MSI controller */
564 void *sysdata; /* Hook for sys-specific extension */
565 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
567 unsigned char number; /* Bus number */
568 unsigned char primary; /* Number of primary bridge */
569 unsigned char max_bus_speed; /* enum pci_bus_speed */
570 unsigned char cur_bus_speed; /* enum pci_bus_speed */
571 #ifdef CONFIG_PCI_DOMAINS_GENERIC
577 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
578 pci_bus_flags_t bus_flags; /* Inherited by child buses */
579 struct device *bridge;
581 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
582 struct bin_attribute *legacy_mem; /* Legacy mem */
583 unsigned int is_added:1;
584 unsigned int unsafe_warn:1; /* warned about RW1C config write */
587 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
590 * Returns true if the PCI bus is root (behind host-PCI bridge),
593 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
594 * This is incorrect because "virtual" buses added for SR-IOV (via
595 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
597 static inline bool pci_is_root_bus(struct pci_bus *pbus)
599 return !(pbus->parent);
603 * pci_is_bridge - check if the PCI device is a bridge
606 * Return true if the PCI device is bridge whether it has subordinate
609 static inline bool pci_is_bridge(struct pci_dev *dev)
611 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
612 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
615 #define for_each_pci_bridge(dev, bus) \
616 list_for_each_entry(dev, &bus->devices, bus_list) \
617 if (!pci_is_bridge(dev)) {} else
619 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
621 dev = pci_physfn(dev);
622 if (pci_is_root_bus(dev->bus))
625 return dev->bus->self;
628 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
629 void pci_put_host_bridge_device(struct device *dev);
631 #ifdef CONFIG_PCI_MSI
632 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
634 return pci_dev->msi_enabled || pci_dev->msix_enabled;
637 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
640 /* Error values that may be returned by PCI functions */
641 #define PCIBIOS_SUCCESSFUL 0x00
642 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
643 #define PCIBIOS_BAD_VENDOR_ID 0x83
644 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
645 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
646 #define PCIBIOS_SET_FAILED 0x88
647 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
649 /* Translate above to generic errno for passing back through non-PCI code */
650 static inline int pcibios_err_to_errno(int err)
652 if (err <= PCIBIOS_SUCCESSFUL)
653 return err; /* Assume already errno */
656 case PCIBIOS_FUNC_NOT_SUPPORTED:
658 case PCIBIOS_BAD_VENDOR_ID:
660 case PCIBIOS_DEVICE_NOT_FOUND:
662 case PCIBIOS_BAD_REGISTER_NUMBER:
664 case PCIBIOS_SET_FAILED:
666 case PCIBIOS_BUFFER_TOO_SMALL:
673 /* Low-level architecture-dependent routines */
676 int (*add_bus)(struct pci_bus *bus);
677 void (*remove_bus)(struct pci_bus *bus);
678 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
679 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
680 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
684 * ACPI needs to be able to access PCI config space before we've done a
685 * PCI bus scan and created pci_bus structures.
687 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
688 int reg, int len, u32 *val);
689 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
690 int reg, int len, u32 val);
692 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
693 typedef u64 pci_bus_addr_t;
695 typedef u32 pci_bus_addr_t;
698 struct pci_bus_region {
699 pci_bus_addr_t start;
704 spinlock_t lock; /* Protects list, index */
705 struct list_head list; /* For IDs added at runtime */
710 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
711 * a set of callbacks in struct pci_error_handlers, that device driver
712 * will be notified of PCI bus errors, and will be driven to recovery
713 * when an error occurs.
716 typedef unsigned int __bitwise pci_ers_result_t;
718 enum pci_ers_result {
719 /* No result/none/not supported in device driver */
720 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
722 /* Device driver can recover without slot reset */
723 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
725 /* Device driver wants slot to be reset */
726 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
728 /* Device has completely failed, is unrecoverable */
729 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
731 /* Device driver is fully recovered and operational */
732 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
734 /* No AER capabilities registered for the driver */
735 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
738 /* PCI bus error event callbacks */
739 struct pci_error_handlers {
740 /* PCI bus error detected on this device */
741 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
742 enum pci_channel_state error);
744 /* MMIO has been re-enabled, but not DMA */
745 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
747 /* PCI slot has been reset */
748 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
750 /* PCI function reset prepare or completed */
751 void (*reset_prepare)(struct pci_dev *dev);
752 void (*reset_done)(struct pci_dev *dev);
754 /* Device driver may resume normal operations */
755 void (*resume)(struct pci_dev *dev);
761 struct list_head node;
763 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
764 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
765 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
766 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
767 int (*suspend_late)(struct pci_dev *dev, pm_message_t state);
768 int (*resume_early)(struct pci_dev *dev);
769 int (*resume) (struct pci_dev *dev); /* Device woken up */
770 void (*shutdown) (struct pci_dev *dev);
771 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* On PF */
772 const struct pci_error_handlers *err_handler;
773 const struct attribute_group **groups;
774 struct device_driver driver;
775 struct pci_dynids dynids;
778 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
781 * PCI_DEVICE - macro used to describe a specific PCI device
782 * @vend: the 16 bit PCI Vendor ID
783 * @dev: the 16 bit PCI Device ID
785 * This macro is used to create a struct pci_device_id that matches a
786 * specific device. The subvendor and subdevice fields will be set to
789 #define PCI_DEVICE(vend,dev) \
790 .vendor = (vend), .device = (dev), \
791 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
794 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
795 * @vend: the 16 bit PCI Vendor ID
796 * @dev: the 16 bit PCI Device ID
797 * @subvend: the 16 bit PCI Subvendor ID
798 * @subdev: the 16 bit PCI Subdevice ID
800 * This macro is used to create a struct pci_device_id that matches a
801 * specific device with subsystem information.
803 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
804 .vendor = (vend), .device = (dev), \
805 .subvendor = (subvend), .subdevice = (subdev)
808 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
809 * @dev_class: the class, subclass, prog-if triple for this device
810 * @dev_class_mask: the class mask for this device
812 * This macro is used to create a struct pci_device_id that matches a
813 * specific PCI class. The vendor, device, subvendor, and subdevice
814 * fields will be set to PCI_ANY_ID.
816 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
817 .class = (dev_class), .class_mask = (dev_class_mask), \
818 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
819 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
822 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
823 * @vend: the vendor name
824 * @dev: the 16 bit PCI Device ID
826 * This macro is used to create a struct pci_device_id that matches a
827 * specific PCI device. The subvendor, and subdevice fields will be set
828 * to PCI_ANY_ID. The macro allows the next field to follow as the device
831 #define PCI_VDEVICE(vend, dev) \
832 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
833 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
836 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
837 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
838 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
839 * @data: the driver data to be filled
841 * This macro is used to create a struct pci_device_id that matches a
842 * specific PCI device. The subvendor, and subdevice fields will be set
845 #define PCI_DEVICE_DATA(vend, dev, data) \
846 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
847 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
848 .driver_data = (kernel_ulong_t)(data)
851 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
852 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
853 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
854 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
855 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
856 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
857 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
860 /* These external functions are only available when PCI support is enabled */
863 extern unsigned int pci_flags;
865 static inline void pci_set_flags(int flags) { pci_flags = flags; }
866 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
867 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
868 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
870 void pcie_bus_configure_settings(struct pci_bus *bus);
872 enum pcie_bus_config_types {
873 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
874 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
875 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
876 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
877 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
880 extern enum pcie_bus_config_types pcie_bus_config;
882 extern struct bus_type pci_bus_type;
884 /* Do NOT directly access these two variables, unless you are arch-specific PCI
885 * code, or PCI core code. */
886 extern struct list_head pci_root_buses; /* List of all known PCI buses */
887 /* Some device drivers need know if PCI is initiated */
888 int no_pci_devices(void);
890 void pcibios_resource_survey_bus(struct pci_bus *bus);
891 void pcibios_bus_add_device(struct pci_dev *pdev);
892 void pcibios_add_bus(struct pci_bus *bus);
893 void pcibios_remove_bus(struct pci_bus *bus);
894 void pcibios_fixup_bus(struct pci_bus *);
895 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
896 /* Architecture-specific versions may override this (weak) */
897 char *pcibios_setup(char *str);
899 /* Used only when drivers/pci/setup.c is used */
900 resource_size_t pcibios_align_resource(void *, const struct resource *,
904 /* Weak but can be overriden by arch */
905 void pci_fixup_cardbus(struct pci_bus *);
907 /* Generic PCI functions used internally */
909 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
910 struct resource *res);
911 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
912 struct pci_bus_region *region);
913 void pcibios_scan_specific_bus(int busn);
914 struct pci_bus *pci_find_bus(int domain, int busnr);
915 void pci_bus_add_devices(const struct pci_bus *bus);
916 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
917 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
918 struct pci_ops *ops, void *sysdata,
919 struct list_head *resources);
920 int pci_host_probe(struct pci_host_bridge *bridge);
921 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
922 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
923 void pci_bus_release_busn_res(struct pci_bus *b);
924 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
925 struct pci_ops *ops, void *sysdata,
926 struct list_head *resources);
927 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
928 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
930 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
931 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
933 struct hotplug_slot *hotplug);
934 void pci_destroy_slot(struct pci_slot *slot);
936 void pci_dev_assign_slot(struct pci_dev *dev);
938 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
940 int pci_scan_slot(struct pci_bus *bus, int devfn);
941 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
942 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
943 unsigned int pci_scan_child_bus(struct pci_bus *bus);
944 void pci_bus_add_device(struct pci_dev *dev);
945 void pci_read_bridge_bases(struct pci_bus *child);
946 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
947 struct resource *res);
948 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
949 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
950 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
951 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
952 struct pci_dev *pci_dev_get(struct pci_dev *dev);
953 void pci_dev_put(struct pci_dev *dev);
954 void pci_remove_bus(struct pci_bus *b);
955 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
956 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
957 void pci_stop_root_bus(struct pci_bus *bus);
958 void pci_remove_root_bus(struct pci_bus *bus);
959 void pci_setup_cardbus(struct pci_bus *bus);
960 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
961 void pci_sort_breadthfirst(void);
962 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
963 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
965 /* Generic PCI functions exported to card drivers */
967 enum pci_lost_interrupt_reason {
968 PCI_LOST_IRQ_NO_INFORMATION = 0,
969 PCI_LOST_IRQ_DISABLE_MSI,
970 PCI_LOST_IRQ_DISABLE_MSIX,
971 PCI_LOST_IRQ_DISABLE_ACPI,
973 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
974 int pci_find_capability(struct pci_dev *dev, int cap);
975 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
976 int pci_find_ext_capability(struct pci_dev *dev, int cap);
977 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
978 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
979 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
980 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
982 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
983 struct pci_dev *from);
984 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
985 unsigned int ss_vendor, unsigned int ss_device,
986 struct pci_dev *from);
987 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
988 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
990 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
991 int pci_dev_present(const struct pci_device_id *ids);
993 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
995 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
996 int where, u16 *val);
997 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
998 int where, u32 *val);
999 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1001 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1002 int where, u16 val);
1003 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1004 int where, u32 val);
1006 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1007 int where, int size, u32 *val);
1008 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1009 int where, int size, u32 val);
1010 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1011 int where, int size, u32 *val);
1012 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1013 int where, int size, u32 val);
1015 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1017 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1018 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1019 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1020 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1021 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1022 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1024 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1025 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1026 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1027 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1028 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1029 u16 clear, u16 set);
1030 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1031 u32 clear, u32 set);
1033 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1036 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1039 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1042 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1045 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1048 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1051 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1054 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1057 /* User-space driven config access */
1058 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1059 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1060 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1061 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1062 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1063 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1065 int __must_check pci_enable_device(struct pci_dev *dev);
1066 int __must_check pci_enable_device_io(struct pci_dev *dev);
1067 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1068 int __must_check pci_reenable_device(struct pci_dev *);
1069 int __must_check pcim_enable_device(struct pci_dev *pdev);
1070 void pcim_pin_device(struct pci_dev *pdev);
1072 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1075 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1076 * writable and no quirk has marked the feature broken.
1078 return !pdev->broken_intx_masking;
1081 static inline int pci_is_enabled(struct pci_dev *pdev)
1083 return (atomic_read(&pdev->enable_cnt) > 0);
1086 static inline int pci_is_managed(struct pci_dev *pdev)
1088 return pdev->is_managed;
1091 void pci_disable_device(struct pci_dev *dev);
1093 extern unsigned int pcibios_max_latency;
1094 void pci_set_master(struct pci_dev *dev);
1095 void pci_clear_master(struct pci_dev *dev);
1097 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1098 int pci_set_cacheline_size(struct pci_dev *dev);
1099 #define HAVE_PCI_SET_MWI
1100 int __must_check pci_set_mwi(struct pci_dev *dev);
1101 int __must_check pcim_set_mwi(struct pci_dev *dev);
1102 int pci_try_set_mwi(struct pci_dev *dev);
1103 void pci_clear_mwi(struct pci_dev *dev);
1104 void pci_intx(struct pci_dev *dev, int enable);
1105 bool pci_check_and_mask_intx(struct pci_dev *dev);
1106 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1107 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1108 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1109 int pcix_get_max_mmrbc(struct pci_dev *dev);
1110 int pcix_get_mmrbc(struct pci_dev *dev);
1111 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1112 int pcie_get_readrq(struct pci_dev *dev);
1113 int pcie_set_readrq(struct pci_dev *dev, int rq);
1114 int pcie_get_mps(struct pci_dev *dev);
1115 int pcie_set_mps(struct pci_dev *dev, int mps);
1116 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1117 enum pci_bus_speed *speed,
1118 enum pcie_link_width *width);
1119 void pcie_print_link_status(struct pci_dev *dev);
1120 bool pcie_has_flr(struct pci_dev *dev);
1121 int pcie_flr(struct pci_dev *dev);
1122 int __pci_reset_function_locked(struct pci_dev *dev);
1123 int pci_reset_function(struct pci_dev *dev);
1124 int pci_reset_function_locked(struct pci_dev *dev);
1125 int pci_try_reset_function(struct pci_dev *dev);
1126 int pci_probe_reset_slot(struct pci_slot *slot);
1127 int pci_probe_reset_bus(struct pci_bus *bus);
1128 int pci_reset_bus(struct pci_dev *dev);
1129 void pci_reset_secondary_bus(struct pci_dev *dev);
1130 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1131 void pci_update_resource(struct pci_dev *dev, int resno);
1132 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1133 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1134 void pci_release_resource(struct pci_dev *dev, int resno);
1135 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1136 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1137 bool pci_device_is_present(struct pci_dev *pdev);
1138 void pci_ignore_hotplug(struct pci_dev *dev);
1140 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1141 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1142 const char *fmt, ...);
1143 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1145 /* ROM control related routines */
1146 int pci_enable_rom(struct pci_dev *pdev);
1147 void pci_disable_rom(struct pci_dev *pdev);
1148 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1149 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1151 /* Power management related routines */
1152 int pci_save_state(struct pci_dev *dev);
1153 void pci_restore_state(struct pci_dev *dev);
1154 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1155 int pci_load_saved_state(struct pci_dev *dev,
1156 struct pci_saved_state *state);
1157 int pci_load_and_free_saved_state(struct pci_dev *dev,
1158 struct pci_saved_state **state);
1159 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1160 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1162 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1163 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1164 u16 cap, unsigned int size);
1165 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1166 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1167 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1168 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1169 void pci_pme_active(struct pci_dev *dev, bool enable);
1170 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1171 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1172 int pci_prepare_to_sleep(struct pci_dev *dev);
1173 int pci_back_from_sleep(struct pci_dev *dev);
1174 bool pci_dev_run_wake(struct pci_dev *dev);
1175 bool pci_check_pme_status(struct pci_dev *dev);
1176 void pci_pme_wakeup_bus(struct pci_bus *bus);
1177 void pci_d3cold_enable(struct pci_dev *dev);
1178 void pci_d3cold_disable(struct pci_dev *dev);
1179 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1180 void pci_wakeup_bus(struct pci_bus *bus);
1181 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1183 /* PCI Virtual Channel */
1184 int pci_save_vc_state(struct pci_dev *dev);
1185 void pci_restore_vc_state(struct pci_dev *dev);
1186 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1188 /* For use by arch with custom probe code */
1189 void set_pcie_port_type(struct pci_dev *pdev);
1190 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1192 /* Functions for PCI Hotplug drivers to use */
1193 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1194 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1195 unsigned int pci_rescan_bus(struct pci_bus *bus);
1196 void pci_lock_rescan_remove(void);
1197 void pci_unlock_rescan_remove(void);
1199 /* Vital Product Data routines */
1200 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1201 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1202 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1204 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1205 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1206 void pci_bus_assign_resources(const struct pci_bus *bus);
1207 void pci_bus_claim_resources(struct pci_bus *bus);
1208 void pci_bus_size_bridges(struct pci_bus *bus);
1209 int pci_claim_resource(struct pci_dev *, int);
1210 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1211 void pci_assign_unassigned_resources(void);
1212 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1213 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1214 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1215 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1216 void pdev_enable_device(struct pci_dev *);
1217 int pci_enable_resources(struct pci_dev *, int mask);
1218 void pci_assign_irq(struct pci_dev *dev);
1219 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1220 #define HAVE_PCI_REQ_REGIONS 2
1221 int __must_check pci_request_regions(struct pci_dev *, const char *);
1222 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1223 void pci_release_regions(struct pci_dev *);
1224 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1225 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1226 void pci_release_region(struct pci_dev *, int);
1227 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1228 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1229 void pci_release_selected_regions(struct pci_dev *, int);
1231 /* drivers/pci/bus.c */
1232 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1233 void pci_bus_put(struct pci_bus *bus);
1234 void pci_add_resource(struct list_head *resources, struct resource *res);
1235 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1236 resource_size_t offset);
1237 void pci_free_resource_list(struct list_head *resources);
1238 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1239 unsigned int flags);
1240 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1241 void pci_bus_remove_resources(struct pci_bus *bus);
1242 int devm_request_pci_bus_resources(struct device *dev,
1243 struct list_head *resources);
1245 /* Temporary until new and working PCI SBR API in place */
1246 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1248 #define pci_bus_for_each_resource(bus, res, i) \
1250 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1253 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1254 struct resource *res, resource_size_t size,
1255 resource_size_t align, resource_size_t min,
1256 unsigned long type_mask,
1257 resource_size_t (*alignf)(void *,
1258 const struct resource *,
1264 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1265 resource_size_t size);
1266 unsigned long pci_address_to_pio(phys_addr_t addr);
1267 phys_addr_t pci_pio_to_address(unsigned long pio);
1268 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1269 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1270 phys_addr_t phys_addr);
1271 void pci_unmap_iospace(struct resource *res);
1272 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1273 resource_size_t offset,
1274 resource_size_t size);
1275 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1276 struct resource *res);
1278 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1280 struct pci_bus_region region;
1282 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1283 return region.start;
1286 /* Proper probing supporting hot-pluggable devices */
1287 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1288 const char *mod_name);
1290 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1291 #define pci_register_driver(driver) \
1292 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1294 void pci_unregister_driver(struct pci_driver *dev);
1297 * module_pci_driver() - Helper macro for registering a PCI driver
1298 * @__pci_driver: pci_driver struct
1300 * Helper macro for PCI drivers which do not do anything special in module
1301 * init/exit. This eliminates a lot of boilerplate. Each module may only
1302 * use this macro once, and calling it replaces module_init() and module_exit()
1304 #define module_pci_driver(__pci_driver) \
1305 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1308 * builtin_pci_driver() - Helper macro for registering a PCI driver
1309 * @__pci_driver: pci_driver struct
1311 * Helper macro for PCI drivers which do not do anything special in their
1312 * init code. This eliminates a lot of boilerplate. Each driver may only
1313 * use this macro once, and calling it replaces device_initcall(...)
1315 #define builtin_pci_driver(__pci_driver) \
1316 builtin_driver(__pci_driver, pci_register_driver)
1318 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1319 int pci_add_dynid(struct pci_driver *drv,
1320 unsigned int vendor, unsigned int device,
1321 unsigned int subvendor, unsigned int subdevice,
1322 unsigned int class, unsigned int class_mask,
1323 unsigned long driver_data);
1324 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1325 struct pci_dev *dev);
1326 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1329 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1331 int pci_cfg_space_size(struct pci_dev *dev);
1332 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1333 void pci_setup_bridge(struct pci_bus *bus);
1334 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1335 unsigned long type);
1337 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1338 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1340 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1341 unsigned int command_bits, u32 flags);
1343 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1344 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1345 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1346 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1347 #define PCI_IRQ_ALL_TYPES \
1348 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1350 /* kmem_cache style wrapper around pci_alloc_consistent() */
1352 #include <linux/pci-dma.h>
1353 #include <linux/dmapool.h>
1355 #define pci_pool dma_pool
1356 #define pci_pool_create(name, pdev, size, align, allocation) \
1357 dma_pool_create(name, &pdev->dev, size, align, allocation)
1358 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1359 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1360 #define pci_pool_zalloc(pool, flags, handle) \
1361 dma_pool_zalloc(pool, flags, handle)
1362 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1365 u32 vector; /* Kernel uses to write allocated vector */
1366 u16 entry; /* Driver uses to specify entry, OS writes */
1369 #ifdef CONFIG_PCI_MSI
1370 int pci_msi_vec_count(struct pci_dev *dev);
1371 void pci_disable_msi(struct pci_dev *dev);
1372 int pci_msix_vec_count(struct pci_dev *dev);
1373 void pci_disable_msix(struct pci_dev *dev);
1374 void pci_restore_msi_state(struct pci_dev *dev);
1375 int pci_msi_enabled(void);
1376 int pci_enable_msi(struct pci_dev *dev);
1377 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1378 int minvec, int maxvec);
1379 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1380 struct msix_entry *entries, int nvec)
1382 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1387 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1388 unsigned int max_vecs, unsigned int flags,
1389 const struct irq_affinity *affd);
1391 void pci_free_irq_vectors(struct pci_dev *dev);
1392 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1393 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1394 int pci_irq_get_node(struct pci_dev *pdev, int vec);
1397 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1398 static inline void pci_disable_msi(struct pci_dev *dev) { }
1399 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1400 static inline void pci_disable_msix(struct pci_dev *dev) { }
1401 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1402 static inline int pci_msi_enabled(void) { return 0; }
1403 static inline int pci_enable_msi(struct pci_dev *dev)
1405 static inline int pci_enable_msix_range(struct pci_dev *dev,
1406 struct msix_entry *entries, int minvec, int maxvec)
1408 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1409 struct msix_entry *entries, int nvec)
1413 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1414 unsigned int max_vecs, unsigned int flags,
1415 const struct irq_affinity *aff_desc)
1417 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1422 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1426 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1428 if (WARN_ON_ONCE(nr > 0))
1432 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1435 return cpu_possible_mask;
1438 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1440 return first_online_node;
1445 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1446 unsigned int max_vecs, unsigned int flags)
1448 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1453 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1454 * @d: the INTx IRQ domain
1455 * @node: the DT node for the device whose interrupt we're translating
1456 * @intspec: the interrupt specifier data from the DT
1457 * @intsize: the number of entries in @intspec
1458 * @out_hwirq: pointer at which to write the hwirq number
1459 * @out_type: pointer at which to write the interrupt type
1461 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1462 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1463 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1464 * INTx value to obtain the hwirq number.
1466 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1468 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1469 struct device_node *node,
1471 unsigned int intsize,
1472 unsigned long *out_hwirq,
1473 unsigned int *out_type)
1475 const u32 intx = intspec[0];
1477 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1480 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1484 #ifdef CONFIG_PCIEPORTBUS
1485 extern bool pcie_ports_disabled;
1486 extern bool pcie_ports_native;
1488 #define pcie_ports_disabled true
1489 #define pcie_ports_native false
1492 #ifdef CONFIG_PCIEASPM
1493 bool pcie_aspm_support_enabled(void);
1495 static inline bool pcie_aspm_support_enabled(void) { return false; }
1498 #ifdef CONFIG_PCIEAER
1499 bool pci_aer_available(void);
1501 static inline bool pci_aer_available(void) { return false; }
1504 #ifdef CONFIG_PCIE_ECRC
1505 void pcie_set_ecrc_checking(struct pci_dev *dev);
1506 void pcie_ecrc_get_policy(char *str);
1508 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1509 static inline void pcie_ecrc_get_policy(char *str) { }
1512 bool pci_ats_disabled(void);
1514 #ifdef CONFIG_PCI_ATS
1515 /* Address Translation Service */
1516 void pci_ats_init(struct pci_dev *dev);
1517 int pci_enable_ats(struct pci_dev *dev, int ps);
1518 void pci_disable_ats(struct pci_dev *dev);
1519 int pci_ats_queue_depth(struct pci_dev *dev);
1521 static inline void pci_ats_init(struct pci_dev *d) { }
1522 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1523 static inline void pci_disable_ats(struct pci_dev *d) { }
1524 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1527 #ifdef CONFIG_PCIE_PTM
1528 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1530 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1534 void pci_cfg_access_lock(struct pci_dev *dev);
1535 bool pci_cfg_access_trylock(struct pci_dev *dev);
1536 void pci_cfg_access_unlock(struct pci_dev *dev);
1539 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1540 * a PCI domain is defined to be a set of PCI buses which share
1541 * configuration space.
1543 #ifdef CONFIG_PCI_DOMAINS
1544 extern int pci_domains_supported;
1546 enum { pci_domains_supported = 0 };
1547 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1548 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1549 #endif /* CONFIG_PCI_DOMAINS */
1552 * Generic implementation for PCI domain support. If your
1553 * architecture does not need custom management of PCI
1554 * domains then this implementation will be used
1556 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1557 static inline int pci_domain_nr(struct pci_bus *bus)
1559 return bus->domain_nr;
1562 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1564 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1567 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1570 /* Some architectures require additional setup to direct VGA traffic */
1571 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1572 unsigned int command_bits, u32 flags);
1573 void pci_register_set_vga_state(arch_set_vga_state_t func);
1576 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1578 return pci_request_selected_regions(pdev,
1579 pci_select_bars(pdev, IORESOURCE_IO), name);
1583 pci_release_io_regions(struct pci_dev *pdev)
1585 return pci_release_selected_regions(pdev,
1586 pci_select_bars(pdev, IORESOURCE_IO));
1590 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1592 return pci_request_selected_regions(pdev,
1593 pci_select_bars(pdev, IORESOURCE_MEM), name);
1597 pci_release_mem_regions(struct pci_dev *pdev)
1599 return pci_release_selected_regions(pdev,
1600 pci_select_bars(pdev, IORESOURCE_MEM));
1603 #else /* CONFIG_PCI is not enabled */
1605 static inline void pci_set_flags(int flags) { }
1606 static inline void pci_add_flags(int flags) { }
1607 static inline void pci_clear_flags(int flags) { }
1608 static inline int pci_has_flag(int flag) { return 0; }
1611 * If the system does not have PCI, clearly these return errors. Define
1612 * these as simple inline functions to avoid hair in drivers.
1614 #define _PCI_NOP(o, s, t) \
1615 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1617 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1619 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1620 _PCI_NOP(o, word, u16 x) \
1621 _PCI_NOP(o, dword, u32 x)
1622 _PCI_NOP_ALL(read, *)
1623 _PCI_NOP_ALL(write,)
1625 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1626 unsigned int device,
1627 struct pci_dev *from)
1630 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1631 unsigned int device,
1632 unsigned int ss_vendor,
1633 unsigned int ss_device,
1634 struct pci_dev *from)
1637 static inline struct pci_dev *pci_get_class(unsigned int class,
1638 struct pci_dev *from)
1641 #define pci_dev_present(ids) (0)
1642 #define no_pci_devices() (1)
1643 #define pci_dev_put(dev) do { } while (0)
1645 static inline void pci_set_master(struct pci_dev *dev) { }
1646 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1647 static inline void pci_disable_device(struct pci_dev *dev) { }
1648 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1650 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1651 struct module *owner,
1652 const char *mod_name)
1654 static inline int pci_register_driver(struct pci_driver *drv)
1656 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1657 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1659 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1662 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1665 /* Power management related routines */
1666 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1667 static inline void pci_restore_state(struct pci_dev *dev) { }
1668 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1670 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1672 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1675 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1679 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1680 struct resource *res)
1682 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1684 static inline void pci_release_regions(struct pci_dev *dev) { }
1686 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1688 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1689 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1691 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1693 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1695 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1698 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1699 unsigned int bus, unsigned int devfn)
1702 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1703 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1705 #define dev_is_pci(d) (false)
1706 #define dev_is_pf(d) (false)
1707 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1709 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1710 struct device_node *node,
1712 unsigned int intsize,
1713 unsigned long *out_hwirq,
1714 unsigned int *out_type)
1716 #endif /* CONFIG_PCI */
1718 /* Include architecture-dependent settings and functions */
1720 #include <asm/pci.h>
1722 /* These two functions provide almost identical functionality. Depennding
1723 * on the architecture, one will be implemented as a wrapper around the
1724 * other (in drivers/pci/mmap.c).
1726 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1727 * is expected to be an offset within that region.
1729 * pci_mmap_page_range() is the legacy architecture-specific interface,
1730 * which accepts a "user visible" resource address converted by
1731 * pci_resource_to_user(), as used in the legacy mmap() interface in
1734 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1735 struct vm_area_struct *vma,
1736 enum pci_mmap_state mmap_state, int write_combine);
1737 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1738 struct vm_area_struct *vma,
1739 enum pci_mmap_state mmap_state, int write_combine);
1741 #ifndef arch_can_pci_mmap_wc
1742 #define arch_can_pci_mmap_wc() 0
1745 #ifndef arch_can_pci_mmap_io
1746 #define arch_can_pci_mmap_io() 0
1747 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1749 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1752 #ifndef pci_root_bus_fwnode
1753 #define pci_root_bus_fwnode(bus) NULL
1757 * These helpers provide future and backwards compatibility
1758 * for accessing popular PCI BAR info
1760 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1761 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1762 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1763 #define pci_resource_len(dev,bar) \
1764 ((pci_resource_start((dev), (bar)) == 0 && \
1765 pci_resource_end((dev), (bar)) == \
1766 pci_resource_start((dev), (bar))) ? 0 : \
1768 (pci_resource_end((dev), (bar)) - \
1769 pci_resource_start((dev), (bar)) + 1))
1772 * Similar to the helpers above, these manipulate per-pci_dev
1773 * driver-specific data. They are really just a wrapper around
1774 * the generic device structure functions of these calls.
1776 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1778 return dev_get_drvdata(&pdev->dev);
1781 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1783 dev_set_drvdata(&pdev->dev, data);
1786 static inline const char *pci_name(const struct pci_dev *pdev)
1788 return dev_name(&pdev->dev);
1793 * Some archs don't want to expose struct resource to userland as-is
1794 * in sysfs and /proc
1796 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1797 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1798 const struct resource *rsrc,
1799 resource_size_t *start, resource_size_t *end);
1801 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1802 const struct resource *rsrc, resource_size_t *start,
1803 resource_size_t *end)
1805 *start = rsrc->start;
1808 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1812 * The world is not perfect and supplies us with broken PCI devices.
1813 * For at least a part of these bugs we need a work-around, so both
1814 * generic (drivers/pci/quirks.c) and per-architecture code can define
1815 * fixup hooks to be called for particular buggy devices.
1819 u16 vendor; /* Or PCI_ANY_ID */
1820 u16 device; /* Or PCI_ANY_ID */
1821 u32 class; /* Or PCI_ANY_ID */
1822 unsigned int class_shift; /* should be 0, 8, 16 */
1823 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1826 void (*hook)(struct pci_dev *dev);
1830 enum pci_fixup_pass {
1831 pci_fixup_early, /* Before probing BARs */
1832 pci_fixup_header, /* After reading configuration header */
1833 pci_fixup_final, /* Final phase of device fixups */
1834 pci_fixup_enable, /* pci_enable_device() time */
1835 pci_fixup_resume, /* pci_device_resume() */
1836 pci_fixup_suspend, /* pci_device_suspend() */
1837 pci_fixup_resume_early, /* pci_device_resume_early() */
1838 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1841 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1842 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1843 class_shift, hook) \
1844 __ADDRESSABLE(hook) \
1845 asm(".section " #sec ", \"a\" \n" \
1847 ".short " #vendor ", " #device " \n" \
1848 ".long " #class ", " #class_shift " \n" \
1849 ".long " #hook " - . \n" \
1851 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1852 class_shift, hook) \
1853 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1856 /* Anonymous variables would be nice... */
1857 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1858 class_shift, hook) \
1859 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1860 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1861 = { vendor, device, class, class_shift, hook };
1864 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1865 class_shift, hook) \
1866 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1867 hook, vendor, device, class, class_shift, hook)
1868 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1869 class_shift, hook) \
1870 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1871 hook, vendor, device, class, class_shift, hook)
1872 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1873 class_shift, hook) \
1874 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1875 hook, vendor, device, class, class_shift, hook)
1876 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1877 class_shift, hook) \
1878 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1879 hook, vendor, device, class, class_shift, hook)
1880 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1881 class_shift, hook) \
1882 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1883 resume##hook, vendor, device, class, class_shift, hook)
1884 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1885 class_shift, hook) \
1886 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1887 resume_early##hook, vendor, device, class, class_shift, hook)
1888 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1889 class_shift, hook) \
1890 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1891 suspend##hook, vendor, device, class, class_shift, hook)
1892 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1893 class_shift, hook) \
1894 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1895 suspend_late##hook, vendor, device, class, class_shift, hook)
1897 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1898 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1899 hook, vendor, device, PCI_ANY_ID, 0, hook)
1900 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1901 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1902 hook, vendor, device, PCI_ANY_ID, 0, hook)
1903 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1904 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1905 hook, vendor, device, PCI_ANY_ID, 0, hook)
1906 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1907 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1908 hook, vendor, device, PCI_ANY_ID, 0, hook)
1909 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1910 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1911 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1912 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1913 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1914 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1915 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1916 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1917 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
1918 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1919 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1920 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1922 #ifdef CONFIG_PCI_QUIRKS
1923 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1925 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1926 struct pci_dev *dev) { }
1929 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1930 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1931 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1932 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1933 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1935 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1937 extern int pci_pci_problems;
1938 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1939 #define PCIPCI_TRITON 2
1940 #define PCIPCI_NATOMA 4
1941 #define PCIPCI_VIAETBF 8
1942 #define PCIPCI_VSFX 16
1943 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1944 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1946 extern unsigned long pci_cardbus_io_size;
1947 extern unsigned long pci_cardbus_mem_size;
1948 extern u8 pci_dfl_cache_line_size;
1949 extern u8 pci_cache_line_size;
1951 extern unsigned long pci_hotplug_io_size;
1952 extern unsigned long pci_hotplug_mem_size;
1953 extern unsigned long pci_hotplug_bus_size;
1955 /* Architecture-specific versions may override these (weak) */
1956 void pcibios_disable_device(struct pci_dev *dev);
1957 void pcibios_set_master(struct pci_dev *dev);
1958 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1959 enum pcie_reset_state state);
1960 int pcibios_add_device(struct pci_dev *dev);
1961 void pcibios_release_device(struct pci_dev *dev);
1962 void pcibios_penalize_isa_irq(int irq, int active);
1963 int pcibios_alloc_irq(struct pci_dev *dev);
1964 void pcibios_free_irq(struct pci_dev *dev);
1965 resource_size_t pcibios_default_alignment(void);
1967 #ifdef CONFIG_HIBERNATE_CALLBACKS
1968 extern struct dev_pm_ops pcibios_pm_ops;
1971 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1972 void __init pci_mmcfg_early_init(void);
1973 void __init pci_mmcfg_late_init(void);
1975 static inline void pci_mmcfg_early_init(void) { }
1976 static inline void pci_mmcfg_late_init(void) { }
1979 int pci_ext_cfg_avail(void);
1981 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1982 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1984 #ifdef CONFIG_PCI_IOV
1985 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1986 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1988 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1989 void pci_disable_sriov(struct pci_dev *dev);
1990 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
1991 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
1992 int pci_num_vf(struct pci_dev *dev);
1993 int pci_vfs_assigned(struct pci_dev *dev);
1994 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1995 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1996 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
1997 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1998 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2000 /* Arch may override these (weak) */
2001 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2002 int pcibios_sriov_disable(struct pci_dev *pdev);
2003 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2005 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2009 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2013 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2015 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2019 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2021 static inline void pci_disable_sriov(struct pci_dev *dev) { }
2022 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2023 static inline int pci_vfs_assigned(struct pci_dev *dev)
2025 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2027 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2029 #define pci_sriov_configure_simple NULL
2030 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2032 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2035 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2036 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2037 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2041 * pci_pcie_cap - get the saved PCIe capability offset
2044 * PCIe capability offset is calculated at PCI device initialization
2045 * time and saved in the data structure. This function returns saved
2046 * PCIe capability offset. Using this instead of pci_find_capability()
2047 * reduces unnecessary search in the PCI configuration space. If you
2048 * need to calculate PCIe capability offset from raw device for some
2049 * reasons, please use pci_find_capability() instead.
2051 static inline int pci_pcie_cap(struct pci_dev *dev)
2053 return dev->pcie_cap;
2057 * pci_is_pcie - check if the PCI device is PCI Express capable
2060 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2062 static inline bool pci_is_pcie(struct pci_dev *dev)
2064 return pci_pcie_cap(dev);
2068 * pcie_caps_reg - get the PCIe Capabilities Register
2071 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2073 return dev->pcie_flags_reg;
2077 * pci_pcie_type - get the PCIe device/port type
2080 static inline int pci_pcie_type(const struct pci_dev *dev)
2082 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2085 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2088 if (!pci_is_pcie(dev))
2090 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2092 if (!dev->bus->self)
2094 dev = dev->bus->self;
2099 void pci_request_acs(void);
2100 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2101 bool pci_acs_path_enabled(struct pci_dev *start,
2102 struct pci_dev *end, u16 acs_flags);
2103 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2105 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2106 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2108 /* Large Resource Data Type Tag Item Names */
2109 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2110 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2111 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2113 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2114 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2115 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2117 /* Small Resource Data Type Tag Item Names */
2118 #define PCI_VPD_STIN_END 0x0f /* End */
2120 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2122 #define PCI_VPD_SRDT_TIN_MASK 0x78
2123 #define PCI_VPD_SRDT_LEN_MASK 0x07
2124 #define PCI_VPD_LRDT_TIN_MASK 0x7f
2126 #define PCI_VPD_LRDT_TAG_SIZE 3
2127 #define PCI_VPD_SRDT_TAG_SIZE 1
2129 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2131 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2132 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2133 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2134 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2137 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2138 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2140 * Returns the extracted Large Resource Data Type length.
2142 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2144 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2148 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2149 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2151 * Returns the extracted Large Resource Data Type Tag item.
2153 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2155 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2159 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2160 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2162 * Returns the extracted Small Resource Data Type length.
2164 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2166 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2170 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2171 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2173 * Returns the extracted Small Resource Data Type Tag Item.
2175 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2177 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2181 * pci_vpd_info_field_size - Extracts the information field length
2182 * @lrdt: Pointer to the beginning of an information field header
2184 * Returns the extracted information field length.
2186 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2188 return info_field[2];
2192 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2193 * @buf: Pointer to buffered vpd data
2194 * @off: The offset into the buffer at which to begin the search
2195 * @len: The length of the vpd buffer
2196 * @rdt: The Resource Data Type to search for
2198 * Returns the index where the Resource Data Type was found or
2199 * -ENOENT otherwise.
2201 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2204 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2205 * @buf: Pointer to buffered vpd data
2206 * @off: The offset into the buffer at which to begin the search
2207 * @len: The length of the buffer area, relative to off, in which to search
2208 * @kw: The keyword to search for
2210 * Returns the index where the information field keyword was found or
2211 * -ENOENT otherwise.
2213 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2214 unsigned int len, const char *kw);
2216 /* PCI <-> OF binding helpers */
2220 void pci_set_of_node(struct pci_dev *dev);
2221 void pci_release_of_node(struct pci_dev *dev);
2222 void pci_set_bus_of_node(struct pci_bus *bus);
2223 void pci_release_bus_of_node(struct pci_bus *bus);
2224 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2225 int pci_parse_request_of_pci_ranges(struct device *dev,
2226 struct list_head *resources,
2227 struct resource **bus_range);
2229 /* Arch may override this (weak) */
2230 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2232 #else /* CONFIG_OF */
2233 static inline void pci_set_of_node(struct pci_dev *dev) { }
2234 static inline void pci_release_of_node(struct pci_dev *dev) { }
2235 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2236 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2237 static inline struct irq_domain *
2238 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2239 static inline int pci_parse_request_of_pci_ranges(struct device *dev,
2240 struct list_head *resources,
2241 struct resource **bus_range)
2245 #endif /* CONFIG_OF */
2247 static inline struct device_node *
2248 pci_device_to_OF_node(const struct pci_dev *pdev)
2250 return pdev ? pdev->dev.of_node : NULL;
2253 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2255 return bus ? bus->dev.of_node : NULL;
2259 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2262 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2264 static inline struct irq_domain *
2265 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2269 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2271 return pdev->dev.archdata.edev;
2275 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2276 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2277 int pci_for_each_dma_alias(struct pci_dev *pdev,
2278 int (*fn)(struct pci_dev *pdev,
2279 u16 alias, void *data), void *data);
2281 /* Helper functions for operation of device flag */
2282 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2284 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2286 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2288 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2290 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2292 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2296 * pci_ari_enabled - query ARI forwarding status
2299 * Returns true if ARI forwarding is enabled.
2301 static inline bool pci_ari_enabled(struct pci_bus *bus)
2303 return bus->self && bus->self->ari_enabled;
2307 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2308 * @pdev: PCI device to check
2310 * Walk upwards from @pdev and check for each encountered bridge if it's part
2311 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2312 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2314 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2316 struct pci_dev *parent = pdev;
2318 if (pdev->is_thunderbolt)
2321 while ((parent = pci_upstream_bridge(parent)))
2322 if (parent->is_thunderbolt)
2328 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2329 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2332 /* Provide the legacy pci_dma_* API */
2333 #include <linux/pci-dma-compat.h>
2335 #define pci_printk(level, pdev, fmt, arg...) \
2336 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2338 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2339 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2340 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2341 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2342 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2343 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2344 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2345 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2347 #endif /* LINUX_PCI_H */