include/linux/nvme.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Definitions for the NVM Express interface
   4  * Copyright (c) 2011-2014, Intel Corporation.
   5  */
   6
   7 #ifndef _LINUX_NVME_H
   8 #define _LINUX_NVME_H
   9
  10 #include <linux/bits.h>
  11 #include <linux/types.h>
  12 #include <linux/uuid.h>
  13
  14 /* NQN names in commands fields specified one size */
  15 #define NVMF_NQN_FIELD_LEN      256
  16
  17 /* However the max length of a qualified name is another size */
  18 #define NVMF_NQN_SIZE           223
  19
  20 #define NVMF_TRSVCID_SIZE       32
  21 #define NVMF_TRADDR_SIZE        256
  22 #define NVMF_TSAS_SIZE          256
  23
  24 #define NVME_DISC_SUBSYS_NAME   "nqn.2014-08.org.nvmexpress.discovery"
  25
  26 #define NVME_RDMA_IP_PORT       4420
  27
  28 #define NVME_NSID_ALL           0xffffffff
  29
  30 enum nvme_subsys_type {
  31         NVME_NQN_DISC   = 1,            /* Discovery type target subsystem */
  32         NVME_NQN_NVME   = 2,            /* NVME type target subsystem */
  33 };
  34
  35 /* Address Family codes for Discovery Log Page entry ADRFAM field */
  36 enum {
  37         NVMF_ADDR_FAMILY_PCI    = 0,    /* PCIe */
  38         NVMF_ADDR_FAMILY_IP4    = 1,    /* IP4 */
  39         NVMF_ADDR_FAMILY_IP6    = 2,    /* IP6 */
  40         NVMF_ADDR_FAMILY_IB     = 3,    /* InfiniBand */
  41         NVMF_ADDR_FAMILY_FC     = 4,    /* Fibre Channel */
  42 };
  43
  44 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
  45 enum {
  46         NVMF_TRTYPE_RDMA        = 1,    /* RDMA */
  47         NVMF_TRTYPE_FC          = 2,    /* Fibre Channel */
  48         NVMF_TRTYPE_TCP         = 3,    /* TCP/IP */
  49         NVMF_TRTYPE_LOOP        = 254,  /* Reserved for host usage */
  50         NVMF_TRTYPE_MAX,
  51 };
  52
  53 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
  54 enum {
  55         NVMF_TREQ_NOT_SPECIFIED = 0,            /* Not specified */
  56         NVMF_TREQ_REQUIRED      = 1,            /* Required */
  57         NVMF_TREQ_NOT_REQUIRED  = 2,            /* Not Required */
  58 #define NVME_TREQ_SECURE_CHANNEL_MASK \
  59         (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
  60
  61         NVMF_TREQ_DISABLE_SQFLOW = (1 << 2),    /* Supports SQ flow control disable */
  62 };
  63
  64 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  65  * RDMA_QPTYPE field
  66  */
  67 enum {
  68         NVMF_RDMA_QPTYPE_CONNECTED      = 1, /* Reliable Connected */
  69         NVMF_RDMA_QPTYPE_DATAGRAM       = 2, /* Reliable Datagram */
  70 };
  71
  72 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  73  * RDMA_QPTYPE field
  74  */
  75 enum {
  76         NVMF_RDMA_PRTYPE_NOT_SPECIFIED  = 1, /* No Provider Specified */
  77         NVMF_RDMA_PRTYPE_IB             = 2, /* InfiniBand */
  78         NVMF_RDMA_PRTYPE_ROCE           = 3, /* InfiniBand RoCE */
  79         NVMF_RDMA_PRTYPE_ROCEV2         = 4, /* InfiniBand RoCEV2 */
  80         NVMF_RDMA_PRTYPE_IWARP          = 5, /* IWARP */
  81 };
  82
  83 /* RDMA Connection Management Service Type codes for Discovery Log Page
  84  * entry TSAS RDMA_CMS field
  85  */
  86 enum {
  87         NVMF_RDMA_CMS_RDMA_CM   = 1, /* Sockets based endpoint addressing */
  88 };
  89
  90 #define NVME_AQ_DEPTH           32
  91 #define NVME_NR_AEN_COMMANDS    1
  92 #define NVME_AQ_BLK_MQ_DEPTH    (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
  93
  94 /*
  95  * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
  96  * NVM-Express 1.2 specification, section 4.1.2.
  97  */
  98 #define NVME_AQ_MQ_TAG_DEPTH    (NVME_AQ_BLK_MQ_DEPTH - 1)
  99
 100 enum {
 101         NVME_REG_CAP    = 0x0000,       /* Controller Capabilities */
 102         NVME_REG_VS     = 0x0008,       /* Version */
 103         NVME_REG_INTMS  = 0x000c,       /* Interrupt Mask Set */
 104         NVME_REG_INTMC  = 0x0010,       /* Interrupt Mask Clear */
 105         NVME_REG_CC     = 0x0014,       /* Controller Configuration */
 106         NVME_REG_CSTS   = 0x001c,       /* Controller Status */
 107         NVME_REG_NSSR   = 0x0020,       /* NVM Subsystem Reset */
 108         NVME_REG_AQA    = 0x0024,       /* Admin Queue Attributes */
 109         NVME_REG_ASQ    = 0x0028,       /* Admin SQ Base Address */
 110         NVME_REG_ACQ    = 0x0030,       /* Admin CQ Base Address */
 111         NVME_REG_CMBLOC = 0x0038,       /* Controller Memory Buffer Location */
 112         NVME_REG_CMBSZ  = 0x003c,       /* Controller Memory Buffer Size */
 113         NVME_REG_BPINFO = 0x0040,       /* Boot Partition Information */
 114         NVME_REG_BPRSEL = 0x0044,       /* Boot Partition Read Select */
 115         NVME_REG_BPMBL  = 0x0048,       /* Boot Partition Memory Buffer
 116                                          * Location
 117                                          */
 118         NVME_REG_PMRCAP = 0x0e00,       /* Persistent Memory Capabilities */
 119         NVME_REG_PMRCTL = 0x0e04,       /* Persistent Memory Region Control */
 120         NVME_REG_PMRSTS = 0x0e08,       /* Persistent Memory Region Status */
 121         NVME_REG_PMREBS = 0x0e0c,       /* Persistent Memory Region Elasticity
 122                                          * Buffer Size
 123                                          */
 124         NVME_REG_PMRSWTP = 0x0e10,      /* Persistent Memory Region Sustained
 125                                          * Write Throughput
 126                                          */
 127         NVME_REG_DBS    = 0x1000,       /* SQ 0 Tail Doorbell */
 128 };
 129
 130 #define NVME_CAP_MQES(cap)      ((cap) & 0xffff)
 131 #define NVME_CAP_TIMEOUT(cap)   (((cap) >> 24) & 0xff)
 132 #define NVME_CAP_STRIDE(cap)    (((cap) >> 32) & 0xf)
 133 #define NVME_CAP_NSSRC(cap)     (((cap) >> 36) & 0x1)
 134 #define NVME_CAP_MPSMIN(cap)    (((cap) >> 48) & 0xf)
 135 #define NVME_CAP_MPSMAX(cap)    (((cap) >> 52) & 0xf)
 136
 137 #define NVME_CMB_BIR(cmbloc)    ((cmbloc) & 0x7)
 138 #define NVME_CMB_OFST(cmbloc)   (((cmbloc) >> 12) & 0xfffff)
 139
 140 enum {
 141         NVME_CMBSZ_SQS          = 1 << 0,
 142         NVME_CMBSZ_CQS          = 1 << 1,
 143         NVME_CMBSZ_LISTS        = 1 << 2,
 144         NVME_CMBSZ_RDS          = 1 << 3,
 145         NVME_CMBSZ_WDS          = 1 << 4,
 146
 147         NVME_CMBSZ_SZ_SHIFT     = 12,
 148         NVME_CMBSZ_SZ_MASK      = 0xfffff,
 149
 150         NVME_CMBSZ_SZU_SHIFT    = 8,
 151         NVME_CMBSZ_SZU_MASK     = 0xf,
 152 };
 153
 154 /*
 155  * Submission and Completion Queue Entry Sizes for the NVM command set.
 156  * (In bytes and specified as a power of two (2^n)).
 157  */
 158 #define NVME_ADM_SQES       6
 159 #define NVME_NVM_IOSQES         6
 160 #define NVME_NVM_IOCQES         4
 161
 162 enum {
 163         NVME_CC_ENABLE          = 1 << 0,
 164         NVME_CC_CSS_NVM         = 0 << 4,
 165         NVME_CC_EN_SHIFT        = 0,
 166         NVME_CC_CSS_SHIFT       = 4,
 167         NVME_CC_MPS_SHIFT       = 7,
 168         NVME_CC_AMS_SHIFT       = 11,
 169         NVME_CC_SHN_SHIFT       = 14,
 170         NVME_CC_IOSQES_SHIFT    = 16,
 171         NVME_CC_IOCQES_SHIFT    = 20,
 172         NVME_CC_AMS_RR          = 0 << NVME_CC_AMS_SHIFT,
 173         NVME_CC_AMS_WRRU        = 1 << NVME_CC_AMS_SHIFT,
 174         NVME_CC_AMS_VS          = 7 << NVME_CC_AMS_SHIFT,
 175         NVME_CC_SHN_NONE        = 0 << NVME_CC_SHN_SHIFT,
 176         NVME_CC_SHN_NORMAL      = 1 << NVME_CC_SHN_SHIFT,
 177         NVME_CC_SHN_ABRUPT      = 2 << NVME_CC_SHN_SHIFT,
 178         NVME_CC_SHN_MASK        = 3 << NVME_CC_SHN_SHIFT,
 179         NVME_CC_IOSQES          = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
 180         NVME_CC_IOCQES          = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
 181         NVME_CSTS_RDY           = 1 << 0,
 182         NVME_CSTS_CFS           = 1 << 1,
 183         NVME_CSTS_NSSRO         = 1 << 4,
 184         NVME_CSTS_PP            = 1 << 5,
 185         NVME_CSTS_SHST_NORMAL   = 0 << 2,
 186         NVME_CSTS_SHST_OCCUR    = 1 << 2,
 187         NVME_CSTS_SHST_CMPLT    = 2 << 2,
 188         NVME_CSTS_SHST_MASK     = 3 << 2,
 189 };
 190
 191 struct nvme_id_power_state {
 192         __le16                  max_power;      /* centiwatts */
 193         __u8                    rsvd2;
 194         __u8                    flags;
 195         __le32                  entry_lat;      /* microseconds */
 196         __le32                  exit_lat;       /* microseconds */
 197         __u8                    read_tput;
 198         __u8                    read_lat;
 199         __u8                    write_tput;
 200         __u8                    write_lat;
 201         __le16                  idle_power;
 202         __u8                    idle_scale;
 203         __u8                    rsvd19;
 204         __le16                  active_power;
 205         __u8                    active_work_scale;
 206         __u8                    rsvd23[9];
 207 };
 208
 209 enum {
 210         NVME_PS_FLAGS_MAX_POWER_SCALE   = 1 << 0,
 211         NVME_PS_FLAGS_NON_OP_STATE      = 1 << 1,
 212 };
 213
 214 enum nvme_ctrl_attr {
 215         NVME_CTRL_ATTR_HID_128_BIT      = (1 << 0),
 216         NVME_CTRL_ATTR_TBKAS            = (1 << 6),
 217 };
 218
 219 struct nvme_id_ctrl {
 220         __le16                  vid;
 221         __le16                  ssvid;
 222         char                    sn[20];
 223         char                    mn[40];
 224         char                    fr[8];
 225         __u8                    rab;
 226         __u8                    ieee[3];
 227         __u8                    cmic;
 228         __u8                    mdts;
 229         __le16                  cntlid;
 230         __le32                  ver;
 231         __le32                  rtd3r;
 232         __le32                  rtd3e;
 233         __le32                  oaes;
 234         __le32                  ctratt;
 235         __u8                    rsvd100[28];
 236         __le16                  crdt1;
 237         __le16                  crdt2;
 238         __le16                  crdt3;
 239         __u8                    rsvd134[122];
 240         __le16                  oacs;
 241         __u8                    acl;
 242         __u8                    aerl;
 243         __u8                    frmw;
 244         __u8                    lpa;
 245         __u8                    elpe;
 246         __u8                    npss;
 247         __u8                    avscc;
 248         __u8                    apsta;
 249         __le16                  wctemp;
 250         __le16                  cctemp;
 251         __le16                  mtfa;
 252         __le32                  hmpre;
 253         __le32                  hmmin;
 254         __u8                    tnvmcap[16];
 255         __u8                    unvmcap[16];
 256         __le32                  rpmbs;
 257         __le16                  edstt;
 258         __u8                    dsto;
 259         __u8                    fwug;
 260         __le16                  kas;
 261         __le16                  hctma;
 262         __le16                  mntmt;
 263         __le16                  mxtmt;
 264         __le32                  sanicap;
 265         __le32                  hmminds;
 266         __le16                  hmmaxd;
 267         __u8                    rsvd338[4];
 268         __u8                    anatt;
 269         __u8                    anacap;
 270         __le32                  anagrpmax;
 271         __le32                  nanagrpid;
 272         __u8                    rsvd352[160];
 273         __u8                    sqes;
 274         __u8                    cqes;
 275         __le16                  maxcmd;
 276         __le32                  nn;
 277         __le16                  oncs;
 278         __le16                  fuses;
 279         __u8                    fna;
 280         __u8                    vwc;
 281         __le16                  awun;
 282         __le16                  awupf;
 283         __u8                    nvscc;
 284         __u8                    nwpc;
 285         __le16                  acwu;
 286         __u8                    rsvd534[2];
 287         __le32                  sgls;
 288         __le32                  mnan;
 289         __u8                    rsvd544[224];
 290         char                    subnqn[256];
 291         __u8                    rsvd1024[768];
 292         __le32                  ioccsz;
 293         __le32                  iorcsz;
 294         __le16                  icdoff;
 295         __u8                    ctrattr;
 296         __u8                    msdbd;
 297         __u8                    rsvd1804[244];
 298         struct nvme_id_power_state      psd[32];
 299         __u8                    vs[1024];
 300 };
 301
 302 enum {
 303         NVME_CTRL_ONCS_COMPARE                  = 1 << 0,
 304         NVME_CTRL_ONCS_WRITE_UNCORRECTABLE      = 1 << 1,
 305         NVME_CTRL_ONCS_DSM                      = 1 << 2,
 306         NVME_CTRL_ONCS_WRITE_ZEROES             = 1 << 3,
 307         NVME_CTRL_ONCS_TIMESTAMP                = 1 << 6,
 308         NVME_CTRL_VWC_PRESENT                   = 1 << 0,
 309         NVME_CTRL_OACS_SEC_SUPP                 = 1 << 0,
 310         NVME_CTRL_OACS_DIRECTIVES               = 1 << 5,
 311         NVME_CTRL_OACS_DBBUF_SUPP               = 1 << 8,
 312         NVME_CTRL_LPA_CMD_EFFECTS_LOG           = 1 << 1,
 313         NVME_CTRL_CTRATT_128_ID                 = 1 << 0,
 314         NVME_CTRL_CTRATT_NON_OP_PSP             = 1 << 1,
 315         NVME_CTRL_CTRATT_NVM_SETS               = 1 << 2,
 316         NVME_CTRL_CTRATT_READ_RECV_LVLS         = 1 << 3,
 317         NVME_CTRL_CTRATT_ENDURANCE_GROUPS       = 1 << 4,
 318         NVME_CTRL_CTRATT_PREDICTABLE_LAT        = 1 << 5,
 319         NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY  = 1 << 7,
 320         NVME_CTRL_CTRATT_UUID_LIST              = 1 << 9,
 321 };
 322
 323 struct nvme_lbaf {
 324         __le16                  ms;
 325         __u8                    ds;
 326         __u8                    rp;
 327 };
 328
 329 struct nvme_id_ns {
 330         __le64                  nsze;
 331         __le64                  ncap;
 332         __le64                  nuse;
 333         __u8                    nsfeat;
 334         __u8                    nlbaf;
 335         __u8                    flbas;
 336         __u8                    mc;
 337         __u8                    dpc;
 338         __u8                    dps;
 339         __u8                    nmic;
 340         __u8                    rescap;
 341         __u8                    fpi;
 342         __u8                    dlfeat;
 343         __le16                  nawun;
 344         __le16                  nawupf;
 345         __le16                  nacwu;
 346         __le16                  nabsn;
 347         __le16                  nabo;
 348         __le16                  nabspf;
 349         __le16                  noiob;
 350         __u8                    nvmcap[16];
 351         __le16                  npwg;
 352         __le16                  npwa;
 353         __le16                  npdg;
 354         __le16                  npda;
 355         __le16                  nows;
 356         __u8                    rsvd74[18];
 357         __le32                  anagrpid;
 358         __u8                    rsvd96[3];
 359         __u8                    nsattr;
 360         __le16                  nvmsetid;
 361         __le16                  endgid;
 362         __u8                    nguid[16];
 363         __u8                    eui64[8];
 364         struct nvme_lbaf        lbaf[16];
 365         __u8                    rsvd192[192];
 366         __u8                    vs[3712];
 367 };
 368
 369 enum {
 370         NVME_ID_CNS_NS                  = 0x00,
 371         NVME_ID_CNS_CTRL                = 0x01,
 372         NVME_ID_CNS_NS_ACTIVE_LIST      = 0x02,
 373         NVME_ID_CNS_NS_DESC_LIST        = 0x03,
 374         NVME_ID_CNS_NS_PRESENT_LIST     = 0x10,
 375         NVME_ID_CNS_NS_PRESENT          = 0x11,
 376         NVME_ID_CNS_CTRL_NS_LIST        = 0x12,
 377         NVME_ID_CNS_CTRL_LIST           = 0x13,
 378         NVME_ID_CNS_SCNDRY_CTRL_LIST    = 0x15,
 379         NVME_ID_CNS_NS_GRANULARITY      = 0x16,
 380         NVME_ID_CNS_UUID_LIST           = 0x17,
 381 };
 382
 383 enum {
 384         NVME_DIR_IDENTIFY               = 0x00,
 385         NVME_DIR_STREAMS                = 0x01,
 386         NVME_DIR_SND_ID_OP_ENABLE       = 0x01,
 387         NVME_DIR_SND_ST_OP_REL_ID       = 0x01,
 388         NVME_DIR_SND_ST_OP_REL_RSC      = 0x02,
 389         NVME_DIR_RCV_ID_OP_PARAM        = 0x01,
 390         NVME_DIR_RCV_ST_OP_PARAM        = 0x01,
 391         NVME_DIR_RCV_ST_OP_STATUS       = 0x02,
 392         NVME_DIR_RCV_ST_OP_RESOURCE     = 0x03,
 393         NVME_DIR_ENDIR                  = 0x01,
 394 };
 395
 396 enum {
 397         NVME_NS_FEAT_THIN       = 1 << 0,
 398         NVME_NS_FLBAS_LBA_MASK  = 0xf,
 399         NVME_NS_FLBAS_META_EXT  = 0x10,
 400         NVME_LBAF_RP_BEST       = 0,
 401         NVME_LBAF_RP_BETTER     = 1,
 402         NVME_LBAF_RP_GOOD       = 2,
 403         NVME_LBAF_RP_DEGRADED   = 3,
 404         NVME_NS_DPC_PI_LAST     = 1 << 4,
 405         NVME_NS_DPC_PI_FIRST    = 1 << 3,
 406         NVME_NS_DPC_PI_TYPE3    = 1 << 2,
 407         NVME_NS_DPC_PI_TYPE2    = 1 << 1,
 408         NVME_NS_DPC_PI_TYPE1    = 1 << 0,
 409         NVME_NS_DPS_PI_FIRST    = 1 << 3,
 410         NVME_NS_DPS_PI_MASK     = 0x7,
 411         NVME_NS_DPS_PI_TYPE1    = 1,
 412         NVME_NS_DPS_PI_TYPE2    = 2,
 413         NVME_NS_DPS_PI_TYPE3    = 3,
 414 };
 415
 416 struct nvme_ns_id_desc {
 417         __u8 nidt;
 418         __u8 nidl;
 419         __le16 reserved;
 420 };
 421
 422 #define NVME_NIDT_EUI64_LEN     8
 423 #define NVME_NIDT_NGUID_LEN     16
 424 #define NVME_NIDT_UUID_LEN      16
 425
 426 enum {
 427         NVME_NIDT_EUI64         = 0x01,
 428         NVME_NIDT_NGUID         = 0x02,
 429         NVME_NIDT_UUID          = 0x03,
 430 };
 431
 432 struct nvme_smart_log {
 433         __u8                    critical_warning;
 434         __u8                    temperature[2];
 435         __u8                    avail_spare;
 436         __u8                    spare_thresh;
 437         __u8                    percent_used;
 438         __u8                    endu_grp_crit_warn_sumry;
 439         __u8                    rsvd7[25];
 440         __u8                    data_units_read[16];
 441         __u8                    data_units_written[16];
 442         __u8                    host_reads[16];
 443         __u8                    host_writes[16];
 444         __u8                    ctrl_busy_time[16];
 445         __u8                    power_cycles[16];
 446         __u8                    power_on_hours[16];
 447         __u8                    unsafe_shutdowns[16];
 448         __u8                    media_errors[16];
 449         __u8                    num_err_log_entries[16];
 450         __le32                  warning_temp_time;
 451         __le32                  critical_comp_time;
 452         __le16                  temp_sensor[8];
 453         __le32                  thm_temp1_trans_count;
 454         __le32                  thm_temp2_trans_count;
 455         __le32                  thm_temp1_total_time;
 456         __le32                  thm_temp2_total_time;
 457         __u8                    rsvd232[280];
 458 };
 459
 460 struct nvme_fw_slot_info_log {
 461         __u8                    afi;
 462         __u8                    rsvd1[7];
 463         __le64                  frs[7];
 464         __u8                    rsvd64[448];
 465 };
 466
 467 enum {
 468         NVME_CMD_EFFECTS_CSUPP          = 1 << 0,
 469         NVME_CMD_EFFECTS_LBCC           = 1 << 1,
 470         NVME_CMD_EFFECTS_NCC            = 1 << 2,
 471         NVME_CMD_EFFECTS_NIC            = 1 << 3,
 472         NVME_CMD_EFFECTS_CCC            = 1 << 4,
 473         NVME_CMD_EFFECTS_CSE_MASK       = GENMASK(18, 16),
 474         NVME_CMD_EFFECTS_UUID_SEL       = 1 << 19,
 475 };
 476
 477 struct nvme_effects_log {
 478         __le32 acs[256];
 479         __le32 iocs[256];
 480         __u8   resv[2048];
 481 };
 482
 483 enum nvme_ana_state {
 484         NVME_ANA_OPTIMIZED              = 0x01,
 485         NVME_ANA_NONOPTIMIZED           = 0x02,
 486         NVME_ANA_INACCESSIBLE           = 0x03,
 487         NVME_ANA_PERSISTENT_LOSS        = 0x04,
 488         NVME_ANA_CHANGE                 = 0x0f,
 489 };
 490
 491 struct nvme_ana_group_desc {
 492         __le32  grpid;
 493         __le32  nnsids;
 494         __le64  chgcnt;
 495         __u8    state;
 496         __u8    rsvd17[15];
 497         __le32  nsids[];
 498 };
 499
 500 /* flag for the log specific field of the ANA log */
 501 #define NVME_ANA_LOG_RGO        (1 << 0)
 502
 503 struct nvme_ana_rsp_hdr {
 504         __le64  chgcnt;
 505         __le16  ngrps;
 506         __le16  rsvd10[3];
 507 };
 508
 509 enum {
 510         NVME_SMART_CRIT_SPARE           = 1 << 0,
 511         NVME_SMART_CRIT_TEMPERATURE     = 1 << 1,
 512         NVME_SMART_CRIT_RELIABILITY     = 1 << 2,
 513         NVME_SMART_CRIT_MEDIA           = 1 << 3,
 514         NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
 515 };
 516
 517 enum {
 518         NVME_AER_ERROR                  = 0,
 519         NVME_AER_SMART                  = 1,
 520         NVME_AER_NOTICE                 = 2,
 521         NVME_AER_CSS                    = 6,
 522         NVME_AER_VS                     = 7,
 523 };
 524
 525 enum {
 526         NVME_AER_NOTICE_NS_CHANGED      = 0x00,
 527         NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
 528         NVME_AER_NOTICE_ANA             = 0x03,
 529         NVME_AER_NOTICE_DISC_CHANGED    = 0xf0,
 530 };
 531
 532 enum {
 533         NVME_AEN_BIT_NS_ATTR            = 8,
 534         NVME_AEN_BIT_FW_ACT             = 9,
 535         NVME_AEN_BIT_ANA_CHANGE         = 11,
 536         NVME_AEN_BIT_DISC_CHANGE        = 31,
 537 };
 538
 539 enum {
 540         NVME_AEN_CFG_NS_ATTR            = 1 << NVME_AEN_BIT_NS_ATTR,
 541         NVME_AEN_CFG_FW_ACT             = 1 << NVME_AEN_BIT_FW_ACT,
 542         NVME_AEN_CFG_ANA_CHANGE         = 1 << NVME_AEN_BIT_ANA_CHANGE,
 543         NVME_AEN_CFG_DISC_CHANGE        = 1 << NVME_AEN_BIT_DISC_CHANGE,
 544 };
 545
 546 struct nvme_lba_range_type {
 547         __u8                    type;
 548         __u8                    attributes;
 549         __u8                    rsvd2[14];
 550         __u64                   slba;
 551         __u64                   nlb;
 552         __u8                    guid[16];
 553         __u8                    rsvd48[16];
 554 };
 555
 556 enum {
 557         NVME_LBART_TYPE_FS      = 0x01,
 558         NVME_LBART_TYPE_RAID    = 0x02,
 559         NVME_LBART_TYPE_CACHE   = 0x03,
 560         NVME_LBART_TYPE_SWAP    = 0x04,
 561
 562         NVME_LBART_ATTRIB_TEMP  = 1 << 0,
 563         NVME_LBART_ATTRIB_HIDE  = 1 << 1,
 564 };
 565
 566 struct nvme_reservation_status {
 567         __le32  gen;
 568         __u8    rtype;
 569         __u8    regctl[2];
 570         __u8    resv5[2];
 571         __u8    ptpls;
 572         __u8    resv10[13];
 573         struct {
 574                 __le16  cntlid;
 575                 __u8    rcsts;
 576                 __u8    resv3[5];
 577                 __le64  hostid;
 578                 __le64  rkey;
 579         } regctl_ds[];
 580 };
 581
 582 enum nvme_async_event_type {
 583         NVME_AER_TYPE_ERROR     = 0,
 584         NVME_AER_TYPE_SMART     = 1,
 585         NVME_AER_TYPE_NOTICE    = 2,
 586 };
 587
 588 /* I/O commands */
 589
 590 enum nvme_opcode {
 591         nvme_cmd_flush          = 0x00,
 592         nvme_cmd_write          = 0x01,
 593         nvme_cmd_read           = 0x02,
 594         nvme_cmd_write_uncor    = 0x04,
 595         nvme_cmd_compare        = 0x05,
 596         nvme_cmd_write_zeroes   = 0x08,
 597         nvme_cmd_dsm            = 0x09,
 598         nvme_cmd_verify         = 0x0c,
 599         nvme_cmd_resv_register  = 0x0d,
 600         nvme_cmd_resv_report    = 0x0e,
 601         nvme_cmd_resv_acquire   = 0x11,
 602         nvme_cmd_resv_release   = 0x15,
 603 };
 604
 605 #define nvme_opcode_name(opcode)        { opcode, #opcode }
 606 #define show_nvm_opcode_name(val)                               \
 607         __print_symbolic(val,                                   \
 608                 nvme_opcode_name(nvme_cmd_flush),               \
 609                 nvme_opcode_name(nvme_cmd_write),               \
 610                 nvme_opcode_name(nvme_cmd_read),                \
 611                 nvme_opcode_name(nvme_cmd_write_uncor),         \
 612                 nvme_opcode_name(nvme_cmd_compare),             \
 613                 nvme_opcode_name(nvme_cmd_write_zeroes),        \
 614                 nvme_opcode_name(nvme_cmd_dsm),                 \
 615                 nvme_opcode_name(nvme_cmd_resv_register),       \
 616                 nvme_opcode_name(nvme_cmd_resv_report),         \
 617                 nvme_opcode_name(nvme_cmd_resv_acquire),        \
 618                 nvme_opcode_name(nvme_cmd_resv_release))
 619
 620
 621 /*
 622  * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
 623  *
 624  * @NVME_SGL_FMT_ADDRESS:     absolute address of the data block
 625  * @NVME_SGL_FMT_OFFSET:      relative offset of the in-capsule data block
 626  * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
 627  * @NVME_SGL_FMT_INVALIDATE:  RDMA transport specific remote invalidation
 628  *                            request subtype
 629  */
 630 enum {
 631         NVME_SGL_FMT_ADDRESS            = 0x00,
 632         NVME_SGL_FMT_OFFSET             = 0x01,
 633         NVME_SGL_FMT_TRANSPORT_A        = 0x0A,
 634         NVME_SGL_FMT_INVALIDATE         = 0x0f,
 635 };
 636
 637 /*
 638  * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
 639  *
 640  * For struct nvme_sgl_desc:
 641  *   @NVME_SGL_FMT_DATA_DESC:           data block descriptor
 642  *   @NVME_SGL_FMT_SEG_DESC:            sgl segment descriptor
 643  *   @NVME_SGL_FMT_LAST_SEG_DESC:       last sgl segment descriptor
 644  *
 645  * For struct nvme_keyed_sgl_desc:
 646  *   @NVME_KEY_SGL_FMT_DATA_DESC:       keyed data block descriptor
 647  *
 648  * Transport-specific SGL types:
 649  *   @NVME_TRANSPORT_SGL_DATA_DESC:     Transport SGL data dlock descriptor
 650  */
 651 enum {
 652         NVME_SGL_FMT_DATA_DESC          = 0x00,
 653         NVME_SGL_FMT_SEG_DESC           = 0x02,
 654         NVME_SGL_FMT_LAST_SEG_DESC      = 0x03,
 655         NVME_KEY_SGL_FMT_DATA_DESC      = 0x04,
 656         NVME_TRANSPORT_SGL_DATA_DESC    = 0x05,
 657 };
 658
 659 struct nvme_sgl_desc {
 660         __le64  addr;
 661         __le32  length;
 662         __u8    rsvd[3];
 663         __u8    type;
 664 };
 665
 666 struct nvme_keyed_sgl_desc {
 667         __le64  addr;
 668         __u8    length[3];
 669         __u8    key[4];
 670         __u8    type;
 671 };
 672
 673 union nvme_data_ptr {
 674         struct {
 675                 __le64  prp1;
 676                 __le64  prp2;
 677         };
 678         struct nvme_sgl_desc    sgl;
 679         struct nvme_keyed_sgl_desc ksgl;
 680 };
 681
 682 /*
 683  * Lowest two bits of our flags field (FUSE field in the spec):
 684  *
 685  * @NVME_CMD_FUSE_FIRST:   Fused Operation, first command
 686  * @NVME_CMD_FUSE_SECOND:  Fused Operation, second command
 687  *
 688  * Highest two bits in our flags field (PSDT field in the spec):
 689  *
 690  * @NVME_CMD_PSDT_SGL_METABUF:  Use SGLS for this transfer,
 691  *      If used, MPTR contains addr of single physical buffer (byte aligned).
 692  * @NVME_CMD_PSDT_SGL_METASEG:  Use SGLS for this transfer,
 693  *      If used, MPTR contains an address of an SGL segment containing
 694  *      exactly 1 SGL descriptor (qword aligned).
 695  */
 696 enum {
 697         NVME_CMD_FUSE_FIRST     = (1 << 0),
 698         NVME_CMD_FUSE_SECOND    = (1 << 1),
 699
 700         NVME_CMD_SGL_METABUF    = (1 << 6),
 701         NVME_CMD_SGL_METASEG    = (1 << 7),
 702         NVME_CMD_SGL_ALL        = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
 703 };
 704
 705 struct nvme_common_command {
 706         __u8                    opcode;
 707         __u8                    flags;
 708         __u16                   command_id;
 709         __le32                  nsid;
 710         __le32                  cdw2[2];
 711         __le64                  metadata;
 712         union nvme_data_ptr     dptr;
 713         __le32                  cdw10;
 714         __le32                  cdw11;
 715         __le32                  cdw12;
 716         __le32                  cdw13;
 717         __le32                  cdw14;
 718         __le32                  cdw15;
 719 };
 720
 721 struct nvme_rw_command {
 722         __u8                    opcode;
 723         __u8                    flags;
 724         __u16                   command_id;
 725         __le32                  nsid;
 726         __u64                   rsvd2;
 727         __le64                  metadata;
 728         union nvme_data_ptr     dptr;
 729         __le64                  slba;
 730         __le16                  length;
 731         __le16                  control;
 732         __le32                  dsmgmt;
 733         __le32                  reftag;
 734         __le16                  apptag;
 735         __le16                  appmask;
 736 };
 737
 738 enum {
 739         NVME_RW_LR                      = 1 << 15,
 740         NVME_RW_FUA                     = 1 << 14,
 741         NVME_RW_DSM_FREQ_UNSPEC         = 0,
 742         NVME_RW_DSM_FREQ_TYPICAL        = 1,
 743         NVME_RW_DSM_FREQ_RARE           = 2,
 744         NVME_RW_DSM_FREQ_READS          = 3,
 745         NVME_RW_DSM_FREQ_WRITES         = 4,
 746         NVME_RW_DSM_FREQ_RW             = 5,
 747         NVME_RW_DSM_FREQ_ONCE           = 6,
 748         NVME_RW_DSM_FREQ_PREFETCH       = 7,
 749         NVME_RW_DSM_FREQ_TEMP           = 8,
 750         NVME_RW_DSM_LATENCY_NONE        = 0 << 4,
 751         NVME_RW_DSM_LATENCY_IDLE        = 1 << 4,
 752         NVME_RW_DSM_LATENCY_NORM        = 2 << 4,
 753         NVME_RW_DSM_LATENCY_LOW         = 3 << 4,
 754         NVME_RW_DSM_SEQ_REQ             = 1 << 6,
 755         NVME_RW_DSM_COMPRESSED          = 1 << 7,
 756         NVME_RW_PRINFO_PRCHK_REF        = 1 << 10,
 757         NVME_RW_PRINFO_PRCHK_APP        = 1 << 11,
 758         NVME_RW_PRINFO_PRCHK_GUARD      = 1 << 12,
 759         NVME_RW_PRINFO_PRACT            = 1 << 13,
 760         NVME_RW_DTYPE_STREAMS           = 1 << 4,
 761 };
 762
 763 struct nvme_dsm_cmd {
 764         __u8                    opcode;
 765         __u8                    flags;
 766         __u16                   command_id;
 767         __le32                  nsid;
 768         __u64                   rsvd2[2];
 769         union nvme_data_ptr     dptr;
 770         __le32                  nr;
 771         __le32                  attributes;
 772         __u32                   rsvd12[4];
 773 };
 774
 775 enum {
 776         NVME_DSMGMT_IDR         = 1 << 0,
 777         NVME_DSMGMT_IDW         = 1 << 1,
 778         NVME_DSMGMT_AD          = 1 << 2,
 779 };
 780
 781 #define NVME_DSM_MAX_RANGES     256
 782
 783 struct nvme_dsm_range {
 784         __le32                  cattr;
 785         __le32                  nlb;
 786         __le64                  slba;
 787 };
 788
 789 struct nvme_write_zeroes_cmd {
 790         __u8                    opcode;
 791         __u8                    flags;
 792         __u16                   command_id;
 793         __le32                  nsid;
 794         __u64                   rsvd2;
 795         __le64                  metadata;
 796         union nvme_data_ptr     dptr;
 797         __le64                  slba;
 798         __le16                  length;
 799         __le16                  control;
 800         __le32                  dsmgmt;
 801         __le32                  reftag;
 802         __le16                  apptag;
 803         __le16                  appmask;
 804 };
 805
 806 /* Features */
 807
 808 struct nvme_feat_auto_pst {
 809         __le64 entries[32];
 810 };
 811
 812 enum {
 813         NVME_HOST_MEM_ENABLE    = (1 << 0),
 814         NVME_HOST_MEM_RETURN    = (1 << 1),
 815 };
 816
 817 struct nvme_feat_host_behavior {
 818         __u8 acre;
 819         __u8 resv1[511];
 820 };
 821
 822 enum {
 823         NVME_ENABLE_ACRE        = 1,
 824 };
 825
 826 /* Admin commands */
 827
 828 enum nvme_admin_opcode {
 829         nvme_admin_delete_sq            = 0x00,
 830         nvme_admin_create_sq            = 0x01,
 831         nvme_admin_get_log_page         = 0x02,
 832         nvme_admin_delete_cq            = 0x04,
 833         nvme_admin_create_cq            = 0x05,
 834         nvme_admin_identify             = 0x06,
 835         nvme_admin_abort_cmd            = 0x08,
 836         nvme_admin_set_features         = 0x09,
 837         nvme_admin_get_features         = 0x0a,
 838         nvme_admin_async_event          = 0x0c,
 839         nvme_admin_ns_mgmt              = 0x0d,
 840         nvme_admin_activate_fw          = 0x10,
 841         nvme_admin_download_fw          = 0x11,
 842         nvme_admin_dev_self_test        = 0x14,
 843         nvme_admin_ns_attach            = 0x15,
 844         nvme_admin_keep_alive           = 0x18,
 845         nvme_admin_directive_send       = 0x19,
 846         nvme_admin_directive_recv       = 0x1a,
 847         nvme_admin_virtual_mgmt         = 0x1c,
 848         nvme_admin_nvme_mi_send         = 0x1d,
 849         nvme_admin_nvme_mi_recv         = 0x1e,
 850         nvme_admin_dbbuf                = 0x7C,
 851         nvme_admin_format_nvm           = 0x80,
 852         nvme_admin_security_send        = 0x81,
 853         nvme_admin_security_recv        = 0x82,
 854         nvme_admin_sanitize_nvm         = 0x84,
 855         nvme_admin_get_lba_status       = 0x86,
 856 };
 857
 858 #define nvme_admin_opcode_name(opcode)  { opcode, #opcode }
 859 #define show_admin_opcode_name(val)                                     \
 860         __print_symbolic(val,                                           \
 861                 nvme_admin_opcode_name(nvme_admin_delete_sq),           \
 862                 nvme_admin_opcode_name(nvme_admin_create_sq),           \
 863                 nvme_admin_opcode_name(nvme_admin_get_log_page),        \
 864                 nvme_admin_opcode_name(nvme_admin_delete_cq),           \
 865                 nvme_admin_opcode_name(nvme_admin_create_cq),           \
 866                 nvme_admin_opcode_name(nvme_admin_identify),            \
 867                 nvme_admin_opcode_name(nvme_admin_abort_cmd),           \
 868                 nvme_admin_opcode_name(nvme_admin_set_features),        \
 869                 nvme_admin_opcode_name(nvme_admin_get_features),        \
 870                 nvme_admin_opcode_name(nvme_admin_async_event),         \
 871                 nvme_admin_opcode_name(nvme_admin_ns_mgmt),             \
 872                 nvme_admin_opcode_name(nvme_admin_activate_fw),         \
 873                 nvme_admin_opcode_name(nvme_admin_download_fw),         \
 874                 nvme_admin_opcode_name(nvme_admin_ns_attach),           \
 875                 nvme_admin_opcode_name(nvme_admin_keep_alive),          \
 876                 nvme_admin_opcode_name(nvme_admin_directive_send),      \
 877                 nvme_admin_opcode_name(nvme_admin_directive_recv),      \
 878                 nvme_admin_opcode_name(nvme_admin_dbbuf),               \
 879                 nvme_admin_opcode_name(nvme_admin_format_nvm),          \
 880                 nvme_admin_opcode_name(nvme_admin_security_send),       \
 881                 nvme_admin_opcode_name(nvme_admin_security_recv),       \
 882                 nvme_admin_opcode_name(nvme_admin_sanitize_nvm),        \
 883                 nvme_admin_opcode_name(nvme_admin_get_lba_status))
 884
 885 enum {
 886         NVME_QUEUE_PHYS_CONTIG  = (1 << 0),
 887         NVME_CQ_IRQ_ENABLED     = (1 << 1),
 888         NVME_SQ_PRIO_URGENT     = (0 << 1),
 889         NVME_SQ_PRIO_HIGH       = (1 << 1),
 890         NVME_SQ_PRIO_MEDIUM     = (2 << 1),
 891         NVME_SQ_PRIO_LOW        = (3 << 1),
 892         NVME_FEAT_ARBITRATION   = 0x01,
 893         NVME_FEAT_POWER_MGMT    = 0x02,
 894         NVME_FEAT_LBA_RANGE     = 0x03,
 895         NVME_FEAT_TEMP_THRESH   = 0x04,
 896         NVME_FEAT_ERR_RECOVERY  = 0x05,
 897         NVME_FEAT_VOLATILE_WC   = 0x06,
 898         NVME_FEAT_NUM_QUEUES    = 0x07,
 899         NVME_FEAT_IRQ_COALESCE  = 0x08,
 900         NVME_FEAT_IRQ_CONFIG    = 0x09,
 901         NVME_FEAT_WRITE_ATOMIC  = 0x0a,
 902         NVME_FEAT_ASYNC_EVENT   = 0x0b,
 903         NVME_FEAT_AUTO_PST      = 0x0c,
 904         NVME_FEAT_HOST_MEM_BUF  = 0x0d,
 905         NVME_FEAT_TIMESTAMP     = 0x0e,
 906         NVME_FEAT_KATO          = 0x0f,
 907         NVME_FEAT_HCTM          = 0x10,
 908         NVME_FEAT_NOPSC         = 0x11,
 909         NVME_FEAT_RRL           = 0x12,
 910         NVME_FEAT_PLM_CONFIG    = 0x13,
 911         NVME_FEAT_PLM_WINDOW    = 0x14,
 912         NVME_FEAT_HOST_BEHAVIOR = 0x16,
 913         NVME_FEAT_SANITIZE      = 0x17,
 914         NVME_FEAT_SW_PROGRESS   = 0x80,
 915         NVME_FEAT_HOST_ID       = 0x81,
 916         NVME_FEAT_RESV_MASK     = 0x82,
 917         NVME_FEAT_RESV_PERSIST  = 0x83,
 918         NVME_FEAT_WRITE_PROTECT = 0x84,
 919         NVME_LOG_ERROR          = 0x01,
 920         NVME_LOG_SMART          = 0x02,
 921         NVME_LOG_FW_SLOT        = 0x03,
 922         NVME_LOG_CHANGED_NS     = 0x04,
 923         NVME_LOG_CMD_EFFECTS    = 0x05,
 924         NVME_LOG_DEVICE_SELF_TEST = 0x06,
 925         NVME_LOG_TELEMETRY_HOST = 0x07,
 926         NVME_LOG_TELEMETRY_CTRL = 0x08,
 927         NVME_LOG_ENDURANCE_GROUP = 0x09,
 928         NVME_LOG_ANA            = 0x0c,
 929         NVME_LOG_DISC           = 0x70,
 930         NVME_LOG_RESERVATION    = 0x80,
 931         NVME_FWACT_REPL         = (0 << 3),
 932         NVME_FWACT_REPL_ACTV    = (1 << 3),
 933         NVME_FWACT_ACTV         = (2 << 3),
 934 };
 935
 936 /* NVMe Namespace Write Protect State */
 937 enum {
 938         NVME_NS_NO_WRITE_PROTECT = 0,
 939         NVME_NS_WRITE_PROTECT,
 940         NVME_NS_WRITE_PROTECT_POWER_CYCLE,
 941         NVME_NS_WRITE_PROTECT_PERMANENT,
 942 };
 943
 944 #define NVME_MAX_CHANGED_NAMESPACES     1024
 945
 946 struct nvme_identify {
 947         __u8                    opcode;
 948         __u8                    flags;
 949         __u16                   command_id;
 950         __le32                  nsid;
 951         __u64                   rsvd2[2];
 952         union nvme_data_ptr     dptr;
 953         __u8                    cns;
 954         __u8                    rsvd3;
 955         __le16                  ctrlid;
 956         __u32                   rsvd11[5];
 957 };
 958
 959 #define NVME_IDENTIFY_DATA_SIZE 4096
 960
 961 struct nvme_features {
 962         __u8                    opcode;
 963         __u8                    flags;
 964         __u16                   command_id;
 965         __le32                  nsid;
 966         __u64                   rsvd2[2];
 967         union nvme_data_ptr     dptr;
 968         __le32                  fid;
 969         __le32                  dword11;
 970         __le32                  dword12;
 971         __le32                  dword13;
 972         __le32                  dword14;
 973         __le32                  dword15;
 974 };
 975
 976 struct nvme_host_mem_buf_desc {
 977         __le64                  addr;
 978         __le32                  size;
 979         __u32                   rsvd;
 980 };
 981
 982 struct nvme_create_cq {
 983         __u8                    opcode;
 984         __u8                    flags;
 985         __u16                   command_id;
 986         __u32                   rsvd1[5];
 987         __le64                  prp1;
 988         __u64                   rsvd8;
 989         __le16                  cqid;
 990         __le16                  qsize;
 991         __le16                  cq_flags;
 992         __le16                  irq_vector;
 993         __u32                   rsvd12[4];
 994 };
 995
 996 struct nvme_create_sq {
 997         __u8                    opcode;
 998         __u8                    flags;
 999         __u16                   command_id;
1000         __u32                   rsvd1[5];
1001         __le64                  prp1;
1002         __u64                   rsvd8;
1003         __le16                  sqid;
1004         __le16                  qsize;
1005         __le16                  sq_flags;
1006         __le16                  cqid;
1007         __u32                   rsvd12[4];
1008 };
1009
1010 struct nvme_delete_queue {
1011         __u8                    opcode;
1012         __u8                    flags;
1013         __u16                   command_id;
1014         __u32                   rsvd1[9];
1015         __le16                  qid;
1016         __u16                   rsvd10;
1017         __u32                   rsvd11[5];
1018 };
1019
1020 struct nvme_abort_cmd {
1021         __u8                    opcode;
1022         __u8                    flags;
1023         __u16                   command_id;
1024         __u32                   rsvd1[9];
1025         __le16                  sqid;
1026         __u16                   cid;
1027         __u32                   rsvd11[5];
1028 };
1029
1030 struct nvme_download_firmware {
1031         __u8                    opcode;
1032         __u8                    flags;
1033         __u16                   command_id;
1034         __u32                   rsvd1[5];
1035         union nvme_data_ptr     dptr;
1036         __le32                  numd;
1037         __le32                  offset;
1038         __u32                   rsvd12[4];
1039 };
1040
1041 struct nvme_format_cmd {
1042         __u8                    opcode;
1043         __u8                    flags;
1044         __u16                   command_id;
1045         __le32                  nsid;
1046         __u64                   rsvd2[4];
1047         __le32                  cdw10;
1048         __u32                   rsvd11[5];
1049 };
1050
1051 struct nvme_get_log_page_command {
1052         __u8                    opcode;
1053         __u8                    flags;
1054         __u16                   command_id;
1055         __le32                  nsid;
1056         __u64                   rsvd2[2];
1057         union nvme_data_ptr     dptr;
1058         __u8                    lid;
1059         __u8                    lsp; /* upper 4 bits reserved */
1060         __le16                  numdl;
1061         __le16                  numdu;
1062         __u16                   rsvd11;
1063         union {
1064                 struct {
1065                         __le32 lpol;
1066                         __le32 lpou;
1067                 };
1068                 __le64 lpo;
1069         };
1070         __u32                   rsvd14[2];
1071 };
1072
1073 struct nvme_directive_cmd {
1074         __u8                    opcode;
1075         __u8                    flags;
1076         __u16                   command_id;
1077         __le32                  nsid;
1078         __u64                   rsvd2[2];
1079         union nvme_data_ptr     dptr;
1080         __le32                  numd;
1081         __u8                    doper;
1082         __u8                    dtype;
1083         __le16                  dspec;
1084         __u8                    endir;
1085         __u8                    tdtype;
1086         __u16                   rsvd15;
1087
1088         __u32                   rsvd16[3];
1089 };
1090
1091 /*
1092  * Fabrics subcommands.
1093  */
1094 enum nvmf_fabrics_opcode {
1095         nvme_fabrics_command            = 0x7f,
1096 };
1097
1098 enum nvmf_capsule_command {
1099         nvme_fabrics_type_property_set  = 0x00,
1100         nvme_fabrics_type_connect       = 0x01,
1101         nvme_fabrics_type_property_get  = 0x04,
1102 };
1103
1104 #define nvme_fabrics_type_name(type)   { type, #type }
1105 #define show_fabrics_type_name(type)                                    \
1106         __print_symbolic(type,                                          \
1107                 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1108                 nvme_fabrics_type_name(nvme_fabrics_type_connect),      \
1109                 nvme_fabrics_type_name(nvme_fabrics_type_property_get))
1110
1111 /*
1112  * If not fabrics command, fctype will be ignored.
1113  */
1114 #define show_opcode_name(qid, opcode, fctype)                   \
1115         ((opcode) == nvme_fabrics_command ?                     \
1116          show_fabrics_type_name(fctype) :                       \
1117         ((qid) ?                                                \
1118          show_nvm_opcode_name(opcode) :                         \
1119          show_admin_opcode_name(opcode)))
1120
1121 struct nvmf_common_command {
1122         __u8    opcode;
1123         __u8    resv1;
1124         __u16   command_id;
1125         __u8    fctype;
1126         __u8    resv2[35];
1127         __u8    ts[24];
1128 };
1129
1130 /*
1131  * The legal cntlid range a NVMe Target will provide.
1132  * Note that cntlid of value 0 is considered illegal in the fabrics world.
1133  * Devices based on earlier specs did not have the subsystem concept;
1134  * therefore, those devices had their cntlid value set to 0 as a result.
1135  */
1136 #define NVME_CNTLID_MIN         1
1137 #define NVME_CNTLID_MAX         0xffef
1138 #define NVME_CNTLID_DYNAMIC     0xffff
1139
1140 #define MAX_DISC_LOGS   255
1141
1142 /* Discovery log page entry */
1143 struct nvmf_disc_rsp_page_entry {
1144         __u8            trtype;
1145         __u8            adrfam;
1146         __u8            subtype;
1147         __u8            treq;
1148         __le16          portid;
1149         __le16          cntlid;
1150         __le16          asqsz;
1151         __u8            resv8[22];
1152         char            trsvcid[NVMF_TRSVCID_SIZE];
1153         __u8            resv64[192];
1154         char            subnqn[NVMF_NQN_FIELD_LEN];
1155         char            traddr[NVMF_TRADDR_SIZE];
1156         union tsas {
1157                 char            common[NVMF_TSAS_SIZE];
1158                 struct rdma {
1159                         __u8    qptype;
1160                         __u8    prtype;
1161                         __u8    cms;
1162                         __u8    resv3[5];
1163                         __u16   pkey;
1164                         __u8    resv10[246];
1165                 } rdma;
1166         } tsas;
1167 };
1168
1169 /* Discovery log page header */
1170 struct nvmf_disc_rsp_page_hdr {
1171         __le64          genctr;
1172         __le64          numrec;
1173         __le16          recfmt;
1174         __u8            resv14[1006];
1175         struct nvmf_disc_rsp_page_entry entries[0];
1176 };
1177
1178 enum {
1179         NVME_CONNECT_DISABLE_SQFLOW     = (1 << 2),
1180 };
1181
1182 struct nvmf_connect_command {
1183         __u8            opcode;
1184         __u8            resv1;
1185         __u16           command_id;
1186         __u8            fctype;
1187         __u8            resv2[19];
1188         union nvme_data_ptr dptr;
1189         __le16          recfmt;
1190         __le16          qid;
1191         __le16          sqsize;
1192         __u8            cattr;
1193         __u8            resv3;
1194         __le32          kato;
1195         __u8            resv4[12];
1196 };
1197
1198 struct nvmf_connect_data {
1199         uuid_t          hostid;
1200         __le16          cntlid;
1201         char            resv4[238];
1202         char            subsysnqn[NVMF_NQN_FIELD_LEN];
1203         char            hostnqn[NVMF_NQN_FIELD_LEN];
1204         char            resv5[256];
1205 };
1206
1207 struct nvmf_property_set_command {
1208         __u8            opcode;
1209         __u8            resv1;
1210         __u16           command_id;
1211         __u8            fctype;
1212         __u8            resv2[35];
1213         __u8            attrib;
1214         __u8            resv3[3];
1215         __le32          offset;
1216         __le64          value;
1217         __u8            resv4[8];
1218 };
1219
1220 struct nvmf_property_get_command {
1221         __u8            opcode;
1222         __u8            resv1;
1223         __u16           command_id;
1224         __u8            fctype;
1225         __u8            resv2[35];
1226         __u8            attrib;
1227         __u8            resv3[3];
1228         __le32          offset;
1229         __u8            resv4[16];
1230 };
1231
1232 struct nvme_dbbuf {
1233         __u8                    opcode;
1234         __u8                    flags;
1235         __u16                   command_id;
1236         __u32                   rsvd1[5];
1237         __le64                  prp1;
1238         __le64                  prp2;
1239         __u32                   rsvd12[6];
1240 };
1241
1242 struct streams_directive_params {
1243         __le16  msl;
1244         __le16  nssa;
1245         __le16  nsso;
1246         __u8    rsvd[10];
1247         __le32  sws;
1248         __le16  sgs;
1249         __le16  nsa;
1250         __le16  nso;
1251         __u8    rsvd2[6];
1252 };
1253
1254 struct nvme_command {
1255         union {
1256                 struct nvme_common_command common;
1257                 struct nvme_rw_command rw;
1258                 struct nvme_identify identify;
1259                 struct nvme_features features;
1260                 struct nvme_create_cq create_cq;
1261                 struct nvme_create_sq create_sq;
1262                 struct nvme_delete_queue delete_queue;
1263                 struct nvme_download_firmware dlfw;
1264                 struct nvme_format_cmd format;
1265                 struct nvme_dsm_cmd dsm;
1266                 struct nvme_write_zeroes_cmd write_zeroes;
1267                 struct nvme_abort_cmd abort;
1268                 struct nvme_get_log_page_command get_log_page;
1269                 struct nvmf_common_command fabrics;
1270                 struct nvmf_connect_command connect;
1271                 struct nvmf_property_set_command prop_set;
1272                 struct nvmf_property_get_command prop_get;
1273                 struct nvme_dbbuf dbbuf;
1274                 struct nvme_directive_cmd directive;
1275         };
1276 };
1277
1278 static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1279 {
1280         return cmd->common.opcode == nvme_fabrics_command;
1281 }
1282
1283 struct nvme_error_slot {
1284         __le64          error_count;
1285         __le16          sqid;
1286         __le16          cmdid;
1287         __le16          status_field;
1288         __le16          param_error_location;
1289         __le64          lba;
1290         __le32          nsid;
1291         __u8            vs;
1292         __u8            resv[3];
1293         __le64          cs;
1294         __u8            resv2[24];
1295 };
1296
1297 static inline bool nvme_is_write(struct nvme_command *cmd)
1298 {
1299         /*
1300          * What a mess...
1301          *
1302          * Why can't we simply have a Fabrics In and Fabrics out command?
1303          */
1304         if (unlikely(nvme_is_fabrics(cmd)))
1305                 return cmd->fabrics.fctype & 1;
1306         return cmd->common.opcode & 1;
1307 }
1308
1309 enum {
1310         /*
1311          * Generic Command Status:
1312          */
1313         NVME_SC_SUCCESS                 = 0x0,
1314         NVME_SC_INVALID_OPCODE          = 0x1,
1315         NVME_SC_INVALID_FIELD           = 0x2,
1316         NVME_SC_CMDID_CONFLICT          = 0x3,
1317         NVME_SC_DATA_XFER_ERROR         = 0x4,
1318         NVME_SC_POWER_LOSS              = 0x5,
1319         NVME_SC_INTERNAL                = 0x6,
1320         NVME_SC_ABORT_REQ               = 0x7,
1321         NVME_SC_ABORT_QUEUE             = 0x8,
1322         NVME_SC_FUSED_FAIL              = 0x9,
1323         NVME_SC_FUSED_MISSING           = 0xa,
1324         NVME_SC_INVALID_NS              = 0xb,
1325         NVME_SC_CMD_SEQ_ERROR           = 0xc,
1326         NVME_SC_SGL_INVALID_LAST        = 0xd,
1327         NVME_SC_SGL_INVALID_COUNT       = 0xe,
1328         NVME_SC_SGL_INVALID_DATA        = 0xf,
1329         NVME_SC_SGL_INVALID_METADATA    = 0x10,
1330         NVME_SC_SGL_INVALID_TYPE        = 0x11,
1331
1332         NVME_SC_SGL_INVALID_OFFSET      = 0x16,
1333         NVME_SC_SGL_INVALID_SUBTYPE     = 0x17,
1334
1335         NVME_SC_SANITIZE_FAILED         = 0x1C,
1336         NVME_SC_SANITIZE_IN_PROGRESS    = 0x1D,
1337
1338         NVME_SC_NS_WRITE_PROTECTED      = 0x20,
1339         NVME_SC_CMD_INTERRUPTED         = 0x21,
1340
1341         NVME_SC_LBA_RANGE               = 0x80,
1342         NVME_SC_CAP_EXCEEDED            = 0x81,
1343         NVME_SC_NS_NOT_READY            = 0x82,
1344         NVME_SC_RESERVATION_CONFLICT    = 0x83,
1345
1346         /*
1347          * Command Specific Status:
1348          */
1349         NVME_SC_CQ_INVALID              = 0x100,
1350         NVME_SC_QID_INVALID             = 0x101,
1351         NVME_SC_QUEUE_SIZE              = 0x102,
1352         NVME_SC_ABORT_LIMIT             = 0x103,
1353         NVME_SC_ABORT_MISSING           = 0x104,
1354         NVME_SC_ASYNC_LIMIT             = 0x105,
1355         NVME_SC_FIRMWARE_SLOT           = 0x106,
1356         NVME_SC_FIRMWARE_IMAGE          = 0x107,
1357         NVME_SC_INVALID_VECTOR          = 0x108,
1358         NVME_SC_INVALID_LOG_PAGE        = 0x109,
1359         NVME_SC_INVALID_FORMAT          = 0x10a,
1360         NVME_SC_FW_NEEDS_CONV_RESET     = 0x10b,
1361         NVME_SC_INVALID_QUEUE           = 0x10c,
1362         NVME_SC_FEATURE_NOT_SAVEABLE    = 0x10d,
1363         NVME_SC_FEATURE_NOT_CHANGEABLE  = 0x10e,
1364         NVME_SC_FEATURE_NOT_PER_NS      = 0x10f,
1365         NVME_SC_FW_NEEDS_SUBSYS_RESET   = 0x110,
1366         NVME_SC_FW_NEEDS_RESET          = 0x111,
1367         NVME_SC_FW_NEEDS_MAX_TIME       = 0x112,
1368         NVME_SC_FW_ACTIVATE_PROHIBITED  = 0x113,
1369         NVME_SC_OVERLAPPING_RANGE       = 0x114,
1370         NVME_SC_NS_INSUFFICIENT_CAP     = 0x115,
1371         NVME_SC_NS_ID_UNAVAILABLE       = 0x116,
1372         NVME_SC_NS_ALREADY_ATTACHED     = 0x118,
1373         NVME_SC_NS_IS_PRIVATE           = 0x119,
1374         NVME_SC_NS_NOT_ATTACHED         = 0x11a,
1375         NVME_SC_THIN_PROV_NOT_SUPP      = 0x11b,
1376         NVME_SC_CTRL_LIST_INVALID       = 0x11c,
1377         NVME_SC_BP_WRITE_PROHIBITED     = 0x11e,
1378         NVME_SC_PMR_SAN_PROHIBITED      = 0x123,
1379
1380         /*
1381          * I/O Command Set Specific - NVM commands:
1382          */
1383         NVME_SC_BAD_ATTRIBUTES          = 0x180,
1384         NVME_SC_INVALID_PI              = 0x181,
1385         NVME_SC_READ_ONLY               = 0x182,
1386         NVME_SC_ONCS_NOT_SUPPORTED      = 0x183,
1387
1388         /*
1389          * I/O Command Set Specific - Fabrics commands:
1390          */
1391         NVME_SC_CONNECT_FORMAT          = 0x180,
1392         NVME_SC_CONNECT_CTRL_BUSY       = 0x181,
1393         NVME_SC_CONNECT_INVALID_PARAM   = 0x182,
1394         NVME_SC_CONNECT_RESTART_DISC    = 0x183,
1395         NVME_SC_CONNECT_INVALID_HOST    = 0x184,
1396
1397         NVME_SC_DISCOVERY_RESTART       = 0x190,
1398         NVME_SC_AUTH_REQUIRED           = 0x191,
1399
1400         /*
1401          * Media and Data Integrity Errors:
1402          */
1403         NVME_SC_WRITE_FAULT             = 0x280,
1404         NVME_SC_READ_ERROR              = 0x281,
1405         NVME_SC_GUARD_CHECK             = 0x282,
1406         NVME_SC_APPTAG_CHECK            = 0x283,
1407         NVME_SC_REFTAG_CHECK            = 0x284,
1408         NVME_SC_COMPARE_FAILED          = 0x285,
1409         NVME_SC_ACCESS_DENIED           = 0x286,
1410         NVME_SC_UNWRITTEN_BLOCK         = 0x287,
1411
1412         /*
1413          * Path-related Errors:
1414          */
1415         NVME_SC_ANA_PERSISTENT_LOSS     = 0x301,
1416         NVME_SC_ANA_INACCESSIBLE        = 0x302,
1417         NVME_SC_ANA_TRANSITION          = 0x303,
1418         NVME_SC_HOST_PATH_ERROR         = 0x370,
1419         NVME_SC_HOST_ABORTED_CMD        = 0x371,
1420
1421         NVME_SC_CRD                     = 0x1800,
1422         NVME_SC_DNR                     = 0x4000,
1423 };
1424
1425 struct nvme_completion {
1426         /*
1427          * Used by Admin and Fabrics commands to return data:
1428          */
1429         union nvme_result {
1430                 __le16  u16;
1431                 __le32  u32;
1432                 __le64  u64;
1433         } result;
1434         __le16  sq_head;        /* how much of this queue may be reclaimed */
1435         __le16  sq_id;          /* submission queue that generated this entry */
1436         __u16   command_id;     /* of the command which completed */
1437         __le16  status;         /* did the command fail, and if so, why? */
1438 };
1439
1440 #define NVME_VS(major, minor, tertiary) \
1441         (((major) << 16) | ((minor) << 8) | (tertiary))
1442
1443 #define NVME_MAJOR(ver)         ((ver) >> 16)
1444 #define NVME_MINOR(ver)         (((ver) >> 8) & 0xff)
1445 #define NVME_TERTIARY(ver)      ((ver) & 0xff)
1446
1447 #endif /* _LINUX_NVME_H */