2 * linux/include/linux/mtd/nand.h
4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * Contains standard defines and IDs for NAND flash devices
18 #ifndef __LINUX_MTD_NAND_H
19 #define __LINUX_MTD_NAND_H
21 #include <linux/wait.h>
22 #include <linux/spinlock.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/flashchip.h>
25 #include <linux/mtd/bbm.h>
29 struct nand_flash_dev;
32 /* Scan and identify a NAND device */
33 int nand_scan(struct mtd_info *mtd, int max_chips);
35 * Separate phases of nand_scan(), allowing board driver to intervene
36 * and override command or ECC setup according to flash type.
38 int nand_scan_ident(struct mtd_info *mtd, int max_chips,
39 struct nand_flash_dev *table);
40 int nand_scan_tail(struct mtd_info *mtd);
42 /* Unregister the MTD device and free resources held by the NAND device */
43 void nand_release(struct nand_chip *chip);
45 /* Internal helper for board drivers which need to override command function */
46 void nand_wait_ready(struct mtd_info *mtd);
48 /* locks all blocks present in the device */
49 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
51 /* unlocks specified locked blocks */
52 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
54 /* The maximum number of NAND chips in an array */
55 #define NAND_MAX_CHIPS 8
58 * Constants for hardware specific CLE/ALE/NCE function
60 * These are bits which can be or'ed to set/clear multiple
63 /* Select the chip by setting nCE to low */
65 /* Select the command latch by setting CLE to high */
67 /* Select the address latch by setting ALE to high */
70 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
71 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
72 #define NAND_CTRL_CHANGE 0x80
75 * Standard NAND flash commands
77 #define NAND_CMD_READ0 0
78 #define NAND_CMD_READ1 1
79 #define NAND_CMD_RNDOUT 5
80 #define NAND_CMD_PAGEPROG 0x10
81 #define NAND_CMD_READOOB 0x50
82 #define NAND_CMD_ERASE1 0x60
83 #define NAND_CMD_STATUS 0x70
84 #define NAND_CMD_SEQIN 0x80
85 #define NAND_CMD_RNDIN 0x85
86 #define NAND_CMD_READID 0x90
87 #define NAND_CMD_ERASE2 0xd0
88 #define NAND_CMD_PARAM 0xec
89 #define NAND_CMD_GET_FEATURES 0xee
90 #define NAND_CMD_SET_FEATURES 0xef
91 #define NAND_CMD_RESET 0xff
93 #define NAND_CMD_LOCK 0x2a
94 #define NAND_CMD_UNLOCK1 0x23
95 #define NAND_CMD_UNLOCK2 0x24
97 /* Extended commands for large page devices */
98 #define NAND_CMD_READSTART 0x30
99 #define NAND_CMD_RNDOUTSTART 0xE0
100 #define NAND_CMD_CACHEDPROG 0x15
102 #define NAND_CMD_NONE -1
105 #define NAND_STATUS_FAIL 0x01
106 #define NAND_STATUS_FAIL_N1 0x02
107 #define NAND_STATUS_TRUE_READY 0x20
108 #define NAND_STATUS_READY 0x40
109 #define NAND_STATUS_WP 0x80
112 * Constants for ECC_MODES
118 NAND_ECC_HW_SYNDROME,
119 NAND_ECC_HW_OOB_FIRST,
129 * Constants for Hardware ECC
131 /* Reset Hardware ECC for read */
132 #define NAND_ECC_READ 0
133 /* Reset Hardware ECC for write */
134 #define NAND_ECC_WRITE 1
135 /* Enable Hardware ECC before syndrome is read back from flash */
136 #define NAND_ECC_READSYN 2
139 * Enable generic NAND 'page erased' check. This check is only done when
140 * ecc.correct() returns -EBADMSG.
141 * Set this flag if your implementation does not fix bitflips in erased
142 * pages and you want to rely on the default implementation.
144 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
145 #define NAND_ECC_MAXIMIZE BIT(1)
147 /* Bit mask for flags passed to do_nand_read_ecc */
148 #define NAND_GET_DEVICE 0x80
152 * Option constants for bizarre disfunctionality and real
155 /* Buswidth is 16 bit */
156 #define NAND_BUSWIDTH_16 0x00000002
157 /* Chip has cache program function */
158 #define NAND_CACHEPRG 0x00000008
160 * Chip requires ready check on read (for auto-incremented sequential read).
161 * True only for small page devices; large page devices do not support
164 #define NAND_NEED_READRDY 0x00000100
166 /* Chip does not allow subpage writes */
167 #define NAND_NO_SUBPAGE_WRITE 0x00000200
169 /* Device is one of 'new' xD cards that expose fake nand command set */
170 #define NAND_BROKEN_XD 0x00000400
172 /* Device behaves just like nand, but is readonly */
173 #define NAND_ROM 0x00000800
175 /* Device supports subpage reads */
176 #define NAND_SUBPAGE_READ 0x00001000
179 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
182 #define NAND_NEED_SCRAMBLING 0x00002000
184 /* Options valid for Samsung large page devices */
185 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
187 /* Macros to identify the above */
188 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
189 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
191 /* Non chip related options */
192 /* This option skips the bbt scan during initialization. */
193 #define NAND_SKIP_BBTSCAN 0x00010000
195 * This option is defined if the board driver allocates its own buffers
196 * (e.g. because it needs them DMA-coherent).
198 #define NAND_OWN_BUFFERS 0x00020000
199 /* Chip may not exist, so silence any errors in scan */
200 #define NAND_SCAN_SILENT_NODEV 0x00040000
202 * Autodetect nand buswidth with readid/onfi.
203 * This suppose the driver will configure the hardware in 8 bits mode
204 * when calling nand_scan_ident, and update its configuration
205 * before calling nand_scan_tail.
207 #define NAND_BUSWIDTH_AUTO 0x00080000
209 * This option could be defined by controller drivers to protect against
210 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
212 #define NAND_USE_BOUNCE_BUFFER 0x00100000
214 /* Options set by nand scan */
215 /* Nand scan has allocated controller struct */
216 #define NAND_CONTROLLER_ALLOC 0x80000000
218 /* Cell info constants */
219 #define NAND_CI_CHIPNR_MSK 0x03
220 #define NAND_CI_CELLTYPE_MSK 0x0C
221 #define NAND_CI_CELLTYPE_SHIFT 2
224 #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
225 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
227 /* ONFI timing mode, used in both asynchronous and synchronous mode */
228 #define ONFI_TIMING_MODE_0 (1 << 0)
229 #define ONFI_TIMING_MODE_1 (1 << 1)
230 #define ONFI_TIMING_MODE_2 (1 << 2)
231 #define ONFI_TIMING_MODE_3 (1 << 3)
232 #define ONFI_TIMING_MODE_4 (1 << 4)
233 #define ONFI_TIMING_MODE_5 (1 << 5)
234 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
236 /* ONFI feature address */
237 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
239 /* Vendor-specific feature address (Micron) */
240 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
242 /* ONFI subfeature parameters length */
243 #define ONFI_SUBFEATURE_PARAM_LEN 4
245 /* ONFI optional commands SET/GET FEATURES supported? */
246 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
248 struct nand_onfi_params {
249 /* rev info and features block */
250 /* 'O' 'N' 'F' 'I' */
256 __le16 ext_param_page_length; /* since ONFI 2.1 */
257 u8 num_of_param_pages; /* since ONFI 2.1 */
260 /* manufacturer information block */
261 char manufacturer[12];
267 /* memory organization block */
268 __le32 byte_per_page;
269 __le16 spare_bytes_per_page;
270 __le32 data_bytes_per_ppage;
271 __le16 spare_bytes_per_ppage;
272 __le32 pages_per_block;
273 __le32 blocks_per_lun;
278 __le16 block_endurance;
279 u8 guaranteed_good_blocks;
280 __le16 guaranteed_block_endurance;
281 u8 programs_per_page;
288 /* electrical parameter block */
289 u8 io_pin_capacitance_max;
290 __le16 async_timing_mode;
291 __le16 program_cache_timing_mode;
296 __le16 src_sync_timing_mode;
297 u8 src_ssync_features;
298 __le16 clk_pin_capacitance_typ;
299 __le16 io_pin_capacitance_typ;
300 __le16 input_pin_capacitance_typ;
301 u8 input_pin_capacitance_max;
302 u8 driver_strength_support;
308 __le16 vendor_revision;
314 #define ONFI_CRC_BASE 0x4F4E
316 /* Extended ECC information Block Definition (since ONFI 2.1) */
317 struct onfi_ext_ecc_info {
321 __le16 block_endurance;
325 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
326 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
327 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
328 struct onfi_ext_section {
333 #define ONFI_EXT_SECTION_MAX 8
335 /* Extended Parameter Page Definition (since ONFI 2.1) */
336 struct onfi_ext_param_page {
338 u8 sig[4]; /* 'E' 'P' 'P' 'S' */
340 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
343 * The actual size of the Extended Parameter Page is in
344 * @ext_param_page_length of nand_onfi_params{}.
345 * The following are the variable length sections.
346 * So we do not add any fields below. Please see the ONFI spec.
350 struct nand_onfi_vendor_micron {
355 u8 dq_imped_num_settings;
356 u8 dq_imped_feat_addr;
357 u8 rb_pulldown_strength;
358 u8 rb_pulldown_strength_feat_addr;
359 u8 rb_pulldown_strength_num_settings;
362 u8 otp_data_prot_addr;
365 u8 read_retry_options;
370 struct jedec_ecc_info {
374 __le16 block_endurance;
379 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
381 struct nand_jedec_params {
382 /* rev info and features block */
383 /* 'J' 'E' 'S' 'D' */
389 u8 num_of_param_pages;
392 /* manufacturer information block */
393 char manufacturer[12];
398 /* memory organization block */
399 __le32 byte_per_page;
400 __le16 spare_bytes_per_page;
402 __le32 pages_per_block;
403 __le32 blocks_per_lun;
407 u8 programs_per_page;
409 u8 multi_plane_op_attr;
412 /* electrical parameter block */
413 __le16 async_sdr_speed_grade;
414 __le16 toggle_ddr_speed_grade;
415 __le16 sync_ddr_speed_grade;
416 u8 async_sdr_features;
417 u8 toggle_ddr_features;
418 u8 sync_ddr_features;
422 __le16 t_r_multi_plane;
424 __le16 io_pin_capacitance_typ;
425 __le16 input_pin_capacitance_typ;
426 __le16 clk_pin_capacitance_typ;
427 u8 driver_strength_support;
431 /* ECC and endurance block */
432 u8 guaranteed_good_blocks;
433 __le16 guaranteed_block_endurance;
434 struct jedec_ecc_info ecc_info[4];
441 __le16 vendor_rev_num;
444 /* CRC for Parameter Page */
449 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
450 * @lock: protection lock
451 * @active: the mtd device which holds the controller currently
452 * @wq: wait queue to sleep on if a NAND operation is in
453 * progress used instead of the per chip wait queue
454 * when a hw controller is available.
456 struct nand_hw_control {
458 struct nand_chip *active;
459 wait_queue_head_t wq;
462 static inline void nand_hw_control_init(struct nand_hw_control *nfc)
465 spin_lock_init(&nfc->lock);
466 init_waitqueue_head(&nfc->wq);
470 * struct nand_ecc_ctrl - Control structure for ECC
472 * @algo: ECC algorithm
473 * @steps: number of ECC steps per page
474 * @size: data bytes per ECC step
475 * @bytes: ECC bytes per step
476 * @strength: max number of correctible bits per ECC step
477 * @total: total number of ECC bytes per page
478 * @prepad: padding information for syndrome based ECC generators
479 * @postpad: padding information for syndrome based ECC generators
480 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
481 * @priv: pointer to private ECC control data
482 * @hwctl: function to control hardware ECC generator. Must only
483 * be provided if an hardware ECC is available
484 * @calculate: function for ECC calculation or readback from ECC hardware
485 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
486 * Should return a positive number representing the number of
487 * corrected bitflips, -EBADMSG if the number of bitflips exceed
488 * ECC strength, or any other error code if the error is not
489 * directly related to correction.
490 * If -EBADMSG is returned the input buffers should be left
492 * @read_page_raw: function to read a raw page without ECC. This function
493 * should hide the specific layout used by the ECC
494 * controller and always return contiguous in-band and
495 * out-of-band data even if they're not stored
496 * contiguously on the NAND chip (e.g.
497 * NAND_ECC_HW_SYNDROME interleaves in-band and
499 * @write_page_raw: function to write a raw page without ECC. This function
500 * should hide the specific layout used by the ECC
501 * controller and consider the passed data as contiguous
502 * in-band and out-of-band data. ECC controller is
503 * responsible for doing the appropriate transformations
504 * to adapt to its specific layout (e.g.
505 * NAND_ECC_HW_SYNDROME interleaves in-band and
507 * @read_page: function to read a page according to the ECC generator
508 * requirements; returns maximum number of bitflips corrected in
509 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
510 * @read_subpage: function to read parts of the page covered by ECC;
511 * returns same as read_page()
512 * @write_subpage: function to write parts of the page covered by ECC.
513 * @write_page: function to write a page according to the ECC generator
515 * @write_oob_raw: function to write chip OOB data without ECC
516 * @read_oob_raw: function to read chip OOB data without ECC
517 * @read_oob: function to read chip OOB data
518 * @write_oob: function to write chip OOB data
520 struct nand_ecc_ctrl {
521 nand_ecc_modes_t mode;
522 enum nand_ecc_algo algo;
530 unsigned int options;
532 void (*hwctl)(struct mtd_info *mtd, int mode);
533 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
535 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
537 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
538 uint8_t *buf, int oob_required, int page);
539 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
540 const uint8_t *buf, int oob_required, int page);
541 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
542 uint8_t *buf, int oob_required, int page);
543 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
544 uint32_t offs, uint32_t len, uint8_t *buf, int page);
545 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
546 uint32_t offset, uint32_t data_len,
547 const uint8_t *data_buf, int oob_required, int page);
548 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
549 const uint8_t *buf, int oob_required, int page);
550 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
552 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
554 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
555 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
560 * struct nand_buffers - buffer structure for read/write
561 * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
562 * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
563 * @databuf: buffer pointer for data, size is (page size + oobsize).
565 * Do not change the order of buffers. databuf and oobrbuf must be in
568 struct nand_buffers {
575 * struct nand_sdr_timings - SDR NAND chip timings
577 * This struct defines the timing requirements of a SDR NAND chip.
578 * These information can be found in every NAND datasheets and the timings
579 * meaning are described in the ONFI specifications:
580 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
583 * All these timings are expressed in picoseconds.
585 * @tALH_min: ALE hold time
586 * @tADL_min: ALE to data loading time
587 * @tALS_min: ALE setup time
588 * @tAR_min: ALE to RE# delay
589 * @tCEA_max: CE# access time
591 * @tCH_min: CE# hold time
592 * @tCHZ_max: CE# high to output hi-Z
593 * @tCLH_min: CLE hold time
594 * @tCLR_min: CLE to RE# delay
595 * @tCLS_min: CLE setup time
596 * @tCOH_min: CE# high to output hold
597 * @tCS_min: CE# setup time
598 * @tDH_min: Data hold time
599 * @tDS_min: Data setup time
600 * @tFEAT_max: Busy time for Set Features and Get Features
601 * @tIR_min: Output hi-Z to RE# low
602 * @tITC_max: Interface and Timing Mode Change time
603 * @tRC_min: RE# cycle time
604 * @tREA_max: RE# access time
605 * @tREH_min: RE# high hold time
606 * @tRHOH_min: RE# high to output hold
607 * @tRHW_min: RE# high to WE# low
608 * @tRHZ_max: RE# high to output hi-Z
609 * @tRLOH_min: RE# low to output hold
610 * @tRP_min: RE# pulse width
611 * @tRR_min: Ready to RE# low (data only)
612 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
613 * rising edge of R/B#.
614 * @tWB_max: WE# high to SR[6] low
615 * @tWC_min: WE# cycle time
616 * @tWH_min: WE# high hold time
617 * @tWHR_min: WE# high to RE# low
618 * @tWP_min: WE# pulse width
619 * @tWW_min: WP# transition to WE# low
621 struct nand_sdr_timings {
659 * enum nand_data_interface_type - NAND interface timing type
660 * @NAND_SDR_IFACE: Single Data Rate interface
662 enum nand_data_interface_type {
667 * struct nand_data_interface - NAND interface timing
668 * @type: type of the timing
669 * @timings: The timing, type according to @type
671 struct nand_data_interface {
672 enum nand_data_interface_type type;
674 struct nand_sdr_timings sdr;
679 * nand_get_sdr_timings - get SDR timing from data interface
680 * @conf: The data interface
682 static inline const struct nand_sdr_timings *
683 nand_get_sdr_timings(const struct nand_data_interface *conf)
685 if (conf->type != NAND_SDR_IFACE)
686 return ERR_PTR(-EINVAL);
688 return &conf->timings.sdr;
692 * struct nand_chip - NAND Private Flash Chip Data
693 * @mtd: MTD device registered to the MTD framework
694 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
696 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
698 * @read_byte: [REPLACEABLE] read one byte from the chip
699 * @read_word: [REPLACEABLE] read one word from the chip
700 * @write_byte: [REPLACEABLE] write a single byte to the chip on the
702 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
703 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
704 * @select_chip: [REPLACEABLE] select chip nr
705 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
706 * @block_markbad: [REPLACEABLE] mark a block bad
707 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
708 * ALE/CLE/nCE. Also used to write command and address
709 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
710 * device ready/busy line. If set to NULL no access to
711 * ready/busy is available and the ready/busy information
712 * is read from the chip status register.
713 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
714 * commands to the chip.
715 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
717 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
718 * setting the read-retry mode. Mostly needed for MLC NAND.
719 * @ecc: [BOARDSPECIFIC] ECC control structure
720 * @buffers: buffer structure for read/write
721 * @hwcontrol: platform-specific hardware control structure
722 * @erase: [REPLACEABLE] erase function
723 * @scan_bbt: [REPLACEABLE] function to scan bad block table
724 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
725 * data from array to read regs (tR).
726 * @state: [INTERN] the current state of the NAND device
727 * @oob_poi: "poison value buffer," used for laying out OOB data
729 * @page_shift: [INTERN] number of address bits in a page (column
731 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
732 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
733 * @chip_shift: [INTERN] number of address bits in one chip
734 * @options: [BOARDSPECIFIC] various chip options. They can partly
735 * be set to inform nand_scan about special functionality.
736 * See the defines for further explanation.
737 * @bbt_options: [INTERN] bad block specific options. All options used
738 * here must come from bbm.h. By default, these options
739 * will be copied to the appropriate nand_bbt_descr's.
740 * @badblockpos: [INTERN] position of the bad block marker in the oob
742 * @badblockbits: [INTERN] minimum number of set bits in a good block's
743 * bad block marker position; i.e., BBM == 11110111b is
744 * not bad when badblockbits == 7
745 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
746 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
747 * Minimum amount of bit errors per @ecc_step_ds guaranteed
748 * to be correctable. If unknown, set to zero.
749 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
750 * also from the datasheet. It is the recommended ECC step
751 * size, if known; if unknown, set to zero.
752 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
753 * set to the actually used ONFI mode if the chip is
754 * ONFI compliant or deduced from the datasheet if
755 * the NAND chip is not ONFI compliant.
756 * @numchips: [INTERN] number of physical chips
757 * @chipsize: [INTERN] the size of one chip for multichip arrays
758 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
759 * @pagebuf: [INTERN] holds the pagenumber which is currently in
761 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
762 * currently in data_buf.
763 * @subpagesize: [INTERN] holds the subpagesize
764 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
765 * non 0 if ONFI supported.
766 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),
767 * non 0 if JEDEC supported.
768 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
769 * supported, 0 otherwise.
770 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is
771 * supported, 0 otherwise.
772 * @read_retries: [INTERN] the number of read retry modes supported
773 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
774 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
775 * @setup_data_interface: [OPTIONAL] setup the data interface and timing
776 * @bbt: [INTERN] bad block table pointer
777 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
779 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
780 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
782 * @controller: [REPLACEABLE] a pointer to a hardware controller
783 * structure which is shared among multiple independent
785 * @priv: [OPTIONAL] pointer to private chip data
786 * @errstat: [OPTIONAL] hardware specific function to perform
787 * additional error status checks (determine if errors are
789 * @write_page: [REPLACEABLE] High-level page write function
794 void __iomem *IO_ADDR_R;
795 void __iomem *IO_ADDR_W;
797 uint8_t (*read_byte)(struct mtd_info *mtd);
798 u16 (*read_word)(struct mtd_info *mtd);
799 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
800 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
801 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
802 void (*select_chip)(struct mtd_info *mtd, int chip);
803 int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
804 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
805 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
806 int (*dev_ready)(struct mtd_info *mtd);
807 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
809 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
810 int (*erase)(struct mtd_info *mtd, int page);
811 int (*scan_bbt)(struct mtd_info *mtd);
812 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
813 int status, int page);
814 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
815 uint32_t offset, int data_len, const uint8_t *buf,
816 int oob_required, int page, int cached, int raw);
817 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
818 int feature_addr, uint8_t *subfeature_para);
819 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
820 int feature_addr, uint8_t *subfeature_para);
821 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
822 int (*setup_data_interface)(struct mtd_info *mtd,
823 const struct nand_data_interface *conf,
828 unsigned int options;
829 unsigned int bbt_options;
832 int phys_erase_shift;
839 unsigned int pagebuf_bitflips;
841 uint8_t bits_per_cell;
842 uint16_t ecc_strength_ds;
843 uint16_t ecc_step_ds;
844 int onfi_timing_mode_default;
851 struct nand_onfi_params onfi_params;
852 struct nand_jedec_params jedec_params;
855 struct nand_data_interface *data_interface;
862 struct nand_hw_control *controller;
864 struct nand_ecc_ctrl ecc;
865 struct nand_buffers *buffers;
866 struct nand_hw_control hwcontrol;
869 struct nand_bbt_descr *bbt_td;
870 struct nand_bbt_descr *bbt_md;
872 struct nand_bbt_descr *badblock_pattern;
877 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops;
878 extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops;
880 static inline void nand_set_flash_node(struct nand_chip *chip,
881 struct device_node *np)
883 mtd_set_of_node(&chip->mtd, np);
886 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
888 return mtd_get_of_node(&chip->mtd);
891 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
893 return container_of(mtd, struct nand_chip, mtd);
896 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
901 static inline void *nand_get_controller_data(struct nand_chip *chip)
906 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
912 * NAND Flash Manufacturer ID Codes
914 #define NAND_MFR_TOSHIBA 0x98
915 #define NAND_MFR_ESMT 0xc8
916 #define NAND_MFR_SAMSUNG 0xec
917 #define NAND_MFR_FUJITSU 0x04
918 #define NAND_MFR_NATIONAL 0x8f
919 #define NAND_MFR_RENESAS 0x07
920 #define NAND_MFR_STMICRO 0x20
921 #define NAND_MFR_HYNIX 0xad
922 #define NAND_MFR_MICRON 0x2c
923 #define NAND_MFR_AMD 0x01
924 #define NAND_MFR_MACRONIX 0xc2
925 #define NAND_MFR_EON 0x92
926 #define NAND_MFR_SANDISK 0x45
927 #define NAND_MFR_INTEL 0x89
928 #define NAND_MFR_ATO 0x9b
930 /* The maximum expected count of bytes in the NAND ID sequence */
931 #define NAND_MAX_ID_LEN 8
934 * A helper for defining older NAND chips where the second ID byte fully
935 * defined the chip, including the geometry (chip size, eraseblock size, page
936 * size). All these chips have 512 bytes NAND page size.
938 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
939 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
940 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
943 * A helper for defining newer chips which report their page size and
944 * eraseblock size via the extended ID bytes.
946 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
947 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
948 * device ID now only represented a particular total chip size (and voltage,
949 * buswidth), and the page size, eraseblock size, and OOB size could vary while
950 * using the same device ID.
952 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
953 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
956 #define NAND_ECC_INFO(_strength, _step) \
957 { .strength_ds = (_strength), .step_ds = (_step) }
958 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
959 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
962 * struct nand_flash_dev - NAND Flash Device ID Structure
963 * @name: a human-readable name of the NAND chip
964 * @dev_id: the device ID (the second byte of the full chip ID array)
965 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
966 * memory address as @id[0])
967 * @dev_id: device ID part of the full chip ID array (refers the same memory
969 * @id: full device ID array
970 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
971 * well as the eraseblock size) is determined from the extended NAND
973 * @chipsize: total chip size in MiB
974 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
975 * @options: stores various chip bit options
976 * @id_len: The valid length of the @id.
978 * @ecc: ECC correctability and step information from the datasheet.
979 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
980 * @ecc_strength_ds in nand_chip{}.
981 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
982 * @ecc_step_ds in nand_chip{}, also from the datasheet.
983 * For example, the "4bit ECC for each 512Byte" can be set with
984 * NAND_ECC_INFO(4, 512).
985 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
986 * reset. Should be deduced from timings described
990 struct nand_flash_dev {
997 uint8_t id[NAND_MAX_ID_LEN];
999 unsigned int pagesize;
1000 unsigned int chipsize;
1001 unsigned int erasesize;
1002 unsigned int options;
1006 uint16_t strength_ds;
1009 int onfi_timing_mode_default;
1013 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
1014 * @name: Manufacturer name
1015 * @id: manufacturer ID code of device.
1017 struct nand_manufacturers {
1022 extern struct nand_flash_dev nand_flash_ids[];
1023 extern struct nand_manufacturers nand_manuf_ids[];
1025 int nand_default_bbt(struct mtd_info *mtd);
1026 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
1027 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
1028 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
1029 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1031 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
1032 size_t *retlen, uint8_t *buf);
1035 * struct platform_nand_chip - chip level device structure
1036 * @nr_chips: max. number of chips to scan for
1037 * @chip_offset: chip number offset
1038 * @nr_partitions: number of partitions pointed to by partitions (or zero)
1039 * @partitions: mtd partition list
1040 * @chip_delay: R/B delay value in us
1041 * @options: Option flags, e.g. 16bit buswidth
1042 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
1043 * @part_probe_types: NULL-terminated array of probe types
1045 struct platform_nand_chip {
1049 struct mtd_partition *partitions;
1051 unsigned int options;
1052 unsigned int bbt_options;
1053 const char **part_probe_types;
1056 /* Keep gcc happy */
1057 struct platform_device;
1060 * struct platform_nand_ctrl - controller level device structure
1061 * @probe: platform specific function to probe/setup hardware
1062 * @remove: platform specific function to remove/teardown hardware
1063 * @hwcontrol: platform specific hardware control structure
1064 * @dev_ready: platform specific function to read ready/busy pin
1065 * @select_chip: platform specific chip select function
1066 * @cmd_ctrl: platform specific function for controlling
1067 * ALE/CLE/nCE. Also used to write command and address
1068 * @write_buf: platform specific function for write buffer
1069 * @read_buf: platform specific function for read buffer
1070 * @read_byte: platform specific function to read one byte from chip
1071 * @priv: private data to transport driver specific settings
1073 * All fields are optional and depend on the hardware driver requirements
1075 struct platform_nand_ctrl {
1076 int (*probe)(struct platform_device *pdev);
1077 void (*remove)(struct platform_device *pdev);
1078 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
1079 int (*dev_ready)(struct mtd_info *mtd);
1080 void (*select_chip)(struct mtd_info *mtd, int chip);
1081 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1082 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1083 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1084 unsigned char (*read_byte)(struct mtd_info *mtd);
1089 * struct platform_nand_data - container structure for platform-specific data
1090 * @chip: chip level chip structure
1091 * @ctrl: controller level device structure
1093 struct platform_nand_data {
1094 struct platform_nand_chip chip;
1095 struct platform_nand_ctrl ctrl;
1098 /* return the supported features. */
1099 static inline int onfi_feature(struct nand_chip *chip)
1101 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
1104 /* return the supported asynchronous timing mode. */
1105 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1107 if (!chip->onfi_version)
1108 return ONFI_TIMING_MODE_UNKNOWN;
1109 return le16_to_cpu(chip->onfi_params.async_timing_mode);
1112 /* return the supported synchronous timing mode. */
1113 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1115 if (!chip->onfi_version)
1116 return ONFI_TIMING_MODE_UNKNOWN;
1117 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
1120 int onfi_init_data_interface(struct nand_chip *chip,
1121 struct nand_data_interface *iface,
1122 enum nand_data_interface_type type,
1126 * Check if it is a SLC nand.
1127 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1128 * We do not distinguish the MLC and TLC now.
1130 static inline bool nand_is_slc(struct nand_chip *chip)
1132 return chip->bits_per_cell == 1;
1136 * Check if the opcode's address should be sent only on the lower 8 bits
1137 * @command: opcode to check
1139 static inline int nand_opcode_8bits(unsigned int command)
1142 case NAND_CMD_READID:
1143 case NAND_CMD_PARAM:
1144 case NAND_CMD_GET_FEATURES:
1145 case NAND_CMD_SET_FEATURES:
1153 /* return the supported JEDEC features. */
1154 static inline int jedec_feature(struct nand_chip *chip)
1156 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
1160 /* get timing characteristics from ONFI timing mode. */
1161 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1162 /* get data interface from ONFI timing mode 0, used after reset. */
1163 const struct nand_data_interface *nand_get_default_data_interface(void);
1165 int nand_check_erased_ecc_chunk(void *data, int datalen,
1166 void *ecc, int ecclen,
1167 void *extraoob, int extraooblen,
1170 /* Default write_oob implementation */
1171 int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
1173 /* Default write_oob syndrome implementation */
1174 int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1177 /* Default read_oob implementation */
1178 int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
1180 /* Default read_oob syndrome implementation */
1181 int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1184 /* Reset and initialize a NAND device */
1185 int nand_reset(struct nand_chip *chip, int chipnr);
1187 /* Free resources held by the NAND device */
1188 void nand_cleanup(struct nand_chip *chip);
1190 #endif /* __LINUX_MTD_NAND_H */