2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
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5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
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8 * OpenIB.org BSD license below:
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11 * without modification, are permitted provided that the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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33 #ifndef __MLX5_PORT_H__
34 #define __MLX5_PORT_H__
36 #include <linux/mlx5/driver.h>
38 enum mlx5_beacon_duration {
39 MLX5_BEACON_DURATION_OFF = 0x0,
40 MLX5_BEACON_DURATION_INF = 0xffff,
44 MLX5_MODULE_ID_SFP = 0x3,
45 MLX5_MODULE_ID_QSFP = 0xC,
46 MLX5_MODULE_ID_QSFP_PLUS = 0xD,
47 MLX5_MODULE_ID_QSFP28 = 0x11,
48 MLX5_MODULE_ID_DSFP = 0x1B,
52 MLX5_AN_UNAVAILABLE = 0,
56 MLX5_AN_LINK_DOWN = 4,
59 #define MLX5_EEPROM_MAX_BYTES 32
60 #define MLX5_EEPROM_IDENTIFIER_BYTE_MASK 0x000000ff
61 #define MLX5_I2C_ADDR_LOW 0x50
62 #define MLX5_I2C_ADDR_HIGH 0x51
63 #define MLX5_EEPROM_PAGE_LENGTH 256
64 #define MLX5_EEPROM_HIGH_PAGE_LENGTH 128
66 struct mlx5_module_eeprom_query_params {
75 enum mlx5e_link_mode {
76 MLX5E_1000BASE_CX_SGMII = 0,
77 MLX5E_1000BASE_KX = 1,
78 MLX5E_10GBASE_CX4 = 2,
79 MLX5E_10GBASE_KX4 = 3,
81 MLX5E_20GBASE_KR2 = 5,
82 MLX5E_40GBASE_CR4 = 6,
83 MLX5E_40GBASE_KR4 = 7,
85 MLX5E_10GBASE_CR = 12,
86 MLX5E_10GBASE_SR = 13,
87 MLX5E_10GBASE_ER = 14,
88 MLX5E_40GBASE_SR4 = 15,
89 MLX5E_40GBASE_LR4 = 16,
90 MLX5E_50GBASE_SR2 = 18,
91 MLX5E_100GBASE_CR4 = 20,
92 MLX5E_100GBASE_SR4 = 21,
93 MLX5E_100GBASE_KR4 = 22,
94 MLX5E_100GBASE_LR4 = 23,
95 MLX5E_100BASE_TX = 24,
96 MLX5E_1000BASE_T = 25,
98 MLX5E_25GBASE_CR = 27,
99 MLX5E_25GBASE_KR = 28,
100 MLX5E_25GBASE_SR = 29,
101 MLX5E_50GBASE_CR2 = 30,
102 MLX5E_50GBASE_KR2 = 31,
103 MLX5E_LINK_MODES_NUMBER,
106 enum mlx5e_ext_link_mode {
107 MLX5E_SGMII_100M = 0,
108 MLX5E_1000BASE_X_SGMII = 1,
110 MLX5E_10GBASE_XFI_XAUI_1 = 4,
111 MLX5E_40GBASE_XLAUI_4_XLPPI_4 = 5,
112 MLX5E_25GAUI_1_25GBASE_CR_KR = 6,
113 MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 = 7,
114 MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR = 8,
115 MLX5E_CAUI_4_100GBASE_CR4_KR4 = 9,
116 MLX5E_100GAUI_2_100GBASE_CR2_KR2 = 10,
117 MLX5E_100GAUI_1_100GBASE_CR_KR = 11,
118 MLX5E_200GAUI_4_200GBASE_CR4_KR4 = 12,
119 MLX5E_200GAUI_2_200GBASE_CR2_KR2 = 13,
120 MLX5E_400GAUI_8 = 15,
121 MLX5E_400GAUI_4_400GBASE_CR4_KR4 = 16,
122 MLX5E_EXT_LINK_MODES_NUMBER,
125 enum mlx5e_connector_type {
126 MLX5E_PORT_UNKNOWN = 0,
132 MLX5E_PORT_FIBRE = 6,
134 MLX5E_PORT_OTHER = 8,
135 MLX5E_CONNECTOR_TYPE_NUMBER,
138 enum mlx5_ptys_width {
139 MLX5_PTYS_WIDTH_1X = 1 << 0,
140 MLX5_PTYS_WIDTH_2X = 1 << 1,
141 MLX5_PTYS_WIDTH_4X = 1 << 2,
142 MLX5_PTYS_WIDTH_8X = 1 << 3,
143 MLX5_PTYS_WIDTH_12X = 1 << 4,
146 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
147 #define MLX5_GET_ETH_PROTO(reg, out, ext, field) \
148 (ext ? MLX5_GET(reg, out, ext_##field) : \
149 MLX5_GET(reg, out, field))
151 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
152 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
153 int ptys_size, int proto_mask, u8 local_port);
155 int mlx5_query_ib_port_oper(struct mlx5_core_dev *dev, u16 *link_width_oper,
156 u16 *proto_oper, u8 local_port);
157 void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
158 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
159 enum mlx5_port_status status);
160 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
161 enum mlx5_port_status *status);
162 int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration);
164 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port);
165 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu, u8 port);
166 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu,
169 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
170 u8 *vl_hw_cap, u8 local_port);
172 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause);
173 int mlx5_query_port_pause(struct mlx5_core_dev *dev,
174 u32 *rx_pause, u32 *tx_pause);
176 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx);
177 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx,
180 int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev,
181 u16 stall_critical_watermark,
182 u16 stall_minor_watermark);
183 int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev,
184 u16 *stall_critical_watermark, u16 *stall_minor_watermark);
186 int mlx5_max_tc(struct mlx5_core_dev *mdev);
188 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc);
189 int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev,
191 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group);
192 int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev,
193 u8 tc, u8 *tc_group);
194 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw);
195 int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev,
197 int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
200 int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
203 int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode);
204 int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode);
206 int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out, int outlen);
207 int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen);
208 int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable);
209 void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported,
211 int mlx5_query_module_eeprom(struct mlx5_core_dev *dev,
212 u16 offset, u16 size, u8 *data);
213 int mlx5_query_module_eeprom_by_page(struct mlx5_core_dev *dev,
214 struct mlx5_module_eeprom_query_params *params, u8 *data);
216 int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out);
217 int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in);
219 int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state);
220 int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state);
221 int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio);
222 int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio);
223 #endif /* __MLX5_PORT_H__ */