2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
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5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
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11 * without modification, are permitted provided that the following
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15 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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33 #ifndef __MLX5_PORT_H__
34 #define __MLX5_PORT_H__
36 #include <linux/mlx5/driver.h>
38 enum mlx5_beacon_duration {
39 MLX5_BEACON_DURATION_OFF = 0x0,
40 MLX5_BEACON_DURATION_INF = 0xffff,
44 MLX5_MODULE_ID_SFP = 0x3,
45 MLX5_MODULE_ID_QSFP = 0xC,
46 MLX5_MODULE_ID_QSFP_PLUS = 0xD,
47 MLX5_MODULE_ID_QSFP28 = 0x11,
51 MLX5_AN_UNAVAILABLE = 0,
55 MLX5_AN_LINK_DOWN = 4,
58 #define MLX5_EEPROM_MAX_BYTES 32
59 #define MLX5_EEPROM_IDENTIFIER_BYTE_MASK 0x000000ff
60 #define MLX5_I2C_ADDR_LOW 0x50
61 #define MLX5_I2C_ADDR_HIGH 0x51
62 #define MLX5_EEPROM_PAGE_LENGTH 256
63 #define MLX5_EEPROM_HIGH_PAGE_LENGTH 128
65 enum mlx5e_link_mode {
66 MLX5E_1000BASE_CX_SGMII = 0,
67 MLX5E_1000BASE_KX = 1,
68 MLX5E_10GBASE_CX4 = 2,
69 MLX5E_10GBASE_KX4 = 3,
71 MLX5E_20GBASE_KR2 = 5,
72 MLX5E_40GBASE_CR4 = 6,
73 MLX5E_40GBASE_KR4 = 7,
75 MLX5E_10GBASE_CR = 12,
76 MLX5E_10GBASE_SR = 13,
77 MLX5E_10GBASE_ER = 14,
78 MLX5E_40GBASE_SR4 = 15,
79 MLX5E_40GBASE_LR4 = 16,
80 MLX5E_50GBASE_SR2 = 18,
81 MLX5E_100GBASE_CR4 = 20,
82 MLX5E_100GBASE_SR4 = 21,
83 MLX5E_100GBASE_KR4 = 22,
84 MLX5E_100GBASE_LR4 = 23,
85 MLX5E_100BASE_TX = 24,
86 MLX5E_1000BASE_T = 25,
88 MLX5E_25GBASE_CR = 27,
89 MLX5E_25GBASE_KR = 28,
90 MLX5E_25GBASE_SR = 29,
91 MLX5E_50GBASE_CR2 = 30,
92 MLX5E_50GBASE_KR2 = 31,
93 MLX5E_LINK_MODES_NUMBER,
96 enum mlx5e_ext_link_mode {
98 MLX5E_1000BASE_X_SGMII = 1,
100 MLX5E_10GBASE_XFI_XAUI_1 = 4,
101 MLX5E_40GBASE_XLAUI_4_XLPPI_4 = 5,
102 MLX5E_25GAUI_1_25GBASE_CR_KR = 6,
103 MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 = 7,
104 MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR = 8,
105 MLX5E_CAUI_4_100GBASE_CR4_KR4 = 9,
106 MLX5E_100GAUI_2_100GBASE_CR2_KR2 = 10,
107 MLX5E_100GAUI_1_100GBASE_CR_KR = 11,
108 MLX5E_200GAUI_4_200GBASE_CR4_KR4 = 12,
109 MLX5E_200GAUI_2_200GBASE_CR2_KR2 = 13,
110 MLX5E_400GAUI_8 = 15,
111 MLX5E_400GAUI_4_400GBASE_CR4_KR4 = 16,
112 MLX5E_EXT_LINK_MODES_NUMBER,
115 enum mlx5e_connector_type {
116 MLX5E_PORT_UNKNOWN = 0,
122 MLX5E_PORT_FIBRE = 6,
124 MLX5E_PORT_OTHER = 8,
125 MLX5E_CONNECTOR_TYPE_NUMBER,
128 enum mlx5_ptys_width {
129 MLX5_PTYS_WIDTH_1X = 1 << 0,
130 MLX5_PTYS_WIDTH_2X = 1 << 1,
131 MLX5_PTYS_WIDTH_4X = 1 << 2,
132 MLX5_PTYS_WIDTH_8X = 1 << 3,
133 MLX5_PTYS_WIDTH_12X = 1 << 4,
136 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
137 #define MLX5_GET_ETH_PROTO(reg, out, ext, field) \
138 (ext ? MLX5_GET(reg, out, ext_##field) : \
139 MLX5_GET(reg, out, field))
141 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
142 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
143 int ptys_size, int proto_mask, u8 local_port);
145 int mlx5_query_ib_port_oper(struct mlx5_core_dev *dev, u16 *link_width_oper,
146 u16 *proto_oper, u8 local_port);
147 void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
148 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
149 enum mlx5_port_status status);
150 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
151 enum mlx5_port_status *status);
152 int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration);
154 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port);
155 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu, u8 port);
156 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu,
159 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
160 u8 *vl_hw_cap, u8 local_port);
162 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause);
163 int mlx5_query_port_pause(struct mlx5_core_dev *dev,
164 u32 *rx_pause, u32 *tx_pause);
166 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx);
167 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx,
170 int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev,
171 u16 stall_critical_watermark,
172 u16 stall_minor_watermark);
173 int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev,
174 u16 *stall_critical_watermark, u16 *stall_minor_watermark);
176 int mlx5_max_tc(struct mlx5_core_dev *mdev);
178 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc);
179 int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev,
181 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group);
182 int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev,
183 u8 tc, u8 *tc_group);
184 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw);
185 int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev,
187 int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
190 int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
193 int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode);
194 int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode);
196 int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out, int outlen);
197 int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen);
198 int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable);
199 void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported,
201 int mlx5_query_module_eeprom(struct mlx5_core_dev *dev,
202 u16 offset, u16 size, u8 *data);
204 int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out);
205 int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in);
207 int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state);
208 int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state);
209 int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio);
210 int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio);
211 #endif /* __MLX5_PORT_H__ */