1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2020 Mellanox Technologies Ltd. */
4 #ifndef __MLX5_IFC_VDPA_H_
5 #define __MLX5_IFC_VDPA_H_
8 MLX5_VIRTIO_Q_EVENT_MODE_NO_MSIX_MODE = 0x0,
9 MLX5_VIRTIO_Q_EVENT_MODE_QP_MODE = 0x1,
10 MLX5_VIRTIO_Q_EVENT_MODE_MSIX_MODE = 0x2,
14 MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYPE_SPLIT = 0,
15 MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYPE_PACKED = 1,
19 MLX5_VIRTIO_EMULATION_CAP_VIRTIO_QUEUE_TYPE_SPLIT =
20 BIT(MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYPE_SPLIT),
21 MLX5_VIRTIO_EMULATION_CAP_VIRTIO_QUEUE_TYPE_PACKED =
22 BIT(MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYPE_PACKED),
25 struct mlx5_ifc_virtio_q_bits {
26 u8 virtio_q_type[0x8];
27 u8 reserved_at_8[0x5];
31 u8 full_emulation[0x1];
32 u8 virtio_version_1_0[0x1];
33 u8 reserved_at_22[0x2];
35 u8 event_qpn_or_msix[0x18];
37 u8 doorbell_stride_index[0x10];
40 u8 device_emulation_id[0x20];
46 u8 available_addr[0x40];
48 u8 virtio_q_mkey[0x20];
50 u8 max_tunnel_desc[0x10];
51 u8 reserved_at_170[0x8];
58 u8 umem_1_offset[0x40];
64 u8 umem_2_offset[0x40];
70 u8 umem_3_offset[0x40];
72 u8 counter_set_id[0x20];
74 u8 reserved_at_320[0x8];
77 u8 reserved_at_340[0xc0];
80 struct mlx5_ifc_virtio_net_q_object_bits {
81 u8 modify_field_select[0x40];
83 u8 reserved_at_40[0x20];
86 u8 reserved_at_70[0x10];
88 u8 queue_feature_bit_mask_12_3[0xa];
89 u8 dirty_bitmap_dump_enable[0x1];
90 u8 vhost_log_page[0x5];
91 u8 reserved_at_90[0xc];
94 u8 reserved_at_a0[0x5];
95 u8 queue_feature_bit_mask_2_0[0x3];
98 u8 dirty_bitmap_mkey[0x20];
100 u8 dirty_bitmap_size[0x20];
102 u8 dirty_bitmap_addr[0x40];
104 u8 hw_available_index[0x10];
105 u8 hw_used_index[0x10];
107 u8 reserved_at_160[0xa0];
109 struct mlx5_ifc_virtio_q_bits virtio_q_context;
112 struct mlx5_ifc_create_virtio_net_q_in_bits {
113 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
115 struct mlx5_ifc_virtio_net_q_object_bits obj_context;
118 struct mlx5_ifc_create_virtio_net_q_out_bits {
119 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
122 struct mlx5_ifc_destroy_virtio_net_q_in_bits {
123 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_out_cmd_hdr;
126 struct mlx5_ifc_destroy_virtio_net_q_out_bits {
127 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
130 struct mlx5_ifc_query_virtio_net_q_in_bits {
131 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
134 struct mlx5_ifc_query_virtio_net_q_out_bits {
135 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
137 struct mlx5_ifc_virtio_net_q_object_bits obj_context;
141 MLX5_VIRTQ_MODIFY_MASK_STATE = (u64)1 << 0,
142 MLX5_VIRTQ_MODIFY_MASK_DIRTY_BITMAP_PARAMS = (u64)1 << 3,
143 MLX5_VIRTQ_MODIFY_MASK_DIRTY_BITMAP_DUMP_ENABLE = (u64)1 << 4,
147 MLX5_VIRTIO_NET_Q_OBJECT_STATE_INIT = 0x0,
148 MLX5_VIRTIO_NET_Q_OBJECT_STATE_RDY = 0x1,
149 MLX5_VIRTIO_NET_Q_OBJECT_STATE_SUSPEND = 0x2,
150 MLX5_VIRTIO_NET_Q_OBJECT_STATE_ERR = 0x3,
154 MLX5_RQTC_LIST_Q_TYPE_RQ = 0x0,
155 MLX5_RQTC_LIST_Q_TYPE_VIRTIO_NET_Q = 0x1,
158 struct mlx5_ifc_modify_virtio_net_q_in_bits {
159 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
161 struct mlx5_ifc_virtio_net_q_object_bits obj_context;
164 struct mlx5_ifc_modify_virtio_net_q_out_bits {
165 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
168 #endif /* __MLX5_IFC_VDPA_H_ */