2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 #ifndef MLX5_IFC_FPGA_H
33 #define MLX5_IFC_FPGA_H
36 MLX5_FPGA_CAP_SANDBOX_VENDOR_ID_MLNX = 0x2c9,
40 MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_IPSEC = 0x2,
43 struct mlx5_ifc_fpga_shell_caps_bits {
45 u8 reserved_at_10[0x8];
46 u8 total_rcv_credits[0x8];
48 u8 reserved_at_20[0xe];
50 u8 reserved_at_30[0x5];
54 u8 reserved_at_38[0x4];
60 u8 reserved_at_40[0x1a];
63 u8 max_fpga_qp_msg_size[0x20];
65 u8 reserved_at_80[0x180];
68 struct mlx5_ifc_fpga_cap_bits {
72 u8 register_file_ver[0x20];
74 u8 fpga_ctrl_modify[0x1];
75 u8 reserved_at_41[0x5];
76 u8 access_reg_query_mode[0x2];
77 u8 reserved_at_48[0x6];
78 u8 access_reg_modify_mode[0x2];
79 u8 reserved_at_50[0x10];
81 u8 reserved_at_60[0x20];
83 u8 image_version[0x20];
89 u8 shell_version[0x20];
91 u8 reserved_at_100[0x80];
93 struct mlx5_ifc_fpga_shell_caps_bits shell_caps;
95 u8 reserved_at_380[0x8];
96 u8 ieee_vendor_id[0x18];
98 u8 sandbox_product_version[0x10];
99 u8 sandbox_product_id[0x10];
101 u8 sandbox_basic_caps[0x20];
103 u8 reserved_at_3e0[0x10];
104 u8 sandbox_extended_caps_len[0x10];
106 u8 sandbox_extended_caps_addr[0x40];
108 u8 fpga_ddr_start_addr[0x40];
110 u8 fpga_cr_space_start_addr[0x40];
112 u8 fpga_ddr_size[0x20];
114 u8 fpga_cr_space_size[0x20];
116 u8 reserved_at_500[0x300];
120 MLX5_FPGA_CTRL_OPERATION_LOAD = 0x1,
121 MLX5_FPGA_CTRL_OPERATION_RESET = 0x2,
122 MLX5_FPGA_CTRL_OPERATION_FLASH_SELECT = 0x3,
123 MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_ON = 0x4,
124 MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_OFF = 0x5,
125 MLX5_FPGA_CTRL_OPERATION_RESET_SANDBOX = 0x6,
128 struct mlx5_ifc_fpga_ctrl_bits {
129 u8 reserved_at_0[0x8];
131 u8 reserved_at_10[0x8];
134 u8 reserved_at_20[0x8];
135 u8 flash_select_admin[0x8];
136 u8 reserved_at_30[0x8];
137 u8 flash_select_oper[0x8];
139 u8 reserved_at_40[0x40];
143 MLX5_FPGA_ERROR_EVENT_SYNDROME_CORRUPTED_DDR = 0x1,
144 MLX5_FPGA_ERROR_EVENT_SYNDROME_FLASH_TIMEOUT = 0x2,
145 MLX5_FPGA_ERROR_EVENT_SYNDROME_INTERNAL_LINK_ERROR = 0x3,
146 MLX5_FPGA_ERROR_EVENT_SYNDROME_WATCHDOG_FAILURE = 0x4,
147 MLX5_FPGA_ERROR_EVENT_SYNDROME_I2C_FAILURE = 0x5,
148 MLX5_FPGA_ERROR_EVENT_SYNDROME_IMAGE_CHANGED = 0x6,
149 MLX5_FPGA_ERROR_EVENT_SYNDROME_TEMPERATURE_CRITICAL = 0x7,
152 struct mlx5_ifc_fpga_error_event_bits {
153 u8 reserved_at_0[0x40];
155 u8 reserved_at_40[0x18];
158 u8 reserved_at_60[0x80];
161 #define MLX5_FPGA_ACCESS_REG_SIZE_MAX 64
163 struct mlx5_ifc_fpga_access_reg_bits {
164 u8 reserved_at_0[0x20];
166 u8 reserved_at_20[0x10];
174 enum mlx5_ifc_fpga_qp_state {
175 MLX5_FPGA_QPC_STATE_INIT = 0x0,
176 MLX5_FPGA_QPC_STATE_ACTIVE = 0x1,
177 MLX5_FPGA_QPC_STATE_ERROR = 0x2,
180 enum mlx5_ifc_fpga_qp_type {
181 MLX5_FPGA_QPC_QP_TYPE_SHELL_QP = 0x0,
182 MLX5_FPGA_QPC_QP_TYPE_SANDBOX_QP = 0x1,
185 enum mlx5_ifc_fpga_qp_service_type {
186 MLX5_FPGA_QPC_ST_RC = 0x0,
189 struct mlx5_ifc_fpga_qpc_bits {
191 u8 reserved_at_4[0x1b];
194 u8 reserved_at_20[0x4];
196 u8 reserved_at_28[0x10];
197 u8 traffic_class[0x8];
204 u8 reserved_at_60[0x20];
206 u8 reserved_at_80[0x8];
207 u8 next_rcv_psn[0x18];
209 u8 reserved_at_a0[0x8];
210 u8 next_send_psn[0x18];
212 u8 reserved_at_c0[0x10];
215 u8 reserved_at_e0[0x8];
218 u8 reserved_at_100[0x15];
220 u8 reserved_at_118[0x5];
223 u8 reserved_at_120[0x20];
225 u8 reserved_at_140[0x10];
226 u8 remote_mac_47_32[0x10];
228 u8 remote_mac_31_0[0x20];
230 u8 remote_ip[16][0x8];
232 u8 reserved_at_200[0x40];
234 u8 reserved_at_240[0x10];
235 u8 fpga_mac_47_32[0x10];
237 u8 fpga_mac_31_0[0x20];
242 struct mlx5_ifc_fpga_create_qp_in_bits {
244 u8 reserved_at_10[0x10];
246 u8 reserved_at_20[0x10];
249 u8 reserved_at_40[0x40];
251 struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
254 struct mlx5_ifc_fpga_create_qp_out_bits {
256 u8 reserved_at_8[0x18];
260 u8 reserved_at_40[0x8];
263 u8 reserved_at_60[0x20];
265 struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
268 struct mlx5_ifc_fpga_modify_qp_in_bits {
270 u8 reserved_at_10[0x10];
272 u8 reserved_at_20[0x10];
275 u8 reserved_at_40[0x8];
278 u8 field_select[0x20];
280 struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
283 struct mlx5_ifc_fpga_modify_qp_out_bits {
285 u8 reserved_at_8[0x18];
289 u8 reserved_at_40[0x40];
292 struct mlx5_ifc_fpga_query_qp_in_bits {
294 u8 reserved_at_10[0x10];
296 u8 reserved_at_20[0x10];
299 u8 reserved_at_40[0x8];
302 u8 reserved_at_60[0x20];
305 struct mlx5_ifc_fpga_query_qp_out_bits {
307 u8 reserved_at_8[0x18];
311 u8 reserved_at_40[0x40];
313 struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
316 struct mlx5_ifc_fpga_query_qp_counters_in_bits {
318 u8 reserved_at_10[0x10];
320 u8 reserved_at_20[0x10];
324 u8 reserved_at_41[0x7];
327 u8 reserved_at_60[0x20];
330 struct mlx5_ifc_fpga_query_qp_counters_out_bits {
332 u8 reserved_at_8[0x18];
336 u8 reserved_at_40[0x40];
338 u8 rx_ack_packets[0x40];
340 u8 rx_send_packets[0x40];
342 u8 tx_ack_packets[0x40];
344 u8 tx_send_packets[0x40];
346 u8 rx_total_drop[0x40];
348 u8 reserved_at_1c0[0x1c0];
351 struct mlx5_ifc_fpga_destroy_qp_in_bits {
353 u8 reserved_at_10[0x10];
355 u8 reserved_at_20[0x10];
358 u8 reserved_at_40[0x8];
361 u8 reserved_at_60[0x20];
364 struct mlx5_ifc_fpga_destroy_qp_out_bits {
366 u8 reserved_at_8[0x18];
370 u8 reserved_at_40[0x40];
373 struct mlx5_ifc_ipsec_extended_cap_bits {
374 u8 encapsulation[0x20];
377 u8 ipv4_fragment[0x1];
381 u8 transport_and_tunnel_mode[0x1];
383 u8 transport_mode[0x1];
387 u8 ipv4_options[0x1];
396 u8 number_of_ipsec_counters[0x10];
398 u8 ipsec_counters_addr_low[0x20];
399 u8 ipsec_counters_addr_high[0x20];
402 struct mlx5_ifc_ipsec_counters_bits {
403 u8 dec_in_packets[0x40];
405 u8 dec_out_packets[0x40];
407 u8 dec_bypass_packets[0x40];
409 u8 enc_in_packets[0x40];
411 u8 enc_out_packets[0x40];
413 u8 enc_bypass_packets[0x40];
415 u8 drop_dec_packets[0x40];
417 u8 failed_auth_dec_packets[0x40];
419 u8 drop_enc_packets[0x40];
421 u8 success_add_sa[0x40];
423 u8 fail_add_sa[0x40];
425 u8 success_delete_sa[0x40];
427 u8 fail_delete_sa[0x40];
429 u8 dropped_cmd[0x40];
432 #endif /* MLX5_IFC_FPGA_H */