2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 #ifndef MLX5_IFC_FPGA_H
33 #define MLX5_IFC_FPGA_H
35 struct mlx5_ifc_ipv4_layout_bits {
36 u8 reserved_at_0[0x60];
41 struct mlx5_ifc_ipv6_layout_bits {
45 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
46 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
47 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
48 u8 reserved_at_0[0x80];
52 MLX5_FPGA_CAP_SANDBOX_VENDOR_ID_MLNX = 0x2c9,
56 MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_IPSEC = 0x2,
57 MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_TLS = 0x3,
60 struct mlx5_ifc_fpga_shell_caps_bits {
62 u8 reserved_at_10[0x8];
63 u8 total_rcv_credits[0x8];
65 u8 reserved_at_20[0xe];
67 u8 reserved_at_30[0x5];
71 u8 reserved_at_38[0x4];
77 u8 reserved_at_40[0x1a];
80 u8 max_fpga_qp_msg_size[0x20];
82 u8 reserved_at_80[0x180];
85 struct mlx5_ifc_fpga_cap_bits {
89 u8 register_file_ver[0x20];
91 u8 fpga_ctrl_modify[0x1];
92 u8 reserved_at_41[0x5];
93 u8 access_reg_query_mode[0x2];
94 u8 reserved_at_48[0x6];
95 u8 access_reg_modify_mode[0x2];
96 u8 reserved_at_50[0x10];
98 u8 reserved_at_60[0x20];
100 u8 image_version[0x20];
106 u8 shell_version[0x20];
108 u8 reserved_at_100[0x80];
110 struct mlx5_ifc_fpga_shell_caps_bits shell_caps;
112 u8 reserved_at_380[0x8];
113 u8 ieee_vendor_id[0x18];
115 u8 sandbox_product_version[0x10];
116 u8 sandbox_product_id[0x10];
118 u8 sandbox_basic_caps[0x20];
120 u8 reserved_at_3e0[0x10];
121 u8 sandbox_extended_caps_len[0x10];
123 u8 sandbox_extended_caps_addr[0x40];
125 u8 fpga_ddr_start_addr[0x40];
127 u8 fpga_cr_space_start_addr[0x40];
129 u8 fpga_ddr_size[0x20];
131 u8 fpga_cr_space_size[0x20];
133 u8 reserved_at_500[0x300];
137 MLX5_FPGA_CTRL_OPERATION_LOAD = 0x1,
138 MLX5_FPGA_CTRL_OPERATION_RESET = 0x2,
139 MLX5_FPGA_CTRL_OPERATION_FLASH_SELECT = 0x3,
140 MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_ON = 0x4,
141 MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_OFF = 0x5,
142 MLX5_FPGA_CTRL_OPERATION_RESET_SANDBOX = 0x6,
145 struct mlx5_ifc_fpga_ctrl_bits {
146 u8 reserved_at_0[0x8];
148 u8 reserved_at_10[0x8];
151 u8 reserved_at_20[0x8];
152 u8 flash_select_admin[0x8];
153 u8 reserved_at_30[0x8];
154 u8 flash_select_oper[0x8];
156 u8 reserved_at_40[0x40];
160 MLX5_FPGA_ERROR_EVENT_SYNDROME_CORRUPTED_DDR = 0x1,
161 MLX5_FPGA_ERROR_EVENT_SYNDROME_FLASH_TIMEOUT = 0x2,
162 MLX5_FPGA_ERROR_EVENT_SYNDROME_INTERNAL_LINK_ERROR = 0x3,
163 MLX5_FPGA_ERROR_EVENT_SYNDROME_WATCHDOG_FAILURE = 0x4,
164 MLX5_FPGA_ERROR_EVENT_SYNDROME_I2C_FAILURE = 0x5,
165 MLX5_FPGA_ERROR_EVENT_SYNDROME_IMAGE_CHANGED = 0x6,
166 MLX5_FPGA_ERROR_EVENT_SYNDROME_TEMPERATURE_CRITICAL = 0x7,
169 struct mlx5_ifc_fpga_error_event_bits {
170 u8 reserved_at_0[0x40];
172 u8 reserved_at_40[0x18];
175 u8 reserved_at_60[0x80];
178 #define MLX5_FPGA_ACCESS_REG_SIZE_MAX 64
180 struct mlx5_ifc_fpga_access_reg_bits {
181 u8 reserved_at_0[0x20];
183 u8 reserved_at_20[0x10];
191 enum mlx5_ifc_fpga_qp_state {
192 MLX5_FPGA_QPC_STATE_INIT = 0x0,
193 MLX5_FPGA_QPC_STATE_ACTIVE = 0x1,
194 MLX5_FPGA_QPC_STATE_ERROR = 0x2,
197 enum mlx5_ifc_fpga_qp_type {
198 MLX5_FPGA_QPC_QP_TYPE_SHELL_QP = 0x0,
199 MLX5_FPGA_QPC_QP_TYPE_SANDBOX_QP = 0x1,
202 enum mlx5_ifc_fpga_qp_service_type {
203 MLX5_FPGA_QPC_ST_RC = 0x0,
206 struct mlx5_ifc_fpga_qpc_bits {
208 u8 reserved_at_4[0x1b];
211 u8 reserved_at_20[0x4];
213 u8 reserved_at_28[0x10];
214 u8 traffic_class[0x8];
221 u8 reserved_at_60[0x20];
223 u8 reserved_at_80[0x8];
224 u8 next_rcv_psn[0x18];
226 u8 reserved_at_a0[0x8];
227 u8 next_send_psn[0x18];
229 u8 reserved_at_c0[0x10];
232 u8 reserved_at_e0[0x8];
235 u8 reserved_at_100[0x15];
237 u8 reserved_at_118[0x5];
240 u8 reserved_at_120[0x20];
242 u8 reserved_at_140[0x10];
243 u8 remote_mac_47_32[0x10];
245 u8 remote_mac_31_0[0x20];
247 u8 remote_ip[16][0x8];
249 u8 reserved_at_200[0x40];
251 u8 reserved_at_240[0x10];
252 u8 fpga_mac_47_32[0x10];
254 u8 fpga_mac_31_0[0x20];
259 struct mlx5_ifc_fpga_create_qp_in_bits {
261 u8 reserved_at_10[0x10];
263 u8 reserved_at_20[0x10];
266 u8 reserved_at_40[0x40];
268 struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
271 struct mlx5_ifc_fpga_create_qp_out_bits {
273 u8 reserved_at_8[0x18];
277 u8 reserved_at_40[0x8];
280 u8 reserved_at_60[0x20];
282 struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
285 struct mlx5_ifc_fpga_modify_qp_in_bits {
287 u8 reserved_at_10[0x10];
289 u8 reserved_at_20[0x10];
292 u8 reserved_at_40[0x8];
295 u8 field_select[0x20];
297 struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
300 struct mlx5_ifc_fpga_modify_qp_out_bits {
302 u8 reserved_at_8[0x18];
306 u8 reserved_at_40[0x40];
309 struct mlx5_ifc_fpga_query_qp_in_bits {
311 u8 reserved_at_10[0x10];
313 u8 reserved_at_20[0x10];
316 u8 reserved_at_40[0x8];
319 u8 reserved_at_60[0x20];
322 struct mlx5_ifc_fpga_query_qp_out_bits {
324 u8 reserved_at_8[0x18];
328 u8 reserved_at_40[0x40];
330 struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
333 struct mlx5_ifc_fpga_query_qp_counters_in_bits {
335 u8 reserved_at_10[0x10];
337 u8 reserved_at_20[0x10];
341 u8 reserved_at_41[0x7];
344 u8 reserved_at_60[0x20];
347 struct mlx5_ifc_fpga_query_qp_counters_out_bits {
349 u8 reserved_at_8[0x18];
353 u8 reserved_at_40[0x40];
355 u8 rx_ack_packets[0x40];
357 u8 rx_send_packets[0x40];
359 u8 tx_ack_packets[0x40];
361 u8 tx_send_packets[0x40];
363 u8 rx_total_drop[0x40];
365 u8 reserved_at_1c0[0x1c0];
368 struct mlx5_ifc_fpga_destroy_qp_in_bits {
370 u8 reserved_at_10[0x10];
372 u8 reserved_at_20[0x10];
375 u8 reserved_at_40[0x8];
378 u8 reserved_at_60[0x20];
381 struct mlx5_ifc_fpga_destroy_qp_out_bits {
383 u8 reserved_at_8[0x18];
387 u8 reserved_at_40[0x40];
390 struct mlx5_ifc_tls_extended_cap_bits {
393 u8 reserved_at_2[0x1e];
394 u8 reserved_at_20[0x20];
395 u8 context_capacity_total[0x20];
396 u8 context_capacity_rx[0x20];
397 u8 context_capacity_tx[0x20];
398 u8 reserved_at_a0[0x10];
399 u8 tls_counter_size[0x10];
400 u8 tls_counters_addr_low[0x20];
401 u8 tls_counters_addr_high[0x20];
408 u8 reserved_at_106[0x1a];
411 struct mlx5_ifc_ipsec_extended_cap_bits {
412 u8 encapsulation[0x20];
417 u8 rx_no_trailer[0x1];
418 u8 ipv4_fragment[0x1];
422 u8 transport_and_tunnel_mode[0x1];
424 u8 transport_mode[0x1];
428 u8 ipv4_options[0x1];
437 u8 number_of_ipsec_counters[0x10];
439 u8 ipsec_counters_addr_low[0x20];
440 u8 ipsec_counters_addr_high[0x20];
443 struct mlx5_ifc_ipsec_counters_bits {
444 u8 dec_in_packets[0x40];
446 u8 dec_out_packets[0x40];
448 u8 dec_bypass_packets[0x40];
450 u8 enc_in_packets[0x40];
452 u8 enc_out_packets[0x40];
454 u8 enc_bypass_packets[0x40];
456 u8 drop_dec_packets[0x40];
458 u8 failed_auth_dec_packets[0x40];
460 u8 drop_enc_packets[0x40];
462 u8 success_add_sa[0x40];
464 u8 fail_add_sa[0x40];
466 u8 success_delete_sa[0x40];
468 u8 fail_delete_sa[0x40];
470 u8 dropped_cmd[0x40];
474 MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RETRY_COUNTER_EXPIRED = 0x1,
475 MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RNR_EXPIRED = 0x2,
478 struct mlx5_ifc_fpga_qp_error_event_bits {
479 u8 reserved_at_0[0x40];
481 u8 reserved_at_40[0x18];
484 u8 reserved_at_60[0x60];
486 u8 reserved_at_c0[0x8];
489 enum mlx5_ifc_fpga_ipsec_response_syndrome {
490 MLX5_FPGA_IPSEC_RESPONSE_SUCCESS = 0,
491 MLX5_FPGA_IPSEC_RESPONSE_ILLEGAL_REQUEST = 1,
492 MLX5_FPGA_IPSEC_RESPONSE_SADB_ISSUE = 2,
493 MLX5_FPGA_IPSEC_RESPONSE_WRITE_RESPONSE_ISSUE = 3,
496 struct mlx5_ifc_fpga_ipsec_cmd_resp {
505 enum mlx5_ifc_fpga_ipsec_cmd_opcode {
506 MLX5_FPGA_IPSEC_CMD_OP_ADD_SA = 0,
507 MLX5_FPGA_IPSEC_CMD_OP_DEL_SA = 1,
508 MLX5_FPGA_IPSEC_CMD_OP_ADD_SA_V2 = 2,
509 MLX5_FPGA_IPSEC_CMD_OP_DEL_SA_V2 = 3,
510 MLX5_FPGA_IPSEC_CMD_OP_MOD_SA_V2 = 4,
511 MLX5_FPGA_IPSEC_CMD_OP_SET_CAP = 5,
514 enum mlx5_ifc_fpga_ipsec_cap {
515 MLX5_FPGA_IPSEC_CAP_NO_TRAILER = BIT(0),
518 struct mlx5_ifc_fpga_ipsec_cmd_cap {
524 enum mlx5_ifc_fpga_ipsec_sa_flags {
525 MLX5_FPGA_IPSEC_SA_ESN_EN = BIT(0),
526 MLX5_FPGA_IPSEC_SA_ESN_OVERLAP = BIT(1),
527 MLX5_FPGA_IPSEC_SA_IPV6 = BIT(2),
528 MLX5_FPGA_IPSEC_SA_DIR_SX = BIT(3),
529 MLX5_FPGA_IPSEC_SA_SPI_EN = BIT(4),
530 MLX5_FPGA_IPSEC_SA_SA_VALID = BIT(5),
531 MLX5_FPGA_IPSEC_SA_IP_ESP = BIT(6),
532 MLX5_FPGA_IPSEC_SA_IP_AH = BIT(7),
535 enum mlx5_ifc_fpga_ipsec_sa_enc_mode {
536 MLX5_FPGA_IPSEC_SA_ENC_MODE_NONE = 0,
537 MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_128_AUTH_128 = 1,
538 MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_256_AUTH_128 = 3,
541 struct mlx5_ifc_fpga_ipsec_sa_v1 {
566 struct mlx5_ifc_fpga_ipsec_sa {
567 struct mlx5_ifc_fpga_ipsec_sa_v1 ipsec_sa_v1;
572 __be16 vid; /* only 12 bits, rest is reserved */
577 CMD_SETUP_STREAM = 0x1001,
578 CMD_TEARDOWN_STREAM = 0x1002,
579 CMD_RESYNC_RX = 0x1003,
582 #define MLX5_TLS_1_2 (0)
584 #define MLX5_TLS_ALG_AES_GCM_128 (0)
585 #define MLX5_TLS_ALG_AES_GCM_256 (1)
587 struct mlx5_ifc_tls_cmd_bits {
588 u8 command_type[0x20];
590 u8 direction_sx[0x1];
596 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
597 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
600 u8 tls_implicit_iv[0x20];
602 u8 encryption_key[0x100];
608 struct mlx5_ifc_tls_resp_bits {
614 #define MLX5_TLS_COMMAND_SIZE (0x100)
616 #endif /* MLX5_IFC_FPGA_H */