2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "mlx5_ifc_fpga.h"
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
75 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
79 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4),
80 MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5),
84 MLX5_OBJ_TYPE_UCTX = 0x0004,
85 MLX5_OBJ_TYPE_UMEM = 0x0005,
89 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
90 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
91 MLX5_CMD_OP_INIT_HCA = 0x102,
92 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
93 MLX5_CMD_OP_ENABLE_HCA = 0x104,
94 MLX5_CMD_OP_DISABLE_HCA = 0x105,
95 MLX5_CMD_OP_QUERY_PAGES = 0x107,
96 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
97 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
98 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
99 MLX5_CMD_OP_SET_ISSI = 0x10b,
100 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
101 MLX5_CMD_OP_CREATE_MKEY = 0x200,
102 MLX5_CMD_OP_QUERY_MKEY = 0x201,
103 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
104 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
105 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
106 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
107 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
108 MLX5_CMD_OP_CREATE_EQ = 0x301,
109 MLX5_CMD_OP_DESTROY_EQ = 0x302,
110 MLX5_CMD_OP_QUERY_EQ = 0x303,
111 MLX5_CMD_OP_GEN_EQE = 0x304,
112 MLX5_CMD_OP_CREATE_CQ = 0x400,
113 MLX5_CMD_OP_DESTROY_CQ = 0x401,
114 MLX5_CMD_OP_QUERY_CQ = 0x402,
115 MLX5_CMD_OP_MODIFY_CQ = 0x403,
116 MLX5_CMD_OP_CREATE_QP = 0x500,
117 MLX5_CMD_OP_DESTROY_QP = 0x501,
118 MLX5_CMD_OP_RST2INIT_QP = 0x502,
119 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
120 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
121 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
122 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
123 MLX5_CMD_OP_2ERR_QP = 0x507,
124 MLX5_CMD_OP_2RST_QP = 0x50a,
125 MLX5_CMD_OP_QUERY_QP = 0x50b,
126 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
127 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
128 MLX5_CMD_OP_CREATE_PSV = 0x600,
129 MLX5_CMD_OP_DESTROY_PSV = 0x601,
130 MLX5_CMD_OP_CREATE_SRQ = 0x700,
131 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
132 MLX5_CMD_OP_QUERY_SRQ = 0x702,
133 MLX5_CMD_OP_ARM_RQ = 0x703,
134 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
135 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
136 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
137 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
138 MLX5_CMD_OP_CREATE_DCT = 0x710,
139 MLX5_CMD_OP_DESTROY_DCT = 0x711,
140 MLX5_CMD_OP_DRAIN_DCT = 0x712,
141 MLX5_CMD_OP_QUERY_DCT = 0x713,
142 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
143 MLX5_CMD_OP_CREATE_XRQ = 0x717,
144 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
145 MLX5_CMD_OP_QUERY_XRQ = 0x719,
146 MLX5_CMD_OP_ARM_XRQ = 0x71a,
147 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
148 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
149 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
150 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
151 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
152 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
153 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
154 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
155 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
156 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
157 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
158 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
159 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
160 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
161 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
162 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
163 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
164 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
165 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
166 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
167 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
168 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
169 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
170 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
171 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
172 MLX5_CMD_OP_ALLOC_PD = 0x800,
173 MLX5_CMD_OP_DEALLOC_PD = 0x801,
174 MLX5_CMD_OP_ALLOC_UAR = 0x802,
175 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
176 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
177 MLX5_CMD_OP_ACCESS_REG = 0x805,
178 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
179 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
180 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
181 MLX5_CMD_OP_MAD_IFC = 0x50d,
182 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
183 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
184 MLX5_CMD_OP_NOP = 0x80d,
185 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
186 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
187 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
188 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
189 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
190 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
191 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
192 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
193 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
194 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
195 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
196 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
197 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
198 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
199 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
200 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
201 MLX5_CMD_OP_CREATE_LAG = 0x840,
202 MLX5_CMD_OP_MODIFY_LAG = 0x841,
203 MLX5_CMD_OP_QUERY_LAG = 0x842,
204 MLX5_CMD_OP_DESTROY_LAG = 0x843,
205 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
206 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
207 MLX5_CMD_OP_CREATE_TIR = 0x900,
208 MLX5_CMD_OP_MODIFY_TIR = 0x901,
209 MLX5_CMD_OP_DESTROY_TIR = 0x902,
210 MLX5_CMD_OP_QUERY_TIR = 0x903,
211 MLX5_CMD_OP_CREATE_SQ = 0x904,
212 MLX5_CMD_OP_MODIFY_SQ = 0x905,
213 MLX5_CMD_OP_DESTROY_SQ = 0x906,
214 MLX5_CMD_OP_QUERY_SQ = 0x907,
215 MLX5_CMD_OP_CREATE_RQ = 0x908,
216 MLX5_CMD_OP_MODIFY_RQ = 0x909,
217 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
218 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
219 MLX5_CMD_OP_QUERY_RQ = 0x90b,
220 MLX5_CMD_OP_CREATE_RMP = 0x90c,
221 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
222 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
223 MLX5_CMD_OP_QUERY_RMP = 0x90f,
224 MLX5_CMD_OP_CREATE_TIS = 0x912,
225 MLX5_CMD_OP_MODIFY_TIS = 0x913,
226 MLX5_CMD_OP_DESTROY_TIS = 0x914,
227 MLX5_CMD_OP_QUERY_TIS = 0x915,
228 MLX5_CMD_OP_CREATE_RQT = 0x916,
229 MLX5_CMD_OP_MODIFY_RQT = 0x917,
230 MLX5_CMD_OP_DESTROY_RQT = 0x918,
231 MLX5_CMD_OP_QUERY_RQT = 0x919,
232 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
233 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
234 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
235 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
236 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
237 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
238 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
239 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
240 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
241 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
242 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
243 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
244 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
245 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
246 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
247 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
248 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
249 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
250 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
251 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
252 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
253 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
254 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
255 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
256 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
257 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
258 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
259 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
263 struct mlx5_ifc_flow_table_fields_supported_bits {
266 u8 outer_ether_type[0x1];
267 u8 outer_ip_version[0x1];
268 u8 outer_first_prio[0x1];
269 u8 outer_first_cfi[0x1];
270 u8 outer_first_vid[0x1];
271 u8 outer_ipv4_ttl[0x1];
272 u8 outer_second_prio[0x1];
273 u8 outer_second_cfi[0x1];
274 u8 outer_second_vid[0x1];
275 u8 reserved_at_b[0x1];
279 u8 outer_ip_protocol[0x1];
280 u8 outer_ip_ecn[0x1];
281 u8 outer_ip_dscp[0x1];
282 u8 outer_udp_sport[0x1];
283 u8 outer_udp_dport[0x1];
284 u8 outer_tcp_sport[0x1];
285 u8 outer_tcp_dport[0x1];
286 u8 outer_tcp_flags[0x1];
287 u8 outer_gre_protocol[0x1];
288 u8 outer_gre_key[0x1];
289 u8 outer_vxlan_vni[0x1];
290 u8 reserved_at_1a[0x5];
291 u8 source_eswitch_port[0x1];
295 u8 inner_ether_type[0x1];
296 u8 inner_ip_version[0x1];
297 u8 inner_first_prio[0x1];
298 u8 inner_first_cfi[0x1];
299 u8 inner_first_vid[0x1];
300 u8 reserved_at_27[0x1];
301 u8 inner_second_prio[0x1];
302 u8 inner_second_cfi[0x1];
303 u8 inner_second_vid[0x1];
304 u8 reserved_at_2b[0x1];
308 u8 inner_ip_protocol[0x1];
309 u8 inner_ip_ecn[0x1];
310 u8 inner_ip_dscp[0x1];
311 u8 inner_udp_sport[0x1];
312 u8 inner_udp_dport[0x1];
313 u8 inner_tcp_sport[0x1];
314 u8 inner_tcp_dport[0x1];
315 u8 inner_tcp_flags[0x1];
316 u8 reserved_at_37[0x9];
318 u8 reserved_at_40[0x5];
319 u8 outer_first_mpls_over_udp[0x4];
320 u8 outer_first_mpls_over_gre[0x4];
321 u8 inner_first_mpls[0x4];
322 u8 outer_first_mpls[0x4];
323 u8 reserved_at_55[0x2];
324 u8 outer_esp_spi[0x1];
325 u8 reserved_at_58[0x2];
328 u8 reserved_at_5b[0x25];
331 struct mlx5_ifc_flow_table_prop_layout_bits {
333 u8 reserved_at_1[0x1];
334 u8 flow_counter[0x1];
335 u8 flow_modify_en[0x1];
337 u8 identified_miss_table_mode[0x1];
338 u8 flow_table_modify[0x1];
341 u8 reserved_at_9[0x1];
344 u8 reserved_at_c[0x1];
347 u8 reserved_at_f[0x11];
349 u8 reserved_at_20[0x2];
350 u8 log_max_ft_size[0x6];
351 u8 log_max_modify_header_context[0x8];
352 u8 max_modify_header_actions[0x8];
353 u8 max_ft_level[0x8];
355 u8 reserved_at_40[0x20];
357 u8 reserved_at_60[0x18];
358 u8 log_max_ft_num[0x8];
360 u8 reserved_at_80[0x10];
361 u8 log_max_flow_counter[0x8];
362 u8 log_max_destination[0x8];
364 u8 reserved_at_a0[0x18];
365 u8 log_max_flow[0x8];
367 u8 reserved_at_c0[0x40];
369 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
371 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
374 struct mlx5_ifc_odp_per_transport_service_cap_bits {
381 u8 reserved_at_6[0x1a];
384 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
409 u8 reserved_at_c0[0x18];
410 u8 ttl_hoplimit[0x8];
415 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
417 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
420 struct mlx5_ifc_fte_match_set_misc_bits {
421 u8 reserved_at_0[0x8];
424 u8 source_eswitch_owner_vhca_id[0x10];
425 u8 source_port[0x10];
427 u8 outer_second_prio[0x3];
428 u8 outer_second_cfi[0x1];
429 u8 outer_second_vid[0xc];
430 u8 inner_second_prio[0x3];
431 u8 inner_second_cfi[0x1];
432 u8 inner_second_vid[0xc];
434 u8 outer_second_cvlan_tag[0x1];
435 u8 inner_second_cvlan_tag[0x1];
436 u8 outer_second_svlan_tag[0x1];
437 u8 inner_second_svlan_tag[0x1];
438 u8 reserved_at_64[0xc];
439 u8 gre_protocol[0x10];
445 u8 reserved_at_b8[0x8];
447 u8 reserved_at_c0[0x20];
449 u8 reserved_at_e0[0xc];
450 u8 outer_ipv6_flow_label[0x14];
452 u8 reserved_at_100[0xc];
453 u8 inner_ipv6_flow_label[0x14];
455 u8 reserved_at_120[0x28];
457 u8 reserved_at_160[0x20];
458 u8 outer_esp_spi[0x20];
459 u8 reserved_at_1a0[0x60];
462 struct mlx5_ifc_fte_match_mpls_bits {
469 struct mlx5_ifc_fte_match_set_misc2_bits {
470 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
472 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
474 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
476 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
478 u8 reserved_at_80[0x100];
480 u8 metadata_reg_a[0x20];
482 u8 reserved_at_1a0[0x60];
485 struct mlx5_ifc_cmd_pas_bits {
489 u8 reserved_at_34[0xc];
492 struct mlx5_ifc_uint64_bits {
499 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
500 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
501 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
502 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
503 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
504 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
505 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
506 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
507 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
508 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
511 struct mlx5_ifc_ads_bits {
514 u8 reserved_at_2[0xe];
517 u8 reserved_at_20[0x8];
523 u8 reserved_at_45[0x3];
524 u8 src_addr_index[0x8];
525 u8 reserved_at_50[0x4];
529 u8 reserved_at_60[0x4];
533 u8 rgid_rip[16][0x8];
535 u8 reserved_at_100[0x4];
538 u8 reserved_at_106[0x1];
547 u8 vhca_port_num[0x8];
553 struct mlx5_ifc_flow_table_nic_cap_bits {
554 u8 nic_rx_multi_path_tirs[0x1];
555 u8 nic_rx_multi_path_tirs_fts[0x1];
556 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
557 u8 reserved_at_3[0x1fd];
559 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
561 u8 reserved_at_400[0x200];
563 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
565 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
567 u8 reserved_at_a00[0x200];
569 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
571 u8 reserved_at_e00[0x7200];
574 struct mlx5_ifc_flow_table_eswitch_cap_bits {
575 u8 reserved_at_0[0x1c];
576 u8 fdb_multi_path_to_table[0x1];
577 u8 reserved_at_1d[0x1e3];
579 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
581 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
583 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
585 u8 reserved_at_800[0x7800];
588 struct mlx5_ifc_e_switch_cap_bits {
589 u8 vport_svlan_strip[0x1];
590 u8 vport_cvlan_strip[0x1];
591 u8 vport_svlan_insert[0x1];
592 u8 vport_cvlan_insert_if_not_exist[0x1];
593 u8 vport_cvlan_insert_overwrite[0x1];
594 u8 reserved_at_5[0x18];
595 u8 merged_eswitch[0x1];
596 u8 nic_vport_node_guid_modify[0x1];
597 u8 nic_vport_port_guid_modify[0x1];
599 u8 vxlan_encap_decap[0x1];
600 u8 nvgre_encap_decap[0x1];
601 u8 reserved_at_22[0x9];
602 u8 log_max_encap_headers[0x5];
604 u8 max_encap_header_size[0xa];
606 u8 reserved_40[0x7c0];
610 struct mlx5_ifc_qos_cap_bits {
611 u8 packet_pacing[0x1];
612 u8 esw_scheduling[0x1];
613 u8 esw_bw_share[0x1];
614 u8 esw_rate_limit[0x1];
615 u8 reserved_at_4[0x1];
616 u8 packet_pacing_burst_bound[0x1];
617 u8 packet_pacing_typical_size[0x1];
618 u8 reserved_at_7[0x19];
620 u8 reserved_at_20[0x20];
622 u8 packet_pacing_max_rate[0x20];
624 u8 packet_pacing_min_rate[0x20];
626 u8 reserved_at_80[0x10];
627 u8 packet_pacing_rate_table_size[0x10];
629 u8 esw_element_type[0x10];
630 u8 esw_tsar_type[0x10];
632 u8 reserved_at_c0[0x10];
633 u8 max_qos_para_vport[0x10];
635 u8 max_tsar_bw_share[0x20];
637 u8 reserved_at_100[0x700];
640 struct mlx5_ifc_debug_cap_bits {
641 u8 reserved_at_0[0x20];
643 u8 reserved_at_20[0x2];
644 u8 stall_detect[0x1];
645 u8 reserved_at_23[0x1d];
647 u8 reserved_at_40[0x7c0];
650 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
654 u8 lro_psh_flag[0x1];
655 u8 lro_time_stamp[0x1];
656 u8 reserved_at_5[0x2];
657 u8 wqe_vlan_insert[0x1];
658 u8 self_lb_en_modifiable[0x1];
659 u8 reserved_at_9[0x2];
661 u8 multi_pkt_send_wqe[0x2];
662 u8 wqe_inline_mode[0x2];
663 u8 rss_ind_tbl_cap[0x4];
666 u8 enhanced_multi_pkt_send_wqe[0x1];
667 u8 tunnel_lso_const_out_ip_id[0x1];
668 u8 reserved_at_1c[0x2];
669 u8 tunnel_stateless_gre[0x1];
670 u8 tunnel_stateless_vxlan[0x1];
675 u8 cqe_checksum_full[0x1];
676 u8 tunnel_stateless_geneve_tx[0x1];
677 u8 tunnel_stateless_mpls_over_udp[0x1];
678 u8 tunnel_stateless_mpls_over_gre[0x1];
679 u8 tunnel_stateless_vxlan_gpe[0x1];
680 u8 tunnel_stateless_ipv4_over_vxlan[0x1];
681 u8 tunnel_stateless_ip_over_ip[0x1];
682 u8 reserved_at_2a[0x6];
683 u8 max_vxlan_udp_ports[0x8];
684 u8 reserved_at_38[0x6];
685 u8 max_geneve_opt_len[0x1];
686 u8 tunnel_stateless_geneve_rx[0x1];
688 u8 reserved_at_40[0x10];
689 u8 lro_min_mss_size[0x10];
691 u8 reserved_at_60[0x120];
693 u8 lro_timer_supported_periods[4][0x20];
695 u8 reserved_at_200[0x600];
698 struct mlx5_ifc_roce_cap_bits {
700 u8 reserved_at_1[0x1f];
702 u8 reserved_at_20[0x60];
704 u8 reserved_at_80[0xc];
706 u8 reserved_at_90[0x8];
707 u8 roce_version[0x8];
709 u8 reserved_at_a0[0x10];
710 u8 r_roce_dest_udp_port[0x10];
712 u8 r_roce_max_src_udp_port[0x10];
713 u8 r_roce_min_src_udp_port[0x10];
715 u8 reserved_at_e0[0x10];
716 u8 roce_address_table_size[0x10];
718 u8 reserved_at_100[0x700];
721 struct mlx5_ifc_device_mem_cap_bits {
723 u8 reserved_at_1[0x1f];
725 u8 reserved_at_20[0xb];
726 u8 log_min_memic_alloc_size[0x5];
727 u8 reserved_at_30[0x8];
728 u8 log_max_memic_addr_alignment[0x8];
730 u8 memic_bar_start_addr[0x40];
732 u8 memic_bar_size[0x20];
734 u8 max_memic_size[0x20];
736 u8 reserved_at_c0[0x740];
740 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
741 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
742 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
743 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
744 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
745 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
746 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
747 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
748 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
752 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
753 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
754 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
755 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
756 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
757 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
758 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
759 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
760 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
763 struct mlx5_ifc_atomic_caps_bits {
764 u8 reserved_at_0[0x40];
766 u8 atomic_req_8B_endianness_mode[0x2];
767 u8 reserved_at_42[0x4];
768 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
770 u8 reserved_at_47[0x19];
772 u8 reserved_at_60[0x20];
774 u8 reserved_at_80[0x10];
775 u8 atomic_operations[0x10];
777 u8 reserved_at_a0[0x10];
778 u8 atomic_size_qp[0x10];
780 u8 reserved_at_c0[0x10];
781 u8 atomic_size_dc[0x10];
783 u8 reserved_at_e0[0x720];
786 struct mlx5_ifc_odp_cap_bits {
787 u8 reserved_at_0[0x40];
790 u8 reserved_at_41[0x1f];
792 u8 reserved_at_60[0x20];
794 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
796 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
798 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
800 u8 reserved_at_e0[0x720];
803 struct mlx5_ifc_calc_op {
804 u8 reserved_at_0[0x10];
805 u8 reserved_at_10[0x9];
806 u8 op_swap_endianness[0x1];
815 struct mlx5_ifc_vector_calc_cap_bits {
817 u8 reserved_at_1[0x1f];
818 u8 reserved_at_20[0x8];
819 u8 max_vec_count[0x8];
820 u8 reserved_at_30[0xd];
821 u8 max_chunk_size[0x3];
822 struct mlx5_ifc_calc_op calc0;
823 struct mlx5_ifc_calc_op calc1;
824 struct mlx5_ifc_calc_op calc2;
825 struct mlx5_ifc_calc_op calc3;
827 u8 reserved_at_e0[0x720];
831 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
832 MLX5_WQ_TYPE_CYCLIC = 0x1,
833 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
834 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
838 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
839 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
843 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
844 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
845 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
846 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
847 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
851 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
852 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
853 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
854 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
855 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
856 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
860 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
861 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
865 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
866 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
867 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
871 MLX5_CAP_PORT_TYPE_IB = 0x0,
872 MLX5_CAP_PORT_TYPE_ETH = 0x1,
876 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
877 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
878 MLX5_CAP_UMR_FENCE_NONE = 0x2,
881 struct mlx5_ifc_cmd_hca_cap_bits {
882 u8 reserved_at_0[0x30];
885 u8 reserved_at_40[0x40];
887 u8 log_max_srq_sz[0x8];
888 u8 log_max_qp_sz[0x8];
889 u8 reserved_at_90[0xb];
892 u8 reserved_at_a0[0xb];
894 u8 reserved_at_b0[0x10];
896 u8 reserved_at_c0[0x8];
897 u8 log_max_cq_sz[0x8];
898 u8 reserved_at_d0[0xb];
901 u8 log_max_eq_sz[0x8];
902 u8 reserved_at_e8[0x2];
903 u8 log_max_mkey[0x6];
904 u8 reserved_at_f0[0x8];
905 u8 dump_fill_mkey[0x1];
906 u8 reserved_at_f9[0x3];
909 u8 max_indirection[0x8];
910 u8 fixed_buffer_size[0x1];
911 u8 log_max_mrw_sz[0x7];
912 u8 force_teardown[0x1];
913 u8 reserved_at_111[0x1];
914 u8 log_max_bsf_list_size[0x6];
915 u8 umr_extended_translation_offset[0x1];
917 u8 log_max_klm_list_size[0x6];
919 u8 reserved_at_120[0xa];
920 u8 log_max_ra_req_dc[0x6];
921 u8 reserved_at_130[0xa];
922 u8 log_max_ra_res_dc[0x6];
924 u8 reserved_at_140[0xa];
925 u8 log_max_ra_req_qp[0x6];
926 u8 reserved_at_150[0xa];
927 u8 log_max_ra_res_qp[0x6];
930 u8 cc_query_allowed[0x1];
931 u8 cc_modify_allowed[0x1];
933 u8 cache_line_128byte[0x1];
934 u8 reserved_at_165[0xa];
936 u8 gid_table_size[0x10];
938 u8 out_of_seq_cnt[0x1];
939 u8 vport_counters[0x1];
940 u8 retransmission_q_counters[0x1];
942 u8 modify_rq_counter_set_id[0x1];
943 u8 rq_delay_drop[0x1];
945 u8 pkey_table_size[0x10];
947 u8 vport_group_manager[0x1];
948 u8 vhca_group_manager[0x1];
951 u8 vnic_env_queue_counters[0x1];
953 u8 nic_flow_table[0x1];
954 u8 eswitch_manager[0x1];
955 u8 device_memory[0x1];
958 u8 local_ca_ack_delay[0x5];
959 u8 port_module_event[0x1];
960 u8 enhanced_error_q_counters[0x1];
962 u8 reserved_at_1b3[0x1];
963 u8 disable_link_up[0x1];
968 u8 reserved_at_1c0[0x1];
972 u8 reserved_at_1c8[0x4];
974 u8 temp_warn_event[0x1];
976 u8 general_notification_event[0x1];
977 u8 reserved_at_1d3[0x2];
981 u8 reserved_at_1d8[0x1];
990 u8 stat_rate_support[0x10];
991 u8 reserved_at_1f0[0xc];
994 u8 compact_address_vector[0x1];
996 u8 reserved_at_202[0x1];
997 u8 ipoib_enhanced_offloads[0x1];
998 u8 ipoib_basic_offloads[0x1];
999 u8 reserved_at_205[0x1];
1000 u8 repeated_block_disabled[0x1];
1001 u8 umr_modify_entity_size_disabled[0x1];
1002 u8 umr_modify_atomic_disabled[0x1];
1003 u8 umr_indirect_mkey_disabled[0x1];
1005 u8 reserved_at_20c[0x3];
1006 u8 drain_sigerr[0x1];
1007 u8 cmdif_checksum[0x2];
1009 u8 reserved_at_213[0x1];
1010 u8 wq_signature[0x1];
1011 u8 sctr_data_cqe[0x1];
1012 u8 reserved_at_216[0x1];
1018 u8 eth_net_offloads[0x1];
1021 u8 reserved_at_21f[0x1];
1025 u8 cq_moderation[0x1];
1026 u8 reserved_at_223[0x3];
1027 u8 cq_eq_remap[0x1];
1029 u8 block_lb_mc[0x1];
1030 u8 reserved_at_229[0x1];
1031 u8 scqe_break_moderation[0x1];
1032 u8 cq_period_start_from_cqe[0x1];
1034 u8 reserved_at_22d[0x1];
1036 u8 vector_calc[0x1];
1037 u8 umr_ptr_rlky[0x1];
1039 u8 reserved_at_232[0x4];
1042 u8 set_deth_sqpn[0x1];
1043 u8 reserved_at_239[0x3];
1050 u8 reserved_at_241[0x9];
1052 u8 reserved_at_250[0x8];
1056 u8 driver_version[0x1];
1057 u8 pad_tx_eth_packet[0x1];
1058 u8 reserved_at_263[0x8];
1059 u8 log_bf_reg_size[0x5];
1061 u8 reserved_at_270[0xb];
1063 u8 num_lag_ports[0x4];
1065 u8 reserved_at_280[0x10];
1066 u8 max_wqe_sz_sq[0x10];
1068 u8 reserved_at_2a0[0x10];
1069 u8 max_wqe_sz_rq[0x10];
1071 u8 max_flow_counter_31_16[0x10];
1072 u8 max_wqe_sz_sq_dc[0x10];
1074 u8 reserved_at_2e0[0x7];
1075 u8 max_qp_mcg[0x19];
1077 u8 reserved_at_300[0x18];
1078 u8 log_max_mcg[0x8];
1080 u8 reserved_at_320[0x3];
1081 u8 log_max_transport_domain[0x5];
1082 u8 reserved_at_328[0x3];
1084 u8 reserved_at_330[0xb];
1085 u8 log_max_xrcd[0x5];
1087 u8 nic_receive_steering_discard[0x1];
1088 u8 receive_discard_vport_down[0x1];
1089 u8 transmit_discard_vport_down[0x1];
1090 u8 reserved_at_343[0x5];
1091 u8 log_max_flow_counter_bulk[0x8];
1092 u8 max_flow_counter_15_0[0x10];
1095 u8 reserved_at_360[0x3];
1097 u8 reserved_at_368[0x3];
1099 u8 reserved_at_370[0x3];
1100 u8 log_max_tir[0x5];
1101 u8 reserved_at_378[0x3];
1102 u8 log_max_tis[0x5];
1104 u8 basic_cyclic_rcv_wqe[0x1];
1105 u8 reserved_at_381[0x2];
1106 u8 log_max_rmp[0x5];
1107 u8 reserved_at_388[0x3];
1108 u8 log_max_rqt[0x5];
1109 u8 reserved_at_390[0x3];
1110 u8 log_max_rqt_size[0x5];
1111 u8 reserved_at_398[0x3];
1112 u8 log_max_tis_per_sq[0x5];
1114 u8 ext_stride_num_range[0x1];
1115 u8 reserved_at_3a1[0x2];
1116 u8 log_max_stride_sz_rq[0x5];
1117 u8 reserved_at_3a8[0x3];
1118 u8 log_min_stride_sz_rq[0x5];
1119 u8 reserved_at_3b0[0x3];
1120 u8 log_max_stride_sz_sq[0x5];
1121 u8 reserved_at_3b8[0x3];
1122 u8 log_min_stride_sz_sq[0x5];
1125 u8 reserved_at_3c1[0x2];
1126 u8 log_max_hairpin_queues[0x5];
1127 u8 reserved_at_3c8[0x3];
1128 u8 log_max_hairpin_wq_data_sz[0x5];
1129 u8 reserved_at_3d0[0x3];
1130 u8 log_max_hairpin_num_packets[0x5];
1131 u8 reserved_at_3d8[0x3];
1132 u8 log_max_wq_sz[0x5];
1134 u8 nic_vport_change_event[0x1];
1135 u8 disable_local_lb_uc[0x1];
1136 u8 disable_local_lb_mc[0x1];
1137 u8 log_min_hairpin_wq_data_sz[0x5];
1138 u8 reserved_at_3e8[0x3];
1139 u8 log_max_vlan_list[0x5];
1140 u8 reserved_at_3f0[0x3];
1141 u8 log_max_current_mc_list[0x5];
1142 u8 reserved_at_3f8[0x3];
1143 u8 log_max_current_uc_list[0x5];
1145 u8 general_obj_types[0x40];
1147 u8 reserved_at_440[0x20];
1149 u8 reserved_at_460[0x10];
1150 u8 max_num_eqs[0x10];
1152 u8 reserved_at_480[0x3];
1153 u8 log_max_l2_table[0x5];
1154 u8 reserved_at_488[0x8];
1155 u8 log_uar_page_sz[0x10];
1157 u8 reserved_at_4a0[0x20];
1158 u8 device_frequency_mhz[0x20];
1159 u8 device_frequency_khz[0x20];
1161 u8 reserved_at_500[0x20];
1162 u8 num_of_uars_per_page[0x20];
1164 u8 flex_parser_protocols[0x20];
1165 u8 reserved_at_560[0x20];
1167 u8 reserved_at_580[0x3c];
1168 u8 mini_cqe_resp_stride_index[0x1];
1169 u8 cqe_128_always[0x1];
1170 u8 cqe_compression_128[0x1];
1171 u8 cqe_compression[0x1];
1173 u8 cqe_compression_timeout[0x10];
1174 u8 cqe_compression_max_num[0x10];
1176 u8 reserved_at_5e0[0x10];
1177 u8 tag_matching[0x1];
1178 u8 rndv_offload_rc[0x1];
1179 u8 rndv_offload_dc[0x1];
1180 u8 log_tag_matching_list_sz[0x5];
1181 u8 reserved_at_5f8[0x3];
1182 u8 log_max_xrq[0x5];
1184 u8 affiliate_nic_vport_criteria[0x8];
1185 u8 native_port_num[0x8];
1186 u8 num_vhca_ports[0x8];
1187 u8 reserved_at_618[0x6];
1188 u8 sw_owner_id[0x1];
1189 u8 reserved_at_61f[0x1e1];
1192 enum mlx5_flow_destination_type {
1193 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1194 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1195 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1197 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
1198 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1199 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1202 struct mlx5_ifc_dest_format_struct_bits {
1203 u8 destination_type[0x8];
1204 u8 destination_id[0x18];
1205 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1206 u8 reserved_at_21[0xf];
1207 u8 destination_eswitch_owner_vhca_id[0x10];
1210 struct mlx5_ifc_flow_counter_list_bits {
1211 u8 flow_counter_id[0x20];
1213 u8 reserved_at_20[0x20];
1216 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1217 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1218 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1219 u8 reserved_at_0[0x40];
1222 struct mlx5_ifc_fte_match_param_bits {
1223 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1225 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1227 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1229 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1231 u8 reserved_at_800[0x800];
1235 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1236 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1237 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1238 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1239 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1242 struct mlx5_ifc_rx_hash_field_select_bits {
1243 u8 l3_prot_type[0x1];
1244 u8 l4_prot_type[0x1];
1245 u8 selected_fields[0x1e];
1249 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1250 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1254 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1255 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1258 struct mlx5_ifc_wq_bits {
1260 u8 wq_signature[0x1];
1261 u8 end_padding_mode[0x2];
1263 u8 reserved_at_8[0x18];
1265 u8 hds_skip_first_sge[0x1];
1266 u8 log2_hds_buf_size[0x3];
1267 u8 reserved_at_24[0x7];
1268 u8 page_offset[0x5];
1271 u8 reserved_at_40[0x8];
1274 u8 reserved_at_60[0x8];
1279 u8 hw_counter[0x20];
1281 u8 sw_counter[0x20];
1283 u8 reserved_at_100[0xc];
1284 u8 log_wq_stride[0x4];
1285 u8 reserved_at_110[0x3];
1286 u8 log_wq_pg_sz[0x5];
1287 u8 reserved_at_118[0x3];
1290 u8 reserved_at_120[0x3];
1291 u8 log_hairpin_num_packets[0x5];
1292 u8 reserved_at_128[0x3];
1293 u8 log_hairpin_data_sz[0x5];
1295 u8 reserved_at_130[0x4];
1296 u8 log_wqe_num_of_strides[0x4];
1297 u8 two_byte_shift_en[0x1];
1298 u8 reserved_at_139[0x4];
1299 u8 log_wqe_stride_size[0x3];
1301 u8 reserved_at_140[0x4c0];
1303 struct mlx5_ifc_cmd_pas_bits pas[0];
1306 struct mlx5_ifc_rq_num_bits {
1307 u8 reserved_at_0[0x8];
1311 struct mlx5_ifc_mac_address_layout_bits {
1312 u8 reserved_at_0[0x10];
1313 u8 mac_addr_47_32[0x10];
1315 u8 mac_addr_31_0[0x20];
1318 struct mlx5_ifc_vlan_layout_bits {
1319 u8 reserved_at_0[0x14];
1322 u8 reserved_at_20[0x20];
1325 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1326 u8 reserved_at_0[0xa0];
1328 u8 min_time_between_cnps[0x20];
1330 u8 reserved_at_c0[0x12];
1332 u8 reserved_at_d8[0x4];
1333 u8 cnp_prio_mode[0x1];
1334 u8 cnp_802p_prio[0x3];
1336 u8 reserved_at_e0[0x720];
1339 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1340 u8 reserved_at_0[0x60];
1342 u8 reserved_at_60[0x4];
1343 u8 clamp_tgt_rate[0x1];
1344 u8 reserved_at_65[0x3];
1345 u8 clamp_tgt_rate_after_time_inc[0x1];
1346 u8 reserved_at_69[0x17];
1348 u8 reserved_at_80[0x20];
1350 u8 rpg_time_reset[0x20];
1352 u8 rpg_byte_reset[0x20];
1354 u8 rpg_threshold[0x20];
1356 u8 rpg_max_rate[0x20];
1358 u8 rpg_ai_rate[0x20];
1360 u8 rpg_hai_rate[0x20];
1364 u8 rpg_min_dec_fac[0x20];
1366 u8 rpg_min_rate[0x20];
1368 u8 reserved_at_1c0[0xe0];
1370 u8 rate_to_set_on_first_cnp[0x20];
1374 u8 dce_tcp_rtt[0x20];
1376 u8 rate_reduce_monitor_period[0x20];
1378 u8 reserved_at_320[0x20];
1380 u8 initial_alpha_value[0x20];
1382 u8 reserved_at_360[0x4a0];
1385 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1386 u8 reserved_at_0[0x80];
1388 u8 rppp_max_rps[0x20];
1390 u8 rpg_time_reset[0x20];
1392 u8 rpg_byte_reset[0x20];
1394 u8 rpg_threshold[0x20];
1396 u8 rpg_max_rate[0x20];
1398 u8 rpg_ai_rate[0x20];
1400 u8 rpg_hai_rate[0x20];
1404 u8 rpg_min_dec_fac[0x20];
1406 u8 rpg_min_rate[0x20];
1408 u8 reserved_at_1c0[0x640];
1412 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1413 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1414 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1417 struct mlx5_ifc_resize_field_select_bits {
1418 u8 resize_field_select[0x20];
1422 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1423 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1424 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1425 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1428 struct mlx5_ifc_modify_field_select_bits {
1429 u8 modify_field_select[0x20];
1432 struct mlx5_ifc_field_select_r_roce_np_bits {
1433 u8 field_select_r_roce_np[0x20];
1436 struct mlx5_ifc_field_select_r_roce_rp_bits {
1437 u8 field_select_r_roce_rp[0x20];
1441 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1442 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1443 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1444 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1445 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1446 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1447 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1448 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1449 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1450 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1453 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1454 u8 field_select_8021qaurp[0x20];
1457 struct mlx5_ifc_phys_layer_cntrs_bits {
1458 u8 time_since_last_clear_high[0x20];
1460 u8 time_since_last_clear_low[0x20];
1462 u8 symbol_errors_high[0x20];
1464 u8 symbol_errors_low[0x20];
1466 u8 sync_headers_errors_high[0x20];
1468 u8 sync_headers_errors_low[0x20];
1470 u8 edpl_bip_errors_lane0_high[0x20];
1472 u8 edpl_bip_errors_lane0_low[0x20];
1474 u8 edpl_bip_errors_lane1_high[0x20];
1476 u8 edpl_bip_errors_lane1_low[0x20];
1478 u8 edpl_bip_errors_lane2_high[0x20];
1480 u8 edpl_bip_errors_lane2_low[0x20];
1482 u8 edpl_bip_errors_lane3_high[0x20];
1484 u8 edpl_bip_errors_lane3_low[0x20];
1486 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1488 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1490 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1492 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1494 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1496 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1498 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1500 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1502 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1504 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1506 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1508 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1510 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1512 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1514 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1516 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1518 u8 rs_fec_corrected_blocks_high[0x20];
1520 u8 rs_fec_corrected_blocks_low[0x20];
1522 u8 rs_fec_uncorrectable_blocks_high[0x20];
1524 u8 rs_fec_uncorrectable_blocks_low[0x20];
1526 u8 rs_fec_no_errors_blocks_high[0x20];
1528 u8 rs_fec_no_errors_blocks_low[0x20];
1530 u8 rs_fec_single_error_blocks_high[0x20];
1532 u8 rs_fec_single_error_blocks_low[0x20];
1534 u8 rs_fec_corrected_symbols_total_high[0x20];
1536 u8 rs_fec_corrected_symbols_total_low[0x20];
1538 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1540 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1542 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1544 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1546 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1548 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1550 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1552 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1554 u8 link_down_events[0x20];
1556 u8 successful_recovery_events[0x20];
1558 u8 reserved_at_640[0x180];
1561 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1562 u8 time_since_last_clear_high[0x20];
1564 u8 time_since_last_clear_low[0x20];
1566 u8 phy_received_bits_high[0x20];
1568 u8 phy_received_bits_low[0x20];
1570 u8 phy_symbol_errors_high[0x20];
1572 u8 phy_symbol_errors_low[0x20];
1574 u8 phy_corrected_bits_high[0x20];
1576 u8 phy_corrected_bits_low[0x20];
1578 u8 phy_corrected_bits_lane0_high[0x20];
1580 u8 phy_corrected_bits_lane0_low[0x20];
1582 u8 phy_corrected_bits_lane1_high[0x20];
1584 u8 phy_corrected_bits_lane1_low[0x20];
1586 u8 phy_corrected_bits_lane2_high[0x20];
1588 u8 phy_corrected_bits_lane2_low[0x20];
1590 u8 phy_corrected_bits_lane3_high[0x20];
1592 u8 phy_corrected_bits_lane3_low[0x20];
1594 u8 reserved_at_200[0x5c0];
1597 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1598 u8 symbol_error_counter[0x10];
1600 u8 link_error_recovery_counter[0x8];
1602 u8 link_downed_counter[0x8];
1604 u8 port_rcv_errors[0x10];
1606 u8 port_rcv_remote_physical_errors[0x10];
1608 u8 port_rcv_switch_relay_errors[0x10];
1610 u8 port_xmit_discards[0x10];
1612 u8 port_xmit_constraint_errors[0x8];
1614 u8 port_rcv_constraint_errors[0x8];
1616 u8 reserved_at_70[0x8];
1618 u8 link_overrun_errors[0x8];
1620 u8 reserved_at_80[0x10];
1622 u8 vl_15_dropped[0x10];
1624 u8 reserved_at_a0[0x80];
1626 u8 port_xmit_wait[0x20];
1629 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1630 u8 transmit_queue_high[0x20];
1632 u8 transmit_queue_low[0x20];
1634 u8 reserved_at_40[0x780];
1637 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1638 u8 rx_octets_high[0x20];
1640 u8 rx_octets_low[0x20];
1642 u8 reserved_at_40[0xc0];
1644 u8 rx_frames_high[0x20];
1646 u8 rx_frames_low[0x20];
1648 u8 tx_octets_high[0x20];
1650 u8 tx_octets_low[0x20];
1652 u8 reserved_at_180[0xc0];
1654 u8 tx_frames_high[0x20];
1656 u8 tx_frames_low[0x20];
1658 u8 rx_pause_high[0x20];
1660 u8 rx_pause_low[0x20];
1662 u8 rx_pause_duration_high[0x20];
1664 u8 rx_pause_duration_low[0x20];
1666 u8 tx_pause_high[0x20];
1668 u8 tx_pause_low[0x20];
1670 u8 tx_pause_duration_high[0x20];
1672 u8 tx_pause_duration_low[0x20];
1674 u8 rx_pause_transition_high[0x20];
1676 u8 rx_pause_transition_low[0x20];
1678 u8 reserved_at_3c0[0x40];
1680 u8 device_stall_minor_watermark_cnt_high[0x20];
1682 u8 device_stall_minor_watermark_cnt_low[0x20];
1684 u8 device_stall_critical_watermark_cnt_high[0x20];
1686 u8 device_stall_critical_watermark_cnt_low[0x20];
1688 u8 reserved_at_480[0x340];
1691 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1692 u8 port_transmit_wait_high[0x20];
1694 u8 port_transmit_wait_low[0x20];
1696 u8 reserved_at_40[0x100];
1698 u8 rx_buffer_almost_full_high[0x20];
1700 u8 rx_buffer_almost_full_low[0x20];
1702 u8 rx_buffer_full_high[0x20];
1704 u8 rx_buffer_full_low[0x20];
1706 u8 rx_icrc_encapsulated_high[0x20];
1708 u8 rx_icrc_encapsulated_low[0x20];
1710 u8 reserved_at_200[0x5c0];
1713 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1714 u8 dot3stats_alignment_errors_high[0x20];
1716 u8 dot3stats_alignment_errors_low[0x20];
1718 u8 dot3stats_fcs_errors_high[0x20];
1720 u8 dot3stats_fcs_errors_low[0x20];
1722 u8 dot3stats_single_collision_frames_high[0x20];
1724 u8 dot3stats_single_collision_frames_low[0x20];
1726 u8 dot3stats_multiple_collision_frames_high[0x20];
1728 u8 dot3stats_multiple_collision_frames_low[0x20];
1730 u8 dot3stats_sqe_test_errors_high[0x20];
1732 u8 dot3stats_sqe_test_errors_low[0x20];
1734 u8 dot3stats_deferred_transmissions_high[0x20];
1736 u8 dot3stats_deferred_transmissions_low[0x20];
1738 u8 dot3stats_late_collisions_high[0x20];
1740 u8 dot3stats_late_collisions_low[0x20];
1742 u8 dot3stats_excessive_collisions_high[0x20];
1744 u8 dot3stats_excessive_collisions_low[0x20];
1746 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1748 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1750 u8 dot3stats_carrier_sense_errors_high[0x20];
1752 u8 dot3stats_carrier_sense_errors_low[0x20];
1754 u8 dot3stats_frame_too_longs_high[0x20];
1756 u8 dot3stats_frame_too_longs_low[0x20];
1758 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1760 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1762 u8 dot3stats_symbol_errors_high[0x20];
1764 u8 dot3stats_symbol_errors_low[0x20];
1766 u8 dot3control_in_unknown_opcodes_high[0x20];
1768 u8 dot3control_in_unknown_opcodes_low[0x20];
1770 u8 dot3in_pause_frames_high[0x20];
1772 u8 dot3in_pause_frames_low[0x20];
1774 u8 dot3out_pause_frames_high[0x20];
1776 u8 dot3out_pause_frames_low[0x20];
1778 u8 reserved_at_400[0x3c0];
1781 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1782 u8 ether_stats_drop_events_high[0x20];
1784 u8 ether_stats_drop_events_low[0x20];
1786 u8 ether_stats_octets_high[0x20];
1788 u8 ether_stats_octets_low[0x20];
1790 u8 ether_stats_pkts_high[0x20];
1792 u8 ether_stats_pkts_low[0x20];
1794 u8 ether_stats_broadcast_pkts_high[0x20];
1796 u8 ether_stats_broadcast_pkts_low[0x20];
1798 u8 ether_stats_multicast_pkts_high[0x20];
1800 u8 ether_stats_multicast_pkts_low[0x20];
1802 u8 ether_stats_crc_align_errors_high[0x20];
1804 u8 ether_stats_crc_align_errors_low[0x20];
1806 u8 ether_stats_undersize_pkts_high[0x20];
1808 u8 ether_stats_undersize_pkts_low[0x20];
1810 u8 ether_stats_oversize_pkts_high[0x20];
1812 u8 ether_stats_oversize_pkts_low[0x20];
1814 u8 ether_stats_fragments_high[0x20];
1816 u8 ether_stats_fragments_low[0x20];
1818 u8 ether_stats_jabbers_high[0x20];
1820 u8 ether_stats_jabbers_low[0x20];
1822 u8 ether_stats_collisions_high[0x20];
1824 u8 ether_stats_collisions_low[0x20];
1826 u8 ether_stats_pkts64octets_high[0x20];
1828 u8 ether_stats_pkts64octets_low[0x20];
1830 u8 ether_stats_pkts65to127octets_high[0x20];
1832 u8 ether_stats_pkts65to127octets_low[0x20];
1834 u8 ether_stats_pkts128to255octets_high[0x20];
1836 u8 ether_stats_pkts128to255octets_low[0x20];
1838 u8 ether_stats_pkts256to511octets_high[0x20];
1840 u8 ether_stats_pkts256to511octets_low[0x20];
1842 u8 ether_stats_pkts512to1023octets_high[0x20];
1844 u8 ether_stats_pkts512to1023octets_low[0x20];
1846 u8 ether_stats_pkts1024to1518octets_high[0x20];
1848 u8 ether_stats_pkts1024to1518octets_low[0x20];
1850 u8 ether_stats_pkts1519to2047octets_high[0x20];
1852 u8 ether_stats_pkts1519to2047octets_low[0x20];
1854 u8 ether_stats_pkts2048to4095octets_high[0x20];
1856 u8 ether_stats_pkts2048to4095octets_low[0x20];
1858 u8 ether_stats_pkts4096to8191octets_high[0x20];
1860 u8 ether_stats_pkts4096to8191octets_low[0x20];
1862 u8 ether_stats_pkts8192to10239octets_high[0x20];
1864 u8 ether_stats_pkts8192to10239octets_low[0x20];
1866 u8 reserved_at_540[0x280];
1869 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1870 u8 if_in_octets_high[0x20];
1872 u8 if_in_octets_low[0x20];
1874 u8 if_in_ucast_pkts_high[0x20];
1876 u8 if_in_ucast_pkts_low[0x20];
1878 u8 if_in_discards_high[0x20];
1880 u8 if_in_discards_low[0x20];
1882 u8 if_in_errors_high[0x20];
1884 u8 if_in_errors_low[0x20];
1886 u8 if_in_unknown_protos_high[0x20];
1888 u8 if_in_unknown_protos_low[0x20];
1890 u8 if_out_octets_high[0x20];
1892 u8 if_out_octets_low[0x20];
1894 u8 if_out_ucast_pkts_high[0x20];
1896 u8 if_out_ucast_pkts_low[0x20];
1898 u8 if_out_discards_high[0x20];
1900 u8 if_out_discards_low[0x20];
1902 u8 if_out_errors_high[0x20];
1904 u8 if_out_errors_low[0x20];
1906 u8 if_in_multicast_pkts_high[0x20];
1908 u8 if_in_multicast_pkts_low[0x20];
1910 u8 if_in_broadcast_pkts_high[0x20];
1912 u8 if_in_broadcast_pkts_low[0x20];
1914 u8 if_out_multicast_pkts_high[0x20];
1916 u8 if_out_multicast_pkts_low[0x20];
1918 u8 if_out_broadcast_pkts_high[0x20];
1920 u8 if_out_broadcast_pkts_low[0x20];
1922 u8 reserved_at_340[0x480];
1925 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1926 u8 a_frames_transmitted_ok_high[0x20];
1928 u8 a_frames_transmitted_ok_low[0x20];
1930 u8 a_frames_received_ok_high[0x20];
1932 u8 a_frames_received_ok_low[0x20];
1934 u8 a_frame_check_sequence_errors_high[0x20];
1936 u8 a_frame_check_sequence_errors_low[0x20];
1938 u8 a_alignment_errors_high[0x20];
1940 u8 a_alignment_errors_low[0x20];
1942 u8 a_octets_transmitted_ok_high[0x20];
1944 u8 a_octets_transmitted_ok_low[0x20];
1946 u8 a_octets_received_ok_high[0x20];
1948 u8 a_octets_received_ok_low[0x20];
1950 u8 a_multicast_frames_xmitted_ok_high[0x20];
1952 u8 a_multicast_frames_xmitted_ok_low[0x20];
1954 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1956 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1958 u8 a_multicast_frames_received_ok_high[0x20];
1960 u8 a_multicast_frames_received_ok_low[0x20];
1962 u8 a_broadcast_frames_received_ok_high[0x20];
1964 u8 a_broadcast_frames_received_ok_low[0x20];
1966 u8 a_in_range_length_errors_high[0x20];
1968 u8 a_in_range_length_errors_low[0x20];
1970 u8 a_out_of_range_length_field_high[0x20];
1972 u8 a_out_of_range_length_field_low[0x20];
1974 u8 a_frame_too_long_errors_high[0x20];
1976 u8 a_frame_too_long_errors_low[0x20];
1978 u8 a_symbol_error_during_carrier_high[0x20];
1980 u8 a_symbol_error_during_carrier_low[0x20];
1982 u8 a_mac_control_frames_transmitted_high[0x20];
1984 u8 a_mac_control_frames_transmitted_low[0x20];
1986 u8 a_mac_control_frames_received_high[0x20];
1988 u8 a_mac_control_frames_received_low[0x20];
1990 u8 a_unsupported_opcodes_received_high[0x20];
1992 u8 a_unsupported_opcodes_received_low[0x20];
1994 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1996 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1998 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2000 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2002 u8 reserved_at_4c0[0x300];
2005 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2006 u8 life_time_counter_high[0x20];
2008 u8 life_time_counter_low[0x20];
2014 u8 l0_to_recovery_eieos[0x20];
2016 u8 l0_to_recovery_ts[0x20];
2018 u8 l0_to_recovery_framing[0x20];
2020 u8 l0_to_recovery_retrain[0x20];
2022 u8 crc_error_dllp[0x20];
2024 u8 crc_error_tlp[0x20];
2026 u8 tx_overflow_buffer_pkt_high[0x20];
2028 u8 tx_overflow_buffer_pkt_low[0x20];
2030 u8 outbound_stalled_reads[0x20];
2032 u8 outbound_stalled_writes[0x20];
2034 u8 outbound_stalled_reads_events[0x20];
2036 u8 outbound_stalled_writes_events[0x20];
2038 u8 reserved_at_200[0x5c0];
2041 struct mlx5_ifc_cmd_inter_comp_event_bits {
2042 u8 command_completion_vector[0x20];
2044 u8 reserved_at_20[0xc0];
2047 struct mlx5_ifc_stall_vl_event_bits {
2048 u8 reserved_at_0[0x18];
2050 u8 reserved_at_19[0x3];
2053 u8 reserved_at_20[0xa0];
2056 struct mlx5_ifc_db_bf_congestion_event_bits {
2057 u8 event_subtype[0x8];
2058 u8 reserved_at_8[0x8];
2059 u8 congestion_level[0x8];
2060 u8 reserved_at_18[0x8];
2062 u8 reserved_at_20[0xa0];
2065 struct mlx5_ifc_gpio_event_bits {
2066 u8 reserved_at_0[0x60];
2068 u8 gpio_event_hi[0x20];
2070 u8 gpio_event_lo[0x20];
2072 u8 reserved_at_a0[0x40];
2075 struct mlx5_ifc_port_state_change_event_bits {
2076 u8 reserved_at_0[0x40];
2079 u8 reserved_at_44[0x1c];
2081 u8 reserved_at_60[0x80];
2084 struct mlx5_ifc_dropped_packet_logged_bits {
2085 u8 reserved_at_0[0xe0];
2089 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2090 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2093 struct mlx5_ifc_cq_error_bits {
2094 u8 reserved_at_0[0x8];
2097 u8 reserved_at_20[0x20];
2099 u8 reserved_at_40[0x18];
2102 u8 reserved_at_60[0x80];
2105 struct mlx5_ifc_rdma_page_fault_event_bits {
2106 u8 bytes_committed[0x20];
2110 u8 reserved_at_40[0x10];
2111 u8 packet_len[0x10];
2113 u8 rdma_op_len[0x20];
2117 u8 reserved_at_c0[0x5];
2124 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2125 u8 bytes_committed[0x20];
2127 u8 reserved_at_20[0x10];
2130 u8 reserved_at_40[0x10];
2133 u8 reserved_at_60[0x60];
2135 u8 reserved_at_c0[0x5];
2142 struct mlx5_ifc_qp_events_bits {
2143 u8 reserved_at_0[0xa0];
2146 u8 reserved_at_a8[0x18];
2148 u8 reserved_at_c0[0x8];
2149 u8 qpn_rqn_sqn[0x18];
2152 struct mlx5_ifc_dct_events_bits {
2153 u8 reserved_at_0[0xc0];
2155 u8 reserved_at_c0[0x8];
2156 u8 dct_number[0x18];
2159 struct mlx5_ifc_comp_event_bits {
2160 u8 reserved_at_0[0xc0];
2162 u8 reserved_at_c0[0x8];
2167 MLX5_QPC_STATE_RST = 0x0,
2168 MLX5_QPC_STATE_INIT = 0x1,
2169 MLX5_QPC_STATE_RTR = 0x2,
2170 MLX5_QPC_STATE_RTS = 0x3,
2171 MLX5_QPC_STATE_SQER = 0x4,
2172 MLX5_QPC_STATE_ERR = 0x6,
2173 MLX5_QPC_STATE_SQD = 0x7,
2174 MLX5_QPC_STATE_SUSPENDED = 0x9,
2178 MLX5_QPC_ST_RC = 0x0,
2179 MLX5_QPC_ST_UC = 0x1,
2180 MLX5_QPC_ST_UD = 0x2,
2181 MLX5_QPC_ST_XRC = 0x3,
2182 MLX5_QPC_ST_DCI = 0x5,
2183 MLX5_QPC_ST_QP0 = 0x7,
2184 MLX5_QPC_ST_QP1 = 0x8,
2185 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2186 MLX5_QPC_ST_REG_UMR = 0xc,
2190 MLX5_QPC_PM_STATE_ARMED = 0x0,
2191 MLX5_QPC_PM_STATE_REARM = 0x1,
2192 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2193 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2197 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2201 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2202 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2206 MLX5_QPC_MTU_256_BYTES = 0x1,
2207 MLX5_QPC_MTU_512_BYTES = 0x2,
2208 MLX5_QPC_MTU_1K_BYTES = 0x3,
2209 MLX5_QPC_MTU_2K_BYTES = 0x4,
2210 MLX5_QPC_MTU_4K_BYTES = 0x5,
2211 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2215 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2216 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2217 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2218 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2219 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2220 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2221 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2222 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2226 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2227 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2228 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2232 MLX5_QPC_CS_RES_DISABLE = 0x0,
2233 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2234 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2237 struct mlx5_ifc_qpc_bits {
2239 u8 lag_tx_port_affinity[0x4];
2241 u8 reserved_at_10[0x3];
2243 u8 reserved_at_15[0x3];
2244 u8 offload_type[0x4];
2245 u8 end_padding_mode[0x2];
2246 u8 reserved_at_1e[0x2];
2248 u8 wq_signature[0x1];
2249 u8 block_lb_mc[0x1];
2250 u8 atomic_like_write_en[0x1];
2251 u8 latency_sensitive[0x1];
2252 u8 reserved_at_24[0x1];
2253 u8 drain_sigerr[0x1];
2254 u8 reserved_at_26[0x2];
2258 u8 log_msg_max[0x5];
2259 u8 reserved_at_48[0x1];
2260 u8 log_rq_size[0x4];
2261 u8 log_rq_stride[0x3];
2263 u8 log_sq_size[0x4];
2264 u8 reserved_at_55[0x6];
2266 u8 ulp_stateless_offload_mode[0x4];
2268 u8 counter_set_id[0x8];
2271 u8 reserved_at_80[0x8];
2272 u8 user_index[0x18];
2274 u8 reserved_at_a0[0x3];
2275 u8 log_page_size[0x5];
2276 u8 remote_qpn[0x18];
2278 struct mlx5_ifc_ads_bits primary_address_path;
2280 struct mlx5_ifc_ads_bits secondary_address_path;
2282 u8 log_ack_req_freq[0x4];
2283 u8 reserved_at_384[0x4];
2284 u8 log_sra_max[0x3];
2285 u8 reserved_at_38b[0x2];
2286 u8 retry_count[0x3];
2288 u8 reserved_at_393[0x1];
2290 u8 cur_rnr_retry[0x3];
2291 u8 cur_retry_count[0x3];
2292 u8 reserved_at_39b[0x5];
2294 u8 reserved_at_3a0[0x20];
2296 u8 reserved_at_3c0[0x8];
2297 u8 next_send_psn[0x18];
2299 u8 reserved_at_3e0[0x8];
2302 u8 reserved_at_400[0x8];
2305 u8 reserved_at_420[0x20];
2307 u8 reserved_at_440[0x8];
2308 u8 last_acked_psn[0x18];
2310 u8 reserved_at_460[0x8];
2313 u8 reserved_at_480[0x8];
2314 u8 log_rra_max[0x3];
2315 u8 reserved_at_48b[0x1];
2316 u8 atomic_mode[0x4];
2320 u8 reserved_at_493[0x1];
2321 u8 page_offset[0x6];
2322 u8 reserved_at_49a[0x3];
2323 u8 cd_slave_receive[0x1];
2324 u8 cd_slave_send[0x1];
2327 u8 reserved_at_4a0[0x3];
2328 u8 min_rnr_nak[0x5];
2329 u8 next_rcv_psn[0x18];
2331 u8 reserved_at_4c0[0x8];
2334 u8 reserved_at_4e0[0x8];
2341 u8 reserved_at_560[0x5];
2343 u8 srqn_rmpn_xrqn[0x18];
2345 u8 reserved_at_580[0x8];
2348 u8 hw_sq_wqebb_counter[0x10];
2349 u8 sw_sq_wqebb_counter[0x10];
2351 u8 hw_rq_counter[0x20];
2353 u8 sw_rq_counter[0x20];
2355 u8 reserved_at_600[0x20];
2357 u8 reserved_at_620[0xf];
2362 u8 dc_access_key[0x40];
2364 u8 reserved_at_680[0xc0];
2367 struct mlx5_ifc_roce_addr_layout_bits {
2368 u8 source_l3_address[16][0x8];
2370 u8 reserved_at_80[0x3];
2373 u8 source_mac_47_32[0x10];
2375 u8 source_mac_31_0[0x20];
2377 u8 reserved_at_c0[0x14];
2378 u8 roce_l3_type[0x4];
2379 u8 roce_version[0x8];
2381 u8 reserved_at_e0[0x20];
2384 union mlx5_ifc_hca_cap_union_bits {
2385 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2386 struct mlx5_ifc_odp_cap_bits odp_cap;
2387 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2388 struct mlx5_ifc_roce_cap_bits roce_cap;
2389 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2390 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2391 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2392 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2393 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2394 struct mlx5_ifc_qos_cap_bits qos_cap;
2395 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2396 u8 reserved_at_0[0x8000];
2400 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2401 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2402 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2403 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2404 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2405 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2406 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2407 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2408 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2409 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
2410 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2413 struct mlx5_ifc_vlan_bits {
2420 struct mlx5_ifc_flow_context_bits {
2421 struct mlx5_ifc_vlan_bits push_vlan;
2425 u8 reserved_at_40[0x8];
2428 u8 reserved_at_60[0x10];
2431 u8 reserved_at_80[0x8];
2432 u8 destination_list_size[0x18];
2434 u8 reserved_at_a0[0x8];
2435 u8 flow_counter_list_size[0x18];
2439 u8 modify_header_id[0x20];
2441 struct mlx5_ifc_vlan_bits push_vlan_2;
2443 u8 reserved_at_120[0xe0];
2445 struct mlx5_ifc_fte_match_param_bits match_value;
2447 u8 reserved_at_1200[0x600];
2449 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2453 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2454 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2457 struct mlx5_ifc_xrc_srqc_bits {
2459 u8 log_xrc_srq_size[0x4];
2460 u8 reserved_at_8[0x18];
2462 u8 wq_signature[0x1];
2464 u8 reserved_at_22[0x1];
2466 u8 basic_cyclic_rcv_wqe[0x1];
2467 u8 log_rq_stride[0x3];
2470 u8 page_offset[0x6];
2471 u8 reserved_at_46[0x2];
2474 u8 reserved_at_60[0x20];
2476 u8 user_index_equal_xrc_srqn[0x1];
2477 u8 reserved_at_81[0x1];
2478 u8 log_page_size[0x6];
2479 u8 user_index[0x18];
2481 u8 reserved_at_a0[0x20];
2483 u8 reserved_at_c0[0x8];
2489 u8 reserved_at_100[0x40];
2491 u8 db_record_addr_h[0x20];
2493 u8 db_record_addr_l[0x1e];
2494 u8 reserved_at_17e[0x2];
2496 u8 reserved_at_180[0x80];
2499 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2500 u8 counter_error_queues[0x20];
2502 u8 total_error_queues[0x20];
2504 u8 send_queue_priority_update_flow[0x20];
2506 u8 reserved_at_60[0x20];
2508 u8 nic_receive_steering_discard[0x40];
2510 u8 receive_discard_vport_down[0x40];
2512 u8 transmit_discard_vport_down[0x40];
2514 u8 reserved_at_140[0xec0];
2517 struct mlx5_ifc_traffic_counter_bits {
2523 struct mlx5_ifc_tisc_bits {
2524 u8 strict_lag_tx_port_affinity[0x1];
2525 u8 reserved_at_1[0x3];
2526 u8 lag_tx_port_affinity[0x04];
2528 u8 reserved_at_8[0x4];
2530 u8 reserved_at_10[0x10];
2532 u8 reserved_at_20[0x100];
2534 u8 reserved_at_120[0x8];
2535 u8 transport_domain[0x18];
2537 u8 reserved_at_140[0x8];
2538 u8 underlay_qpn[0x18];
2539 u8 reserved_at_160[0x3a0];
2543 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2544 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2548 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2549 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2553 MLX5_RX_HASH_FN_NONE = 0x0,
2554 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2555 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2559 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2560 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2563 struct mlx5_ifc_tirc_bits {
2564 u8 reserved_at_0[0x20];
2567 u8 reserved_at_24[0x1c];
2569 u8 reserved_at_40[0x40];
2571 u8 reserved_at_80[0x4];
2572 u8 lro_timeout_period_usecs[0x10];
2573 u8 lro_enable_mask[0x4];
2574 u8 lro_max_ip_payload_size[0x8];
2576 u8 reserved_at_a0[0x40];
2578 u8 reserved_at_e0[0x8];
2579 u8 inline_rqn[0x18];
2581 u8 rx_hash_symmetric[0x1];
2582 u8 reserved_at_101[0x1];
2583 u8 tunneled_offload_en[0x1];
2584 u8 reserved_at_103[0x5];
2585 u8 indirect_table[0x18];
2588 u8 reserved_at_124[0x2];
2589 u8 self_lb_block[0x2];
2590 u8 transport_domain[0x18];
2592 u8 rx_hash_toeplitz_key[10][0x20];
2594 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2596 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2598 u8 reserved_at_2c0[0x4c0];
2602 MLX5_SRQC_STATE_GOOD = 0x0,
2603 MLX5_SRQC_STATE_ERROR = 0x1,
2606 struct mlx5_ifc_srqc_bits {
2608 u8 log_srq_size[0x4];
2609 u8 reserved_at_8[0x18];
2611 u8 wq_signature[0x1];
2613 u8 reserved_at_22[0x1];
2615 u8 reserved_at_24[0x1];
2616 u8 log_rq_stride[0x3];
2619 u8 page_offset[0x6];
2620 u8 reserved_at_46[0x2];
2623 u8 reserved_at_60[0x20];
2625 u8 reserved_at_80[0x2];
2626 u8 log_page_size[0x6];
2627 u8 reserved_at_88[0x18];
2629 u8 reserved_at_a0[0x20];
2631 u8 reserved_at_c0[0x8];
2637 u8 reserved_at_100[0x40];
2641 u8 reserved_at_180[0x80];
2645 MLX5_SQC_STATE_RST = 0x0,
2646 MLX5_SQC_STATE_RDY = 0x1,
2647 MLX5_SQC_STATE_ERR = 0x3,
2650 struct mlx5_ifc_sqc_bits {
2654 u8 flush_in_error_en[0x1];
2655 u8 allow_multi_pkt_send_wqe[0x1];
2656 u8 min_wqe_inline_mode[0x3];
2661 u8 reserved_at_f[0x11];
2663 u8 reserved_at_20[0x8];
2664 u8 user_index[0x18];
2666 u8 reserved_at_40[0x8];
2669 u8 reserved_at_60[0x8];
2670 u8 hairpin_peer_rq[0x18];
2672 u8 reserved_at_80[0x10];
2673 u8 hairpin_peer_vhca[0x10];
2675 u8 reserved_at_a0[0x50];
2677 u8 packet_pacing_rate_limit_index[0x10];
2678 u8 tis_lst_sz[0x10];
2679 u8 reserved_at_110[0x10];
2681 u8 reserved_at_120[0x40];
2683 u8 reserved_at_160[0x8];
2686 struct mlx5_ifc_wq_bits wq;
2690 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2691 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2692 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2693 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2696 struct mlx5_ifc_scheduling_context_bits {
2697 u8 element_type[0x8];
2698 u8 reserved_at_8[0x18];
2700 u8 element_attributes[0x20];
2702 u8 parent_element_id[0x20];
2704 u8 reserved_at_60[0x40];
2708 u8 max_average_bw[0x20];
2710 u8 reserved_at_e0[0x120];
2713 struct mlx5_ifc_rqtc_bits {
2714 u8 reserved_at_0[0xa0];
2716 u8 reserved_at_a0[0x10];
2717 u8 rqt_max_size[0x10];
2719 u8 reserved_at_c0[0x10];
2720 u8 rqt_actual_size[0x10];
2722 u8 reserved_at_e0[0x6a0];
2724 struct mlx5_ifc_rq_num_bits rq_num[0];
2728 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2729 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2733 MLX5_RQC_STATE_RST = 0x0,
2734 MLX5_RQC_STATE_RDY = 0x1,
2735 MLX5_RQC_STATE_ERR = 0x3,
2738 struct mlx5_ifc_rqc_bits {
2740 u8 delay_drop_en[0x1];
2741 u8 scatter_fcs[0x1];
2743 u8 mem_rq_type[0x4];
2745 u8 reserved_at_c[0x1];
2746 u8 flush_in_error_en[0x1];
2748 u8 reserved_at_f[0x11];
2750 u8 reserved_at_20[0x8];
2751 u8 user_index[0x18];
2753 u8 reserved_at_40[0x8];
2756 u8 counter_set_id[0x8];
2757 u8 reserved_at_68[0x18];
2759 u8 reserved_at_80[0x8];
2762 u8 reserved_at_a0[0x8];
2763 u8 hairpin_peer_sq[0x18];
2765 u8 reserved_at_c0[0x10];
2766 u8 hairpin_peer_vhca[0x10];
2768 u8 reserved_at_e0[0xa0];
2770 struct mlx5_ifc_wq_bits wq;
2774 MLX5_RMPC_STATE_RDY = 0x1,
2775 MLX5_RMPC_STATE_ERR = 0x3,
2778 struct mlx5_ifc_rmpc_bits {
2779 u8 reserved_at_0[0x8];
2781 u8 reserved_at_c[0x14];
2783 u8 basic_cyclic_rcv_wqe[0x1];
2784 u8 reserved_at_21[0x1f];
2786 u8 reserved_at_40[0x140];
2788 struct mlx5_ifc_wq_bits wq;
2791 struct mlx5_ifc_nic_vport_context_bits {
2792 u8 reserved_at_0[0x5];
2793 u8 min_wqe_inline_mode[0x3];
2794 u8 reserved_at_8[0x15];
2795 u8 disable_mc_local_lb[0x1];
2796 u8 disable_uc_local_lb[0x1];
2799 u8 arm_change_event[0x1];
2800 u8 reserved_at_21[0x1a];
2801 u8 event_on_mtu[0x1];
2802 u8 event_on_promisc_change[0x1];
2803 u8 event_on_vlan_change[0x1];
2804 u8 event_on_mc_address_change[0x1];
2805 u8 event_on_uc_address_change[0x1];
2807 u8 reserved_at_40[0xc];
2809 u8 affiliation_criteria[0x4];
2810 u8 affiliated_vhca_id[0x10];
2812 u8 reserved_at_60[0xd0];
2816 u8 system_image_guid[0x40];
2820 u8 reserved_at_200[0x140];
2821 u8 qkey_violation_counter[0x10];
2822 u8 reserved_at_350[0x430];
2826 u8 promisc_all[0x1];
2827 u8 reserved_at_783[0x2];
2828 u8 allowed_list_type[0x3];
2829 u8 reserved_at_788[0xc];
2830 u8 allowed_list_size[0xc];
2832 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2834 u8 reserved_at_7e0[0x20];
2836 u8 current_uc_mac_address[0][0x40];
2840 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2841 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2842 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2843 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
2844 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2847 struct mlx5_ifc_mkc_bits {
2848 u8 reserved_at_0[0x1];
2850 u8 reserved_at_2[0x1];
2851 u8 access_mode_4_2[0x3];
2852 u8 reserved_at_6[0x7];
2853 u8 relaxed_ordering_write[0x1];
2854 u8 reserved_at_e[0x1];
2855 u8 small_fence_on_rdma_read_response[0x1];
2862 u8 access_mode_1_0[0x2];
2863 u8 reserved_at_18[0x8];
2868 u8 reserved_at_40[0x20];
2873 u8 reserved_at_63[0x2];
2874 u8 expected_sigerr_count[0x1];
2875 u8 reserved_at_66[0x1];
2879 u8 start_addr[0x40];
2883 u8 bsf_octword_size[0x20];
2885 u8 reserved_at_120[0x80];
2887 u8 translations_octword_size[0x20];
2889 u8 reserved_at_1c0[0x1b];
2890 u8 log_page_size[0x5];
2892 u8 reserved_at_1e0[0x20];
2895 struct mlx5_ifc_pkey_bits {
2896 u8 reserved_at_0[0x10];
2900 struct mlx5_ifc_array128_auto_bits {
2901 u8 array128_auto[16][0x8];
2904 struct mlx5_ifc_hca_vport_context_bits {
2905 u8 field_select[0x20];
2907 u8 reserved_at_20[0xe0];
2909 u8 sm_virt_aware[0x1];
2912 u8 grh_required[0x1];
2913 u8 reserved_at_104[0xc];
2914 u8 port_physical_state[0x4];
2915 u8 vport_state_policy[0x4];
2917 u8 vport_state[0x4];
2919 u8 reserved_at_120[0x20];
2921 u8 system_image_guid[0x40];
2929 u8 cap_mask1_field_select[0x20];
2933 u8 cap_mask2_field_select[0x20];
2935 u8 reserved_at_280[0x80];
2938 u8 reserved_at_310[0x4];
2939 u8 init_type_reply[0x4];
2941 u8 subnet_timeout[0x5];
2945 u8 reserved_at_334[0xc];
2947 u8 qkey_violation_counter[0x10];
2948 u8 pkey_violation_counter[0x10];
2950 u8 reserved_at_360[0xca0];
2953 struct mlx5_ifc_esw_vport_context_bits {
2954 u8 reserved_at_0[0x3];
2955 u8 vport_svlan_strip[0x1];
2956 u8 vport_cvlan_strip[0x1];
2957 u8 vport_svlan_insert[0x1];
2958 u8 vport_cvlan_insert[0x2];
2959 u8 reserved_at_8[0x18];
2961 u8 reserved_at_20[0x20];
2970 u8 reserved_at_60[0x7a0];
2974 MLX5_EQC_STATUS_OK = 0x0,
2975 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2979 MLX5_EQC_ST_ARMED = 0x9,
2980 MLX5_EQC_ST_FIRED = 0xa,
2983 struct mlx5_ifc_eqc_bits {
2985 u8 reserved_at_4[0x9];
2988 u8 reserved_at_f[0x5];
2990 u8 reserved_at_18[0x8];
2992 u8 reserved_at_20[0x20];
2994 u8 reserved_at_40[0x14];
2995 u8 page_offset[0x6];
2996 u8 reserved_at_5a[0x6];
2998 u8 reserved_at_60[0x3];
2999 u8 log_eq_size[0x5];
3002 u8 reserved_at_80[0x20];
3004 u8 reserved_at_a0[0x18];
3007 u8 reserved_at_c0[0x3];
3008 u8 log_page_size[0x5];
3009 u8 reserved_at_c8[0x18];
3011 u8 reserved_at_e0[0x60];
3013 u8 reserved_at_140[0x8];
3014 u8 consumer_counter[0x18];
3016 u8 reserved_at_160[0x8];
3017 u8 producer_counter[0x18];
3019 u8 reserved_at_180[0x80];
3023 MLX5_DCTC_STATE_ACTIVE = 0x0,
3024 MLX5_DCTC_STATE_DRAINING = 0x1,
3025 MLX5_DCTC_STATE_DRAINED = 0x2,
3029 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3030 MLX5_DCTC_CS_RES_NA = 0x1,
3031 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3035 MLX5_DCTC_MTU_256_BYTES = 0x1,
3036 MLX5_DCTC_MTU_512_BYTES = 0x2,
3037 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3038 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3039 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3042 struct mlx5_ifc_dctc_bits {
3043 u8 reserved_at_0[0x4];
3045 u8 reserved_at_8[0x18];
3047 u8 reserved_at_20[0x8];
3048 u8 user_index[0x18];
3050 u8 reserved_at_40[0x8];
3053 u8 counter_set_id[0x8];
3054 u8 atomic_mode[0x4];
3058 u8 atomic_like_write_en[0x1];
3059 u8 latency_sensitive[0x1];
3062 u8 reserved_at_73[0xd];
3064 u8 reserved_at_80[0x8];
3066 u8 reserved_at_90[0x3];
3067 u8 min_rnr_nak[0x5];
3068 u8 reserved_at_98[0x8];
3070 u8 reserved_at_a0[0x8];
3073 u8 reserved_at_c0[0x8];
3077 u8 reserved_at_e8[0x4];
3078 u8 flow_label[0x14];
3080 u8 dc_access_key[0x40];
3082 u8 reserved_at_140[0x5];
3085 u8 pkey_index[0x10];
3087 u8 reserved_at_160[0x8];
3088 u8 my_addr_index[0x8];
3089 u8 reserved_at_170[0x8];
3092 u8 dc_access_key_violation_count[0x20];
3094 u8 reserved_at_1a0[0x14];
3100 u8 reserved_at_1c0[0x40];
3104 MLX5_CQC_STATUS_OK = 0x0,
3105 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3106 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3110 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3111 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3115 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3116 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3117 MLX5_CQC_ST_FIRED = 0xa,
3121 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3122 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3123 MLX5_CQ_PERIOD_NUM_MODES
3126 struct mlx5_ifc_cqc_bits {
3128 u8 reserved_at_4[0x4];
3131 u8 reserved_at_c[0x1];
3132 u8 scqe_break_moderation_en[0x1];
3134 u8 cq_period_mode[0x2];
3135 u8 cqe_comp_en[0x1];
3136 u8 mini_cqe_res_format[0x2];
3138 u8 reserved_at_18[0x8];
3140 u8 reserved_at_20[0x20];
3142 u8 reserved_at_40[0x14];
3143 u8 page_offset[0x6];
3144 u8 reserved_at_5a[0x6];
3146 u8 reserved_at_60[0x3];
3147 u8 log_cq_size[0x5];
3150 u8 reserved_at_80[0x4];
3152 u8 cq_max_count[0x10];
3154 u8 reserved_at_a0[0x18];
3157 u8 reserved_at_c0[0x3];
3158 u8 log_page_size[0x5];
3159 u8 reserved_at_c8[0x18];
3161 u8 reserved_at_e0[0x20];
3163 u8 reserved_at_100[0x8];
3164 u8 last_notified_index[0x18];
3166 u8 reserved_at_120[0x8];
3167 u8 last_solicit_index[0x18];
3169 u8 reserved_at_140[0x8];
3170 u8 consumer_counter[0x18];
3172 u8 reserved_at_160[0x8];
3173 u8 producer_counter[0x18];
3175 u8 reserved_at_180[0x40];
3180 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3181 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3182 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3183 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3184 u8 reserved_at_0[0x800];
3187 struct mlx5_ifc_query_adapter_param_block_bits {
3188 u8 reserved_at_0[0xc0];
3190 u8 reserved_at_c0[0x8];
3191 u8 ieee_vendor_id[0x18];
3193 u8 reserved_at_e0[0x10];
3194 u8 vsd_vendor_id[0x10];
3198 u8 vsd_contd_psid[16][0x8];
3202 MLX5_XRQC_STATE_GOOD = 0x0,
3203 MLX5_XRQC_STATE_ERROR = 0x1,
3207 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3208 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3212 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3215 struct mlx5_ifc_tag_matching_topology_context_bits {
3216 u8 log_matching_list_sz[0x4];
3217 u8 reserved_at_4[0xc];
3218 u8 append_next_index[0x10];
3220 u8 sw_phase_cnt[0x10];
3221 u8 hw_phase_cnt[0x10];
3223 u8 reserved_at_40[0x40];
3226 struct mlx5_ifc_xrqc_bits {
3229 u8 reserved_at_5[0xf];
3231 u8 reserved_at_18[0x4];
3234 u8 reserved_at_20[0x8];
3235 u8 user_index[0x18];
3237 u8 reserved_at_40[0x8];
3240 u8 reserved_at_60[0xa0];
3242 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3244 u8 reserved_at_180[0x280];
3246 struct mlx5_ifc_wq_bits wq;
3249 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3250 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3251 struct mlx5_ifc_resize_field_select_bits resize_field_select;
3252 u8 reserved_at_0[0x20];
3255 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3256 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3257 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3258 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3259 u8 reserved_at_0[0x20];
3262 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3263 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3264 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3265 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3266 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3267 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3268 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3269 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3270 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3271 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3272 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3273 u8 reserved_at_0[0x7c0];
3276 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3277 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3278 u8 reserved_at_0[0x7c0];
3281 union mlx5_ifc_event_auto_bits {
3282 struct mlx5_ifc_comp_event_bits comp_event;
3283 struct mlx5_ifc_dct_events_bits dct_events;
3284 struct mlx5_ifc_qp_events_bits qp_events;
3285 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3286 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3287 struct mlx5_ifc_cq_error_bits cq_error;
3288 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3289 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3290 struct mlx5_ifc_gpio_event_bits gpio_event;
3291 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3292 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3293 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3294 u8 reserved_at_0[0xe0];
3297 struct mlx5_ifc_health_buffer_bits {
3298 u8 reserved_at_0[0x100];
3300 u8 assert_existptr[0x20];
3302 u8 assert_callra[0x20];
3304 u8 reserved_at_140[0x40];
3306 u8 fw_version[0x20];
3310 u8 reserved_at_1c0[0x20];
3312 u8 irisc_index[0x8];
3317 struct mlx5_ifc_register_loopback_control_bits {
3319 u8 reserved_at_1[0x7];
3321 u8 reserved_at_10[0x10];
3323 u8 reserved_at_20[0x60];
3326 struct mlx5_ifc_vport_tc_element_bits {
3327 u8 traffic_class[0x4];
3328 u8 reserved_at_4[0xc];
3329 u8 vport_number[0x10];
3332 struct mlx5_ifc_vport_element_bits {
3333 u8 reserved_at_0[0x10];
3334 u8 vport_number[0x10];
3338 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3339 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3340 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3343 struct mlx5_ifc_tsar_element_bits {
3344 u8 reserved_at_0[0x8];
3346 u8 reserved_at_10[0x10];
3350 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3351 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3354 struct mlx5_ifc_teardown_hca_out_bits {
3356 u8 reserved_at_8[0x18];
3360 u8 reserved_at_40[0x3f];
3362 u8 force_state[0x1];
3366 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3367 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
3370 struct mlx5_ifc_teardown_hca_in_bits {
3372 u8 reserved_at_10[0x10];
3374 u8 reserved_at_20[0x10];
3377 u8 reserved_at_40[0x10];
3380 u8 reserved_at_60[0x20];
3383 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3385 u8 reserved_at_8[0x18];
3389 u8 reserved_at_40[0x40];
3392 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3394 u8 reserved_at_10[0x10];
3396 u8 reserved_at_20[0x10];
3399 u8 reserved_at_40[0x8];
3402 u8 reserved_at_60[0x20];
3404 u8 opt_param_mask[0x20];
3406 u8 reserved_at_a0[0x20];
3408 struct mlx5_ifc_qpc_bits qpc;
3410 u8 reserved_at_800[0x80];
3413 struct mlx5_ifc_sqd2rts_qp_out_bits {
3415 u8 reserved_at_8[0x18];
3419 u8 reserved_at_40[0x40];
3422 struct mlx5_ifc_sqd2rts_qp_in_bits {
3424 u8 reserved_at_10[0x10];
3426 u8 reserved_at_20[0x10];
3429 u8 reserved_at_40[0x8];
3432 u8 reserved_at_60[0x20];
3434 u8 opt_param_mask[0x20];
3436 u8 reserved_at_a0[0x20];
3438 struct mlx5_ifc_qpc_bits qpc;
3440 u8 reserved_at_800[0x80];
3443 struct mlx5_ifc_set_roce_address_out_bits {
3445 u8 reserved_at_8[0x18];
3449 u8 reserved_at_40[0x40];
3452 struct mlx5_ifc_set_roce_address_in_bits {
3454 u8 reserved_at_10[0x10];
3456 u8 reserved_at_20[0x10];
3459 u8 roce_address_index[0x10];
3460 u8 reserved_at_50[0xc];
3461 u8 vhca_port_num[0x4];
3463 u8 reserved_at_60[0x20];
3465 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3468 struct mlx5_ifc_set_mad_demux_out_bits {
3470 u8 reserved_at_8[0x18];
3474 u8 reserved_at_40[0x40];
3478 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3479 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3482 struct mlx5_ifc_set_mad_demux_in_bits {
3484 u8 reserved_at_10[0x10];
3486 u8 reserved_at_20[0x10];
3489 u8 reserved_at_40[0x20];
3491 u8 reserved_at_60[0x6];
3493 u8 reserved_at_68[0x18];
3496 struct mlx5_ifc_set_l2_table_entry_out_bits {
3498 u8 reserved_at_8[0x18];
3502 u8 reserved_at_40[0x40];
3505 struct mlx5_ifc_set_l2_table_entry_in_bits {
3507 u8 reserved_at_10[0x10];
3509 u8 reserved_at_20[0x10];
3512 u8 reserved_at_40[0x60];
3514 u8 reserved_at_a0[0x8];
3515 u8 table_index[0x18];
3517 u8 reserved_at_c0[0x20];
3519 u8 reserved_at_e0[0x13];
3523 struct mlx5_ifc_mac_address_layout_bits mac_address;
3525 u8 reserved_at_140[0xc0];
3528 struct mlx5_ifc_set_issi_out_bits {
3530 u8 reserved_at_8[0x18];
3534 u8 reserved_at_40[0x40];
3537 struct mlx5_ifc_set_issi_in_bits {
3539 u8 reserved_at_10[0x10];
3541 u8 reserved_at_20[0x10];
3544 u8 reserved_at_40[0x10];
3545 u8 current_issi[0x10];
3547 u8 reserved_at_60[0x20];
3550 struct mlx5_ifc_set_hca_cap_out_bits {
3552 u8 reserved_at_8[0x18];
3556 u8 reserved_at_40[0x40];
3559 struct mlx5_ifc_set_hca_cap_in_bits {
3561 u8 reserved_at_10[0x10];
3563 u8 reserved_at_20[0x10];
3566 u8 reserved_at_40[0x40];
3568 union mlx5_ifc_hca_cap_union_bits capability;
3572 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3573 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3574 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3575 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3578 struct mlx5_ifc_set_fte_out_bits {
3580 u8 reserved_at_8[0x18];
3584 u8 reserved_at_40[0x40];
3587 struct mlx5_ifc_set_fte_in_bits {
3589 u8 reserved_at_10[0x10];
3591 u8 reserved_at_20[0x10];
3594 u8 other_vport[0x1];
3595 u8 reserved_at_41[0xf];
3596 u8 vport_number[0x10];
3598 u8 reserved_at_60[0x20];
3601 u8 reserved_at_88[0x18];
3603 u8 reserved_at_a0[0x8];
3606 u8 reserved_at_c0[0x18];
3607 u8 modify_enable_mask[0x8];
3609 u8 reserved_at_e0[0x20];
3611 u8 flow_index[0x20];
3613 u8 reserved_at_120[0xe0];
3615 struct mlx5_ifc_flow_context_bits flow_context;
3618 struct mlx5_ifc_rts2rts_qp_out_bits {
3620 u8 reserved_at_8[0x18];
3624 u8 reserved_at_40[0x40];
3627 struct mlx5_ifc_rts2rts_qp_in_bits {
3629 u8 reserved_at_10[0x10];
3631 u8 reserved_at_20[0x10];
3634 u8 reserved_at_40[0x8];
3637 u8 reserved_at_60[0x20];
3639 u8 opt_param_mask[0x20];
3641 u8 reserved_at_a0[0x20];
3643 struct mlx5_ifc_qpc_bits qpc;
3645 u8 reserved_at_800[0x80];
3648 struct mlx5_ifc_rtr2rts_qp_out_bits {
3650 u8 reserved_at_8[0x18];
3654 u8 reserved_at_40[0x40];
3657 struct mlx5_ifc_rtr2rts_qp_in_bits {
3659 u8 reserved_at_10[0x10];
3661 u8 reserved_at_20[0x10];
3664 u8 reserved_at_40[0x8];
3667 u8 reserved_at_60[0x20];
3669 u8 opt_param_mask[0x20];
3671 u8 reserved_at_a0[0x20];
3673 struct mlx5_ifc_qpc_bits qpc;
3675 u8 reserved_at_800[0x80];
3678 struct mlx5_ifc_rst2init_qp_out_bits {
3680 u8 reserved_at_8[0x18];
3684 u8 reserved_at_40[0x40];
3687 struct mlx5_ifc_rst2init_qp_in_bits {
3689 u8 reserved_at_10[0x10];
3691 u8 reserved_at_20[0x10];
3694 u8 reserved_at_40[0x8];
3697 u8 reserved_at_60[0x20];
3699 u8 opt_param_mask[0x20];
3701 u8 reserved_at_a0[0x20];
3703 struct mlx5_ifc_qpc_bits qpc;
3705 u8 reserved_at_800[0x80];
3708 struct mlx5_ifc_query_xrq_out_bits {
3710 u8 reserved_at_8[0x18];
3714 u8 reserved_at_40[0x40];
3716 struct mlx5_ifc_xrqc_bits xrq_context;
3719 struct mlx5_ifc_query_xrq_in_bits {
3721 u8 reserved_at_10[0x10];
3723 u8 reserved_at_20[0x10];
3726 u8 reserved_at_40[0x8];
3729 u8 reserved_at_60[0x20];
3732 struct mlx5_ifc_query_xrc_srq_out_bits {
3734 u8 reserved_at_8[0x18];
3738 u8 reserved_at_40[0x40];
3740 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3742 u8 reserved_at_280[0x600];
3747 struct mlx5_ifc_query_xrc_srq_in_bits {
3749 u8 reserved_at_10[0x10];
3751 u8 reserved_at_20[0x10];
3754 u8 reserved_at_40[0x8];
3757 u8 reserved_at_60[0x20];
3761 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3762 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3765 struct mlx5_ifc_query_vport_state_out_bits {
3767 u8 reserved_at_8[0x18];
3771 u8 reserved_at_40[0x20];
3773 u8 reserved_at_60[0x18];
3774 u8 admin_state[0x4];
3779 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
3780 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
3783 struct mlx5_ifc_query_vport_state_in_bits {
3785 u8 reserved_at_10[0x10];
3787 u8 reserved_at_20[0x10];
3790 u8 other_vport[0x1];
3791 u8 reserved_at_41[0xf];
3792 u8 vport_number[0x10];
3794 u8 reserved_at_60[0x20];
3797 struct mlx5_ifc_query_vnic_env_out_bits {
3799 u8 reserved_at_8[0x18];
3803 u8 reserved_at_40[0x40];
3805 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3809 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
3812 struct mlx5_ifc_query_vnic_env_in_bits {
3814 u8 reserved_at_10[0x10];
3816 u8 reserved_at_20[0x10];
3819 u8 other_vport[0x1];
3820 u8 reserved_at_41[0xf];
3821 u8 vport_number[0x10];
3823 u8 reserved_at_60[0x20];
3826 struct mlx5_ifc_query_vport_counter_out_bits {
3828 u8 reserved_at_8[0x18];
3832 u8 reserved_at_40[0x40];
3834 struct mlx5_ifc_traffic_counter_bits received_errors;
3836 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3838 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3840 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3842 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3844 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3846 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3848 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3850 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3852 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3854 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3856 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3858 u8 reserved_at_680[0xa00];
3862 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3865 struct mlx5_ifc_query_vport_counter_in_bits {
3867 u8 reserved_at_10[0x10];
3869 u8 reserved_at_20[0x10];
3872 u8 other_vport[0x1];
3873 u8 reserved_at_41[0xb];
3875 u8 vport_number[0x10];
3877 u8 reserved_at_60[0x60];
3880 u8 reserved_at_c1[0x1f];
3882 u8 reserved_at_e0[0x20];
3885 struct mlx5_ifc_query_tis_out_bits {
3887 u8 reserved_at_8[0x18];
3891 u8 reserved_at_40[0x40];
3893 struct mlx5_ifc_tisc_bits tis_context;
3896 struct mlx5_ifc_query_tis_in_bits {
3898 u8 reserved_at_10[0x10];
3900 u8 reserved_at_20[0x10];
3903 u8 reserved_at_40[0x8];
3906 u8 reserved_at_60[0x20];
3909 struct mlx5_ifc_query_tir_out_bits {
3911 u8 reserved_at_8[0x18];
3915 u8 reserved_at_40[0xc0];
3917 struct mlx5_ifc_tirc_bits tir_context;
3920 struct mlx5_ifc_query_tir_in_bits {
3922 u8 reserved_at_10[0x10];
3924 u8 reserved_at_20[0x10];
3927 u8 reserved_at_40[0x8];
3930 u8 reserved_at_60[0x20];
3933 struct mlx5_ifc_query_srq_out_bits {
3935 u8 reserved_at_8[0x18];
3939 u8 reserved_at_40[0x40];
3941 struct mlx5_ifc_srqc_bits srq_context_entry;
3943 u8 reserved_at_280[0x600];
3948 struct mlx5_ifc_query_srq_in_bits {
3950 u8 reserved_at_10[0x10];
3952 u8 reserved_at_20[0x10];
3955 u8 reserved_at_40[0x8];
3958 u8 reserved_at_60[0x20];
3961 struct mlx5_ifc_query_sq_out_bits {
3963 u8 reserved_at_8[0x18];
3967 u8 reserved_at_40[0xc0];
3969 struct mlx5_ifc_sqc_bits sq_context;
3972 struct mlx5_ifc_query_sq_in_bits {
3974 u8 reserved_at_10[0x10];
3976 u8 reserved_at_20[0x10];
3979 u8 reserved_at_40[0x8];
3982 u8 reserved_at_60[0x20];
3985 struct mlx5_ifc_query_special_contexts_out_bits {
3987 u8 reserved_at_8[0x18];
3991 u8 dump_fill_mkey[0x20];
3997 u8 reserved_at_a0[0x60];
4000 struct mlx5_ifc_query_special_contexts_in_bits {
4002 u8 reserved_at_10[0x10];
4004 u8 reserved_at_20[0x10];
4007 u8 reserved_at_40[0x40];
4010 struct mlx5_ifc_query_scheduling_element_out_bits {
4012 u8 reserved_at_10[0x10];
4014 u8 reserved_at_20[0x10];
4017 u8 reserved_at_40[0xc0];
4019 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4021 u8 reserved_at_300[0x100];
4025 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4028 struct mlx5_ifc_query_scheduling_element_in_bits {
4030 u8 reserved_at_10[0x10];
4032 u8 reserved_at_20[0x10];
4035 u8 scheduling_hierarchy[0x8];
4036 u8 reserved_at_48[0x18];
4038 u8 scheduling_element_id[0x20];
4040 u8 reserved_at_80[0x180];
4043 struct mlx5_ifc_query_rqt_out_bits {
4045 u8 reserved_at_8[0x18];
4049 u8 reserved_at_40[0xc0];
4051 struct mlx5_ifc_rqtc_bits rqt_context;
4054 struct mlx5_ifc_query_rqt_in_bits {
4056 u8 reserved_at_10[0x10];
4058 u8 reserved_at_20[0x10];
4061 u8 reserved_at_40[0x8];
4064 u8 reserved_at_60[0x20];
4067 struct mlx5_ifc_query_rq_out_bits {
4069 u8 reserved_at_8[0x18];
4073 u8 reserved_at_40[0xc0];
4075 struct mlx5_ifc_rqc_bits rq_context;
4078 struct mlx5_ifc_query_rq_in_bits {
4080 u8 reserved_at_10[0x10];
4082 u8 reserved_at_20[0x10];
4085 u8 reserved_at_40[0x8];
4088 u8 reserved_at_60[0x20];
4091 struct mlx5_ifc_query_roce_address_out_bits {
4093 u8 reserved_at_8[0x18];
4097 u8 reserved_at_40[0x40];
4099 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4102 struct mlx5_ifc_query_roce_address_in_bits {
4104 u8 reserved_at_10[0x10];
4106 u8 reserved_at_20[0x10];
4109 u8 roce_address_index[0x10];
4110 u8 reserved_at_50[0xc];
4111 u8 vhca_port_num[0x4];
4113 u8 reserved_at_60[0x20];
4116 struct mlx5_ifc_query_rmp_out_bits {
4118 u8 reserved_at_8[0x18];
4122 u8 reserved_at_40[0xc0];
4124 struct mlx5_ifc_rmpc_bits rmp_context;
4127 struct mlx5_ifc_query_rmp_in_bits {
4129 u8 reserved_at_10[0x10];
4131 u8 reserved_at_20[0x10];
4134 u8 reserved_at_40[0x8];
4137 u8 reserved_at_60[0x20];
4140 struct mlx5_ifc_query_qp_out_bits {
4142 u8 reserved_at_8[0x18];
4146 u8 reserved_at_40[0x40];
4148 u8 opt_param_mask[0x20];
4150 u8 reserved_at_a0[0x20];
4152 struct mlx5_ifc_qpc_bits qpc;
4154 u8 reserved_at_800[0x80];
4159 struct mlx5_ifc_query_qp_in_bits {
4161 u8 reserved_at_10[0x10];
4163 u8 reserved_at_20[0x10];
4166 u8 reserved_at_40[0x8];
4169 u8 reserved_at_60[0x20];
4172 struct mlx5_ifc_query_q_counter_out_bits {
4174 u8 reserved_at_8[0x18];
4178 u8 reserved_at_40[0x40];
4180 u8 rx_write_requests[0x20];
4182 u8 reserved_at_a0[0x20];
4184 u8 rx_read_requests[0x20];
4186 u8 reserved_at_e0[0x20];
4188 u8 rx_atomic_requests[0x20];
4190 u8 reserved_at_120[0x20];
4192 u8 rx_dct_connect[0x20];
4194 u8 reserved_at_160[0x20];
4196 u8 out_of_buffer[0x20];
4198 u8 reserved_at_1a0[0x20];
4200 u8 out_of_sequence[0x20];
4202 u8 reserved_at_1e0[0x20];
4204 u8 duplicate_request[0x20];
4206 u8 reserved_at_220[0x20];
4208 u8 rnr_nak_retry_err[0x20];
4210 u8 reserved_at_260[0x20];
4212 u8 packet_seq_err[0x20];
4214 u8 reserved_at_2a0[0x20];
4216 u8 implied_nak_seq_err[0x20];
4218 u8 reserved_at_2e0[0x20];
4220 u8 local_ack_timeout_err[0x20];
4222 u8 reserved_at_320[0xa0];
4224 u8 resp_local_length_error[0x20];
4226 u8 req_local_length_error[0x20];
4228 u8 resp_local_qp_error[0x20];
4230 u8 local_operation_error[0x20];
4232 u8 resp_local_protection[0x20];
4234 u8 req_local_protection[0x20];
4236 u8 resp_cqe_error[0x20];
4238 u8 req_cqe_error[0x20];
4240 u8 req_mw_binding[0x20];
4242 u8 req_bad_response[0x20];
4244 u8 req_remote_invalid_request[0x20];
4246 u8 resp_remote_invalid_request[0x20];
4248 u8 req_remote_access_errors[0x20];
4250 u8 resp_remote_access_errors[0x20];
4252 u8 req_remote_operation_errors[0x20];
4254 u8 req_transport_retries_exceeded[0x20];
4256 u8 cq_overflow[0x20];
4258 u8 resp_cqe_flush_error[0x20];
4260 u8 req_cqe_flush_error[0x20];
4262 u8 reserved_at_620[0x1e0];
4265 struct mlx5_ifc_query_q_counter_in_bits {
4267 u8 reserved_at_10[0x10];
4269 u8 reserved_at_20[0x10];
4272 u8 reserved_at_40[0x80];
4275 u8 reserved_at_c1[0x1f];
4277 u8 reserved_at_e0[0x18];
4278 u8 counter_set_id[0x8];
4281 struct mlx5_ifc_query_pages_out_bits {
4283 u8 reserved_at_8[0x18];
4287 u8 reserved_at_40[0x10];
4288 u8 function_id[0x10];
4294 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4295 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4296 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4299 struct mlx5_ifc_query_pages_in_bits {
4301 u8 reserved_at_10[0x10];
4303 u8 reserved_at_20[0x10];
4306 u8 reserved_at_40[0x10];
4307 u8 function_id[0x10];
4309 u8 reserved_at_60[0x20];
4312 struct mlx5_ifc_query_nic_vport_context_out_bits {
4314 u8 reserved_at_8[0x18];
4318 u8 reserved_at_40[0x40];
4320 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4323 struct mlx5_ifc_query_nic_vport_context_in_bits {
4325 u8 reserved_at_10[0x10];
4327 u8 reserved_at_20[0x10];
4330 u8 other_vport[0x1];
4331 u8 reserved_at_41[0xf];
4332 u8 vport_number[0x10];
4334 u8 reserved_at_60[0x5];
4335 u8 allowed_list_type[0x3];
4336 u8 reserved_at_68[0x18];
4339 struct mlx5_ifc_query_mkey_out_bits {
4341 u8 reserved_at_8[0x18];
4345 u8 reserved_at_40[0x40];
4347 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4349 u8 reserved_at_280[0x600];
4351 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4353 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4356 struct mlx5_ifc_query_mkey_in_bits {
4358 u8 reserved_at_10[0x10];
4360 u8 reserved_at_20[0x10];
4363 u8 reserved_at_40[0x8];
4364 u8 mkey_index[0x18];
4367 u8 reserved_at_61[0x1f];
4370 struct mlx5_ifc_query_mad_demux_out_bits {
4372 u8 reserved_at_8[0x18];
4376 u8 reserved_at_40[0x40];
4378 u8 mad_dumux_parameters_block[0x20];
4381 struct mlx5_ifc_query_mad_demux_in_bits {
4383 u8 reserved_at_10[0x10];
4385 u8 reserved_at_20[0x10];
4388 u8 reserved_at_40[0x40];
4391 struct mlx5_ifc_query_l2_table_entry_out_bits {
4393 u8 reserved_at_8[0x18];
4397 u8 reserved_at_40[0xa0];
4399 u8 reserved_at_e0[0x13];
4403 struct mlx5_ifc_mac_address_layout_bits mac_address;
4405 u8 reserved_at_140[0xc0];
4408 struct mlx5_ifc_query_l2_table_entry_in_bits {
4410 u8 reserved_at_10[0x10];
4412 u8 reserved_at_20[0x10];
4415 u8 reserved_at_40[0x60];
4417 u8 reserved_at_a0[0x8];
4418 u8 table_index[0x18];
4420 u8 reserved_at_c0[0x140];
4423 struct mlx5_ifc_query_issi_out_bits {
4425 u8 reserved_at_8[0x18];
4429 u8 reserved_at_40[0x10];
4430 u8 current_issi[0x10];
4432 u8 reserved_at_60[0xa0];
4434 u8 reserved_at_100[76][0x8];
4435 u8 supported_issi_dw0[0x20];
4438 struct mlx5_ifc_query_issi_in_bits {
4440 u8 reserved_at_10[0x10];
4442 u8 reserved_at_20[0x10];
4445 u8 reserved_at_40[0x40];
4448 struct mlx5_ifc_set_driver_version_out_bits {
4450 u8 reserved_0[0x18];
4453 u8 reserved_1[0x40];
4456 struct mlx5_ifc_set_driver_version_in_bits {
4458 u8 reserved_0[0x10];
4460 u8 reserved_1[0x10];
4463 u8 reserved_2[0x40];
4464 u8 driver_version[64][0x8];
4467 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4469 u8 reserved_at_8[0x18];
4473 u8 reserved_at_40[0x40];
4475 struct mlx5_ifc_pkey_bits pkey[0];
4478 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4480 u8 reserved_at_10[0x10];
4482 u8 reserved_at_20[0x10];
4485 u8 other_vport[0x1];
4486 u8 reserved_at_41[0xb];
4488 u8 vport_number[0x10];
4490 u8 reserved_at_60[0x10];
4491 u8 pkey_index[0x10];
4495 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4496 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4497 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4500 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4502 u8 reserved_at_8[0x18];
4506 u8 reserved_at_40[0x20];
4509 u8 reserved_at_70[0x10];
4511 struct mlx5_ifc_array128_auto_bits gid[0];
4514 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4516 u8 reserved_at_10[0x10];
4518 u8 reserved_at_20[0x10];
4521 u8 other_vport[0x1];
4522 u8 reserved_at_41[0xb];
4524 u8 vport_number[0x10];
4526 u8 reserved_at_60[0x10];
4530 struct mlx5_ifc_query_hca_vport_context_out_bits {
4532 u8 reserved_at_8[0x18];
4536 u8 reserved_at_40[0x40];
4538 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4541 struct mlx5_ifc_query_hca_vport_context_in_bits {
4543 u8 reserved_at_10[0x10];
4545 u8 reserved_at_20[0x10];
4548 u8 other_vport[0x1];
4549 u8 reserved_at_41[0xb];
4551 u8 vport_number[0x10];
4553 u8 reserved_at_60[0x20];
4556 struct mlx5_ifc_query_hca_cap_out_bits {
4558 u8 reserved_at_8[0x18];
4562 u8 reserved_at_40[0x40];
4564 union mlx5_ifc_hca_cap_union_bits capability;
4567 struct mlx5_ifc_query_hca_cap_in_bits {
4569 u8 reserved_at_10[0x10];
4571 u8 reserved_at_20[0x10];
4574 u8 reserved_at_40[0x40];
4577 struct mlx5_ifc_query_flow_table_out_bits {
4579 u8 reserved_at_8[0x18];
4583 u8 reserved_at_40[0x80];
4585 u8 reserved_at_c0[0x8];
4587 u8 reserved_at_d0[0x8];
4590 u8 reserved_at_e0[0x120];
4593 struct mlx5_ifc_query_flow_table_in_bits {
4595 u8 reserved_at_10[0x10];
4597 u8 reserved_at_20[0x10];
4600 u8 reserved_at_40[0x40];
4603 u8 reserved_at_88[0x18];
4605 u8 reserved_at_a0[0x8];
4608 u8 reserved_at_c0[0x140];
4611 struct mlx5_ifc_query_fte_out_bits {
4613 u8 reserved_at_8[0x18];
4617 u8 reserved_at_40[0x1c0];
4619 struct mlx5_ifc_flow_context_bits flow_context;
4622 struct mlx5_ifc_query_fte_in_bits {
4624 u8 reserved_at_10[0x10];
4626 u8 reserved_at_20[0x10];
4629 u8 reserved_at_40[0x40];
4632 u8 reserved_at_88[0x18];
4634 u8 reserved_at_a0[0x8];
4637 u8 reserved_at_c0[0x40];
4639 u8 flow_index[0x20];
4641 u8 reserved_at_120[0xe0];
4645 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4646 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4647 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4648 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0X3,
4651 struct mlx5_ifc_query_flow_group_out_bits {
4653 u8 reserved_at_8[0x18];
4657 u8 reserved_at_40[0xa0];
4659 u8 start_flow_index[0x20];
4661 u8 reserved_at_100[0x20];
4663 u8 end_flow_index[0x20];
4665 u8 reserved_at_140[0xa0];
4667 u8 reserved_at_1e0[0x18];
4668 u8 match_criteria_enable[0x8];
4670 struct mlx5_ifc_fte_match_param_bits match_criteria;
4672 u8 reserved_at_1200[0xe00];
4675 struct mlx5_ifc_query_flow_group_in_bits {
4677 u8 reserved_at_10[0x10];
4679 u8 reserved_at_20[0x10];
4682 u8 reserved_at_40[0x40];
4685 u8 reserved_at_88[0x18];
4687 u8 reserved_at_a0[0x8];
4692 u8 reserved_at_e0[0x120];
4695 struct mlx5_ifc_query_flow_counter_out_bits {
4697 u8 reserved_at_8[0x18];
4701 u8 reserved_at_40[0x40];
4703 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4706 struct mlx5_ifc_query_flow_counter_in_bits {
4708 u8 reserved_at_10[0x10];
4710 u8 reserved_at_20[0x10];
4713 u8 reserved_at_40[0x80];
4716 u8 reserved_at_c1[0xf];
4717 u8 num_of_counters[0x10];
4719 u8 flow_counter_id[0x20];
4722 struct mlx5_ifc_query_esw_vport_context_out_bits {
4724 u8 reserved_at_8[0x18];
4728 u8 reserved_at_40[0x40];
4730 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4733 struct mlx5_ifc_query_esw_vport_context_in_bits {
4735 u8 reserved_at_10[0x10];
4737 u8 reserved_at_20[0x10];
4740 u8 other_vport[0x1];
4741 u8 reserved_at_41[0xf];
4742 u8 vport_number[0x10];
4744 u8 reserved_at_60[0x20];
4747 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4749 u8 reserved_at_8[0x18];
4753 u8 reserved_at_40[0x40];
4756 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4757 u8 reserved_at_0[0x1c];
4758 u8 vport_cvlan_insert[0x1];
4759 u8 vport_svlan_insert[0x1];
4760 u8 vport_cvlan_strip[0x1];
4761 u8 vport_svlan_strip[0x1];
4764 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4766 u8 reserved_at_10[0x10];
4768 u8 reserved_at_20[0x10];
4771 u8 other_vport[0x1];
4772 u8 reserved_at_41[0xf];
4773 u8 vport_number[0x10];
4775 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4777 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4780 struct mlx5_ifc_query_eq_out_bits {
4782 u8 reserved_at_8[0x18];
4786 u8 reserved_at_40[0x40];
4788 struct mlx5_ifc_eqc_bits eq_context_entry;
4790 u8 reserved_at_280[0x40];
4792 u8 event_bitmask[0x40];
4794 u8 reserved_at_300[0x580];
4799 struct mlx5_ifc_query_eq_in_bits {
4801 u8 reserved_at_10[0x10];
4803 u8 reserved_at_20[0x10];
4806 u8 reserved_at_40[0x18];
4809 u8 reserved_at_60[0x20];
4812 struct mlx5_ifc_encap_header_in_bits {
4813 u8 reserved_at_0[0x5];
4814 u8 header_type[0x3];
4815 u8 reserved_at_8[0xe];
4816 u8 encap_header_size[0xa];
4818 u8 reserved_at_20[0x10];
4819 u8 encap_header[2][0x8];
4821 u8 more_encap_header[0][0x8];
4824 struct mlx5_ifc_query_encap_header_out_bits {
4826 u8 reserved_at_8[0x18];
4830 u8 reserved_at_40[0xa0];
4832 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4835 struct mlx5_ifc_query_encap_header_in_bits {
4837 u8 reserved_at_10[0x10];
4839 u8 reserved_at_20[0x10];
4844 u8 reserved_at_60[0xa0];
4847 struct mlx5_ifc_alloc_encap_header_out_bits {
4849 u8 reserved_at_8[0x18];
4855 u8 reserved_at_60[0x20];
4858 struct mlx5_ifc_alloc_encap_header_in_bits {
4860 u8 reserved_at_10[0x10];
4862 u8 reserved_at_20[0x10];
4865 u8 reserved_at_40[0xa0];
4867 struct mlx5_ifc_encap_header_in_bits encap_header;
4870 struct mlx5_ifc_dealloc_encap_header_out_bits {
4872 u8 reserved_at_8[0x18];
4876 u8 reserved_at_40[0x40];
4879 struct mlx5_ifc_dealloc_encap_header_in_bits {
4881 u8 reserved_at_10[0x10];
4883 u8 reserved_20[0x10];
4888 u8 reserved_60[0x20];
4891 struct mlx5_ifc_set_action_in_bits {
4892 u8 action_type[0x4];
4894 u8 reserved_at_10[0x3];
4896 u8 reserved_at_18[0x3];
4902 struct mlx5_ifc_add_action_in_bits {
4903 u8 action_type[0x4];
4905 u8 reserved_at_10[0x10];
4910 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4911 struct mlx5_ifc_set_action_in_bits set_action_in;
4912 struct mlx5_ifc_add_action_in_bits add_action_in;
4913 u8 reserved_at_0[0x40];
4917 MLX5_ACTION_TYPE_SET = 0x1,
4918 MLX5_ACTION_TYPE_ADD = 0x2,
4922 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4923 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4924 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4925 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4926 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4927 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4928 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4929 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4930 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4931 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4932 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4933 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4934 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4935 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4936 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4937 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4938 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4939 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4940 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4941 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4942 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4943 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
4944 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4947 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4949 u8 reserved_at_8[0x18];
4953 u8 modify_header_id[0x20];
4955 u8 reserved_at_60[0x20];
4958 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4960 u8 reserved_at_10[0x10];
4962 u8 reserved_at_20[0x10];
4965 u8 reserved_at_40[0x20];
4968 u8 reserved_at_68[0x10];
4969 u8 num_of_actions[0x8];
4971 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4974 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4976 u8 reserved_at_8[0x18];
4980 u8 reserved_at_40[0x40];
4983 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4985 u8 reserved_at_10[0x10];
4987 u8 reserved_at_20[0x10];
4990 u8 modify_header_id[0x20];
4992 u8 reserved_at_60[0x20];
4995 struct mlx5_ifc_query_dct_out_bits {
4997 u8 reserved_at_8[0x18];
5001 u8 reserved_at_40[0x40];
5003 struct mlx5_ifc_dctc_bits dct_context_entry;
5005 u8 reserved_at_280[0x180];
5008 struct mlx5_ifc_query_dct_in_bits {
5010 u8 reserved_at_10[0x10];
5012 u8 reserved_at_20[0x10];
5015 u8 reserved_at_40[0x8];
5018 u8 reserved_at_60[0x20];
5021 struct mlx5_ifc_query_cq_out_bits {
5023 u8 reserved_at_8[0x18];
5027 u8 reserved_at_40[0x40];
5029 struct mlx5_ifc_cqc_bits cq_context;
5031 u8 reserved_at_280[0x600];
5036 struct mlx5_ifc_query_cq_in_bits {
5038 u8 reserved_at_10[0x10];
5040 u8 reserved_at_20[0x10];
5043 u8 reserved_at_40[0x8];
5046 u8 reserved_at_60[0x20];
5049 struct mlx5_ifc_query_cong_status_out_bits {
5051 u8 reserved_at_8[0x18];
5055 u8 reserved_at_40[0x20];
5059 u8 reserved_at_62[0x1e];
5062 struct mlx5_ifc_query_cong_status_in_bits {
5064 u8 reserved_at_10[0x10];
5066 u8 reserved_at_20[0x10];
5069 u8 reserved_at_40[0x18];
5071 u8 cong_protocol[0x4];
5073 u8 reserved_at_60[0x20];
5076 struct mlx5_ifc_query_cong_statistics_out_bits {
5078 u8 reserved_at_8[0x18];
5082 u8 reserved_at_40[0x40];
5084 u8 rp_cur_flows[0x20];
5088 u8 rp_cnp_ignored_high[0x20];
5090 u8 rp_cnp_ignored_low[0x20];
5092 u8 rp_cnp_handled_high[0x20];
5094 u8 rp_cnp_handled_low[0x20];
5096 u8 reserved_at_140[0x100];
5098 u8 time_stamp_high[0x20];
5100 u8 time_stamp_low[0x20];
5102 u8 accumulators_period[0x20];
5104 u8 np_ecn_marked_roce_packets_high[0x20];
5106 u8 np_ecn_marked_roce_packets_low[0x20];
5108 u8 np_cnp_sent_high[0x20];
5110 u8 np_cnp_sent_low[0x20];
5112 u8 reserved_at_320[0x560];
5115 struct mlx5_ifc_query_cong_statistics_in_bits {
5117 u8 reserved_at_10[0x10];
5119 u8 reserved_at_20[0x10];
5123 u8 reserved_at_41[0x1f];
5125 u8 reserved_at_60[0x20];
5128 struct mlx5_ifc_query_cong_params_out_bits {
5130 u8 reserved_at_8[0x18];
5134 u8 reserved_at_40[0x40];
5136 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5139 struct mlx5_ifc_query_cong_params_in_bits {
5141 u8 reserved_at_10[0x10];
5143 u8 reserved_at_20[0x10];
5146 u8 reserved_at_40[0x1c];
5147 u8 cong_protocol[0x4];
5149 u8 reserved_at_60[0x20];
5152 struct mlx5_ifc_query_adapter_out_bits {
5154 u8 reserved_at_8[0x18];
5158 u8 reserved_at_40[0x40];
5160 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5163 struct mlx5_ifc_query_adapter_in_bits {
5165 u8 reserved_at_10[0x10];
5167 u8 reserved_at_20[0x10];
5170 u8 reserved_at_40[0x40];
5173 struct mlx5_ifc_qp_2rst_out_bits {
5175 u8 reserved_at_8[0x18];
5179 u8 reserved_at_40[0x40];
5182 struct mlx5_ifc_qp_2rst_in_bits {
5184 u8 reserved_at_10[0x10];
5186 u8 reserved_at_20[0x10];
5189 u8 reserved_at_40[0x8];
5192 u8 reserved_at_60[0x20];
5195 struct mlx5_ifc_qp_2err_out_bits {
5197 u8 reserved_at_8[0x18];
5201 u8 reserved_at_40[0x40];
5204 struct mlx5_ifc_qp_2err_in_bits {
5206 u8 reserved_at_10[0x10];
5208 u8 reserved_at_20[0x10];
5211 u8 reserved_at_40[0x8];
5214 u8 reserved_at_60[0x20];
5217 struct mlx5_ifc_page_fault_resume_out_bits {
5219 u8 reserved_at_8[0x18];
5223 u8 reserved_at_40[0x40];
5226 struct mlx5_ifc_page_fault_resume_in_bits {
5228 u8 reserved_at_10[0x10];
5230 u8 reserved_at_20[0x10];
5234 u8 reserved_at_41[0x4];
5235 u8 page_fault_type[0x3];
5238 u8 reserved_at_60[0x8];
5242 struct mlx5_ifc_nop_out_bits {
5244 u8 reserved_at_8[0x18];
5248 u8 reserved_at_40[0x40];
5251 struct mlx5_ifc_nop_in_bits {
5253 u8 reserved_at_10[0x10];
5255 u8 reserved_at_20[0x10];
5258 u8 reserved_at_40[0x40];
5261 struct mlx5_ifc_modify_vport_state_out_bits {
5263 u8 reserved_at_8[0x18];
5267 u8 reserved_at_40[0x40];
5270 struct mlx5_ifc_modify_vport_state_in_bits {
5272 u8 reserved_at_10[0x10];
5274 u8 reserved_at_20[0x10];
5277 u8 other_vport[0x1];
5278 u8 reserved_at_41[0xf];
5279 u8 vport_number[0x10];
5281 u8 reserved_at_60[0x18];
5282 u8 admin_state[0x4];
5283 u8 reserved_at_7c[0x4];
5286 struct mlx5_ifc_modify_tis_out_bits {
5288 u8 reserved_at_8[0x18];
5292 u8 reserved_at_40[0x40];
5295 struct mlx5_ifc_modify_tis_bitmask_bits {
5296 u8 reserved_at_0[0x20];
5298 u8 reserved_at_20[0x1d];
5299 u8 lag_tx_port_affinity[0x1];
5300 u8 strict_lag_tx_port_affinity[0x1];
5304 struct mlx5_ifc_modify_tis_in_bits {
5306 u8 reserved_at_10[0x10];
5308 u8 reserved_at_20[0x10];
5311 u8 reserved_at_40[0x8];
5314 u8 reserved_at_60[0x20];
5316 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5318 u8 reserved_at_c0[0x40];
5320 struct mlx5_ifc_tisc_bits ctx;
5323 struct mlx5_ifc_modify_tir_bitmask_bits {
5324 u8 reserved_at_0[0x20];
5326 u8 reserved_at_20[0x1b];
5328 u8 reserved_at_3c[0x1];
5330 u8 reserved_at_3e[0x1];
5334 struct mlx5_ifc_modify_tir_out_bits {
5336 u8 reserved_at_8[0x18];
5340 u8 reserved_at_40[0x40];
5343 struct mlx5_ifc_modify_tir_in_bits {
5345 u8 reserved_at_10[0x10];
5347 u8 reserved_at_20[0x10];
5350 u8 reserved_at_40[0x8];
5353 u8 reserved_at_60[0x20];
5355 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5357 u8 reserved_at_c0[0x40];
5359 struct mlx5_ifc_tirc_bits ctx;
5362 struct mlx5_ifc_modify_sq_out_bits {
5364 u8 reserved_at_8[0x18];
5368 u8 reserved_at_40[0x40];
5371 struct mlx5_ifc_modify_sq_in_bits {
5373 u8 reserved_at_10[0x10];
5375 u8 reserved_at_20[0x10];
5379 u8 reserved_at_44[0x4];
5382 u8 reserved_at_60[0x20];
5384 u8 modify_bitmask[0x40];
5386 u8 reserved_at_c0[0x40];
5388 struct mlx5_ifc_sqc_bits ctx;
5391 struct mlx5_ifc_modify_scheduling_element_out_bits {
5393 u8 reserved_at_8[0x18];
5397 u8 reserved_at_40[0x1c0];
5401 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5402 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5405 struct mlx5_ifc_modify_scheduling_element_in_bits {
5407 u8 reserved_at_10[0x10];
5409 u8 reserved_at_20[0x10];
5412 u8 scheduling_hierarchy[0x8];
5413 u8 reserved_at_48[0x18];
5415 u8 scheduling_element_id[0x20];
5417 u8 reserved_at_80[0x20];
5419 u8 modify_bitmask[0x20];
5421 u8 reserved_at_c0[0x40];
5423 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5425 u8 reserved_at_300[0x100];
5428 struct mlx5_ifc_modify_rqt_out_bits {
5430 u8 reserved_at_8[0x18];
5434 u8 reserved_at_40[0x40];
5437 struct mlx5_ifc_rqt_bitmask_bits {
5438 u8 reserved_at_0[0x20];
5440 u8 reserved_at_20[0x1f];
5444 struct mlx5_ifc_modify_rqt_in_bits {
5446 u8 reserved_at_10[0x10];
5448 u8 reserved_at_20[0x10];
5451 u8 reserved_at_40[0x8];
5454 u8 reserved_at_60[0x20];
5456 struct mlx5_ifc_rqt_bitmask_bits bitmask;
5458 u8 reserved_at_c0[0x40];
5460 struct mlx5_ifc_rqtc_bits ctx;
5463 struct mlx5_ifc_modify_rq_out_bits {
5465 u8 reserved_at_8[0x18];
5469 u8 reserved_at_40[0x40];
5473 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5474 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5475 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5478 struct mlx5_ifc_modify_rq_in_bits {
5480 u8 reserved_at_10[0x10];
5482 u8 reserved_at_20[0x10];
5486 u8 reserved_at_44[0x4];
5489 u8 reserved_at_60[0x20];
5491 u8 modify_bitmask[0x40];
5493 u8 reserved_at_c0[0x40];
5495 struct mlx5_ifc_rqc_bits ctx;
5498 struct mlx5_ifc_modify_rmp_out_bits {
5500 u8 reserved_at_8[0x18];
5504 u8 reserved_at_40[0x40];
5507 struct mlx5_ifc_rmp_bitmask_bits {
5508 u8 reserved_at_0[0x20];
5510 u8 reserved_at_20[0x1f];
5514 struct mlx5_ifc_modify_rmp_in_bits {
5516 u8 reserved_at_10[0x10];
5518 u8 reserved_at_20[0x10];
5522 u8 reserved_at_44[0x4];
5525 u8 reserved_at_60[0x20];
5527 struct mlx5_ifc_rmp_bitmask_bits bitmask;
5529 u8 reserved_at_c0[0x40];
5531 struct mlx5_ifc_rmpc_bits ctx;
5534 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5536 u8 reserved_at_8[0x18];
5540 u8 reserved_at_40[0x40];
5543 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5544 u8 reserved_at_0[0x12];
5545 u8 affiliation[0x1];
5546 u8 reserved_at_e[0x1];
5547 u8 disable_uc_local_lb[0x1];
5548 u8 disable_mc_local_lb[0x1];
5553 u8 change_event[0x1];
5555 u8 permanent_address[0x1];
5556 u8 addresses_list[0x1];
5558 u8 reserved_at_1f[0x1];
5561 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5563 u8 reserved_at_10[0x10];
5565 u8 reserved_at_20[0x10];
5568 u8 other_vport[0x1];
5569 u8 reserved_at_41[0xf];
5570 u8 vport_number[0x10];
5572 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5574 u8 reserved_at_80[0x780];
5576 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5579 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5581 u8 reserved_at_8[0x18];
5585 u8 reserved_at_40[0x40];
5588 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5590 u8 reserved_at_10[0x10];
5592 u8 reserved_at_20[0x10];
5595 u8 other_vport[0x1];
5596 u8 reserved_at_41[0xb];
5598 u8 vport_number[0x10];
5600 u8 reserved_at_60[0x20];
5602 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5605 struct mlx5_ifc_modify_cq_out_bits {
5607 u8 reserved_at_8[0x18];
5611 u8 reserved_at_40[0x40];
5615 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5616 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5619 struct mlx5_ifc_modify_cq_in_bits {
5621 u8 reserved_at_10[0x10];
5623 u8 reserved_at_20[0x10];
5626 u8 reserved_at_40[0x8];
5629 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5631 struct mlx5_ifc_cqc_bits cq_context;
5633 u8 reserved_at_280[0x60];
5635 u8 cq_umem_valid[0x1];
5636 u8 reserved_at_2e1[0x1f];
5638 u8 reserved_at_300[0x580];
5643 struct mlx5_ifc_modify_cong_status_out_bits {
5645 u8 reserved_at_8[0x18];
5649 u8 reserved_at_40[0x40];
5652 struct mlx5_ifc_modify_cong_status_in_bits {
5654 u8 reserved_at_10[0x10];
5656 u8 reserved_at_20[0x10];
5659 u8 reserved_at_40[0x18];
5661 u8 cong_protocol[0x4];
5665 u8 reserved_at_62[0x1e];
5668 struct mlx5_ifc_modify_cong_params_out_bits {
5670 u8 reserved_at_8[0x18];
5674 u8 reserved_at_40[0x40];
5677 struct mlx5_ifc_modify_cong_params_in_bits {
5679 u8 reserved_at_10[0x10];
5681 u8 reserved_at_20[0x10];
5684 u8 reserved_at_40[0x1c];
5685 u8 cong_protocol[0x4];
5687 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5689 u8 reserved_at_80[0x80];
5691 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5694 struct mlx5_ifc_manage_pages_out_bits {
5696 u8 reserved_at_8[0x18];
5700 u8 output_num_entries[0x20];
5702 u8 reserved_at_60[0x20];
5708 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5709 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5710 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5713 struct mlx5_ifc_manage_pages_in_bits {
5715 u8 reserved_at_10[0x10];
5717 u8 reserved_at_20[0x10];
5720 u8 reserved_at_40[0x10];
5721 u8 function_id[0x10];
5723 u8 input_num_entries[0x20];
5728 struct mlx5_ifc_mad_ifc_out_bits {
5730 u8 reserved_at_8[0x18];
5734 u8 reserved_at_40[0x40];
5736 u8 response_mad_packet[256][0x8];
5739 struct mlx5_ifc_mad_ifc_in_bits {
5741 u8 reserved_at_10[0x10];
5743 u8 reserved_at_20[0x10];
5746 u8 remote_lid[0x10];
5747 u8 reserved_at_50[0x8];
5750 u8 reserved_at_60[0x20];
5755 struct mlx5_ifc_init_hca_out_bits {
5757 u8 reserved_at_8[0x18];
5761 u8 reserved_at_40[0x40];
5764 struct mlx5_ifc_init_hca_in_bits {
5766 u8 reserved_at_10[0x10];
5768 u8 reserved_at_20[0x10];
5771 u8 reserved_at_40[0x40];
5772 u8 sw_owner_id[4][0x20];
5775 struct mlx5_ifc_init2rtr_qp_out_bits {
5777 u8 reserved_at_8[0x18];
5781 u8 reserved_at_40[0x40];
5784 struct mlx5_ifc_init2rtr_qp_in_bits {
5786 u8 reserved_at_10[0x10];
5788 u8 reserved_at_20[0x10];
5791 u8 reserved_at_40[0x8];
5794 u8 reserved_at_60[0x20];
5796 u8 opt_param_mask[0x20];
5798 u8 reserved_at_a0[0x20];
5800 struct mlx5_ifc_qpc_bits qpc;
5802 u8 reserved_at_800[0x80];
5805 struct mlx5_ifc_init2init_qp_out_bits {
5807 u8 reserved_at_8[0x18];
5811 u8 reserved_at_40[0x40];
5814 struct mlx5_ifc_init2init_qp_in_bits {
5816 u8 reserved_at_10[0x10];
5818 u8 reserved_at_20[0x10];
5821 u8 reserved_at_40[0x8];
5824 u8 reserved_at_60[0x20];
5826 u8 opt_param_mask[0x20];
5828 u8 reserved_at_a0[0x20];
5830 struct mlx5_ifc_qpc_bits qpc;
5832 u8 reserved_at_800[0x80];
5835 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5837 u8 reserved_at_8[0x18];
5841 u8 reserved_at_40[0x40];
5843 u8 packet_headers_log[128][0x8];
5845 u8 packet_syndrome[64][0x8];
5848 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5850 u8 reserved_at_10[0x10];
5852 u8 reserved_at_20[0x10];
5855 u8 reserved_at_40[0x40];
5858 struct mlx5_ifc_gen_eqe_in_bits {
5860 u8 reserved_at_10[0x10];
5862 u8 reserved_at_20[0x10];
5865 u8 reserved_at_40[0x18];
5868 u8 reserved_at_60[0x20];
5873 struct mlx5_ifc_gen_eq_out_bits {
5875 u8 reserved_at_8[0x18];
5879 u8 reserved_at_40[0x40];
5882 struct mlx5_ifc_enable_hca_out_bits {
5884 u8 reserved_at_8[0x18];
5888 u8 reserved_at_40[0x20];
5891 struct mlx5_ifc_enable_hca_in_bits {
5893 u8 reserved_at_10[0x10];
5895 u8 reserved_at_20[0x10];
5898 u8 reserved_at_40[0x10];
5899 u8 function_id[0x10];
5901 u8 reserved_at_60[0x20];
5904 struct mlx5_ifc_drain_dct_out_bits {
5906 u8 reserved_at_8[0x18];
5910 u8 reserved_at_40[0x40];
5913 struct mlx5_ifc_drain_dct_in_bits {
5915 u8 reserved_at_10[0x10];
5917 u8 reserved_at_20[0x10];
5920 u8 reserved_at_40[0x8];
5923 u8 reserved_at_60[0x20];
5926 struct mlx5_ifc_disable_hca_out_bits {
5928 u8 reserved_at_8[0x18];
5932 u8 reserved_at_40[0x20];
5935 struct mlx5_ifc_disable_hca_in_bits {
5937 u8 reserved_at_10[0x10];
5939 u8 reserved_at_20[0x10];
5942 u8 reserved_at_40[0x10];
5943 u8 function_id[0x10];
5945 u8 reserved_at_60[0x20];
5948 struct mlx5_ifc_detach_from_mcg_out_bits {
5950 u8 reserved_at_8[0x18];
5954 u8 reserved_at_40[0x40];
5957 struct mlx5_ifc_detach_from_mcg_in_bits {
5959 u8 reserved_at_10[0x10];
5961 u8 reserved_at_20[0x10];
5964 u8 reserved_at_40[0x8];
5967 u8 reserved_at_60[0x20];
5969 u8 multicast_gid[16][0x8];
5972 struct mlx5_ifc_destroy_xrq_out_bits {
5974 u8 reserved_at_8[0x18];
5978 u8 reserved_at_40[0x40];
5981 struct mlx5_ifc_destroy_xrq_in_bits {
5983 u8 reserved_at_10[0x10];
5985 u8 reserved_at_20[0x10];
5988 u8 reserved_at_40[0x8];
5991 u8 reserved_at_60[0x20];
5994 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5996 u8 reserved_at_8[0x18];
6000 u8 reserved_at_40[0x40];
6003 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6005 u8 reserved_at_10[0x10];
6007 u8 reserved_at_20[0x10];
6010 u8 reserved_at_40[0x8];
6013 u8 reserved_at_60[0x20];
6016 struct mlx5_ifc_destroy_tis_out_bits {
6018 u8 reserved_at_8[0x18];
6022 u8 reserved_at_40[0x40];
6025 struct mlx5_ifc_destroy_tis_in_bits {
6027 u8 reserved_at_10[0x10];
6029 u8 reserved_at_20[0x10];
6032 u8 reserved_at_40[0x8];
6035 u8 reserved_at_60[0x20];
6038 struct mlx5_ifc_destroy_tir_out_bits {
6040 u8 reserved_at_8[0x18];
6044 u8 reserved_at_40[0x40];
6047 struct mlx5_ifc_destroy_tir_in_bits {
6049 u8 reserved_at_10[0x10];
6051 u8 reserved_at_20[0x10];
6054 u8 reserved_at_40[0x8];
6057 u8 reserved_at_60[0x20];
6060 struct mlx5_ifc_destroy_srq_out_bits {
6062 u8 reserved_at_8[0x18];
6066 u8 reserved_at_40[0x40];
6069 struct mlx5_ifc_destroy_srq_in_bits {
6071 u8 reserved_at_10[0x10];
6073 u8 reserved_at_20[0x10];
6076 u8 reserved_at_40[0x8];
6079 u8 reserved_at_60[0x20];
6082 struct mlx5_ifc_destroy_sq_out_bits {
6084 u8 reserved_at_8[0x18];
6088 u8 reserved_at_40[0x40];
6091 struct mlx5_ifc_destroy_sq_in_bits {
6093 u8 reserved_at_10[0x10];
6095 u8 reserved_at_20[0x10];
6098 u8 reserved_at_40[0x8];
6101 u8 reserved_at_60[0x20];
6104 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6106 u8 reserved_at_8[0x18];
6110 u8 reserved_at_40[0x1c0];
6113 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6115 u8 reserved_at_10[0x10];
6117 u8 reserved_at_20[0x10];
6120 u8 scheduling_hierarchy[0x8];
6121 u8 reserved_at_48[0x18];
6123 u8 scheduling_element_id[0x20];
6125 u8 reserved_at_80[0x180];
6128 struct mlx5_ifc_destroy_rqt_out_bits {
6130 u8 reserved_at_8[0x18];
6134 u8 reserved_at_40[0x40];
6137 struct mlx5_ifc_destroy_rqt_in_bits {
6139 u8 reserved_at_10[0x10];
6141 u8 reserved_at_20[0x10];
6144 u8 reserved_at_40[0x8];
6147 u8 reserved_at_60[0x20];
6150 struct mlx5_ifc_destroy_rq_out_bits {
6152 u8 reserved_at_8[0x18];
6156 u8 reserved_at_40[0x40];
6159 struct mlx5_ifc_destroy_rq_in_bits {
6161 u8 reserved_at_10[0x10];
6163 u8 reserved_at_20[0x10];
6166 u8 reserved_at_40[0x8];
6169 u8 reserved_at_60[0x20];
6172 struct mlx5_ifc_set_delay_drop_params_in_bits {
6174 u8 reserved_at_10[0x10];
6176 u8 reserved_at_20[0x10];
6179 u8 reserved_at_40[0x20];
6181 u8 reserved_at_60[0x10];
6182 u8 delay_drop_timeout[0x10];
6185 struct mlx5_ifc_set_delay_drop_params_out_bits {
6187 u8 reserved_at_8[0x18];
6191 u8 reserved_at_40[0x40];
6194 struct mlx5_ifc_destroy_rmp_out_bits {
6196 u8 reserved_at_8[0x18];
6200 u8 reserved_at_40[0x40];
6203 struct mlx5_ifc_destroy_rmp_in_bits {
6205 u8 reserved_at_10[0x10];
6207 u8 reserved_at_20[0x10];
6210 u8 reserved_at_40[0x8];
6213 u8 reserved_at_60[0x20];
6216 struct mlx5_ifc_destroy_qp_out_bits {
6218 u8 reserved_at_8[0x18];
6222 u8 reserved_at_40[0x40];
6225 struct mlx5_ifc_destroy_qp_in_bits {
6227 u8 reserved_at_10[0x10];
6229 u8 reserved_at_20[0x10];
6232 u8 reserved_at_40[0x8];
6235 u8 reserved_at_60[0x20];
6238 struct mlx5_ifc_destroy_psv_out_bits {
6240 u8 reserved_at_8[0x18];
6244 u8 reserved_at_40[0x40];
6247 struct mlx5_ifc_destroy_psv_in_bits {
6249 u8 reserved_at_10[0x10];
6251 u8 reserved_at_20[0x10];
6254 u8 reserved_at_40[0x8];
6257 u8 reserved_at_60[0x20];
6260 struct mlx5_ifc_destroy_mkey_out_bits {
6262 u8 reserved_at_8[0x18];
6266 u8 reserved_at_40[0x40];
6269 struct mlx5_ifc_destroy_mkey_in_bits {
6271 u8 reserved_at_10[0x10];
6273 u8 reserved_at_20[0x10];
6276 u8 reserved_at_40[0x8];
6277 u8 mkey_index[0x18];
6279 u8 reserved_at_60[0x20];
6282 struct mlx5_ifc_destroy_flow_table_out_bits {
6284 u8 reserved_at_8[0x18];
6288 u8 reserved_at_40[0x40];
6291 struct mlx5_ifc_destroy_flow_table_in_bits {
6293 u8 reserved_at_10[0x10];
6295 u8 reserved_at_20[0x10];
6298 u8 other_vport[0x1];
6299 u8 reserved_at_41[0xf];
6300 u8 vport_number[0x10];
6302 u8 reserved_at_60[0x20];
6305 u8 reserved_at_88[0x18];
6307 u8 reserved_at_a0[0x8];
6310 u8 reserved_at_c0[0x140];
6313 struct mlx5_ifc_destroy_flow_group_out_bits {
6315 u8 reserved_at_8[0x18];
6319 u8 reserved_at_40[0x40];
6322 struct mlx5_ifc_destroy_flow_group_in_bits {
6324 u8 reserved_at_10[0x10];
6326 u8 reserved_at_20[0x10];
6329 u8 other_vport[0x1];
6330 u8 reserved_at_41[0xf];
6331 u8 vport_number[0x10];
6333 u8 reserved_at_60[0x20];
6336 u8 reserved_at_88[0x18];
6338 u8 reserved_at_a0[0x8];
6343 u8 reserved_at_e0[0x120];
6346 struct mlx5_ifc_destroy_eq_out_bits {
6348 u8 reserved_at_8[0x18];
6352 u8 reserved_at_40[0x40];
6355 struct mlx5_ifc_destroy_eq_in_bits {
6357 u8 reserved_at_10[0x10];
6359 u8 reserved_at_20[0x10];
6362 u8 reserved_at_40[0x18];
6365 u8 reserved_at_60[0x20];
6368 struct mlx5_ifc_destroy_dct_out_bits {
6370 u8 reserved_at_8[0x18];
6374 u8 reserved_at_40[0x40];
6377 struct mlx5_ifc_destroy_dct_in_bits {
6379 u8 reserved_at_10[0x10];
6381 u8 reserved_at_20[0x10];
6384 u8 reserved_at_40[0x8];
6387 u8 reserved_at_60[0x20];
6390 struct mlx5_ifc_destroy_cq_out_bits {
6392 u8 reserved_at_8[0x18];
6396 u8 reserved_at_40[0x40];
6399 struct mlx5_ifc_destroy_cq_in_bits {
6401 u8 reserved_at_10[0x10];
6403 u8 reserved_at_20[0x10];
6406 u8 reserved_at_40[0x8];
6409 u8 reserved_at_60[0x20];
6412 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6414 u8 reserved_at_8[0x18];
6418 u8 reserved_at_40[0x40];
6421 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6423 u8 reserved_at_10[0x10];
6425 u8 reserved_at_20[0x10];
6428 u8 reserved_at_40[0x20];
6430 u8 reserved_at_60[0x10];
6431 u8 vxlan_udp_port[0x10];
6434 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6436 u8 reserved_at_8[0x18];
6440 u8 reserved_at_40[0x40];
6443 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6445 u8 reserved_at_10[0x10];
6447 u8 reserved_at_20[0x10];
6450 u8 reserved_at_40[0x60];
6452 u8 reserved_at_a0[0x8];
6453 u8 table_index[0x18];
6455 u8 reserved_at_c0[0x140];
6458 struct mlx5_ifc_delete_fte_out_bits {
6460 u8 reserved_at_8[0x18];
6464 u8 reserved_at_40[0x40];
6467 struct mlx5_ifc_delete_fte_in_bits {
6469 u8 reserved_at_10[0x10];
6471 u8 reserved_at_20[0x10];
6474 u8 other_vport[0x1];
6475 u8 reserved_at_41[0xf];
6476 u8 vport_number[0x10];
6478 u8 reserved_at_60[0x20];
6481 u8 reserved_at_88[0x18];
6483 u8 reserved_at_a0[0x8];
6486 u8 reserved_at_c0[0x40];
6488 u8 flow_index[0x20];
6490 u8 reserved_at_120[0xe0];
6493 struct mlx5_ifc_dealloc_xrcd_out_bits {
6495 u8 reserved_at_8[0x18];
6499 u8 reserved_at_40[0x40];
6502 struct mlx5_ifc_dealloc_xrcd_in_bits {
6504 u8 reserved_at_10[0x10];
6506 u8 reserved_at_20[0x10];
6509 u8 reserved_at_40[0x8];
6512 u8 reserved_at_60[0x20];
6515 struct mlx5_ifc_dealloc_uar_out_bits {
6517 u8 reserved_at_8[0x18];
6521 u8 reserved_at_40[0x40];
6524 struct mlx5_ifc_dealloc_uar_in_bits {
6526 u8 reserved_at_10[0x10];
6528 u8 reserved_at_20[0x10];
6531 u8 reserved_at_40[0x8];
6534 u8 reserved_at_60[0x20];
6537 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6539 u8 reserved_at_8[0x18];
6543 u8 reserved_at_40[0x40];
6546 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6548 u8 reserved_at_10[0x10];
6550 u8 reserved_at_20[0x10];
6553 u8 reserved_at_40[0x8];
6554 u8 transport_domain[0x18];
6556 u8 reserved_at_60[0x20];
6559 struct mlx5_ifc_dealloc_q_counter_out_bits {
6561 u8 reserved_at_8[0x18];
6565 u8 reserved_at_40[0x40];
6568 struct mlx5_ifc_dealloc_q_counter_in_bits {
6570 u8 reserved_at_10[0x10];
6572 u8 reserved_at_20[0x10];
6575 u8 reserved_at_40[0x18];
6576 u8 counter_set_id[0x8];
6578 u8 reserved_at_60[0x20];
6581 struct mlx5_ifc_dealloc_pd_out_bits {
6583 u8 reserved_at_8[0x18];
6587 u8 reserved_at_40[0x40];
6590 struct mlx5_ifc_dealloc_pd_in_bits {
6592 u8 reserved_at_10[0x10];
6594 u8 reserved_at_20[0x10];
6597 u8 reserved_at_40[0x8];
6600 u8 reserved_at_60[0x20];
6603 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6605 u8 reserved_at_8[0x18];
6609 u8 reserved_at_40[0x40];
6612 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6614 u8 reserved_at_10[0x10];
6616 u8 reserved_at_20[0x10];
6619 u8 flow_counter_id[0x20];
6621 u8 reserved_at_60[0x20];
6624 struct mlx5_ifc_create_xrq_out_bits {
6626 u8 reserved_at_8[0x18];
6630 u8 reserved_at_40[0x8];
6633 u8 reserved_at_60[0x20];
6636 struct mlx5_ifc_create_xrq_in_bits {
6638 u8 reserved_at_10[0x10];
6640 u8 reserved_at_20[0x10];
6643 u8 reserved_at_40[0x40];
6645 struct mlx5_ifc_xrqc_bits xrq_context;
6648 struct mlx5_ifc_create_xrc_srq_out_bits {
6650 u8 reserved_at_8[0x18];
6654 u8 reserved_at_40[0x8];
6657 u8 reserved_at_60[0x20];
6660 struct mlx5_ifc_create_xrc_srq_in_bits {
6662 u8 reserved_at_10[0x10];
6664 u8 reserved_at_20[0x10];
6667 u8 reserved_at_40[0x40];
6669 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6671 u8 reserved_at_280[0x600];
6676 struct mlx5_ifc_create_tis_out_bits {
6678 u8 reserved_at_8[0x18];
6682 u8 reserved_at_40[0x8];
6685 u8 reserved_at_60[0x20];
6688 struct mlx5_ifc_create_tis_in_bits {
6690 u8 reserved_at_10[0x10];
6692 u8 reserved_at_20[0x10];
6695 u8 reserved_at_40[0xc0];
6697 struct mlx5_ifc_tisc_bits ctx;
6700 struct mlx5_ifc_create_tir_out_bits {
6702 u8 reserved_at_8[0x18];
6706 u8 reserved_at_40[0x8];
6709 u8 reserved_at_60[0x20];
6712 struct mlx5_ifc_create_tir_in_bits {
6714 u8 reserved_at_10[0x10];
6716 u8 reserved_at_20[0x10];
6719 u8 reserved_at_40[0xc0];
6721 struct mlx5_ifc_tirc_bits ctx;
6724 struct mlx5_ifc_create_srq_out_bits {
6726 u8 reserved_at_8[0x18];
6730 u8 reserved_at_40[0x8];
6733 u8 reserved_at_60[0x20];
6736 struct mlx5_ifc_create_srq_in_bits {
6738 u8 reserved_at_10[0x10];
6740 u8 reserved_at_20[0x10];
6743 u8 reserved_at_40[0x40];
6745 struct mlx5_ifc_srqc_bits srq_context_entry;
6747 u8 reserved_at_280[0x600];
6752 struct mlx5_ifc_create_sq_out_bits {
6754 u8 reserved_at_8[0x18];
6758 u8 reserved_at_40[0x8];
6761 u8 reserved_at_60[0x20];
6764 struct mlx5_ifc_create_sq_in_bits {
6766 u8 reserved_at_10[0x10];
6768 u8 reserved_at_20[0x10];
6771 u8 reserved_at_40[0xc0];
6773 struct mlx5_ifc_sqc_bits ctx;
6776 struct mlx5_ifc_create_scheduling_element_out_bits {
6778 u8 reserved_at_8[0x18];
6782 u8 reserved_at_40[0x40];
6784 u8 scheduling_element_id[0x20];
6786 u8 reserved_at_a0[0x160];
6789 struct mlx5_ifc_create_scheduling_element_in_bits {
6791 u8 reserved_at_10[0x10];
6793 u8 reserved_at_20[0x10];
6796 u8 scheduling_hierarchy[0x8];
6797 u8 reserved_at_48[0x18];
6799 u8 reserved_at_60[0xa0];
6801 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6803 u8 reserved_at_300[0x100];
6806 struct mlx5_ifc_create_rqt_out_bits {
6808 u8 reserved_at_8[0x18];
6812 u8 reserved_at_40[0x8];
6815 u8 reserved_at_60[0x20];
6818 struct mlx5_ifc_create_rqt_in_bits {
6820 u8 reserved_at_10[0x10];
6822 u8 reserved_at_20[0x10];
6825 u8 reserved_at_40[0xc0];
6827 struct mlx5_ifc_rqtc_bits rqt_context;
6830 struct mlx5_ifc_create_rq_out_bits {
6832 u8 reserved_at_8[0x18];
6836 u8 reserved_at_40[0x8];
6839 u8 reserved_at_60[0x20];
6842 struct mlx5_ifc_create_rq_in_bits {
6844 u8 reserved_at_10[0x10];
6846 u8 reserved_at_20[0x10];
6849 u8 reserved_at_40[0xc0];
6851 struct mlx5_ifc_rqc_bits ctx;
6854 struct mlx5_ifc_create_rmp_out_bits {
6856 u8 reserved_at_8[0x18];
6860 u8 reserved_at_40[0x8];
6863 u8 reserved_at_60[0x20];
6866 struct mlx5_ifc_create_rmp_in_bits {
6868 u8 reserved_at_10[0x10];
6870 u8 reserved_at_20[0x10];
6873 u8 reserved_at_40[0xc0];
6875 struct mlx5_ifc_rmpc_bits ctx;
6878 struct mlx5_ifc_create_qp_out_bits {
6880 u8 reserved_at_8[0x18];
6884 u8 reserved_at_40[0x8];
6887 u8 reserved_at_60[0x20];
6890 struct mlx5_ifc_create_qp_in_bits {
6892 u8 reserved_at_10[0x10];
6894 u8 reserved_at_20[0x10];
6897 u8 reserved_at_40[0x40];
6899 u8 opt_param_mask[0x20];
6901 u8 reserved_at_a0[0x20];
6903 struct mlx5_ifc_qpc_bits qpc;
6905 u8 reserved_at_800[0x80];
6910 struct mlx5_ifc_create_psv_out_bits {
6912 u8 reserved_at_8[0x18];
6916 u8 reserved_at_40[0x40];
6918 u8 reserved_at_80[0x8];
6919 u8 psv0_index[0x18];
6921 u8 reserved_at_a0[0x8];
6922 u8 psv1_index[0x18];
6924 u8 reserved_at_c0[0x8];
6925 u8 psv2_index[0x18];
6927 u8 reserved_at_e0[0x8];
6928 u8 psv3_index[0x18];
6931 struct mlx5_ifc_create_psv_in_bits {
6933 u8 reserved_at_10[0x10];
6935 u8 reserved_at_20[0x10];
6939 u8 reserved_at_44[0x4];
6942 u8 reserved_at_60[0x20];
6945 struct mlx5_ifc_create_mkey_out_bits {
6947 u8 reserved_at_8[0x18];
6951 u8 reserved_at_40[0x8];
6952 u8 mkey_index[0x18];
6954 u8 reserved_at_60[0x20];
6957 struct mlx5_ifc_create_mkey_in_bits {
6959 u8 reserved_at_10[0x10];
6961 u8 reserved_at_20[0x10];
6964 u8 reserved_at_40[0x20];
6967 u8 reserved_at_61[0x1f];
6969 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6971 u8 reserved_at_280[0x80];
6973 u8 translations_octword_actual_size[0x20];
6975 u8 reserved_at_320[0x560];
6977 u8 klm_pas_mtt[0][0x20];
6980 struct mlx5_ifc_create_flow_table_out_bits {
6982 u8 reserved_at_8[0x18];
6986 u8 reserved_at_40[0x8];
6989 u8 reserved_at_60[0x20];
6992 struct mlx5_ifc_flow_table_context_bits {
6995 u8 reserved_at_2[0x2];
6996 u8 table_miss_action[0x4];
6998 u8 reserved_at_10[0x8];
7001 u8 reserved_at_20[0x8];
7002 u8 table_miss_id[0x18];
7004 u8 reserved_at_40[0x8];
7005 u8 lag_master_next_table_id[0x18];
7007 u8 reserved_at_60[0xe0];
7010 struct mlx5_ifc_create_flow_table_in_bits {
7012 u8 reserved_at_10[0x10];
7014 u8 reserved_at_20[0x10];
7017 u8 other_vport[0x1];
7018 u8 reserved_at_41[0xf];
7019 u8 vport_number[0x10];
7021 u8 reserved_at_60[0x20];
7024 u8 reserved_at_88[0x18];
7026 u8 reserved_at_a0[0x20];
7028 struct mlx5_ifc_flow_table_context_bits flow_table_context;
7031 struct mlx5_ifc_create_flow_group_out_bits {
7033 u8 reserved_at_8[0x18];
7037 u8 reserved_at_40[0x8];
7040 u8 reserved_at_60[0x20];
7044 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7045 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7046 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7047 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7050 struct mlx5_ifc_create_flow_group_in_bits {
7052 u8 reserved_at_10[0x10];
7054 u8 reserved_at_20[0x10];
7057 u8 other_vport[0x1];
7058 u8 reserved_at_41[0xf];
7059 u8 vport_number[0x10];
7061 u8 reserved_at_60[0x20];
7064 u8 reserved_at_88[0x18];
7066 u8 reserved_at_a0[0x8];
7069 u8 source_eswitch_owner_vhca_id_valid[0x1];
7071 u8 reserved_at_c1[0x1f];
7073 u8 start_flow_index[0x20];
7075 u8 reserved_at_100[0x20];
7077 u8 end_flow_index[0x20];
7079 u8 reserved_at_140[0xa0];
7081 u8 reserved_at_1e0[0x18];
7082 u8 match_criteria_enable[0x8];
7084 struct mlx5_ifc_fte_match_param_bits match_criteria;
7086 u8 reserved_at_1200[0xe00];
7089 struct mlx5_ifc_create_eq_out_bits {
7091 u8 reserved_at_8[0x18];
7095 u8 reserved_at_40[0x18];
7098 u8 reserved_at_60[0x20];
7101 struct mlx5_ifc_create_eq_in_bits {
7103 u8 reserved_at_10[0x10];
7105 u8 reserved_at_20[0x10];
7108 u8 reserved_at_40[0x40];
7110 struct mlx5_ifc_eqc_bits eq_context_entry;
7112 u8 reserved_at_280[0x40];
7114 u8 event_bitmask[0x40];
7116 u8 reserved_at_300[0x580];
7121 struct mlx5_ifc_create_dct_out_bits {
7123 u8 reserved_at_8[0x18];
7127 u8 reserved_at_40[0x8];
7130 u8 reserved_at_60[0x20];
7133 struct mlx5_ifc_create_dct_in_bits {
7135 u8 reserved_at_10[0x10];
7137 u8 reserved_at_20[0x10];
7140 u8 reserved_at_40[0x40];
7142 struct mlx5_ifc_dctc_bits dct_context_entry;
7144 u8 reserved_at_280[0x180];
7147 struct mlx5_ifc_create_cq_out_bits {
7149 u8 reserved_at_8[0x18];
7153 u8 reserved_at_40[0x8];
7156 u8 reserved_at_60[0x20];
7159 struct mlx5_ifc_create_cq_in_bits {
7161 u8 reserved_at_10[0x10];
7163 u8 reserved_at_20[0x10];
7166 u8 reserved_at_40[0x40];
7168 struct mlx5_ifc_cqc_bits cq_context;
7170 u8 reserved_at_280[0x600];
7175 struct mlx5_ifc_config_int_moderation_out_bits {
7177 u8 reserved_at_8[0x18];
7181 u8 reserved_at_40[0x4];
7183 u8 int_vector[0x10];
7185 u8 reserved_at_60[0x20];
7189 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7190 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7193 struct mlx5_ifc_config_int_moderation_in_bits {
7195 u8 reserved_at_10[0x10];
7197 u8 reserved_at_20[0x10];
7200 u8 reserved_at_40[0x4];
7202 u8 int_vector[0x10];
7204 u8 reserved_at_60[0x20];
7207 struct mlx5_ifc_attach_to_mcg_out_bits {
7209 u8 reserved_at_8[0x18];
7213 u8 reserved_at_40[0x40];
7216 struct mlx5_ifc_attach_to_mcg_in_bits {
7218 u8 reserved_at_10[0x10];
7220 u8 reserved_at_20[0x10];
7223 u8 reserved_at_40[0x8];
7226 u8 reserved_at_60[0x20];
7228 u8 multicast_gid[16][0x8];
7231 struct mlx5_ifc_arm_xrq_out_bits {
7233 u8 reserved_at_8[0x18];
7237 u8 reserved_at_40[0x40];
7240 struct mlx5_ifc_arm_xrq_in_bits {
7242 u8 reserved_at_10[0x10];
7244 u8 reserved_at_20[0x10];
7247 u8 reserved_at_40[0x8];
7250 u8 reserved_at_60[0x10];
7254 struct mlx5_ifc_arm_xrc_srq_out_bits {
7256 u8 reserved_at_8[0x18];
7260 u8 reserved_at_40[0x40];
7264 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7267 struct mlx5_ifc_arm_xrc_srq_in_bits {
7269 u8 reserved_at_10[0x10];
7271 u8 reserved_at_20[0x10];
7274 u8 reserved_at_40[0x8];
7277 u8 reserved_at_60[0x10];
7281 struct mlx5_ifc_arm_rq_out_bits {
7283 u8 reserved_at_8[0x18];
7287 u8 reserved_at_40[0x40];
7291 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7292 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7295 struct mlx5_ifc_arm_rq_in_bits {
7297 u8 reserved_at_10[0x10];
7299 u8 reserved_at_20[0x10];
7302 u8 reserved_at_40[0x8];
7303 u8 srq_number[0x18];
7305 u8 reserved_at_60[0x10];
7309 struct mlx5_ifc_arm_dct_out_bits {
7311 u8 reserved_at_8[0x18];
7315 u8 reserved_at_40[0x40];
7318 struct mlx5_ifc_arm_dct_in_bits {
7320 u8 reserved_at_10[0x10];
7322 u8 reserved_at_20[0x10];
7325 u8 reserved_at_40[0x8];
7326 u8 dct_number[0x18];
7328 u8 reserved_at_60[0x20];
7331 struct mlx5_ifc_alloc_xrcd_out_bits {
7333 u8 reserved_at_8[0x18];
7337 u8 reserved_at_40[0x8];
7340 u8 reserved_at_60[0x20];
7343 struct mlx5_ifc_alloc_xrcd_in_bits {
7345 u8 reserved_at_10[0x10];
7347 u8 reserved_at_20[0x10];
7350 u8 reserved_at_40[0x40];
7353 struct mlx5_ifc_alloc_uar_out_bits {
7355 u8 reserved_at_8[0x18];
7359 u8 reserved_at_40[0x8];
7362 u8 reserved_at_60[0x20];
7365 struct mlx5_ifc_alloc_uar_in_bits {
7367 u8 reserved_at_10[0x10];
7369 u8 reserved_at_20[0x10];
7372 u8 reserved_at_40[0x40];
7375 struct mlx5_ifc_alloc_transport_domain_out_bits {
7377 u8 reserved_at_8[0x18];
7381 u8 reserved_at_40[0x8];
7382 u8 transport_domain[0x18];
7384 u8 reserved_at_60[0x20];
7387 struct mlx5_ifc_alloc_transport_domain_in_bits {
7389 u8 reserved_at_10[0x10];
7391 u8 reserved_at_20[0x10];
7394 u8 reserved_at_40[0x40];
7397 struct mlx5_ifc_alloc_q_counter_out_bits {
7399 u8 reserved_at_8[0x18];
7403 u8 reserved_at_40[0x18];
7404 u8 counter_set_id[0x8];
7406 u8 reserved_at_60[0x20];
7409 struct mlx5_ifc_alloc_q_counter_in_bits {
7411 u8 reserved_at_10[0x10];
7413 u8 reserved_at_20[0x10];
7416 u8 reserved_at_40[0x40];
7419 struct mlx5_ifc_alloc_pd_out_bits {
7421 u8 reserved_at_8[0x18];
7425 u8 reserved_at_40[0x8];
7428 u8 reserved_at_60[0x20];
7431 struct mlx5_ifc_alloc_pd_in_bits {
7433 u8 reserved_at_10[0x10];
7435 u8 reserved_at_20[0x10];
7438 u8 reserved_at_40[0x40];
7441 struct mlx5_ifc_alloc_flow_counter_out_bits {
7443 u8 reserved_at_8[0x18];
7447 u8 flow_counter_id[0x20];
7449 u8 reserved_at_60[0x20];
7452 struct mlx5_ifc_alloc_flow_counter_in_bits {
7454 u8 reserved_at_10[0x10];
7456 u8 reserved_at_20[0x10];
7459 u8 reserved_at_40[0x40];
7462 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7464 u8 reserved_at_8[0x18];
7468 u8 reserved_at_40[0x40];
7471 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7473 u8 reserved_at_10[0x10];
7475 u8 reserved_at_20[0x10];
7478 u8 reserved_at_40[0x20];
7480 u8 reserved_at_60[0x10];
7481 u8 vxlan_udp_port[0x10];
7484 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7486 u8 reserved_at_8[0x18];
7490 u8 reserved_at_40[0x40];
7493 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7495 u8 reserved_at_10[0x10];
7497 u8 reserved_at_20[0x10];
7500 u8 reserved_at_40[0x10];
7501 u8 rate_limit_index[0x10];
7503 u8 reserved_at_60[0x20];
7505 u8 rate_limit[0x20];
7507 u8 burst_upper_bound[0x20];
7509 u8 reserved_at_c0[0x10];
7510 u8 typical_packet_size[0x10];
7512 u8 reserved_at_e0[0x120];
7515 struct mlx5_ifc_access_register_out_bits {
7517 u8 reserved_at_8[0x18];
7521 u8 reserved_at_40[0x40];
7523 u8 register_data[0][0x20];
7527 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7528 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7531 struct mlx5_ifc_access_register_in_bits {
7533 u8 reserved_at_10[0x10];
7535 u8 reserved_at_20[0x10];
7538 u8 reserved_at_40[0x10];
7539 u8 register_id[0x10];
7543 u8 register_data[0][0x20];
7546 struct mlx5_ifc_sltp_reg_bits {
7551 u8 reserved_at_12[0x2];
7553 u8 reserved_at_18[0x8];
7555 u8 reserved_at_20[0x20];
7557 u8 reserved_at_40[0x7];
7563 u8 reserved_at_60[0xc];
7564 u8 ob_preemp_mode[0x4];
7568 u8 reserved_at_80[0x20];
7571 struct mlx5_ifc_slrg_reg_bits {
7576 u8 reserved_at_12[0x2];
7578 u8 reserved_at_18[0x8];
7580 u8 time_to_link_up[0x10];
7581 u8 reserved_at_30[0xc];
7582 u8 grade_lane_speed[0x4];
7584 u8 grade_version[0x8];
7587 u8 reserved_at_60[0x4];
7588 u8 height_grade_type[0x4];
7589 u8 height_grade[0x18];
7594 u8 reserved_at_a0[0x10];
7595 u8 height_sigma[0x10];
7597 u8 reserved_at_c0[0x20];
7599 u8 reserved_at_e0[0x4];
7600 u8 phase_grade_type[0x4];
7601 u8 phase_grade[0x18];
7603 u8 reserved_at_100[0x8];
7604 u8 phase_eo_pos[0x8];
7605 u8 reserved_at_110[0x8];
7606 u8 phase_eo_neg[0x8];
7608 u8 ffe_set_tested[0x10];
7609 u8 test_errors_per_lane[0x10];
7612 struct mlx5_ifc_pvlc_reg_bits {
7613 u8 reserved_at_0[0x8];
7615 u8 reserved_at_10[0x10];
7617 u8 reserved_at_20[0x1c];
7620 u8 reserved_at_40[0x1c];
7623 u8 reserved_at_60[0x1c];
7624 u8 vl_operational[0x4];
7627 struct mlx5_ifc_pude_reg_bits {
7630 u8 reserved_at_10[0x4];
7631 u8 admin_status[0x4];
7632 u8 reserved_at_18[0x4];
7633 u8 oper_status[0x4];
7635 u8 reserved_at_20[0x60];
7638 struct mlx5_ifc_ptys_reg_bits {
7639 u8 reserved_at_0[0x1];
7640 u8 an_disable_admin[0x1];
7641 u8 an_disable_cap[0x1];
7642 u8 reserved_at_3[0x5];
7644 u8 reserved_at_10[0xd];
7648 u8 reserved_at_24[0x3c];
7650 u8 eth_proto_capability[0x20];
7652 u8 ib_link_width_capability[0x10];
7653 u8 ib_proto_capability[0x10];
7655 u8 reserved_at_a0[0x20];
7657 u8 eth_proto_admin[0x20];
7659 u8 ib_link_width_admin[0x10];
7660 u8 ib_proto_admin[0x10];
7662 u8 reserved_at_100[0x20];
7664 u8 eth_proto_oper[0x20];
7666 u8 ib_link_width_oper[0x10];
7667 u8 ib_proto_oper[0x10];
7669 u8 reserved_at_160[0x1c];
7670 u8 connector_type[0x4];
7672 u8 eth_proto_lp_advertise[0x20];
7674 u8 reserved_at_1a0[0x60];
7677 struct mlx5_ifc_mlcr_reg_bits {
7678 u8 reserved_at_0[0x8];
7680 u8 reserved_at_10[0x20];
7682 u8 beacon_duration[0x10];
7683 u8 reserved_at_40[0x10];
7685 u8 beacon_remain[0x10];
7688 struct mlx5_ifc_ptas_reg_bits {
7689 u8 reserved_at_0[0x20];
7691 u8 algorithm_options[0x10];
7692 u8 reserved_at_30[0x4];
7693 u8 repetitions_mode[0x4];
7694 u8 num_of_repetitions[0x8];
7696 u8 grade_version[0x8];
7697 u8 height_grade_type[0x4];
7698 u8 phase_grade_type[0x4];
7699 u8 height_grade_weight[0x8];
7700 u8 phase_grade_weight[0x8];
7702 u8 gisim_measure_bits[0x10];
7703 u8 adaptive_tap_measure_bits[0x10];
7705 u8 ber_bath_high_error_threshold[0x10];
7706 u8 ber_bath_mid_error_threshold[0x10];
7708 u8 ber_bath_low_error_threshold[0x10];
7709 u8 one_ratio_high_threshold[0x10];
7711 u8 one_ratio_high_mid_threshold[0x10];
7712 u8 one_ratio_low_mid_threshold[0x10];
7714 u8 one_ratio_low_threshold[0x10];
7715 u8 ndeo_error_threshold[0x10];
7717 u8 mixer_offset_step_size[0x10];
7718 u8 reserved_at_110[0x8];
7719 u8 mix90_phase_for_voltage_bath[0x8];
7721 u8 mixer_offset_start[0x10];
7722 u8 mixer_offset_end[0x10];
7724 u8 reserved_at_140[0x15];
7725 u8 ber_test_time[0xb];
7728 struct mlx5_ifc_pspa_reg_bits {
7732 u8 reserved_at_18[0x8];
7734 u8 reserved_at_20[0x20];
7737 struct mlx5_ifc_pqdr_reg_bits {
7738 u8 reserved_at_0[0x8];
7740 u8 reserved_at_10[0x5];
7742 u8 reserved_at_18[0x6];
7745 u8 reserved_at_20[0x20];
7747 u8 reserved_at_40[0x10];
7748 u8 min_threshold[0x10];
7750 u8 reserved_at_60[0x10];
7751 u8 max_threshold[0x10];
7753 u8 reserved_at_80[0x10];
7754 u8 mark_probability_denominator[0x10];
7756 u8 reserved_at_a0[0x60];
7759 struct mlx5_ifc_ppsc_reg_bits {
7760 u8 reserved_at_0[0x8];
7762 u8 reserved_at_10[0x10];
7764 u8 reserved_at_20[0x60];
7766 u8 reserved_at_80[0x1c];
7769 u8 reserved_at_a0[0x1c];
7770 u8 wrps_status[0x4];
7772 u8 reserved_at_c0[0x8];
7773 u8 up_threshold[0x8];
7774 u8 reserved_at_d0[0x8];
7775 u8 down_threshold[0x8];
7777 u8 reserved_at_e0[0x20];
7779 u8 reserved_at_100[0x1c];
7782 u8 reserved_at_120[0x1c];
7783 u8 srps_status[0x4];
7785 u8 reserved_at_140[0x40];
7788 struct mlx5_ifc_pplr_reg_bits {
7789 u8 reserved_at_0[0x8];
7791 u8 reserved_at_10[0x10];
7793 u8 reserved_at_20[0x8];
7795 u8 reserved_at_30[0x8];
7799 struct mlx5_ifc_pplm_reg_bits {
7800 u8 reserved_at_0[0x8];
7802 u8 reserved_at_10[0x10];
7804 u8 reserved_at_20[0x20];
7806 u8 port_profile_mode[0x8];
7807 u8 static_port_profile[0x8];
7808 u8 active_port_profile[0x8];
7809 u8 reserved_at_58[0x8];
7811 u8 retransmission_active[0x8];
7812 u8 fec_mode_active[0x18];
7814 u8 reserved_at_80[0x20];
7817 struct mlx5_ifc_ppcnt_reg_bits {
7821 u8 reserved_at_12[0x8];
7825 u8 reserved_at_21[0x1c];
7828 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7831 struct mlx5_ifc_mpcnt_reg_bits {
7832 u8 reserved_at_0[0x8];
7834 u8 reserved_at_10[0xa];
7838 u8 reserved_at_21[0x1f];
7840 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7843 struct mlx5_ifc_ppad_reg_bits {
7844 u8 reserved_at_0[0x3];
7846 u8 reserved_at_4[0x4];
7852 u8 reserved_at_40[0x40];
7855 struct mlx5_ifc_pmtu_reg_bits {
7856 u8 reserved_at_0[0x8];
7858 u8 reserved_at_10[0x10];
7861 u8 reserved_at_30[0x10];
7864 u8 reserved_at_50[0x10];
7867 u8 reserved_at_70[0x10];
7870 struct mlx5_ifc_pmpr_reg_bits {
7871 u8 reserved_at_0[0x8];
7873 u8 reserved_at_10[0x10];
7875 u8 reserved_at_20[0x18];
7876 u8 attenuation_5g[0x8];
7878 u8 reserved_at_40[0x18];
7879 u8 attenuation_7g[0x8];
7881 u8 reserved_at_60[0x18];
7882 u8 attenuation_12g[0x8];
7885 struct mlx5_ifc_pmpe_reg_bits {
7886 u8 reserved_at_0[0x8];
7888 u8 reserved_at_10[0xc];
7889 u8 module_status[0x4];
7891 u8 reserved_at_20[0x60];
7894 struct mlx5_ifc_pmpc_reg_bits {
7895 u8 module_state_updated[32][0x8];
7898 struct mlx5_ifc_pmlpn_reg_bits {
7899 u8 reserved_at_0[0x4];
7900 u8 mlpn_status[0x4];
7902 u8 reserved_at_10[0x10];
7905 u8 reserved_at_21[0x1f];
7908 struct mlx5_ifc_pmlp_reg_bits {
7910 u8 reserved_at_1[0x7];
7912 u8 reserved_at_10[0x8];
7915 u8 lane0_module_mapping[0x20];
7917 u8 lane1_module_mapping[0x20];
7919 u8 lane2_module_mapping[0x20];
7921 u8 lane3_module_mapping[0x20];
7923 u8 reserved_at_a0[0x160];
7926 struct mlx5_ifc_pmaos_reg_bits {
7927 u8 reserved_at_0[0x8];
7929 u8 reserved_at_10[0x4];
7930 u8 admin_status[0x4];
7931 u8 reserved_at_18[0x4];
7932 u8 oper_status[0x4];
7936 u8 reserved_at_22[0x1c];
7939 u8 reserved_at_40[0x40];
7942 struct mlx5_ifc_plpc_reg_bits {
7943 u8 reserved_at_0[0x4];
7945 u8 reserved_at_10[0x4];
7947 u8 reserved_at_18[0x8];
7949 u8 reserved_at_20[0x10];
7950 u8 lane_speed[0x10];
7952 u8 reserved_at_40[0x17];
7954 u8 fec_mode_policy[0x8];
7956 u8 retransmission_capability[0x8];
7957 u8 fec_mode_capability[0x18];
7959 u8 retransmission_support_admin[0x8];
7960 u8 fec_mode_support_admin[0x18];
7962 u8 retransmission_request_admin[0x8];
7963 u8 fec_mode_request_admin[0x18];
7965 u8 reserved_at_c0[0x80];
7968 struct mlx5_ifc_plib_reg_bits {
7969 u8 reserved_at_0[0x8];
7971 u8 reserved_at_10[0x8];
7974 u8 reserved_at_20[0x60];
7977 struct mlx5_ifc_plbf_reg_bits {
7978 u8 reserved_at_0[0x8];
7980 u8 reserved_at_10[0xd];
7983 u8 reserved_at_20[0x20];
7986 struct mlx5_ifc_pipg_reg_bits {
7987 u8 reserved_at_0[0x8];
7989 u8 reserved_at_10[0x10];
7992 u8 reserved_at_21[0x19];
7994 u8 reserved_at_3e[0x2];
7997 struct mlx5_ifc_pifr_reg_bits {
7998 u8 reserved_at_0[0x8];
8000 u8 reserved_at_10[0x10];
8002 u8 reserved_at_20[0xe0];
8004 u8 port_filter[8][0x20];
8006 u8 port_filter_update_en[8][0x20];
8009 struct mlx5_ifc_pfcc_reg_bits {
8010 u8 reserved_at_0[0x8];
8012 u8 reserved_at_10[0xb];
8013 u8 ppan_mask_n[0x1];
8014 u8 minor_stall_mask[0x1];
8015 u8 critical_stall_mask[0x1];
8016 u8 reserved_at_1e[0x2];
8019 u8 reserved_at_24[0x4];
8020 u8 prio_mask_tx[0x8];
8021 u8 reserved_at_30[0x8];
8022 u8 prio_mask_rx[0x8];
8026 u8 pptx_mask_n[0x1];
8027 u8 reserved_at_43[0x5];
8029 u8 reserved_at_50[0x10];
8033 u8 pprx_mask_n[0x1];
8034 u8 reserved_at_63[0x5];
8036 u8 reserved_at_70[0x10];
8038 u8 device_stall_minor_watermark[0x10];
8039 u8 device_stall_critical_watermark[0x10];
8041 u8 reserved_at_a0[0x60];
8044 struct mlx5_ifc_pelc_reg_bits {
8046 u8 reserved_at_4[0x4];
8048 u8 reserved_at_10[0x10];
8051 u8 op_capability[0x8];
8057 u8 capability[0x40];
8063 u8 reserved_at_140[0x80];
8066 struct mlx5_ifc_peir_reg_bits {
8067 u8 reserved_at_0[0x8];
8069 u8 reserved_at_10[0x10];
8071 u8 reserved_at_20[0xc];
8072 u8 error_count[0x4];
8073 u8 reserved_at_30[0x10];
8075 u8 reserved_at_40[0xc];
8077 u8 reserved_at_50[0x8];
8081 struct mlx5_ifc_mpegc_reg_bits {
8082 u8 reserved_at_0[0x30];
8083 u8 field_select[0x10];
8085 u8 tx_overflow_sense[0x1];
8088 u8 reserved_at_43[0x1b];
8089 u8 tx_lossy_overflow_oper[0x2];
8091 u8 reserved_at_60[0x100];
8094 struct mlx5_ifc_pcam_enhanced_features_bits {
8095 u8 reserved_at_0[0x6d];
8096 u8 rx_icrc_encapsulated_counter[0x1];
8097 u8 reserved_at_6e[0x8];
8099 u8 reserved_at_77[0x4];
8100 u8 rx_buffer_fullness_counters[0x1];
8101 u8 ptys_connector_type[0x1];
8102 u8 reserved_at_7d[0x1];
8103 u8 ppcnt_discard_group[0x1];
8104 u8 ppcnt_statistical_group[0x1];
8107 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8108 u8 port_access_reg_cap_mask_127_to_96[0x20];
8109 u8 port_access_reg_cap_mask_95_to_64[0x20];
8110 u8 port_access_reg_cap_mask_63_to_32[0x20];
8112 u8 port_access_reg_cap_mask_31_to_13[0x13];
8115 u8 port_access_reg_cap_mask_10_to_0[0xb];
8118 struct mlx5_ifc_pcam_reg_bits {
8119 u8 reserved_at_0[0x8];
8120 u8 feature_group[0x8];
8121 u8 reserved_at_10[0x8];
8122 u8 access_reg_group[0x8];
8124 u8 reserved_at_20[0x20];
8127 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8128 u8 reserved_at_0[0x80];
8129 } port_access_reg_cap_mask;
8131 u8 reserved_at_c0[0x80];
8134 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8135 u8 reserved_at_0[0x80];
8138 u8 reserved_at_1c0[0xc0];
8141 struct mlx5_ifc_mcam_enhanced_features_bits {
8142 u8 reserved_at_0[0x74];
8143 u8 mark_tx_action_cnp[0x1];
8144 u8 mark_tx_action_cqe[0x1];
8145 u8 dynamic_tx_overflow[0x1];
8146 u8 reserved_at_77[0x4];
8147 u8 pcie_outbound_stalled[0x1];
8148 u8 tx_overflow_buffer_pkt[0x1];
8149 u8 mtpps_enh_out_per_adj[0x1];
8151 u8 pcie_performance_group[0x1];
8154 struct mlx5_ifc_mcam_access_reg_bits {
8155 u8 reserved_at_0[0x1c];
8159 u8 reserved_at_1f[0x1];
8161 u8 regs_95_to_87[0x9];
8163 u8 regs_85_to_68[0x12];
8164 u8 tracer_registers[0x4];
8166 u8 regs_63_to_32[0x20];
8167 u8 regs_31_to_0[0x20];
8170 struct mlx5_ifc_mcam_reg_bits {
8171 u8 reserved_at_0[0x8];
8172 u8 feature_group[0x8];
8173 u8 reserved_at_10[0x8];
8174 u8 access_reg_group[0x8];
8176 u8 reserved_at_20[0x20];
8179 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8180 u8 reserved_at_0[0x80];
8181 } mng_access_reg_cap_mask;
8183 u8 reserved_at_c0[0x80];
8186 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8187 u8 reserved_at_0[0x80];
8188 } mng_feature_cap_mask;
8190 u8 reserved_at_1c0[0x80];
8193 struct mlx5_ifc_qcam_access_reg_cap_mask {
8194 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8196 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8200 u8 qcam_access_reg_cap_mask_0[0x1];
8203 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8204 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8205 u8 qpts_trust_both[0x1];
8208 struct mlx5_ifc_qcam_reg_bits {
8209 u8 reserved_at_0[0x8];
8210 u8 feature_group[0x8];
8211 u8 reserved_at_10[0x8];
8212 u8 access_reg_group[0x8];
8213 u8 reserved_at_20[0x20];
8216 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8217 u8 reserved_at_0[0x80];
8218 } qos_access_reg_cap_mask;
8220 u8 reserved_at_c0[0x80];
8223 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8224 u8 reserved_at_0[0x80];
8225 } qos_feature_cap_mask;
8227 u8 reserved_at_1c0[0x80];
8230 struct mlx5_ifc_pcap_reg_bits {
8231 u8 reserved_at_0[0x8];
8233 u8 reserved_at_10[0x10];
8235 u8 port_capability_mask[4][0x20];
8238 struct mlx5_ifc_paos_reg_bits {
8241 u8 reserved_at_10[0x4];
8242 u8 admin_status[0x4];
8243 u8 reserved_at_18[0x4];
8244 u8 oper_status[0x4];
8248 u8 reserved_at_22[0x1c];
8251 u8 reserved_at_40[0x40];
8254 struct mlx5_ifc_pamp_reg_bits {
8255 u8 reserved_at_0[0x8];
8256 u8 opamp_group[0x8];
8257 u8 reserved_at_10[0xc];
8258 u8 opamp_group_type[0x4];
8260 u8 start_index[0x10];
8261 u8 reserved_at_30[0x4];
8262 u8 num_of_indices[0xc];
8264 u8 index_data[18][0x10];
8267 struct mlx5_ifc_pcmr_reg_bits {
8268 u8 reserved_at_0[0x8];
8270 u8 reserved_at_10[0x2e];
8272 u8 reserved_at_3f[0x1f];
8274 u8 reserved_at_5f[0x1];
8277 struct mlx5_ifc_lane_2_module_mapping_bits {
8278 u8 reserved_at_0[0x6];
8280 u8 reserved_at_8[0x6];
8282 u8 reserved_at_10[0x8];
8286 struct mlx5_ifc_bufferx_reg_bits {
8287 u8 reserved_at_0[0x6];
8290 u8 reserved_at_8[0xc];
8293 u8 xoff_threshold[0x10];
8294 u8 xon_threshold[0x10];
8297 struct mlx5_ifc_set_node_in_bits {
8298 u8 node_description[64][0x8];
8301 struct mlx5_ifc_register_power_settings_bits {
8302 u8 reserved_at_0[0x18];
8303 u8 power_settings_level[0x8];
8305 u8 reserved_at_20[0x60];
8308 struct mlx5_ifc_register_host_endianness_bits {
8310 u8 reserved_at_1[0x1f];
8312 u8 reserved_at_20[0x60];
8315 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8316 u8 reserved_at_0[0x20];
8320 u8 addressh_63_32[0x20];
8322 u8 addressl_31_0[0x20];
8325 struct mlx5_ifc_ud_adrs_vector_bits {
8329 u8 reserved_at_41[0x7];
8330 u8 destination_qp_dct[0x18];
8332 u8 static_rate[0x4];
8333 u8 sl_eth_prio[0x4];
8336 u8 rlid_udp_sport[0x10];
8338 u8 reserved_at_80[0x20];
8340 u8 rmac_47_16[0x20];
8346 u8 reserved_at_e0[0x1];
8348 u8 reserved_at_e2[0x2];
8349 u8 src_addr_index[0x8];
8350 u8 flow_label[0x14];
8352 u8 rgid_rip[16][0x8];
8355 struct mlx5_ifc_pages_req_event_bits {
8356 u8 reserved_at_0[0x10];
8357 u8 function_id[0x10];
8361 u8 reserved_at_40[0xa0];
8364 struct mlx5_ifc_eqe_bits {
8365 u8 reserved_at_0[0x8];
8367 u8 reserved_at_10[0x8];
8368 u8 event_sub_type[0x8];
8370 u8 reserved_at_20[0xe0];
8372 union mlx5_ifc_event_auto_bits event_data;
8374 u8 reserved_at_1e0[0x10];
8376 u8 reserved_at_1f8[0x7];
8381 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8384 struct mlx5_ifc_cmd_queue_entry_bits {
8386 u8 reserved_at_8[0x18];
8388 u8 input_length[0x20];
8390 u8 input_mailbox_pointer_63_32[0x20];
8392 u8 input_mailbox_pointer_31_9[0x17];
8393 u8 reserved_at_77[0x9];
8395 u8 command_input_inline_data[16][0x8];
8397 u8 command_output_inline_data[16][0x8];
8399 u8 output_mailbox_pointer_63_32[0x20];
8401 u8 output_mailbox_pointer_31_9[0x17];
8402 u8 reserved_at_1b7[0x9];
8404 u8 output_length[0x20];
8408 u8 reserved_at_1f0[0x8];
8413 struct mlx5_ifc_cmd_out_bits {
8415 u8 reserved_at_8[0x18];
8419 u8 command_output[0x20];
8422 struct mlx5_ifc_cmd_in_bits {
8424 u8 reserved_at_10[0x10];
8426 u8 reserved_at_20[0x10];
8429 u8 command[0][0x20];
8432 struct mlx5_ifc_cmd_if_box_bits {
8433 u8 mailbox_data[512][0x8];
8435 u8 reserved_at_1000[0x180];
8437 u8 next_pointer_63_32[0x20];
8439 u8 next_pointer_31_10[0x16];
8440 u8 reserved_at_11b6[0xa];
8442 u8 block_number[0x20];
8444 u8 reserved_at_11e0[0x8];
8446 u8 ctrl_signature[0x8];
8450 struct mlx5_ifc_mtt_bits {
8451 u8 ptag_63_32[0x20];
8454 u8 reserved_at_38[0x6];
8459 struct mlx5_ifc_query_wol_rol_out_bits {
8461 u8 reserved_at_8[0x18];
8465 u8 reserved_at_40[0x10];
8469 u8 reserved_at_60[0x20];
8472 struct mlx5_ifc_query_wol_rol_in_bits {
8474 u8 reserved_at_10[0x10];
8476 u8 reserved_at_20[0x10];
8479 u8 reserved_at_40[0x40];
8482 struct mlx5_ifc_set_wol_rol_out_bits {
8484 u8 reserved_at_8[0x18];
8488 u8 reserved_at_40[0x40];
8491 struct mlx5_ifc_set_wol_rol_in_bits {
8493 u8 reserved_at_10[0x10];
8495 u8 reserved_at_20[0x10];
8498 u8 rol_mode_valid[0x1];
8499 u8 wol_mode_valid[0x1];
8500 u8 reserved_at_42[0xe];
8504 u8 reserved_at_60[0x20];
8508 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8509 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8510 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8514 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8515 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8516 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8520 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8521 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8522 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8523 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8524 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8525 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8526 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8527 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8528 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8529 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8530 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8533 struct mlx5_ifc_initial_seg_bits {
8534 u8 fw_rev_minor[0x10];
8535 u8 fw_rev_major[0x10];
8537 u8 cmd_interface_rev[0x10];
8538 u8 fw_rev_subminor[0x10];
8540 u8 reserved_at_40[0x40];
8542 u8 cmdq_phy_addr_63_32[0x20];
8544 u8 cmdq_phy_addr_31_12[0x14];
8545 u8 reserved_at_b4[0x2];
8546 u8 nic_interface[0x2];
8547 u8 log_cmdq_size[0x4];
8548 u8 log_cmdq_stride[0x4];
8550 u8 command_doorbell_vector[0x20];
8552 u8 reserved_at_e0[0xf00];
8554 u8 initializing[0x1];
8555 u8 reserved_at_fe1[0x4];
8556 u8 nic_interface_supported[0x3];
8557 u8 reserved_at_fe8[0x18];
8559 struct mlx5_ifc_health_buffer_bits health_buffer;
8561 u8 no_dram_nic_offset[0x20];
8563 u8 reserved_at_1220[0x6e40];
8565 u8 reserved_at_8060[0x1f];
8568 u8 health_syndrome[0x8];
8569 u8 health_counter[0x18];
8571 u8 reserved_at_80a0[0x17fc0];
8574 struct mlx5_ifc_mtpps_reg_bits {
8575 u8 reserved_at_0[0xc];
8576 u8 cap_number_of_pps_pins[0x4];
8577 u8 reserved_at_10[0x4];
8578 u8 cap_max_num_of_pps_in_pins[0x4];
8579 u8 reserved_at_18[0x4];
8580 u8 cap_max_num_of_pps_out_pins[0x4];
8582 u8 reserved_at_20[0x24];
8583 u8 cap_pin_3_mode[0x4];
8584 u8 reserved_at_48[0x4];
8585 u8 cap_pin_2_mode[0x4];
8586 u8 reserved_at_50[0x4];
8587 u8 cap_pin_1_mode[0x4];
8588 u8 reserved_at_58[0x4];
8589 u8 cap_pin_0_mode[0x4];
8591 u8 reserved_at_60[0x4];
8592 u8 cap_pin_7_mode[0x4];
8593 u8 reserved_at_68[0x4];
8594 u8 cap_pin_6_mode[0x4];
8595 u8 reserved_at_70[0x4];
8596 u8 cap_pin_5_mode[0x4];
8597 u8 reserved_at_78[0x4];
8598 u8 cap_pin_4_mode[0x4];
8600 u8 field_select[0x20];
8601 u8 reserved_at_a0[0x60];
8604 u8 reserved_at_101[0xb];
8606 u8 reserved_at_110[0x4];
8610 u8 reserved_at_120[0x20];
8612 u8 time_stamp[0x40];
8614 u8 out_pulse_duration[0x10];
8615 u8 out_periodic_adjustment[0x10];
8616 u8 enhanced_out_periodic_adjustment[0x20];
8618 u8 reserved_at_1c0[0x20];
8621 struct mlx5_ifc_mtppse_reg_bits {
8622 u8 reserved_at_0[0x18];
8625 u8 reserved_at_21[0x1b];
8626 u8 event_generation_mode[0x4];
8627 u8 reserved_at_40[0x40];
8630 struct mlx5_ifc_mcqi_cap_bits {
8631 u8 supported_info_bitmask[0x20];
8633 u8 component_size[0x20];
8635 u8 max_component_size[0x20];
8637 u8 log_mcda_word_size[0x4];
8638 u8 reserved_at_64[0xc];
8639 u8 mcda_max_write_size[0x10];
8642 u8 reserved_at_81[0x1];
8643 u8 match_chip_id[0x1];
8645 u8 check_user_timestamp[0x1];
8646 u8 match_base_guid_mac[0x1];
8647 u8 reserved_at_86[0x1a];
8650 struct mlx5_ifc_mcqi_reg_bits {
8651 u8 read_pending_component[0x1];
8652 u8 reserved_at_1[0xf];
8653 u8 component_index[0x10];
8655 u8 reserved_at_20[0x20];
8657 u8 reserved_at_40[0x1b];
8664 u8 reserved_at_a0[0x10];
8670 struct mlx5_ifc_mcc_reg_bits {
8671 u8 reserved_at_0[0x4];
8672 u8 time_elapsed_since_last_cmd[0xc];
8673 u8 reserved_at_10[0x8];
8674 u8 instruction[0x8];
8676 u8 reserved_at_20[0x10];
8677 u8 component_index[0x10];
8679 u8 reserved_at_40[0x8];
8680 u8 update_handle[0x18];
8682 u8 handle_owner_type[0x4];
8683 u8 handle_owner_host_id[0x4];
8684 u8 reserved_at_68[0x1];
8685 u8 control_progress[0x7];
8687 u8 reserved_at_78[0x4];
8688 u8 control_state[0x4];
8690 u8 component_size[0x20];
8692 u8 reserved_at_a0[0x60];
8695 struct mlx5_ifc_mcda_reg_bits {
8696 u8 reserved_at_0[0x8];
8697 u8 update_handle[0x18];
8701 u8 reserved_at_40[0x10];
8704 u8 reserved_at_60[0x20];
8709 union mlx5_ifc_ports_control_registers_document_bits {
8710 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8711 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8712 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8713 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8714 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8715 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8716 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8717 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8718 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8719 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8720 struct mlx5_ifc_paos_reg_bits paos_reg;
8721 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8722 struct mlx5_ifc_peir_reg_bits peir_reg;
8723 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8724 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8725 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8726 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8727 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8728 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8729 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8730 struct mlx5_ifc_plib_reg_bits plib_reg;
8731 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8732 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8733 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8734 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8735 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8736 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8737 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8738 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8739 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8740 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8741 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8742 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8743 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8744 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8745 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8746 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8747 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8748 struct mlx5_ifc_ptys_reg_bits ptys_reg;
8749 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8750 struct mlx5_ifc_pude_reg_bits pude_reg;
8751 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8752 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8753 struct mlx5_ifc_sltp_reg_bits sltp_reg;
8754 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8755 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8756 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8757 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8758 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8759 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8760 struct mlx5_ifc_mcc_reg_bits mcc_reg;
8761 struct mlx5_ifc_mcda_reg_bits mcda_reg;
8762 u8 reserved_at_0[0x60e0];
8765 union mlx5_ifc_debug_enhancements_document_bits {
8766 struct mlx5_ifc_health_buffer_bits health_buffer;
8767 u8 reserved_at_0[0x200];
8770 union mlx5_ifc_uplink_pci_interface_document_bits {
8771 struct mlx5_ifc_initial_seg_bits initial_seg;
8772 u8 reserved_at_0[0x20060];
8775 struct mlx5_ifc_set_flow_table_root_out_bits {
8777 u8 reserved_at_8[0x18];
8781 u8 reserved_at_40[0x40];
8784 struct mlx5_ifc_set_flow_table_root_in_bits {
8786 u8 reserved_at_10[0x10];
8788 u8 reserved_at_20[0x10];
8791 u8 other_vport[0x1];
8792 u8 reserved_at_41[0xf];
8793 u8 vport_number[0x10];
8795 u8 reserved_at_60[0x20];
8798 u8 reserved_at_88[0x18];
8800 u8 reserved_at_a0[0x8];
8803 u8 reserved_at_c0[0x8];
8804 u8 underlay_qpn[0x18];
8805 u8 reserved_at_e0[0x120];
8809 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8810 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8813 struct mlx5_ifc_modify_flow_table_out_bits {
8815 u8 reserved_at_8[0x18];
8819 u8 reserved_at_40[0x40];
8822 struct mlx5_ifc_modify_flow_table_in_bits {
8824 u8 reserved_at_10[0x10];
8826 u8 reserved_at_20[0x10];
8829 u8 other_vport[0x1];
8830 u8 reserved_at_41[0xf];
8831 u8 vport_number[0x10];
8833 u8 reserved_at_60[0x10];
8834 u8 modify_field_select[0x10];
8837 u8 reserved_at_88[0x18];
8839 u8 reserved_at_a0[0x8];
8842 struct mlx5_ifc_flow_table_context_bits flow_table_context;
8845 struct mlx5_ifc_ets_tcn_config_reg_bits {
8849 u8 reserved_at_3[0x9];
8851 u8 reserved_at_10[0x9];
8852 u8 bw_allocation[0x7];
8854 u8 reserved_at_20[0xc];
8855 u8 max_bw_units[0x4];
8856 u8 reserved_at_30[0x8];
8857 u8 max_bw_value[0x8];
8860 struct mlx5_ifc_ets_global_config_reg_bits {
8861 u8 reserved_at_0[0x2];
8863 u8 reserved_at_3[0x1d];
8865 u8 reserved_at_20[0xc];
8866 u8 max_bw_units[0x4];
8867 u8 reserved_at_30[0x8];
8868 u8 max_bw_value[0x8];
8871 struct mlx5_ifc_qetc_reg_bits {
8872 u8 reserved_at_0[0x8];
8873 u8 port_number[0x8];
8874 u8 reserved_at_10[0x30];
8876 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8877 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8880 struct mlx5_ifc_qpdpm_dscp_reg_bits {
8882 u8 reserved_at_01[0x0b];
8886 struct mlx5_ifc_qpdpm_reg_bits {
8887 u8 reserved_at_0[0x8];
8889 u8 reserved_at_10[0x10];
8890 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
8893 struct mlx5_ifc_qpts_reg_bits {
8894 u8 reserved_at_0[0x8];
8896 u8 reserved_at_10[0x2d];
8897 u8 trust_state[0x3];
8900 struct mlx5_ifc_pptb_reg_bits {
8901 u8 reserved_at_0[0x2];
8903 u8 reserved_at_4[0x4];
8905 u8 reserved_at_10[0x6];
8910 u8 prio_x_buff[0x20];
8913 u8 reserved_at_48[0x10];
8915 u8 untagged_buff[0x4];
8918 struct mlx5_ifc_pbmc_reg_bits {
8919 u8 reserved_at_0[0x8];
8921 u8 reserved_at_10[0x10];
8923 u8 xoff_timer_value[0x10];
8924 u8 xoff_refresh[0x10];
8926 u8 reserved_at_40[0x9];
8927 u8 fullness_threshold[0x7];
8928 u8 port_buffer_size[0x10];
8930 struct mlx5_ifc_bufferx_reg_bits buffer[10];
8932 u8 reserved_at_2e0[0x80];
8935 struct mlx5_ifc_qtct_reg_bits {
8936 u8 reserved_at_0[0x8];
8937 u8 port_number[0x8];
8938 u8 reserved_at_10[0xd];
8941 u8 reserved_at_20[0x1d];
8945 struct mlx5_ifc_mcia_reg_bits {
8947 u8 reserved_at_1[0x7];
8949 u8 reserved_at_10[0x8];
8952 u8 i2c_device_address[0x8];
8953 u8 page_number[0x8];
8954 u8 device_address[0x10];
8956 u8 reserved_at_40[0x10];
8959 u8 reserved_at_60[0x20];
8975 struct mlx5_ifc_dcbx_param_bits {
8976 u8 dcbx_cee_cap[0x1];
8977 u8 dcbx_ieee_cap[0x1];
8978 u8 dcbx_standby_cap[0x1];
8979 u8 reserved_at_0[0x5];
8980 u8 port_number[0x8];
8981 u8 reserved_at_10[0xa];
8982 u8 max_application_table_size[6];
8983 u8 reserved_at_20[0x15];
8984 u8 version_oper[0x3];
8985 u8 reserved_at_38[5];
8986 u8 version_admin[0x3];
8987 u8 willing_admin[0x1];
8988 u8 reserved_at_41[0x3];
8989 u8 pfc_cap_oper[0x4];
8990 u8 reserved_at_48[0x4];
8991 u8 pfc_cap_admin[0x4];
8992 u8 reserved_at_50[0x4];
8993 u8 num_of_tc_oper[0x4];
8994 u8 reserved_at_58[0x4];
8995 u8 num_of_tc_admin[0x4];
8996 u8 remote_willing[0x1];
8997 u8 reserved_at_61[3];
8998 u8 remote_pfc_cap[4];
8999 u8 reserved_at_68[0x14];
9000 u8 remote_num_of_tc[0x4];
9001 u8 reserved_at_80[0x18];
9003 u8 reserved_at_a0[0x160];
9006 struct mlx5_ifc_lagc_bits {
9007 u8 reserved_at_0[0x1d];
9010 u8 reserved_at_20[0x14];
9011 u8 tx_remap_affinity_2[0x4];
9012 u8 reserved_at_38[0x4];
9013 u8 tx_remap_affinity_1[0x4];
9016 struct mlx5_ifc_create_lag_out_bits {
9018 u8 reserved_at_8[0x18];
9022 u8 reserved_at_40[0x40];
9025 struct mlx5_ifc_create_lag_in_bits {
9027 u8 reserved_at_10[0x10];
9029 u8 reserved_at_20[0x10];
9032 struct mlx5_ifc_lagc_bits ctx;
9035 struct mlx5_ifc_modify_lag_out_bits {
9037 u8 reserved_at_8[0x18];
9041 u8 reserved_at_40[0x40];
9044 struct mlx5_ifc_modify_lag_in_bits {
9046 u8 reserved_at_10[0x10];
9048 u8 reserved_at_20[0x10];
9051 u8 reserved_at_40[0x20];
9052 u8 field_select[0x20];
9054 struct mlx5_ifc_lagc_bits ctx;
9057 struct mlx5_ifc_query_lag_out_bits {
9059 u8 reserved_at_8[0x18];
9063 struct mlx5_ifc_lagc_bits ctx;
9066 struct mlx5_ifc_query_lag_in_bits {
9068 u8 reserved_at_10[0x10];
9070 u8 reserved_at_20[0x10];
9073 u8 reserved_at_40[0x40];
9076 struct mlx5_ifc_destroy_lag_out_bits {
9078 u8 reserved_at_8[0x18];
9082 u8 reserved_at_40[0x40];
9085 struct mlx5_ifc_destroy_lag_in_bits {
9087 u8 reserved_at_10[0x10];
9089 u8 reserved_at_20[0x10];
9092 u8 reserved_at_40[0x40];
9095 struct mlx5_ifc_create_vport_lag_out_bits {
9097 u8 reserved_at_8[0x18];
9101 u8 reserved_at_40[0x40];
9104 struct mlx5_ifc_create_vport_lag_in_bits {
9106 u8 reserved_at_10[0x10];
9108 u8 reserved_at_20[0x10];
9111 u8 reserved_at_40[0x40];
9114 struct mlx5_ifc_destroy_vport_lag_out_bits {
9116 u8 reserved_at_8[0x18];
9120 u8 reserved_at_40[0x40];
9123 struct mlx5_ifc_destroy_vport_lag_in_bits {
9125 u8 reserved_at_10[0x10];
9127 u8 reserved_at_20[0x10];
9130 u8 reserved_at_40[0x40];
9133 struct mlx5_ifc_alloc_memic_in_bits {
9135 u8 reserved_at_10[0x10];
9137 u8 reserved_at_20[0x10];
9140 u8 reserved_at_30[0x20];
9142 u8 reserved_at_40[0x18];
9143 u8 log_memic_addr_alignment[0x8];
9145 u8 range_start_addr[0x40];
9147 u8 range_size[0x20];
9149 u8 memic_size[0x20];
9152 struct mlx5_ifc_alloc_memic_out_bits {
9154 u8 reserved_at_8[0x18];
9158 u8 memic_start_addr[0x40];
9161 struct mlx5_ifc_dealloc_memic_in_bits {
9163 u8 reserved_at_10[0x10];
9165 u8 reserved_at_20[0x10];
9168 u8 reserved_at_40[0x40];
9170 u8 memic_start_addr[0x40];
9172 u8 memic_size[0x20];
9174 u8 reserved_at_e0[0x20];
9177 struct mlx5_ifc_dealloc_memic_out_bits {
9179 u8 reserved_at_8[0x18];
9183 u8 reserved_at_40[0x40];
9186 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9190 u8 reserved_at_20[0x10];
9195 u8 reserved_at_60[0x20];
9198 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9200 u8 reserved_at_8[0x18];
9206 u8 reserved_at_60[0x20];
9209 struct mlx5_ifc_umem_bits {
9210 u8 modify_field_select[0x40];
9212 u8 reserved_at_40[0x5b];
9213 u8 log_page_size[0x5];
9215 u8 page_offset[0x20];
9217 u8 num_of_mtt[0x40];
9219 struct mlx5_ifc_mtt_bits mtt[0];
9222 struct mlx5_ifc_uctx_bits {
9223 u8 modify_field_select[0x40];
9225 u8 reserved_at_40[0x1c0];
9228 struct mlx5_ifc_create_umem_in_bits {
9229 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
9230 struct mlx5_ifc_umem_bits umem;
9233 struct mlx5_ifc_create_uctx_in_bits {
9234 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
9235 struct mlx5_ifc_uctx_bits uctx;
9238 struct mlx5_ifc_mtrc_string_db_param_bits {
9239 u8 string_db_base_address[0x20];
9241 u8 reserved_at_20[0x8];
9242 u8 string_db_size[0x18];
9245 struct mlx5_ifc_mtrc_cap_bits {
9246 u8 trace_owner[0x1];
9247 u8 trace_to_memory[0x1];
9248 u8 reserved_at_2[0x4];
9250 u8 reserved_at_8[0x14];
9251 u8 num_string_db[0x4];
9253 u8 first_string_trace[0x8];
9254 u8 num_string_trace[0x8];
9255 u8 reserved_at_30[0x28];
9257 u8 log_max_trace_buffer_size[0x8];
9259 u8 reserved_at_60[0x20];
9261 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
9263 u8 reserved_at_280[0x180];
9266 struct mlx5_ifc_mtrc_conf_bits {
9267 u8 reserved_at_0[0x1c];
9269 u8 reserved_at_20[0x18];
9270 u8 log_trace_buffer_size[0x8];
9271 u8 trace_mkey[0x20];
9272 u8 reserved_at_60[0x3a0];
9275 struct mlx5_ifc_mtrc_stdb_bits {
9276 u8 string_db_index[0x4];
9277 u8 reserved_at_4[0x4];
9279 u8 start_offset[0x20];
9280 u8 string_db_data[0];
9283 struct mlx5_ifc_mtrc_ctrl_bits {
9284 u8 trace_status[0x2];
9285 u8 reserved_at_2[0x2];
9287 u8 reserved_at_5[0xb];
9288 u8 modify_field_select[0x10];
9289 u8 reserved_at_20[0x2b];
9290 u8 current_timestamp52_32[0x15];
9291 u8 current_timestamp31_0[0x20];
9292 u8 reserved_at_80[0x180];
9295 #endif /* MLX5_IFC_H */