2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "mlx5_ifc_fpga.h"
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4,
81 MLX5_SHARED_RESOURCE_UID = 0xffff,
85 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
96 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
97 MLX5_OBJ_TYPE_MKEY = 0xff01,
98 MLX5_OBJ_TYPE_QP = 0xff02,
99 MLX5_OBJ_TYPE_PSV = 0xff03,
100 MLX5_OBJ_TYPE_RMP = 0xff04,
101 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
102 MLX5_OBJ_TYPE_RQ = 0xff06,
103 MLX5_OBJ_TYPE_SQ = 0xff07,
104 MLX5_OBJ_TYPE_TIR = 0xff08,
105 MLX5_OBJ_TYPE_TIS = 0xff09,
106 MLX5_OBJ_TYPE_DCT = 0xff0a,
107 MLX5_OBJ_TYPE_XRQ = 0xff0b,
108 MLX5_OBJ_TYPE_RQT = 0xff0e,
109 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
110 MLX5_OBJ_TYPE_CQ = 0xff10,
114 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
115 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
116 MLX5_CMD_OP_INIT_HCA = 0x102,
117 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
118 MLX5_CMD_OP_ENABLE_HCA = 0x104,
119 MLX5_CMD_OP_DISABLE_HCA = 0x105,
120 MLX5_CMD_OP_QUERY_PAGES = 0x107,
121 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
122 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
123 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
124 MLX5_CMD_OP_SET_ISSI = 0x10b,
125 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
126 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
127 MLX5_CMD_OP_ALLOC_SF = 0x113,
128 MLX5_CMD_OP_DEALLOC_SF = 0x114,
129 MLX5_CMD_OP_CREATE_MKEY = 0x200,
130 MLX5_CMD_OP_QUERY_MKEY = 0x201,
131 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
136 MLX5_CMD_OP_CREATE_EQ = 0x301,
137 MLX5_CMD_OP_DESTROY_EQ = 0x302,
138 MLX5_CMD_OP_QUERY_EQ = 0x303,
139 MLX5_CMD_OP_GEN_EQE = 0x304,
140 MLX5_CMD_OP_CREATE_CQ = 0x400,
141 MLX5_CMD_OP_DESTROY_CQ = 0x401,
142 MLX5_CMD_OP_QUERY_CQ = 0x402,
143 MLX5_CMD_OP_MODIFY_CQ = 0x403,
144 MLX5_CMD_OP_CREATE_QP = 0x500,
145 MLX5_CMD_OP_DESTROY_QP = 0x501,
146 MLX5_CMD_OP_RST2INIT_QP = 0x502,
147 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
148 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
149 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
150 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
151 MLX5_CMD_OP_2ERR_QP = 0x507,
152 MLX5_CMD_OP_2RST_QP = 0x50a,
153 MLX5_CMD_OP_QUERY_QP = 0x50b,
154 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
155 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
156 MLX5_CMD_OP_CREATE_PSV = 0x600,
157 MLX5_CMD_OP_DESTROY_PSV = 0x601,
158 MLX5_CMD_OP_CREATE_SRQ = 0x700,
159 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
160 MLX5_CMD_OP_QUERY_SRQ = 0x702,
161 MLX5_CMD_OP_ARM_RQ = 0x703,
162 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
163 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
164 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
165 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
166 MLX5_CMD_OP_CREATE_DCT = 0x710,
167 MLX5_CMD_OP_DESTROY_DCT = 0x711,
168 MLX5_CMD_OP_DRAIN_DCT = 0x712,
169 MLX5_CMD_OP_QUERY_DCT = 0x713,
170 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
171 MLX5_CMD_OP_CREATE_XRQ = 0x717,
172 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
173 MLX5_CMD_OP_QUERY_XRQ = 0x719,
174 MLX5_CMD_OP_ARM_XRQ = 0x71a,
175 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
176 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
177 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
178 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
179 MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
180 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
181 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
182 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
183 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
184 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
185 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
186 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
187 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
188 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
189 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
190 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
191 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
192 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
193 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
194 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
195 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
196 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
197 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
198 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
199 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
200 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
201 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
202 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
203 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
204 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
205 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
206 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
207 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
208 MLX5_CMD_OP_ALLOC_PD = 0x800,
209 MLX5_CMD_OP_DEALLOC_PD = 0x801,
210 MLX5_CMD_OP_ALLOC_UAR = 0x802,
211 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
212 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
213 MLX5_CMD_OP_ACCESS_REG = 0x805,
214 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
215 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
216 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
217 MLX5_CMD_OP_MAD_IFC = 0x50d,
218 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
219 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
220 MLX5_CMD_OP_NOP = 0x80d,
221 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
222 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
223 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
224 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
225 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
226 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
227 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
228 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
229 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
230 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
231 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
232 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
233 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
234 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
235 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
236 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
237 MLX5_CMD_OP_CREATE_LAG = 0x840,
238 MLX5_CMD_OP_MODIFY_LAG = 0x841,
239 MLX5_CMD_OP_QUERY_LAG = 0x842,
240 MLX5_CMD_OP_DESTROY_LAG = 0x843,
241 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
242 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
243 MLX5_CMD_OP_CREATE_TIR = 0x900,
244 MLX5_CMD_OP_MODIFY_TIR = 0x901,
245 MLX5_CMD_OP_DESTROY_TIR = 0x902,
246 MLX5_CMD_OP_QUERY_TIR = 0x903,
247 MLX5_CMD_OP_CREATE_SQ = 0x904,
248 MLX5_CMD_OP_MODIFY_SQ = 0x905,
249 MLX5_CMD_OP_DESTROY_SQ = 0x906,
250 MLX5_CMD_OP_QUERY_SQ = 0x907,
251 MLX5_CMD_OP_CREATE_RQ = 0x908,
252 MLX5_CMD_OP_MODIFY_RQ = 0x909,
253 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
254 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
255 MLX5_CMD_OP_QUERY_RQ = 0x90b,
256 MLX5_CMD_OP_CREATE_RMP = 0x90c,
257 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
258 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
259 MLX5_CMD_OP_QUERY_RMP = 0x90f,
260 MLX5_CMD_OP_CREATE_TIS = 0x912,
261 MLX5_CMD_OP_MODIFY_TIS = 0x913,
262 MLX5_CMD_OP_DESTROY_TIS = 0x914,
263 MLX5_CMD_OP_QUERY_TIS = 0x915,
264 MLX5_CMD_OP_CREATE_RQT = 0x916,
265 MLX5_CMD_OP_MODIFY_RQT = 0x917,
266 MLX5_CMD_OP_DESTROY_RQT = 0x918,
267 MLX5_CMD_OP_QUERY_RQT = 0x919,
268 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
269 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
270 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
271 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
272 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
273 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
274 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
275 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
276 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
277 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
278 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
279 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
280 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
281 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
282 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
283 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
284 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
285 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
286 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
287 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
288 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
289 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
290 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
291 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
292 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
293 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
294 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
295 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
296 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
297 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
298 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
299 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
300 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
301 MLX5_CMD_OP_SYNC_STEERING = 0xb00,
305 /* Valid range for general commands that don't work over an object */
307 MLX5_CMD_OP_GENERAL_START = 0xb00,
308 MLX5_CMD_OP_GENERAL_END = 0xd00,
311 struct mlx5_ifc_flow_table_fields_supported_bits {
314 u8 outer_ether_type[0x1];
315 u8 outer_ip_version[0x1];
316 u8 outer_first_prio[0x1];
317 u8 outer_first_cfi[0x1];
318 u8 outer_first_vid[0x1];
319 u8 outer_ipv4_ttl[0x1];
320 u8 outer_second_prio[0x1];
321 u8 outer_second_cfi[0x1];
322 u8 outer_second_vid[0x1];
323 u8 reserved_at_b[0x1];
327 u8 outer_ip_protocol[0x1];
328 u8 outer_ip_ecn[0x1];
329 u8 outer_ip_dscp[0x1];
330 u8 outer_udp_sport[0x1];
331 u8 outer_udp_dport[0x1];
332 u8 outer_tcp_sport[0x1];
333 u8 outer_tcp_dport[0x1];
334 u8 outer_tcp_flags[0x1];
335 u8 outer_gre_protocol[0x1];
336 u8 outer_gre_key[0x1];
337 u8 outer_vxlan_vni[0x1];
338 u8 outer_geneve_vni[0x1];
339 u8 outer_geneve_oam[0x1];
340 u8 outer_geneve_protocol_type[0x1];
341 u8 outer_geneve_opt_len[0x1];
342 u8 reserved_at_1e[0x1];
343 u8 source_eswitch_port[0x1];
347 u8 inner_ether_type[0x1];
348 u8 inner_ip_version[0x1];
349 u8 inner_first_prio[0x1];
350 u8 inner_first_cfi[0x1];
351 u8 inner_first_vid[0x1];
352 u8 reserved_at_27[0x1];
353 u8 inner_second_prio[0x1];
354 u8 inner_second_cfi[0x1];
355 u8 inner_second_vid[0x1];
356 u8 reserved_at_2b[0x1];
360 u8 inner_ip_protocol[0x1];
361 u8 inner_ip_ecn[0x1];
362 u8 inner_ip_dscp[0x1];
363 u8 inner_udp_sport[0x1];
364 u8 inner_udp_dport[0x1];
365 u8 inner_tcp_sport[0x1];
366 u8 inner_tcp_dport[0x1];
367 u8 inner_tcp_flags[0x1];
368 u8 reserved_at_37[0x9];
370 u8 geneve_tlv_option_0_data[0x1];
371 u8 reserved_at_41[0x4];
372 u8 outer_first_mpls_over_udp[0x4];
373 u8 outer_first_mpls_over_gre[0x4];
374 u8 inner_first_mpls[0x4];
375 u8 outer_first_mpls[0x4];
376 u8 reserved_at_55[0x2];
377 u8 outer_esp_spi[0x1];
378 u8 reserved_at_58[0x2];
380 u8 reserved_at_5b[0x5];
382 u8 reserved_at_60[0x18];
383 u8 metadata_reg_c_7[0x1];
384 u8 metadata_reg_c_6[0x1];
385 u8 metadata_reg_c_5[0x1];
386 u8 metadata_reg_c_4[0x1];
387 u8 metadata_reg_c_3[0x1];
388 u8 metadata_reg_c_2[0x1];
389 u8 metadata_reg_c_1[0x1];
390 u8 metadata_reg_c_0[0x1];
393 struct mlx5_ifc_flow_table_prop_layout_bits {
395 u8 reserved_at_1[0x1];
396 u8 flow_counter[0x1];
397 u8 flow_modify_en[0x1];
399 u8 identified_miss_table_mode[0x1];
400 u8 flow_table_modify[0x1];
403 u8 reserved_at_9[0x1];
406 u8 reserved_at_c[0x1];
409 u8 reformat_and_vlan_action[0x1];
410 u8 reserved_at_10[0x1];
412 u8 reformat_l3_tunnel_to_l2[0x1];
413 u8 reformat_l2_to_l3_tunnel[0x1];
414 u8 reformat_and_modify_action[0x1];
415 u8 ignore_flow_level[0x1];
416 u8 reserved_at_16[0x1];
417 u8 table_miss_action_domain[0x1];
418 u8 termination_table[0x1];
419 u8 reformat_and_fwd_to_table[0x1];
420 u8 reserved_at_1a[0x2];
421 u8 ipsec_encrypt[0x1];
422 u8 ipsec_decrypt[0x1];
424 u8 reserved_at_1f[0x1];
426 u8 termination_table_raw_traffic[0x1];
427 u8 reserved_at_21[0x1];
428 u8 log_max_ft_size[0x6];
429 u8 log_max_modify_header_context[0x8];
430 u8 max_modify_header_actions[0x8];
431 u8 max_ft_level[0x8];
433 u8 reserved_at_40[0x20];
435 u8 reserved_at_60[0x18];
436 u8 log_max_ft_num[0x8];
438 u8 reserved_at_80[0x10];
439 u8 log_max_flow_counter[0x8];
440 u8 log_max_destination[0x8];
442 u8 reserved_at_a0[0x18];
443 u8 log_max_flow[0x8];
445 u8 reserved_at_c0[0x40];
447 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
449 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
452 struct mlx5_ifc_odp_per_transport_service_cap_bits {
459 u8 reserved_at_6[0x1a];
462 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
487 u8 reserved_at_c0[0x18];
488 u8 ttl_hoplimit[0x8];
493 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
495 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
498 struct mlx5_ifc_nvgre_key_bits {
503 union mlx5_ifc_gre_key_bits {
504 struct mlx5_ifc_nvgre_key_bits nvgre;
508 struct mlx5_ifc_fte_match_set_misc_bits {
509 u8 gre_c_present[0x1];
510 u8 reserved_at_1[0x1];
511 u8 gre_k_present[0x1];
512 u8 gre_s_present[0x1];
513 u8 source_vhca_port[0x4];
516 u8 source_eswitch_owner_vhca_id[0x10];
517 u8 source_port[0x10];
519 u8 outer_second_prio[0x3];
520 u8 outer_second_cfi[0x1];
521 u8 outer_second_vid[0xc];
522 u8 inner_second_prio[0x3];
523 u8 inner_second_cfi[0x1];
524 u8 inner_second_vid[0xc];
526 u8 outer_second_cvlan_tag[0x1];
527 u8 inner_second_cvlan_tag[0x1];
528 u8 outer_second_svlan_tag[0x1];
529 u8 inner_second_svlan_tag[0x1];
530 u8 reserved_at_64[0xc];
531 u8 gre_protocol[0x10];
533 union mlx5_ifc_gre_key_bits gre_key;
536 u8 reserved_at_b8[0x8];
539 u8 reserved_at_d8[0x7];
542 u8 reserved_at_e0[0xc];
543 u8 outer_ipv6_flow_label[0x14];
545 u8 reserved_at_100[0xc];
546 u8 inner_ipv6_flow_label[0x14];
548 u8 reserved_at_120[0xa];
549 u8 geneve_opt_len[0x6];
550 u8 geneve_protocol_type[0x10];
552 u8 reserved_at_140[0x8];
554 u8 reserved_at_160[0x20];
555 u8 outer_esp_spi[0x20];
556 u8 reserved_at_1a0[0x60];
559 struct mlx5_ifc_fte_match_mpls_bits {
566 struct mlx5_ifc_fte_match_set_misc2_bits {
567 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
569 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
571 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
573 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
575 u8 metadata_reg_c_7[0x20];
577 u8 metadata_reg_c_6[0x20];
579 u8 metadata_reg_c_5[0x20];
581 u8 metadata_reg_c_4[0x20];
583 u8 metadata_reg_c_3[0x20];
585 u8 metadata_reg_c_2[0x20];
587 u8 metadata_reg_c_1[0x20];
589 u8 metadata_reg_c_0[0x20];
591 u8 metadata_reg_a[0x20];
593 u8 reserved_at_1a0[0x60];
596 struct mlx5_ifc_fte_match_set_misc3_bits {
597 u8 inner_tcp_seq_num[0x20];
599 u8 outer_tcp_seq_num[0x20];
601 u8 inner_tcp_ack_num[0x20];
603 u8 outer_tcp_ack_num[0x20];
605 u8 reserved_at_80[0x8];
606 u8 outer_vxlan_gpe_vni[0x18];
608 u8 outer_vxlan_gpe_next_protocol[0x8];
609 u8 outer_vxlan_gpe_flags[0x8];
610 u8 reserved_at_b0[0x10];
612 u8 icmp_header_data[0x20];
614 u8 icmpv6_header_data[0x20];
621 u8 geneve_tlv_option_0_data[0x20];
623 u8 reserved_at_140[0xc0];
626 struct mlx5_ifc_cmd_pas_bits {
630 u8 reserved_at_34[0xc];
633 struct mlx5_ifc_uint64_bits {
640 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
641 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
642 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
643 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
644 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
645 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
646 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
647 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
648 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
649 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
652 struct mlx5_ifc_ads_bits {
655 u8 reserved_at_2[0xe];
658 u8 reserved_at_20[0x8];
664 u8 reserved_at_45[0x3];
665 u8 src_addr_index[0x8];
666 u8 reserved_at_50[0x4];
670 u8 reserved_at_60[0x4];
674 u8 rgid_rip[16][0x8];
676 u8 reserved_at_100[0x4];
679 u8 reserved_at_106[0x1];
688 u8 vhca_port_num[0x8];
694 struct mlx5_ifc_flow_table_nic_cap_bits {
695 u8 nic_rx_multi_path_tirs[0x1];
696 u8 nic_rx_multi_path_tirs_fts[0x1];
697 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
698 u8 reserved_at_3[0x4];
699 u8 sw_owner_reformat_supported[0x1];
700 u8 reserved_at_8[0x18];
702 u8 encap_general_header[0x1];
703 u8 reserved_at_21[0xa];
704 u8 log_max_packet_reformat_context[0x5];
705 u8 reserved_at_30[0x6];
706 u8 max_encap_header_size[0xa];
707 u8 reserved_at_40[0x1c0];
709 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
711 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
713 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
715 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
717 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
719 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
721 u8 reserved_at_e00[0x1200];
723 u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
725 u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
727 u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
729 u8 reserved_at_20c0[0x5f40];
733 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
734 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
735 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
736 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
737 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
738 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
739 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
740 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
743 struct mlx5_ifc_flow_table_eswitch_cap_bits {
744 u8 fdb_to_vport_reg_c_id[0x8];
745 u8 reserved_at_8[0xd];
746 u8 fdb_modify_header_fwd_to_table[0x1];
747 u8 reserved_at_16[0x1];
749 u8 reserved_at_18[0x2];
750 u8 multi_fdb_encap[0x1];
751 u8 egress_acl_forward_to_vport[0x1];
752 u8 fdb_multi_path_to_table[0x1];
753 u8 reserved_at_1d[0x3];
755 u8 reserved_at_20[0x1e0];
757 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
759 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
761 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
763 u8 reserved_at_800[0x1000];
765 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
767 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
769 u8 sw_steering_uplink_icm_address_rx[0x40];
771 u8 sw_steering_uplink_icm_address_tx[0x40];
773 u8 reserved_at_1900[0x6700];
777 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
778 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
781 struct mlx5_ifc_e_switch_cap_bits {
782 u8 vport_svlan_strip[0x1];
783 u8 vport_cvlan_strip[0x1];
784 u8 vport_svlan_insert[0x1];
785 u8 vport_cvlan_insert_if_not_exist[0x1];
786 u8 vport_cvlan_insert_overwrite[0x1];
787 u8 reserved_at_5[0x3];
788 u8 esw_uplink_ingress_acl[0x1];
789 u8 reserved_at_9[0x10];
790 u8 esw_functions_changed[0x1];
791 u8 reserved_at_1a[0x1];
792 u8 ecpf_vport_exists[0x1];
793 u8 counter_eswitch_affinity[0x1];
794 u8 merged_eswitch[0x1];
795 u8 nic_vport_node_guid_modify[0x1];
796 u8 nic_vport_port_guid_modify[0x1];
798 u8 vxlan_encap_decap[0x1];
799 u8 nvgre_encap_decap[0x1];
800 u8 reserved_at_22[0x1];
801 u8 log_max_fdb_encap_uplink[0x5];
802 u8 reserved_at_21[0x3];
803 u8 log_max_packet_reformat_context[0x5];
805 u8 max_encap_header_size[0xa];
807 u8 reserved_at_40[0xb];
808 u8 log_max_esw_sf[0x5];
809 u8 esw_sf_base_id[0x10];
811 u8 reserved_at_60[0x7a0];
815 struct mlx5_ifc_qos_cap_bits {
816 u8 packet_pacing[0x1];
817 u8 esw_scheduling[0x1];
818 u8 esw_bw_share[0x1];
819 u8 esw_rate_limit[0x1];
820 u8 reserved_at_4[0x1];
821 u8 packet_pacing_burst_bound[0x1];
822 u8 packet_pacing_typical_size[0x1];
823 u8 reserved_at_7[0x4];
824 u8 packet_pacing_uid[0x1];
825 u8 reserved_at_c[0x14];
827 u8 reserved_at_20[0x20];
829 u8 packet_pacing_max_rate[0x20];
831 u8 packet_pacing_min_rate[0x20];
833 u8 reserved_at_80[0x10];
834 u8 packet_pacing_rate_table_size[0x10];
836 u8 esw_element_type[0x10];
837 u8 esw_tsar_type[0x10];
839 u8 reserved_at_c0[0x10];
840 u8 max_qos_para_vport[0x10];
842 u8 max_tsar_bw_share[0x20];
844 u8 reserved_at_100[0x700];
847 struct mlx5_ifc_debug_cap_bits {
848 u8 core_dump_general[0x1];
849 u8 core_dump_qp[0x1];
850 u8 reserved_at_2[0x7];
851 u8 resource_dump[0x1];
852 u8 reserved_at_a[0x16];
854 u8 reserved_at_20[0x2];
855 u8 stall_detect[0x1];
856 u8 reserved_at_23[0x1d];
858 u8 reserved_at_40[0x7c0];
861 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
865 u8 lro_psh_flag[0x1];
866 u8 lro_time_stamp[0x1];
867 u8 reserved_at_5[0x2];
868 u8 wqe_vlan_insert[0x1];
869 u8 self_lb_en_modifiable[0x1];
870 u8 reserved_at_9[0x2];
872 u8 multi_pkt_send_wqe[0x2];
873 u8 wqe_inline_mode[0x2];
874 u8 rss_ind_tbl_cap[0x4];
877 u8 enhanced_multi_pkt_send_wqe[0x1];
878 u8 tunnel_lso_const_out_ip_id[0x1];
879 u8 tunnel_lro_gre[0x1];
880 u8 tunnel_lro_vxlan[0x1];
881 u8 tunnel_stateless_gre[0x1];
882 u8 tunnel_stateless_vxlan[0x1];
887 u8 cqe_checksum_full[0x1];
888 u8 tunnel_stateless_geneve_tx[0x1];
889 u8 tunnel_stateless_mpls_over_udp[0x1];
890 u8 tunnel_stateless_mpls_over_gre[0x1];
891 u8 tunnel_stateless_vxlan_gpe[0x1];
892 u8 tunnel_stateless_ipv4_over_vxlan[0x1];
893 u8 tunnel_stateless_ip_over_ip[0x1];
894 u8 insert_trailer[0x1];
895 u8 reserved_at_2b[0x5];
896 u8 max_vxlan_udp_ports[0x8];
897 u8 reserved_at_38[0x6];
898 u8 max_geneve_opt_len[0x1];
899 u8 tunnel_stateless_geneve_rx[0x1];
901 u8 reserved_at_40[0x10];
902 u8 lro_min_mss_size[0x10];
904 u8 reserved_at_60[0x120];
906 u8 lro_timer_supported_periods[4][0x20];
908 u8 reserved_at_200[0x600];
911 struct mlx5_ifc_roce_cap_bits {
913 u8 reserved_at_1[0x3];
914 u8 sw_r_roce_src_udp_port[0x1];
915 u8 reserved_at_5[0x1b];
917 u8 reserved_at_20[0x60];
919 u8 reserved_at_80[0xc];
921 u8 reserved_at_90[0x8];
922 u8 roce_version[0x8];
924 u8 reserved_at_a0[0x10];
925 u8 r_roce_dest_udp_port[0x10];
927 u8 r_roce_max_src_udp_port[0x10];
928 u8 r_roce_min_src_udp_port[0x10];
930 u8 reserved_at_e0[0x10];
931 u8 roce_address_table_size[0x10];
933 u8 reserved_at_100[0x700];
936 struct mlx5_ifc_sync_steering_in_bits {
940 u8 reserved_at_20[0x10];
943 u8 reserved_at_40[0xc0];
946 struct mlx5_ifc_sync_steering_out_bits {
948 u8 reserved_at_8[0x18];
952 u8 reserved_at_40[0x40];
955 struct mlx5_ifc_device_mem_cap_bits {
957 u8 reserved_at_1[0x1f];
959 u8 reserved_at_20[0xb];
960 u8 log_min_memic_alloc_size[0x5];
961 u8 reserved_at_30[0x8];
962 u8 log_max_memic_addr_alignment[0x8];
964 u8 memic_bar_start_addr[0x40];
966 u8 memic_bar_size[0x20];
968 u8 max_memic_size[0x20];
970 u8 steering_sw_icm_start_address[0x40];
972 u8 reserved_at_100[0x8];
973 u8 log_header_modify_sw_icm_size[0x8];
974 u8 reserved_at_110[0x2];
975 u8 log_sw_icm_alloc_granularity[0x6];
976 u8 log_steering_sw_icm_size[0x8];
978 u8 reserved_at_120[0x20];
980 u8 header_modify_sw_icm_start_address[0x40];
982 u8 reserved_at_180[0x680];
985 struct mlx5_ifc_device_event_cap_bits {
986 u8 user_affiliated_events[4][0x40];
988 u8 user_unaffiliated_events[4][0x40];
991 struct mlx5_ifc_virtio_emulation_cap_bits {
992 u8 desc_tunnel_offload_type[0x1];
993 u8 eth_frame_offload_type[0x1];
994 u8 virtio_version_1_0[0x1];
995 u8 device_features_bits_mask[0xd];
997 u8 virtio_queue_type[0x8];
999 u8 max_tunnel_desc[0x10];
1000 u8 reserved_at_30[0x3];
1001 u8 log_doorbell_stride[0x5];
1002 u8 reserved_at_38[0x3];
1003 u8 log_doorbell_bar_size[0x5];
1005 u8 doorbell_bar_offset[0x40];
1007 u8 max_emulated_devices[0x8];
1008 u8 max_num_virtio_queues[0x18];
1010 u8 reserved_at_a0[0x60];
1012 u8 umem_1_buffer_param_a[0x20];
1014 u8 umem_1_buffer_param_b[0x20];
1016 u8 umem_2_buffer_param_a[0x20];
1018 u8 umem_2_buffer_param_b[0x20];
1020 u8 umem_3_buffer_param_a[0x20];
1022 u8 umem_3_buffer_param_b[0x20];
1024 u8 reserved_at_1c0[0x640];
1028 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
1029 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
1030 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
1031 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
1032 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
1033 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
1034 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
1035 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
1036 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
1040 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
1041 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
1042 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
1043 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
1044 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
1045 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
1046 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
1047 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
1048 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
1051 struct mlx5_ifc_atomic_caps_bits {
1052 u8 reserved_at_0[0x40];
1054 u8 atomic_req_8B_endianness_mode[0x2];
1055 u8 reserved_at_42[0x4];
1056 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
1058 u8 reserved_at_47[0x19];
1060 u8 reserved_at_60[0x20];
1062 u8 reserved_at_80[0x10];
1063 u8 atomic_operations[0x10];
1065 u8 reserved_at_a0[0x10];
1066 u8 atomic_size_qp[0x10];
1068 u8 reserved_at_c0[0x10];
1069 u8 atomic_size_dc[0x10];
1071 u8 reserved_at_e0[0x720];
1074 struct mlx5_ifc_odp_cap_bits {
1075 u8 reserved_at_0[0x40];
1078 u8 reserved_at_41[0x1f];
1080 u8 reserved_at_60[0x20];
1082 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1084 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1086 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1088 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1090 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1092 u8 reserved_at_120[0x6E0];
1095 struct mlx5_ifc_calc_op {
1096 u8 reserved_at_0[0x10];
1097 u8 reserved_at_10[0x9];
1098 u8 op_swap_endianness[0x1];
1107 struct mlx5_ifc_vector_calc_cap_bits {
1108 u8 calc_matrix[0x1];
1109 u8 reserved_at_1[0x1f];
1110 u8 reserved_at_20[0x8];
1111 u8 max_vec_count[0x8];
1112 u8 reserved_at_30[0xd];
1113 u8 max_chunk_size[0x3];
1114 struct mlx5_ifc_calc_op calc0;
1115 struct mlx5_ifc_calc_op calc1;
1116 struct mlx5_ifc_calc_op calc2;
1117 struct mlx5_ifc_calc_op calc3;
1119 u8 reserved_at_c0[0x720];
1122 struct mlx5_ifc_tls_cap_bits {
1123 u8 tls_1_2_aes_gcm_128[0x1];
1124 u8 tls_1_3_aes_gcm_128[0x1];
1125 u8 tls_1_2_aes_gcm_256[0x1];
1126 u8 tls_1_3_aes_gcm_256[0x1];
1127 u8 reserved_at_4[0x1c];
1129 u8 reserved_at_20[0x7e0];
1132 struct mlx5_ifc_ipsec_cap_bits {
1133 u8 ipsec_full_offload[0x1];
1134 u8 ipsec_crypto_offload[0x1];
1136 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1137 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1138 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1139 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1140 u8 reserved_at_7[0x4];
1141 u8 log_max_ipsec_offload[0x5];
1142 u8 reserved_at_10[0x10];
1144 u8 min_log_ipsec_full_replay_window[0x8];
1145 u8 max_log_ipsec_full_replay_window[0x8];
1146 u8 reserved_at_30[0x7d0];
1150 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1151 MLX5_WQ_TYPE_CYCLIC = 0x1,
1152 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1153 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1157 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1158 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1162 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1163 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1164 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1165 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1166 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1170 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1171 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1172 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1173 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1174 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1175 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1179 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1180 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1184 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1185 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1186 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1190 MLX5_CAP_PORT_TYPE_IB = 0x0,
1191 MLX5_CAP_PORT_TYPE_ETH = 0x1,
1195 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1196 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1197 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1201 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3,
1202 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
1203 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
1204 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
1208 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1209 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1212 #define MLX5_FC_BULK_SIZE_FACTOR 128
1214 enum mlx5_fc_bulk_alloc_bitmask {
1215 MLX5_FC_BULK_128 = (1 << 0),
1216 MLX5_FC_BULK_256 = (1 << 1),
1217 MLX5_FC_BULK_512 = (1 << 2),
1218 MLX5_FC_BULK_1024 = (1 << 3),
1219 MLX5_FC_BULK_2048 = (1 << 4),
1220 MLX5_FC_BULK_4096 = (1 << 5),
1221 MLX5_FC_BULK_8192 = (1 << 6),
1222 MLX5_FC_BULK_16384 = (1 << 7),
1225 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1227 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1230 MLX5_STEERING_FORMAT_CONNECTX_5 = 0,
1231 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1234 struct mlx5_ifc_cmd_hca_cap_bits {
1235 u8 reserved_at_0[0x30];
1238 u8 reserved_at_40[0x40];
1240 u8 log_max_srq_sz[0x8];
1241 u8 log_max_qp_sz[0x8];
1243 u8 reserved_at_91[0x7];
1244 u8 prio_tag_required[0x1];
1245 u8 reserved_at_99[0x2];
1248 u8 reserved_at_a0[0x3];
1249 u8 ece_support[0x1];
1250 u8 reserved_at_a4[0x7];
1251 u8 log_max_srq[0x5];
1252 u8 reserved_at_b0[0x10];
1254 u8 max_sgl_for_optimized_performance[0x8];
1255 u8 log_max_cq_sz[0x8];
1256 u8 relaxed_ordering_write_umr[0x1];
1257 u8 relaxed_ordering_read_umr[0x1];
1258 u8 reserved_at_d2[0x7];
1259 u8 virtio_net_device_emualtion_manager[0x1];
1260 u8 virtio_blk_device_emualtion_manager[0x1];
1263 u8 log_max_eq_sz[0x8];
1264 u8 relaxed_ordering_write[0x1];
1265 u8 relaxed_ordering_read[0x1];
1266 u8 log_max_mkey[0x6];
1267 u8 reserved_at_f0[0x8];
1268 u8 dump_fill_mkey[0x1];
1269 u8 reserved_at_f9[0x2];
1270 u8 fast_teardown[0x1];
1273 u8 max_indirection[0x8];
1274 u8 fixed_buffer_size[0x1];
1275 u8 log_max_mrw_sz[0x7];
1276 u8 force_teardown[0x1];
1277 u8 reserved_at_111[0x1];
1278 u8 log_max_bsf_list_size[0x6];
1279 u8 umr_extended_translation_offset[0x1];
1281 u8 log_max_klm_list_size[0x6];
1283 u8 reserved_at_120[0xa];
1284 u8 log_max_ra_req_dc[0x6];
1285 u8 reserved_at_130[0xa];
1286 u8 log_max_ra_res_dc[0x6];
1288 u8 reserved_at_140[0x6];
1289 u8 release_all_pages[0x1];
1290 u8 reserved_at_147[0x2];
1292 u8 log_max_ra_req_qp[0x6];
1293 u8 reserved_at_150[0xa];
1294 u8 log_max_ra_res_qp[0x6];
1297 u8 cc_query_allowed[0x1];
1298 u8 cc_modify_allowed[0x1];
1300 u8 cache_line_128byte[0x1];
1301 u8 reserved_at_165[0x4];
1302 u8 rts2rts_qp_counters_set_id[0x1];
1303 u8 reserved_at_16a[0x2];
1304 u8 vnic_env_int_rq_oob[0x1];
1306 u8 reserved_at_16e[0x1];
1308 u8 gid_table_size[0x10];
1310 u8 out_of_seq_cnt[0x1];
1311 u8 vport_counters[0x1];
1312 u8 retransmission_q_counters[0x1];
1314 u8 modify_rq_counter_set_id[0x1];
1315 u8 rq_delay_drop[0x1];
1317 u8 pkey_table_size[0x10];
1319 u8 vport_group_manager[0x1];
1320 u8 vhca_group_manager[0x1];
1323 u8 vnic_env_queue_counters[0x1];
1325 u8 nic_flow_table[0x1];
1326 u8 eswitch_manager[0x1];
1327 u8 device_memory[0x1];
1330 u8 local_ca_ack_delay[0x5];
1331 u8 port_module_event[0x1];
1332 u8 enhanced_error_q_counters[0x1];
1333 u8 ports_check[0x1];
1334 u8 reserved_at_1b3[0x1];
1335 u8 disable_link_up[0x1];
1340 u8 reserved_at_1c0[0x1];
1343 u8 log_max_msg[0x5];
1344 u8 reserved_at_1c8[0x4];
1346 u8 temp_warn_event[0x1];
1348 u8 general_notification_event[0x1];
1349 u8 reserved_at_1d3[0x2];
1353 u8 reserved_at_1d8[0x1];
1362 u8 stat_rate_support[0x10];
1363 u8 reserved_at_1f0[0x1];
1364 u8 pci_sync_for_fw_update_event[0x1];
1365 u8 reserved_at_1f2[0x6];
1366 u8 init2_lag_tx_port_affinity[0x1];
1367 u8 reserved_at_1fa[0x3];
1368 u8 cqe_version[0x4];
1370 u8 compact_address_vector[0x1];
1371 u8 striding_rq[0x1];
1372 u8 reserved_at_202[0x1];
1373 u8 ipoib_enhanced_offloads[0x1];
1374 u8 ipoib_basic_offloads[0x1];
1375 u8 reserved_at_205[0x1];
1376 u8 repeated_block_disabled[0x1];
1377 u8 umr_modify_entity_size_disabled[0x1];
1378 u8 umr_modify_atomic_disabled[0x1];
1379 u8 umr_indirect_mkey_disabled[0x1];
1381 u8 dc_req_scat_data_cqe[0x1];
1382 u8 reserved_at_20d[0x2];
1383 u8 drain_sigerr[0x1];
1384 u8 cmdif_checksum[0x2];
1386 u8 reserved_at_213[0x1];
1387 u8 wq_signature[0x1];
1388 u8 sctr_data_cqe[0x1];
1389 u8 reserved_at_216[0x1];
1395 u8 eth_net_offloads[0x1];
1398 u8 reserved_at_21f[0x1];
1402 u8 cq_moderation[0x1];
1403 u8 reserved_at_223[0x3];
1404 u8 cq_eq_remap[0x1];
1406 u8 block_lb_mc[0x1];
1407 u8 reserved_at_229[0x1];
1408 u8 scqe_break_moderation[0x1];
1409 u8 cq_period_start_from_cqe[0x1];
1411 u8 reserved_at_22d[0x1];
1413 u8 vector_calc[0x1];
1414 u8 umr_ptr_rlky[0x1];
1416 u8 qp_packet_based[0x1];
1417 u8 reserved_at_233[0x3];
1420 u8 set_deth_sqpn[0x1];
1421 u8 reserved_at_239[0x3];
1428 u8 reserved_at_241[0x9];
1430 u8 reserved_at_250[0x8];
1434 u8 driver_version[0x1];
1435 u8 pad_tx_eth_packet[0x1];
1436 u8 reserved_at_263[0x3];
1437 u8 mkey_by_name[0x1];
1438 u8 reserved_at_267[0x4];
1440 u8 log_bf_reg_size[0x5];
1442 u8 reserved_at_270[0x6];
1444 u8 lag_tx_port_affinity[0x1];
1445 u8 reserved_at_279[0x2];
1447 u8 num_lag_ports[0x4];
1449 u8 reserved_at_280[0x10];
1450 u8 max_wqe_sz_sq[0x10];
1452 u8 reserved_at_2a0[0x10];
1453 u8 max_wqe_sz_rq[0x10];
1455 u8 max_flow_counter_31_16[0x10];
1456 u8 max_wqe_sz_sq_dc[0x10];
1458 u8 reserved_at_2e0[0x7];
1459 u8 max_qp_mcg[0x19];
1461 u8 reserved_at_300[0x10];
1462 u8 flow_counter_bulk_alloc[0x8];
1463 u8 log_max_mcg[0x8];
1465 u8 reserved_at_320[0x3];
1466 u8 log_max_transport_domain[0x5];
1467 u8 reserved_at_328[0x3];
1469 u8 reserved_at_330[0xb];
1470 u8 log_max_xrcd[0x5];
1472 u8 nic_receive_steering_discard[0x1];
1473 u8 receive_discard_vport_down[0x1];
1474 u8 transmit_discard_vport_down[0x1];
1475 u8 reserved_at_343[0x5];
1476 u8 log_max_flow_counter_bulk[0x8];
1477 u8 max_flow_counter_15_0[0x10];
1480 u8 reserved_at_360[0x3];
1482 u8 reserved_at_368[0x3];
1484 u8 reserved_at_370[0x3];
1485 u8 log_max_tir[0x5];
1486 u8 reserved_at_378[0x3];
1487 u8 log_max_tis[0x5];
1489 u8 basic_cyclic_rcv_wqe[0x1];
1490 u8 reserved_at_381[0x2];
1491 u8 log_max_rmp[0x5];
1492 u8 reserved_at_388[0x3];
1493 u8 log_max_rqt[0x5];
1494 u8 reserved_at_390[0x3];
1495 u8 log_max_rqt_size[0x5];
1496 u8 reserved_at_398[0x3];
1497 u8 log_max_tis_per_sq[0x5];
1499 u8 ext_stride_num_range[0x1];
1500 u8 reserved_at_3a1[0x2];
1501 u8 log_max_stride_sz_rq[0x5];
1502 u8 reserved_at_3a8[0x3];
1503 u8 log_min_stride_sz_rq[0x5];
1504 u8 reserved_at_3b0[0x3];
1505 u8 log_max_stride_sz_sq[0x5];
1506 u8 reserved_at_3b8[0x3];
1507 u8 log_min_stride_sz_sq[0x5];
1510 u8 reserved_at_3c1[0x2];
1511 u8 log_max_hairpin_queues[0x5];
1512 u8 reserved_at_3c8[0x3];
1513 u8 log_max_hairpin_wq_data_sz[0x5];
1514 u8 reserved_at_3d0[0x3];
1515 u8 log_max_hairpin_num_packets[0x5];
1516 u8 reserved_at_3d8[0x3];
1517 u8 log_max_wq_sz[0x5];
1519 u8 nic_vport_change_event[0x1];
1520 u8 disable_local_lb_uc[0x1];
1521 u8 disable_local_lb_mc[0x1];
1522 u8 log_min_hairpin_wq_data_sz[0x5];
1523 u8 reserved_at_3e8[0x3];
1524 u8 log_max_vlan_list[0x5];
1525 u8 reserved_at_3f0[0x3];
1526 u8 log_max_current_mc_list[0x5];
1527 u8 reserved_at_3f8[0x3];
1528 u8 log_max_current_uc_list[0x5];
1530 u8 general_obj_types[0x40];
1532 u8 reserved_at_440[0x4];
1533 u8 steering_format_version[0x4];
1534 u8 create_qp_start_hint[0x18];
1536 u8 reserved_at_460[0x3];
1537 u8 log_max_uctx[0x5];
1538 u8 reserved_at_468[0x2];
1539 u8 ipsec_offload[0x1];
1540 u8 log_max_umem[0x5];
1541 u8 max_num_eqs[0x10];
1543 u8 reserved_at_480[0x1];
1546 u8 log_max_l2_table[0x5];
1547 u8 reserved_at_488[0x8];
1548 u8 log_uar_page_sz[0x10];
1550 u8 reserved_at_4a0[0x20];
1551 u8 device_frequency_mhz[0x20];
1552 u8 device_frequency_khz[0x20];
1554 u8 reserved_at_500[0x20];
1555 u8 num_of_uars_per_page[0x20];
1557 u8 flex_parser_protocols[0x20];
1559 u8 max_geneve_tlv_options[0x8];
1560 u8 reserved_at_568[0x3];
1561 u8 max_geneve_tlv_option_data_len[0x5];
1562 u8 reserved_at_570[0x10];
1564 u8 reserved_at_580[0x33];
1565 u8 log_max_dek[0x5];
1566 u8 reserved_at_5b8[0x4];
1567 u8 mini_cqe_resp_stride_index[0x1];
1568 u8 cqe_128_always[0x1];
1569 u8 cqe_compression_128[0x1];
1570 u8 cqe_compression[0x1];
1572 u8 cqe_compression_timeout[0x10];
1573 u8 cqe_compression_max_num[0x10];
1575 u8 reserved_at_5e0[0x10];
1576 u8 tag_matching[0x1];
1577 u8 rndv_offload_rc[0x1];
1578 u8 rndv_offload_dc[0x1];
1579 u8 log_tag_matching_list_sz[0x5];
1580 u8 reserved_at_5f8[0x3];
1581 u8 log_max_xrq[0x5];
1583 u8 affiliate_nic_vport_criteria[0x8];
1584 u8 native_port_num[0x8];
1585 u8 num_vhca_ports[0x8];
1586 u8 reserved_at_618[0x6];
1587 u8 sw_owner_id[0x1];
1588 u8 reserved_at_61f[0x1];
1590 u8 max_num_of_monitor_counters[0x10];
1591 u8 num_ppcnt_monitor_counters[0x10];
1593 u8 reserved_at_640[0x10];
1594 u8 num_q_monitor_counters[0x10];
1596 u8 reserved_at_660[0x20];
1599 u8 sf_set_partition[0x1];
1600 u8 reserved_at_682[0x1];
1602 u8 reserved_at_688[0x8];
1603 u8 log_min_sf_size[0x8];
1604 u8 max_num_sf_partitions[0x8];
1608 u8 reserved_at_6c0[0x4];
1609 u8 flex_parser_id_geneve_tlv_option_0[0x4];
1610 u8 flex_parser_id_icmp_dw1[0x4];
1611 u8 flex_parser_id_icmp_dw0[0x4];
1612 u8 flex_parser_id_icmpv6_dw1[0x4];
1613 u8 flex_parser_id_icmpv6_dw0[0x4];
1614 u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
1615 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1617 u8 reserved_at_6e0[0x10];
1618 u8 sf_base_id[0x10];
1620 u8 reserved_at_700[0x80];
1621 u8 vhca_tunnel_commands[0x40];
1622 u8 reserved_at_7c0[0x40];
1625 enum mlx5_flow_destination_type {
1626 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1627 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1628 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1630 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
1631 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1632 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1635 enum mlx5_flow_table_miss_action {
1636 MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1637 MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1638 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1641 struct mlx5_ifc_dest_format_struct_bits {
1642 u8 destination_type[0x8];
1643 u8 destination_id[0x18];
1645 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1646 u8 packet_reformat[0x1];
1647 u8 reserved_at_22[0xe];
1648 u8 destination_eswitch_owner_vhca_id[0x10];
1651 struct mlx5_ifc_flow_counter_list_bits {
1652 u8 flow_counter_id[0x20];
1654 u8 reserved_at_20[0x20];
1657 struct mlx5_ifc_extended_dest_format_bits {
1658 struct mlx5_ifc_dest_format_struct_bits destination_entry;
1660 u8 packet_reformat_id[0x20];
1662 u8 reserved_at_60[0x20];
1665 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1666 struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1667 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1670 struct mlx5_ifc_fte_match_param_bits {
1671 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1673 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1675 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1677 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1679 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1681 u8 reserved_at_a00[0x600];
1685 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1686 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1687 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1688 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1689 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1692 struct mlx5_ifc_rx_hash_field_select_bits {
1693 u8 l3_prot_type[0x1];
1694 u8 l4_prot_type[0x1];
1695 u8 selected_fields[0x1e];
1699 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1700 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1704 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1705 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1708 struct mlx5_ifc_wq_bits {
1710 u8 wq_signature[0x1];
1711 u8 end_padding_mode[0x2];
1713 u8 reserved_at_8[0x18];
1715 u8 hds_skip_first_sge[0x1];
1716 u8 log2_hds_buf_size[0x3];
1717 u8 reserved_at_24[0x7];
1718 u8 page_offset[0x5];
1721 u8 reserved_at_40[0x8];
1724 u8 reserved_at_60[0x8];
1729 u8 hw_counter[0x20];
1731 u8 sw_counter[0x20];
1733 u8 reserved_at_100[0xc];
1734 u8 log_wq_stride[0x4];
1735 u8 reserved_at_110[0x3];
1736 u8 log_wq_pg_sz[0x5];
1737 u8 reserved_at_118[0x3];
1740 u8 dbr_umem_valid[0x1];
1741 u8 wq_umem_valid[0x1];
1742 u8 reserved_at_122[0x1];
1743 u8 log_hairpin_num_packets[0x5];
1744 u8 reserved_at_128[0x3];
1745 u8 log_hairpin_data_sz[0x5];
1747 u8 reserved_at_130[0x4];
1748 u8 log_wqe_num_of_strides[0x4];
1749 u8 two_byte_shift_en[0x1];
1750 u8 reserved_at_139[0x4];
1751 u8 log_wqe_stride_size[0x3];
1753 u8 reserved_at_140[0x4c0];
1755 struct mlx5_ifc_cmd_pas_bits pas[];
1758 struct mlx5_ifc_rq_num_bits {
1759 u8 reserved_at_0[0x8];
1763 struct mlx5_ifc_mac_address_layout_bits {
1764 u8 reserved_at_0[0x10];
1765 u8 mac_addr_47_32[0x10];
1767 u8 mac_addr_31_0[0x20];
1770 struct mlx5_ifc_vlan_layout_bits {
1771 u8 reserved_at_0[0x14];
1774 u8 reserved_at_20[0x20];
1777 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1778 u8 reserved_at_0[0xa0];
1780 u8 min_time_between_cnps[0x20];
1782 u8 reserved_at_c0[0x12];
1784 u8 reserved_at_d8[0x4];
1785 u8 cnp_prio_mode[0x1];
1786 u8 cnp_802p_prio[0x3];
1788 u8 reserved_at_e0[0x720];
1791 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1792 u8 reserved_at_0[0x60];
1794 u8 reserved_at_60[0x4];
1795 u8 clamp_tgt_rate[0x1];
1796 u8 reserved_at_65[0x3];
1797 u8 clamp_tgt_rate_after_time_inc[0x1];
1798 u8 reserved_at_69[0x17];
1800 u8 reserved_at_80[0x20];
1802 u8 rpg_time_reset[0x20];
1804 u8 rpg_byte_reset[0x20];
1806 u8 rpg_threshold[0x20];
1808 u8 rpg_max_rate[0x20];
1810 u8 rpg_ai_rate[0x20];
1812 u8 rpg_hai_rate[0x20];
1816 u8 rpg_min_dec_fac[0x20];
1818 u8 rpg_min_rate[0x20];
1820 u8 reserved_at_1c0[0xe0];
1822 u8 rate_to_set_on_first_cnp[0x20];
1826 u8 dce_tcp_rtt[0x20];
1828 u8 rate_reduce_monitor_period[0x20];
1830 u8 reserved_at_320[0x20];
1832 u8 initial_alpha_value[0x20];
1834 u8 reserved_at_360[0x4a0];
1837 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1838 u8 reserved_at_0[0x80];
1840 u8 rppp_max_rps[0x20];
1842 u8 rpg_time_reset[0x20];
1844 u8 rpg_byte_reset[0x20];
1846 u8 rpg_threshold[0x20];
1848 u8 rpg_max_rate[0x20];
1850 u8 rpg_ai_rate[0x20];
1852 u8 rpg_hai_rate[0x20];
1856 u8 rpg_min_dec_fac[0x20];
1858 u8 rpg_min_rate[0x20];
1860 u8 reserved_at_1c0[0x640];
1864 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1865 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1866 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1869 struct mlx5_ifc_resize_field_select_bits {
1870 u8 resize_field_select[0x20];
1873 struct mlx5_ifc_resource_dump_bits {
1875 u8 inline_dump[0x1];
1876 u8 reserved_at_2[0xa];
1878 u8 segment_type[0x10];
1880 u8 reserved_at_20[0x10];
1887 u8 num_of_obj1[0x10];
1888 u8 num_of_obj2[0x10];
1890 u8 reserved_at_a0[0x20];
1892 u8 device_opaque[0x40];
1900 u8 inline_data[52][0x20];
1903 struct mlx5_ifc_resource_dump_menu_record_bits {
1904 u8 reserved_at_0[0x4];
1905 u8 num_of_obj2_supports_active[0x1];
1906 u8 num_of_obj2_supports_all[0x1];
1907 u8 must_have_num_of_obj2[0x1];
1908 u8 support_num_of_obj2[0x1];
1909 u8 num_of_obj1_supports_active[0x1];
1910 u8 num_of_obj1_supports_all[0x1];
1911 u8 must_have_num_of_obj1[0x1];
1912 u8 support_num_of_obj1[0x1];
1913 u8 must_have_index2[0x1];
1914 u8 support_index2[0x1];
1915 u8 must_have_index1[0x1];
1916 u8 support_index1[0x1];
1917 u8 segment_type[0x10];
1919 u8 segment_name[4][0x20];
1921 u8 index1_name[4][0x20];
1923 u8 index2_name[4][0x20];
1926 struct mlx5_ifc_resource_dump_segment_header_bits {
1928 u8 segment_type[0x10];
1931 struct mlx5_ifc_resource_dump_command_segment_bits {
1932 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1934 u8 segment_called[0x10];
1941 u8 num_of_obj1[0x10];
1942 u8 num_of_obj2[0x10];
1945 struct mlx5_ifc_resource_dump_error_segment_bits {
1946 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1948 u8 reserved_at_20[0x10];
1949 u8 syndrome_id[0x10];
1951 u8 reserved_at_40[0x40];
1956 struct mlx5_ifc_resource_dump_info_segment_bits {
1957 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1959 u8 reserved_at_20[0x18];
1960 u8 dump_version[0x8];
1962 u8 hw_version[0x20];
1964 u8 fw_version[0x20];
1967 struct mlx5_ifc_resource_dump_menu_segment_bits {
1968 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1970 u8 reserved_at_20[0x10];
1971 u8 num_of_records[0x10];
1973 struct mlx5_ifc_resource_dump_menu_record_bits record[];
1976 struct mlx5_ifc_resource_dump_resource_segment_bits {
1977 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1979 u8 reserved_at_20[0x20];
1988 struct mlx5_ifc_resource_dump_terminate_segment_bits {
1989 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1992 struct mlx5_ifc_menu_resource_dump_response_bits {
1993 struct mlx5_ifc_resource_dump_info_segment_bits info;
1994 struct mlx5_ifc_resource_dump_command_segment_bits cmd;
1995 struct mlx5_ifc_resource_dump_menu_segment_bits menu;
1996 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2000 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
2001 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
2002 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
2003 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
2006 struct mlx5_ifc_modify_field_select_bits {
2007 u8 modify_field_select[0x20];
2010 struct mlx5_ifc_field_select_r_roce_np_bits {
2011 u8 field_select_r_roce_np[0x20];
2014 struct mlx5_ifc_field_select_r_roce_rp_bits {
2015 u8 field_select_r_roce_rp[0x20];
2019 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
2020 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
2021 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
2022 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
2023 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
2024 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
2025 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
2026 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
2027 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
2028 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
2031 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2032 u8 field_select_8021qaurp[0x20];
2035 struct mlx5_ifc_phys_layer_cntrs_bits {
2036 u8 time_since_last_clear_high[0x20];
2038 u8 time_since_last_clear_low[0x20];
2040 u8 symbol_errors_high[0x20];
2042 u8 symbol_errors_low[0x20];
2044 u8 sync_headers_errors_high[0x20];
2046 u8 sync_headers_errors_low[0x20];
2048 u8 edpl_bip_errors_lane0_high[0x20];
2050 u8 edpl_bip_errors_lane0_low[0x20];
2052 u8 edpl_bip_errors_lane1_high[0x20];
2054 u8 edpl_bip_errors_lane1_low[0x20];
2056 u8 edpl_bip_errors_lane2_high[0x20];
2058 u8 edpl_bip_errors_lane2_low[0x20];
2060 u8 edpl_bip_errors_lane3_high[0x20];
2062 u8 edpl_bip_errors_lane3_low[0x20];
2064 u8 fc_fec_corrected_blocks_lane0_high[0x20];
2066 u8 fc_fec_corrected_blocks_lane0_low[0x20];
2068 u8 fc_fec_corrected_blocks_lane1_high[0x20];
2070 u8 fc_fec_corrected_blocks_lane1_low[0x20];
2072 u8 fc_fec_corrected_blocks_lane2_high[0x20];
2074 u8 fc_fec_corrected_blocks_lane2_low[0x20];
2076 u8 fc_fec_corrected_blocks_lane3_high[0x20];
2078 u8 fc_fec_corrected_blocks_lane3_low[0x20];
2080 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
2082 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
2084 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
2086 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
2088 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
2090 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
2092 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
2094 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
2096 u8 rs_fec_corrected_blocks_high[0x20];
2098 u8 rs_fec_corrected_blocks_low[0x20];
2100 u8 rs_fec_uncorrectable_blocks_high[0x20];
2102 u8 rs_fec_uncorrectable_blocks_low[0x20];
2104 u8 rs_fec_no_errors_blocks_high[0x20];
2106 u8 rs_fec_no_errors_blocks_low[0x20];
2108 u8 rs_fec_single_error_blocks_high[0x20];
2110 u8 rs_fec_single_error_blocks_low[0x20];
2112 u8 rs_fec_corrected_symbols_total_high[0x20];
2114 u8 rs_fec_corrected_symbols_total_low[0x20];
2116 u8 rs_fec_corrected_symbols_lane0_high[0x20];
2118 u8 rs_fec_corrected_symbols_lane0_low[0x20];
2120 u8 rs_fec_corrected_symbols_lane1_high[0x20];
2122 u8 rs_fec_corrected_symbols_lane1_low[0x20];
2124 u8 rs_fec_corrected_symbols_lane2_high[0x20];
2126 u8 rs_fec_corrected_symbols_lane2_low[0x20];
2128 u8 rs_fec_corrected_symbols_lane3_high[0x20];
2130 u8 rs_fec_corrected_symbols_lane3_low[0x20];
2132 u8 link_down_events[0x20];
2134 u8 successful_recovery_events[0x20];
2136 u8 reserved_at_640[0x180];
2139 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2140 u8 time_since_last_clear_high[0x20];
2142 u8 time_since_last_clear_low[0x20];
2144 u8 phy_received_bits_high[0x20];
2146 u8 phy_received_bits_low[0x20];
2148 u8 phy_symbol_errors_high[0x20];
2150 u8 phy_symbol_errors_low[0x20];
2152 u8 phy_corrected_bits_high[0x20];
2154 u8 phy_corrected_bits_low[0x20];
2156 u8 phy_corrected_bits_lane0_high[0x20];
2158 u8 phy_corrected_bits_lane0_low[0x20];
2160 u8 phy_corrected_bits_lane1_high[0x20];
2162 u8 phy_corrected_bits_lane1_low[0x20];
2164 u8 phy_corrected_bits_lane2_high[0x20];
2166 u8 phy_corrected_bits_lane2_low[0x20];
2168 u8 phy_corrected_bits_lane3_high[0x20];
2170 u8 phy_corrected_bits_lane3_low[0x20];
2172 u8 reserved_at_200[0x5c0];
2175 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2176 u8 symbol_error_counter[0x10];
2178 u8 link_error_recovery_counter[0x8];
2180 u8 link_downed_counter[0x8];
2182 u8 port_rcv_errors[0x10];
2184 u8 port_rcv_remote_physical_errors[0x10];
2186 u8 port_rcv_switch_relay_errors[0x10];
2188 u8 port_xmit_discards[0x10];
2190 u8 port_xmit_constraint_errors[0x8];
2192 u8 port_rcv_constraint_errors[0x8];
2194 u8 reserved_at_70[0x8];
2196 u8 link_overrun_errors[0x8];
2198 u8 reserved_at_80[0x10];
2200 u8 vl_15_dropped[0x10];
2202 u8 reserved_at_a0[0x80];
2204 u8 port_xmit_wait[0x20];
2207 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2208 u8 transmit_queue_high[0x20];
2210 u8 transmit_queue_low[0x20];
2212 u8 no_buffer_discard_uc_high[0x20];
2214 u8 no_buffer_discard_uc_low[0x20];
2216 u8 reserved_at_80[0x740];
2219 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2220 u8 wred_discard_high[0x20];
2222 u8 wred_discard_low[0x20];
2224 u8 ecn_marked_tc_high[0x20];
2226 u8 ecn_marked_tc_low[0x20];
2228 u8 reserved_at_80[0x740];
2231 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2232 u8 rx_octets_high[0x20];
2234 u8 rx_octets_low[0x20];
2236 u8 reserved_at_40[0xc0];
2238 u8 rx_frames_high[0x20];
2240 u8 rx_frames_low[0x20];
2242 u8 tx_octets_high[0x20];
2244 u8 tx_octets_low[0x20];
2246 u8 reserved_at_180[0xc0];
2248 u8 tx_frames_high[0x20];
2250 u8 tx_frames_low[0x20];
2252 u8 rx_pause_high[0x20];
2254 u8 rx_pause_low[0x20];
2256 u8 rx_pause_duration_high[0x20];
2258 u8 rx_pause_duration_low[0x20];
2260 u8 tx_pause_high[0x20];
2262 u8 tx_pause_low[0x20];
2264 u8 tx_pause_duration_high[0x20];
2266 u8 tx_pause_duration_low[0x20];
2268 u8 rx_pause_transition_high[0x20];
2270 u8 rx_pause_transition_low[0x20];
2272 u8 rx_discards_high[0x20];
2274 u8 rx_discards_low[0x20];
2276 u8 device_stall_minor_watermark_cnt_high[0x20];
2278 u8 device_stall_minor_watermark_cnt_low[0x20];
2280 u8 device_stall_critical_watermark_cnt_high[0x20];
2282 u8 device_stall_critical_watermark_cnt_low[0x20];
2284 u8 reserved_at_480[0x340];
2287 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2288 u8 port_transmit_wait_high[0x20];
2290 u8 port_transmit_wait_low[0x20];
2292 u8 reserved_at_40[0x100];
2294 u8 rx_buffer_almost_full_high[0x20];
2296 u8 rx_buffer_almost_full_low[0x20];
2298 u8 rx_buffer_full_high[0x20];
2300 u8 rx_buffer_full_low[0x20];
2302 u8 rx_icrc_encapsulated_high[0x20];
2304 u8 rx_icrc_encapsulated_low[0x20];
2306 u8 reserved_at_200[0x5c0];
2309 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2310 u8 dot3stats_alignment_errors_high[0x20];
2312 u8 dot3stats_alignment_errors_low[0x20];
2314 u8 dot3stats_fcs_errors_high[0x20];
2316 u8 dot3stats_fcs_errors_low[0x20];
2318 u8 dot3stats_single_collision_frames_high[0x20];
2320 u8 dot3stats_single_collision_frames_low[0x20];
2322 u8 dot3stats_multiple_collision_frames_high[0x20];
2324 u8 dot3stats_multiple_collision_frames_low[0x20];
2326 u8 dot3stats_sqe_test_errors_high[0x20];
2328 u8 dot3stats_sqe_test_errors_low[0x20];
2330 u8 dot3stats_deferred_transmissions_high[0x20];
2332 u8 dot3stats_deferred_transmissions_low[0x20];
2334 u8 dot3stats_late_collisions_high[0x20];
2336 u8 dot3stats_late_collisions_low[0x20];
2338 u8 dot3stats_excessive_collisions_high[0x20];
2340 u8 dot3stats_excessive_collisions_low[0x20];
2342 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
2344 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
2346 u8 dot3stats_carrier_sense_errors_high[0x20];
2348 u8 dot3stats_carrier_sense_errors_low[0x20];
2350 u8 dot3stats_frame_too_longs_high[0x20];
2352 u8 dot3stats_frame_too_longs_low[0x20];
2354 u8 dot3stats_internal_mac_receive_errors_high[0x20];
2356 u8 dot3stats_internal_mac_receive_errors_low[0x20];
2358 u8 dot3stats_symbol_errors_high[0x20];
2360 u8 dot3stats_symbol_errors_low[0x20];
2362 u8 dot3control_in_unknown_opcodes_high[0x20];
2364 u8 dot3control_in_unknown_opcodes_low[0x20];
2366 u8 dot3in_pause_frames_high[0x20];
2368 u8 dot3in_pause_frames_low[0x20];
2370 u8 dot3out_pause_frames_high[0x20];
2372 u8 dot3out_pause_frames_low[0x20];
2374 u8 reserved_at_400[0x3c0];
2377 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2378 u8 ether_stats_drop_events_high[0x20];
2380 u8 ether_stats_drop_events_low[0x20];
2382 u8 ether_stats_octets_high[0x20];
2384 u8 ether_stats_octets_low[0x20];
2386 u8 ether_stats_pkts_high[0x20];
2388 u8 ether_stats_pkts_low[0x20];
2390 u8 ether_stats_broadcast_pkts_high[0x20];
2392 u8 ether_stats_broadcast_pkts_low[0x20];
2394 u8 ether_stats_multicast_pkts_high[0x20];
2396 u8 ether_stats_multicast_pkts_low[0x20];
2398 u8 ether_stats_crc_align_errors_high[0x20];
2400 u8 ether_stats_crc_align_errors_low[0x20];
2402 u8 ether_stats_undersize_pkts_high[0x20];
2404 u8 ether_stats_undersize_pkts_low[0x20];
2406 u8 ether_stats_oversize_pkts_high[0x20];
2408 u8 ether_stats_oversize_pkts_low[0x20];
2410 u8 ether_stats_fragments_high[0x20];
2412 u8 ether_stats_fragments_low[0x20];
2414 u8 ether_stats_jabbers_high[0x20];
2416 u8 ether_stats_jabbers_low[0x20];
2418 u8 ether_stats_collisions_high[0x20];
2420 u8 ether_stats_collisions_low[0x20];
2422 u8 ether_stats_pkts64octets_high[0x20];
2424 u8 ether_stats_pkts64octets_low[0x20];
2426 u8 ether_stats_pkts65to127octets_high[0x20];
2428 u8 ether_stats_pkts65to127octets_low[0x20];
2430 u8 ether_stats_pkts128to255octets_high[0x20];
2432 u8 ether_stats_pkts128to255octets_low[0x20];
2434 u8 ether_stats_pkts256to511octets_high[0x20];
2436 u8 ether_stats_pkts256to511octets_low[0x20];
2438 u8 ether_stats_pkts512to1023octets_high[0x20];
2440 u8 ether_stats_pkts512to1023octets_low[0x20];
2442 u8 ether_stats_pkts1024to1518octets_high[0x20];
2444 u8 ether_stats_pkts1024to1518octets_low[0x20];
2446 u8 ether_stats_pkts1519to2047octets_high[0x20];
2448 u8 ether_stats_pkts1519to2047octets_low[0x20];
2450 u8 ether_stats_pkts2048to4095octets_high[0x20];
2452 u8 ether_stats_pkts2048to4095octets_low[0x20];
2454 u8 ether_stats_pkts4096to8191octets_high[0x20];
2456 u8 ether_stats_pkts4096to8191octets_low[0x20];
2458 u8 ether_stats_pkts8192to10239octets_high[0x20];
2460 u8 ether_stats_pkts8192to10239octets_low[0x20];
2462 u8 reserved_at_540[0x280];
2465 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2466 u8 if_in_octets_high[0x20];
2468 u8 if_in_octets_low[0x20];
2470 u8 if_in_ucast_pkts_high[0x20];
2472 u8 if_in_ucast_pkts_low[0x20];
2474 u8 if_in_discards_high[0x20];
2476 u8 if_in_discards_low[0x20];
2478 u8 if_in_errors_high[0x20];
2480 u8 if_in_errors_low[0x20];
2482 u8 if_in_unknown_protos_high[0x20];
2484 u8 if_in_unknown_protos_low[0x20];
2486 u8 if_out_octets_high[0x20];
2488 u8 if_out_octets_low[0x20];
2490 u8 if_out_ucast_pkts_high[0x20];
2492 u8 if_out_ucast_pkts_low[0x20];
2494 u8 if_out_discards_high[0x20];
2496 u8 if_out_discards_low[0x20];
2498 u8 if_out_errors_high[0x20];
2500 u8 if_out_errors_low[0x20];
2502 u8 if_in_multicast_pkts_high[0x20];
2504 u8 if_in_multicast_pkts_low[0x20];
2506 u8 if_in_broadcast_pkts_high[0x20];
2508 u8 if_in_broadcast_pkts_low[0x20];
2510 u8 if_out_multicast_pkts_high[0x20];
2512 u8 if_out_multicast_pkts_low[0x20];
2514 u8 if_out_broadcast_pkts_high[0x20];
2516 u8 if_out_broadcast_pkts_low[0x20];
2518 u8 reserved_at_340[0x480];
2521 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2522 u8 a_frames_transmitted_ok_high[0x20];
2524 u8 a_frames_transmitted_ok_low[0x20];
2526 u8 a_frames_received_ok_high[0x20];
2528 u8 a_frames_received_ok_low[0x20];
2530 u8 a_frame_check_sequence_errors_high[0x20];
2532 u8 a_frame_check_sequence_errors_low[0x20];
2534 u8 a_alignment_errors_high[0x20];
2536 u8 a_alignment_errors_low[0x20];
2538 u8 a_octets_transmitted_ok_high[0x20];
2540 u8 a_octets_transmitted_ok_low[0x20];
2542 u8 a_octets_received_ok_high[0x20];
2544 u8 a_octets_received_ok_low[0x20];
2546 u8 a_multicast_frames_xmitted_ok_high[0x20];
2548 u8 a_multicast_frames_xmitted_ok_low[0x20];
2550 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2552 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2554 u8 a_multicast_frames_received_ok_high[0x20];
2556 u8 a_multicast_frames_received_ok_low[0x20];
2558 u8 a_broadcast_frames_received_ok_high[0x20];
2560 u8 a_broadcast_frames_received_ok_low[0x20];
2562 u8 a_in_range_length_errors_high[0x20];
2564 u8 a_in_range_length_errors_low[0x20];
2566 u8 a_out_of_range_length_field_high[0x20];
2568 u8 a_out_of_range_length_field_low[0x20];
2570 u8 a_frame_too_long_errors_high[0x20];
2572 u8 a_frame_too_long_errors_low[0x20];
2574 u8 a_symbol_error_during_carrier_high[0x20];
2576 u8 a_symbol_error_during_carrier_low[0x20];
2578 u8 a_mac_control_frames_transmitted_high[0x20];
2580 u8 a_mac_control_frames_transmitted_low[0x20];
2582 u8 a_mac_control_frames_received_high[0x20];
2584 u8 a_mac_control_frames_received_low[0x20];
2586 u8 a_unsupported_opcodes_received_high[0x20];
2588 u8 a_unsupported_opcodes_received_low[0x20];
2590 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2592 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2594 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2596 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2598 u8 reserved_at_4c0[0x300];
2601 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2602 u8 life_time_counter_high[0x20];
2604 u8 life_time_counter_low[0x20];
2610 u8 l0_to_recovery_eieos[0x20];
2612 u8 l0_to_recovery_ts[0x20];
2614 u8 l0_to_recovery_framing[0x20];
2616 u8 l0_to_recovery_retrain[0x20];
2618 u8 crc_error_dllp[0x20];
2620 u8 crc_error_tlp[0x20];
2622 u8 tx_overflow_buffer_pkt_high[0x20];
2624 u8 tx_overflow_buffer_pkt_low[0x20];
2626 u8 outbound_stalled_reads[0x20];
2628 u8 outbound_stalled_writes[0x20];
2630 u8 outbound_stalled_reads_events[0x20];
2632 u8 outbound_stalled_writes_events[0x20];
2634 u8 reserved_at_200[0x5c0];
2637 struct mlx5_ifc_cmd_inter_comp_event_bits {
2638 u8 command_completion_vector[0x20];
2640 u8 reserved_at_20[0xc0];
2643 struct mlx5_ifc_stall_vl_event_bits {
2644 u8 reserved_at_0[0x18];
2646 u8 reserved_at_19[0x3];
2649 u8 reserved_at_20[0xa0];
2652 struct mlx5_ifc_db_bf_congestion_event_bits {
2653 u8 event_subtype[0x8];
2654 u8 reserved_at_8[0x8];
2655 u8 congestion_level[0x8];
2656 u8 reserved_at_18[0x8];
2658 u8 reserved_at_20[0xa0];
2661 struct mlx5_ifc_gpio_event_bits {
2662 u8 reserved_at_0[0x60];
2664 u8 gpio_event_hi[0x20];
2666 u8 gpio_event_lo[0x20];
2668 u8 reserved_at_a0[0x40];
2671 struct mlx5_ifc_port_state_change_event_bits {
2672 u8 reserved_at_0[0x40];
2675 u8 reserved_at_44[0x1c];
2677 u8 reserved_at_60[0x80];
2680 struct mlx5_ifc_dropped_packet_logged_bits {
2681 u8 reserved_at_0[0xe0];
2685 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2686 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2689 struct mlx5_ifc_cq_error_bits {
2690 u8 reserved_at_0[0x8];
2693 u8 reserved_at_20[0x20];
2695 u8 reserved_at_40[0x18];
2698 u8 reserved_at_60[0x80];
2701 struct mlx5_ifc_rdma_page_fault_event_bits {
2702 u8 bytes_committed[0x20];
2706 u8 reserved_at_40[0x10];
2707 u8 packet_len[0x10];
2709 u8 rdma_op_len[0x20];
2713 u8 reserved_at_c0[0x5];
2720 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2721 u8 bytes_committed[0x20];
2723 u8 reserved_at_20[0x10];
2726 u8 reserved_at_40[0x10];
2729 u8 reserved_at_60[0x60];
2731 u8 reserved_at_c0[0x5];
2738 struct mlx5_ifc_qp_events_bits {
2739 u8 reserved_at_0[0xa0];
2742 u8 reserved_at_a8[0x18];
2744 u8 reserved_at_c0[0x8];
2745 u8 qpn_rqn_sqn[0x18];
2748 struct mlx5_ifc_dct_events_bits {
2749 u8 reserved_at_0[0xc0];
2751 u8 reserved_at_c0[0x8];
2752 u8 dct_number[0x18];
2755 struct mlx5_ifc_comp_event_bits {
2756 u8 reserved_at_0[0xc0];
2758 u8 reserved_at_c0[0x8];
2763 MLX5_QPC_STATE_RST = 0x0,
2764 MLX5_QPC_STATE_INIT = 0x1,
2765 MLX5_QPC_STATE_RTR = 0x2,
2766 MLX5_QPC_STATE_RTS = 0x3,
2767 MLX5_QPC_STATE_SQER = 0x4,
2768 MLX5_QPC_STATE_ERR = 0x6,
2769 MLX5_QPC_STATE_SQD = 0x7,
2770 MLX5_QPC_STATE_SUSPENDED = 0x9,
2774 MLX5_QPC_ST_RC = 0x0,
2775 MLX5_QPC_ST_UC = 0x1,
2776 MLX5_QPC_ST_UD = 0x2,
2777 MLX5_QPC_ST_XRC = 0x3,
2778 MLX5_QPC_ST_DCI = 0x5,
2779 MLX5_QPC_ST_QP0 = 0x7,
2780 MLX5_QPC_ST_QP1 = 0x8,
2781 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2782 MLX5_QPC_ST_REG_UMR = 0xc,
2786 MLX5_QPC_PM_STATE_ARMED = 0x0,
2787 MLX5_QPC_PM_STATE_REARM = 0x1,
2788 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2789 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2793 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2797 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2798 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2802 MLX5_QPC_MTU_256_BYTES = 0x1,
2803 MLX5_QPC_MTU_512_BYTES = 0x2,
2804 MLX5_QPC_MTU_1K_BYTES = 0x3,
2805 MLX5_QPC_MTU_2K_BYTES = 0x4,
2806 MLX5_QPC_MTU_4K_BYTES = 0x5,
2807 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2811 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2812 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2813 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2814 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2815 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2816 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2817 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2818 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2822 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2823 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2824 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2828 MLX5_QPC_CS_RES_DISABLE = 0x0,
2829 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2830 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2833 struct mlx5_ifc_qpc_bits {
2835 u8 lag_tx_port_affinity[0x4];
2837 u8 reserved_at_10[0x3];
2839 u8 reserved_at_15[0x1];
2840 u8 req_e2e_credit_mode[0x2];
2841 u8 offload_type[0x4];
2842 u8 end_padding_mode[0x2];
2843 u8 reserved_at_1e[0x2];
2845 u8 wq_signature[0x1];
2846 u8 block_lb_mc[0x1];
2847 u8 atomic_like_write_en[0x1];
2848 u8 latency_sensitive[0x1];
2849 u8 reserved_at_24[0x1];
2850 u8 drain_sigerr[0x1];
2851 u8 reserved_at_26[0x2];
2855 u8 log_msg_max[0x5];
2856 u8 reserved_at_48[0x1];
2857 u8 log_rq_size[0x4];
2858 u8 log_rq_stride[0x3];
2860 u8 log_sq_size[0x4];
2861 u8 reserved_at_55[0x6];
2863 u8 ulp_stateless_offload_mode[0x4];
2865 u8 counter_set_id[0x8];
2868 u8 reserved_at_80[0x8];
2869 u8 user_index[0x18];
2871 u8 reserved_at_a0[0x3];
2872 u8 log_page_size[0x5];
2873 u8 remote_qpn[0x18];
2875 struct mlx5_ifc_ads_bits primary_address_path;
2877 struct mlx5_ifc_ads_bits secondary_address_path;
2879 u8 log_ack_req_freq[0x4];
2880 u8 reserved_at_384[0x4];
2881 u8 log_sra_max[0x3];
2882 u8 reserved_at_38b[0x2];
2883 u8 retry_count[0x3];
2885 u8 reserved_at_393[0x1];
2887 u8 cur_rnr_retry[0x3];
2888 u8 cur_retry_count[0x3];
2889 u8 reserved_at_39b[0x5];
2891 u8 reserved_at_3a0[0x20];
2893 u8 reserved_at_3c0[0x8];
2894 u8 next_send_psn[0x18];
2896 u8 reserved_at_3e0[0x8];
2899 u8 reserved_at_400[0x8];
2902 u8 reserved_at_420[0x20];
2904 u8 reserved_at_440[0x8];
2905 u8 last_acked_psn[0x18];
2907 u8 reserved_at_460[0x8];
2910 u8 reserved_at_480[0x8];
2911 u8 log_rra_max[0x3];
2912 u8 reserved_at_48b[0x1];
2913 u8 atomic_mode[0x4];
2917 u8 reserved_at_493[0x1];
2918 u8 page_offset[0x6];
2919 u8 reserved_at_49a[0x3];
2920 u8 cd_slave_receive[0x1];
2921 u8 cd_slave_send[0x1];
2924 u8 reserved_at_4a0[0x3];
2925 u8 min_rnr_nak[0x5];
2926 u8 next_rcv_psn[0x18];
2928 u8 reserved_at_4c0[0x8];
2931 u8 reserved_at_4e0[0x8];
2938 u8 reserved_at_560[0x5];
2940 u8 srqn_rmpn_xrqn[0x18];
2942 u8 reserved_at_580[0x8];
2945 u8 hw_sq_wqebb_counter[0x10];
2946 u8 sw_sq_wqebb_counter[0x10];
2948 u8 hw_rq_counter[0x20];
2950 u8 sw_rq_counter[0x20];
2952 u8 reserved_at_600[0x20];
2954 u8 reserved_at_620[0xf];
2959 u8 dc_access_key[0x40];
2961 u8 reserved_at_680[0x3];
2962 u8 dbr_umem_valid[0x1];
2964 u8 reserved_at_684[0xbc];
2967 struct mlx5_ifc_roce_addr_layout_bits {
2968 u8 source_l3_address[16][0x8];
2970 u8 reserved_at_80[0x3];
2973 u8 source_mac_47_32[0x10];
2975 u8 source_mac_31_0[0x20];
2977 u8 reserved_at_c0[0x14];
2978 u8 roce_l3_type[0x4];
2979 u8 roce_version[0x8];
2981 u8 reserved_at_e0[0x20];
2984 union mlx5_ifc_hca_cap_union_bits {
2985 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2986 struct mlx5_ifc_odp_cap_bits odp_cap;
2987 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2988 struct mlx5_ifc_roce_cap_bits roce_cap;
2989 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2990 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2991 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2992 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2993 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2994 struct mlx5_ifc_qos_cap_bits qos_cap;
2995 struct mlx5_ifc_debug_cap_bits debug_cap;
2996 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2997 struct mlx5_ifc_tls_cap_bits tls_cap;
2998 struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
2999 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3000 u8 reserved_at_0[0x8000];
3004 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
3005 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
3006 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
3007 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
3008 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3009 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
3010 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
3011 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
3012 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3013 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
3014 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3015 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000,
3016 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000,
3020 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
3021 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
3022 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
3025 struct mlx5_ifc_vlan_bits {
3032 struct mlx5_ifc_flow_context_bits {
3033 struct mlx5_ifc_vlan_bits push_vlan;
3037 u8 reserved_at_40[0x8];
3040 u8 reserved_at_60[0x10];
3043 u8 extended_destination[0x1];
3044 u8 reserved_at_81[0x1];
3045 u8 flow_source[0x2];
3046 u8 reserved_at_84[0x4];
3047 u8 destination_list_size[0x18];
3049 u8 reserved_at_a0[0x8];
3050 u8 flow_counter_list_size[0x18];
3052 u8 packet_reformat_id[0x20];
3054 u8 modify_header_id[0x20];
3056 struct mlx5_ifc_vlan_bits push_vlan_2;
3058 u8 ipsec_obj_id[0x20];
3059 u8 reserved_at_140[0xc0];
3061 struct mlx5_ifc_fte_match_param_bits match_value;
3063 u8 reserved_at_1200[0x600];
3065 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3069 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
3070 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
3073 struct mlx5_ifc_xrc_srqc_bits {
3075 u8 log_xrc_srq_size[0x4];
3076 u8 reserved_at_8[0x18];
3078 u8 wq_signature[0x1];
3080 u8 reserved_at_22[0x1];
3082 u8 basic_cyclic_rcv_wqe[0x1];
3083 u8 log_rq_stride[0x3];
3086 u8 page_offset[0x6];
3087 u8 reserved_at_46[0x1];
3088 u8 dbr_umem_valid[0x1];
3091 u8 reserved_at_60[0x20];
3093 u8 user_index_equal_xrc_srqn[0x1];
3094 u8 reserved_at_81[0x1];
3095 u8 log_page_size[0x6];
3096 u8 user_index[0x18];
3098 u8 reserved_at_a0[0x20];
3100 u8 reserved_at_c0[0x8];
3106 u8 reserved_at_100[0x40];
3108 u8 db_record_addr_h[0x20];
3110 u8 db_record_addr_l[0x1e];
3111 u8 reserved_at_17e[0x2];
3113 u8 reserved_at_180[0x80];
3116 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3117 u8 counter_error_queues[0x20];
3119 u8 total_error_queues[0x20];
3121 u8 send_queue_priority_update_flow[0x20];
3123 u8 reserved_at_60[0x20];
3125 u8 nic_receive_steering_discard[0x40];
3127 u8 receive_discard_vport_down[0x40];
3129 u8 transmit_discard_vport_down[0x40];
3131 u8 reserved_at_140[0xa0];
3133 u8 internal_rq_out_of_buffer[0x20];
3135 u8 reserved_at_200[0xe00];
3138 struct mlx5_ifc_traffic_counter_bits {
3144 struct mlx5_ifc_tisc_bits {
3145 u8 strict_lag_tx_port_affinity[0x1];
3147 u8 reserved_at_2[0x2];
3148 u8 lag_tx_port_affinity[0x04];
3150 u8 reserved_at_8[0x4];
3152 u8 reserved_at_10[0x10];
3154 u8 reserved_at_20[0x100];
3156 u8 reserved_at_120[0x8];
3157 u8 transport_domain[0x18];
3159 u8 reserved_at_140[0x8];
3160 u8 underlay_qpn[0x18];
3162 u8 reserved_at_160[0x8];
3165 u8 reserved_at_180[0x380];
3169 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
3170 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
3174 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
3175 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
3179 MLX5_RX_HASH_FN_NONE = 0x0,
3180 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
3181 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
3185 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
3186 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
3189 struct mlx5_ifc_tirc_bits {
3190 u8 reserved_at_0[0x20];
3194 u8 reserved_at_25[0x1b];
3196 u8 reserved_at_40[0x40];
3198 u8 reserved_at_80[0x4];
3199 u8 lro_timeout_period_usecs[0x10];
3200 u8 lro_enable_mask[0x4];
3201 u8 lro_max_ip_payload_size[0x8];
3203 u8 reserved_at_a0[0x40];
3205 u8 reserved_at_e0[0x8];
3206 u8 inline_rqn[0x18];
3208 u8 rx_hash_symmetric[0x1];
3209 u8 reserved_at_101[0x1];
3210 u8 tunneled_offload_en[0x1];
3211 u8 reserved_at_103[0x5];
3212 u8 indirect_table[0x18];
3215 u8 reserved_at_124[0x2];
3216 u8 self_lb_block[0x2];
3217 u8 transport_domain[0x18];
3219 u8 rx_hash_toeplitz_key[10][0x20];
3221 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3223 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3225 u8 reserved_at_2c0[0x4c0];
3229 MLX5_SRQC_STATE_GOOD = 0x0,
3230 MLX5_SRQC_STATE_ERROR = 0x1,
3233 struct mlx5_ifc_srqc_bits {
3235 u8 log_srq_size[0x4];
3236 u8 reserved_at_8[0x18];
3238 u8 wq_signature[0x1];
3240 u8 reserved_at_22[0x1];
3242 u8 reserved_at_24[0x1];
3243 u8 log_rq_stride[0x3];
3246 u8 page_offset[0x6];
3247 u8 reserved_at_46[0x2];
3250 u8 reserved_at_60[0x20];
3252 u8 reserved_at_80[0x2];
3253 u8 log_page_size[0x6];
3254 u8 reserved_at_88[0x18];
3256 u8 reserved_at_a0[0x20];
3258 u8 reserved_at_c0[0x8];
3264 u8 reserved_at_100[0x40];
3268 u8 reserved_at_180[0x80];
3272 MLX5_SQC_STATE_RST = 0x0,
3273 MLX5_SQC_STATE_RDY = 0x1,
3274 MLX5_SQC_STATE_ERR = 0x3,
3277 struct mlx5_ifc_sqc_bits {
3281 u8 flush_in_error_en[0x1];
3282 u8 allow_multi_pkt_send_wqe[0x1];
3283 u8 min_wqe_inline_mode[0x3];
3288 u8 reserved_at_f[0x11];
3290 u8 reserved_at_20[0x8];
3291 u8 user_index[0x18];
3293 u8 reserved_at_40[0x8];
3296 u8 reserved_at_60[0x8];
3297 u8 hairpin_peer_rq[0x18];
3299 u8 reserved_at_80[0x10];
3300 u8 hairpin_peer_vhca[0x10];
3302 u8 reserved_at_a0[0x50];
3304 u8 packet_pacing_rate_limit_index[0x10];
3305 u8 tis_lst_sz[0x10];
3306 u8 reserved_at_110[0x10];
3308 u8 reserved_at_120[0x40];
3310 u8 reserved_at_160[0x8];
3313 struct mlx5_ifc_wq_bits wq;
3317 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3318 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3319 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3320 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3324 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0,
3325 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1,
3326 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2,
3327 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,
3330 struct mlx5_ifc_scheduling_context_bits {
3331 u8 element_type[0x8];
3332 u8 reserved_at_8[0x18];
3334 u8 element_attributes[0x20];
3336 u8 parent_element_id[0x20];
3338 u8 reserved_at_60[0x40];
3342 u8 max_average_bw[0x20];
3344 u8 reserved_at_e0[0x120];
3347 struct mlx5_ifc_rqtc_bits {
3348 u8 reserved_at_0[0xa0];
3350 u8 reserved_at_a0[0x5];
3351 u8 list_q_type[0x3];
3352 u8 reserved_at_a8[0x8];
3353 u8 rqt_max_size[0x10];
3355 u8 rq_vhca_id_format[0x1];
3356 u8 reserved_at_c1[0xf];
3357 u8 rqt_actual_size[0x10];
3359 u8 reserved_at_e0[0x6a0];
3361 struct mlx5_ifc_rq_num_bits rq_num[];
3365 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
3366 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
3370 MLX5_RQC_STATE_RST = 0x0,
3371 MLX5_RQC_STATE_RDY = 0x1,
3372 MLX5_RQC_STATE_ERR = 0x3,
3375 struct mlx5_ifc_rqc_bits {
3377 u8 delay_drop_en[0x1];
3378 u8 scatter_fcs[0x1];
3380 u8 mem_rq_type[0x4];
3382 u8 reserved_at_c[0x1];
3383 u8 flush_in_error_en[0x1];
3385 u8 reserved_at_f[0x11];
3387 u8 reserved_at_20[0x8];
3388 u8 user_index[0x18];
3390 u8 reserved_at_40[0x8];
3393 u8 counter_set_id[0x8];
3394 u8 reserved_at_68[0x18];
3396 u8 reserved_at_80[0x8];
3399 u8 reserved_at_a0[0x8];
3400 u8 hairpin_peer_sq[0x18];
3402 u8 reserved_at_c0[0x10];
3403 u8 hairpin_peer_vhca[0x10];
3405 u8 reserved_at_e0[0xa0];
3407 struct mlx5_ifc_wq_bits wq;
3411 MLX5_RMPC_STATE_RDY = 0x1,
3412 MLX5_RMPC_STATE_ERR = 0x3,
3415 struct mlx5_ifc_rmpc_bits {
3416 u8 reserved_at_0[0x8];
3418 u8 reserved_at_c[0x14];
3420 u8 basic_cyclic_rcv_wqe[0x1];
3421 u8 reserved_at_21[0x1f];
3423 u8 reserved_at_40[0x140];
3425 struct mlx5_ifc_wq_bits wq;
3428 struct mlx5_ifc_nic_vport_context_bits {
3429 u8 reserved_at_0[0x5];
3430 u8 min_wqe_inline_mode[0x3];
3431 u8 reserved_at_8[0x15];
3432 u8 disable_mc_local_lb[0x1];
3433 u8 disable_uc_local_lb[0x1];
3436 u8 arm_change_event[0x1];
3437 u8 reserved_at_21[0x1a];
3438 u8 event_on_mtu[0x1];
3439 u8 event_on_promisc_change[0x1];
3440 u8 event_on_vlan_change[0x1];
3441 u8 event_on_mc_address_change[0x1];
3442 u8 event_on_uc_address_change[0x1];
3444 u8 reserved_at_40[0xc];
3446 u8 affiliation_criteria[0x4];
3447 u8 affiliated_vhca_id[0x10];
3449 u8 reserved_at_60[0xd0];
3453 u8 system_image_guid[0x40];
3457 u8 reserved_at_200[0x140];
3458 u8 qkey_violation_counter[0x10];
3459 u8 reserved_at_350[0x430];
3463 u8 promisc_all[0x1];
3464 u8 reserved_at_783[0x2];
3465 u8 allowed_list_type[0x3];
3466 u8 reserved_at_788[0xc];
3467 u8 allowed_list_size[0xc];
3469 struct mlx5_ifc_mac_address_layout_bits permanent_address;
3471 u8 reserved_at_7e0[0x20];
3473 u8 current_uc_mac_address[][0x40];
3477 MLX5_MKC_ACCESS_MODE_PA = 0x0,
3478 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
3479 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
3480 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
3481 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3482 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3485 struct mlx5_ifc_mkc_bits {
3486 u8 reserved_at_0[0x1];
3488 u8 reserved_at_2[0x1];
3489 u8 access_mode_4_2[0x3];
3490 u8 reserved_at_6[0x7];
3491 u8 relaxed_ordering_write[0x1];
3492 u8 reserved_at_e[0x1];
3493 u8 small_fence_on_rdma_read_response[0x1];
3500 u8 access_mode_1_0[0x2];
3501 u8 reserved_at_18[0x8];
3506 u8 reserved_at_40[0x20];
3511 u8 reserved_at_63[0x2];
3512 u8 expected_sigerr_count[0x1];
3513 u8 reserved_at_66[0x1];
3517 u8 start_addr[0x40];
3521 u8 bsf_octword_size[0x20];
3523 u8 reserved_at_120[0x80];
3525 u8 translations_octword_size[0x20];
3527 u8 reserved_at_1c0[0x19];
3528 u8 relaxed_ordering_read[0x1];
3529 u8 reserved_at_1d9[0x1];
3530 u8 log_page_size[0x5];
3532 u8 reserved_at_1e0[0x20];
3535 struct mlx5_ifc_pkey_bits {
3536 u8 reserved_at_0[0x10];
3540 struct mlx5_ifc_array128_auto_bits {
3541 u8 array128_auto[16][0x8];
3544 struct mlx5_ifc_hca_vport_context_bits {
3545 u8 field_select[0x20];
3547 u8 reserved_at_20[0xe0];
3549 u8 sm_virt_aware[0x1];
3552 u8 grh_required[0x1];
3553 u8 reserved_at_104[0xc];
3554 u8 port_physical_state[0x4];
3555 u8 vport_state_policy[0x4];
3557 u8 vport_state[0x4];
3559 u8 reserved_at_120[0x20];
3561 u8 system_image_guid[0x40];
3569 u8 cap_mask1_field_select[0x20];
3573 u8 cap_mask2_field_select[0x20];
3575 u8 reserved_at_280[0x80];
3578 u8 reserved_at_310[0x4];
3579 u8 init_type_reply[0x4];
3581 u8 subnet_timeout[0x5];
3585 u8 reserved_at_334[0xc];
3587 u8 qkey_violation_counter[0x10];
3588 u8 pkey_violation_counter[0x10];
3590 u8 reserved_at_360[0xca0];
3593 struct mlx5_ifc_esw_vport_context_bits {
3594 u8 fdb_to_vport_reg_c[0x1];
3595 u8 reserved_at_1[0x2];
3596 u8 vport_svlan_strip[0x1];
3597 u8 vport_cvlan_strip[0x1];
3598 u8 vport_svlan_insert[0x1];
3599 u8 vport_cvlan_insert[0x2];
3600 u8 fdb_to_vport_reg_c_id[0x8];
3601 u8 reserved_at_10[0x10];
3603 u8 reserved_at_20[0x20];
3612 u8 reserved_at_60[0x720];
3614 u8 sw_steering_vport_icm_address_rx[0x40];
3616 u8 sw_steering_vport_icm_address_tx[0x40];
3620 MLX5_EQC_STATUS_OK = 0x0,
3621 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
3625 MLX5_EQC_ST_ARMED = 0x9,
3626 MLX5_EQC_ST_FIRED = 0xa,
3629 struct mlx5_ifc_eqc_bits {
3631 u8 reserved_at_4[0x9];
3634 u8 reserved_at_f[0x5];
3636 u8 reserved_at_18[0x8];
3638 u8 reserved_at_20[0x20];
3640 u8 reserved_at_40[0x14];
3641 u8 page_offset[0x6];
3642 u8 reserved_at_5a[0x6];
3644 u8 reserved_at_60[0x3];
3645 u8 log_eq_size[0x5];
3648 u8 reserved_at_80[0x20];
3650 u8 reserved_at_a0[0x18];
3653 u8 reserved_at_c0[0x3];
3654 u8 log_page_size[0x5];
3655 u8 reserved_at_c8[0x18];
3657 u8 reserved_at_e0[0x60];
3659 u8 reserved_at_140[0x8];
3660 u8 consumer_counter[0x18];
3662 u8 reserved_at_160[0x8];
3663 u8 producer_counter[0x18];
3665 u8 reserved_at_180[0x80];
3669 MLX5_DCTC_STATE_ACTIVE = 0x0,
3670 MLX5_DCTC_STATE_DRAINING = 0x1,
3671 MLX5_DCTC_STATE_DRAINED = 0x2,
3675 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3676 MLX5_DCTC_CS_RES_NA = 0x1,
3677 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3681 MLX5_DCTC_MTU_256_BYTES = 0x1,
3682 MLX5_DCTC_MTU_512_BYTES = 0x2,
3683 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3684 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3685 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3688 struct mlx5_ifc_dctc_bits {
3689 u8 reserved_at_0[0x4];
3691 u8 reserved_at_8[0x18];
3693 u8 reserved_at_20[0x8];
3694 u8 user_index[0x18];
3696 u8 reserved_at_40[0x8];
3699 u8 counter_set_id[0x8];
3700 u8 atomic_mode[0x4];
3704 u8 atomic_like_write_en[0x1];
3705 u8 latency_sensitive[0x1];
3708 u8 reserved_at_73[0xd];
3710 u8 reserved_at_80[0x8];
3712 u8 reserved_at_90[0x3];
3713 u8 min_rnr_nak[0x5];
3714 u8 reserved_at_98[0x8];
3716 u8 reserved_at_a0[0x8];
3719 u8 reserved_at_c0[0x8];
3723 u8 reserved_at_e8[0x4];
3724 u8 flow_label[0x14];
3726 u8 dc_access_key[0x40];
3728 u8 reserved_at_140[0x5];
3731 u8 pkey_index[0x10];
3733 u8 reserved_at_160[0x8];
3734 u8 my_addr_index[0x8];
3735 u8 reserved_at_170[0x8];
3738 u8 dc_access_key_violation_count[0x20];
3740 u8 reserved_at_1a0[0x14];
3746 u8 reserved_at_1c0[0x20];
3751 MLX5_CQC_STATUS_OK = 0x0,
3752 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3753 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3757 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3758 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3762 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3763 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3764 MLX5_CQC_ST_FIRED = 0xa,
3768 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3769 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3770 MLX5_CQ_PERIOD_NUM_MODES
3773 struct mlx5_ifc_cqc_bits {
3775 u8 reserved_at_4[0x2];
3776 u8 dbr_umem_valid[0x1];
3777 u8 reserved_at_7[0x1];
3780 u8 reserved_at_c[0x1];
3781 u8 scqe_break_moderation_en[0x1];
3783 u8 cq_period_mode[0x2];
3784 u8 cqe_comp_en[0x1];
3785 u8 mini_cqe_res_format[0x2];
3787 u8 reserved_at_18[0x8];
3789 u8 reserved_at_20[0x20];
3791 u8 reserved_at_40[0x14];
3792 u8 page_offset[0x6];
3793 u8 reserved_at_5a[0x6];
3795 u8 reserved_at_60[0x3];
3796 u8 log_cq_size[0x5];
3799 u8 reserved_at_80[0x4];
3801 u8 cq_max_count[0x10];
3803 u8 reserved_at_a0[0x18];
3806 u8 reserved_at_c0[0x3];
3807 u8 log_page_size[0x5];
3808 u8 reserved_at_c8[0x18];
3810 u8 reserved_at_e0[0x20];
3812 u8 reserved_at_100[0x8];
3813 u8 last_notified_index[0x18];
3815 u8 reserved_at_120[0x8];
3816 u8 last_solicit_index[0x18];
3818 u8 reserved_at_140[0x8];
3819 u8 consumer_counter[0x18];
3821 u8 reserved_at_160[0x8];
3822 u8 producer_counter[0x18];
3824 u8 reserved_at_180[0x40];
3829 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3830 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3831 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3832 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3833 u8 reserved_at_0[0x800];
3836 struct mlx5_ifc_query_adapter_param_block_bits {
3837 u8 reserved_at_0[0xc0];
3839 u8 reserved_at_c0[0x8];
3840 u8 ieee_vendor_id[0x18];
3842 u8 reserved_at_e0[0x10];
3843 u8 vsd_vendor_id[0x10];
3847 u8 vsd_contd_psid[16][0x8];
3851 MLX5_XRQC_STATE_GOOD = 0x0,
3852 MLX5_XRQC_STATE_ERROR = 0x1,
3856 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3857 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3861 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3864 struct mlx5_ifc_tag_matching_topology_context_bits {
3865 u8 log_matching_list_sz[0x4];
3866 u8 reserved_at_4[0xc];
3867 u8 append_next_index[0x10];
3869 u8 sw_phase_cnt[0x10];
3870 u8 hw_phase_cnt[0x10];
3872 u8 reserved_at_40[0x40];
3875 struct mlx5_ifc_xrqc_bits {
3878 u8 reserved_at_5[0xf];
3880 u8 reserved_at_18[0x4];
3883 u8 reserved_at_20[0x8];
3884 u8 user_index[0x18];
3886 u8 reserved_at_40[0x8];
3889 u8 reserved_at_60[0xa0];
3891 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3893 u8 reserved_at_180[0x280];
3895 struct mlx5_ifc_wq_bits wq;
3898 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3899 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3900 struct mlx5_ifc_resize_field_select_bits resize_field_select;
3901 u8 reserved_at_0[0x20];
3904 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3905 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3906 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3907 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3908 u8 reserved_at_0[0x20];
3911 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3912 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3913 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3914 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3915 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3916 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3917 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3918 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
3919 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
3920 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3921 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3922 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3923 u8 reserved_at_0[0x7c0];
3926 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3927 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3928 u8 reserved_at_0[0x7c0];
3931 union mlx5_ifc_event_auto_bits {
3932 struct mlx5_ifc_comp_event_bits comp_event;
3933 struct mlx5_ifc_dct_events_bits dct_events;
3934 struct mlx5_ifc_qp_events_bits qp_events;
3935 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3936 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3937 struct mlx5_ifc_cq_error_bits cq_error;
3938 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3939 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3940 struct mlx5_ifc_gpio_event_bits gpio_event;
3941 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3942 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3943 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3944 u8 reserved_at_0[0xe0];
3947 struct mlx5_ifc_health_buffer_bits {
3948 u8 reserved_at_0[0x100];
3950 u8 assert_existptr[0x20];
3952 u8 assert_callra[0x20];
3954 u8 reserved_at_140[0x40];
3956 u8 fw_version[0x20];
3960 u8 reserved_at_1c0[0x20];
3962 u8 irisc_index[0x8];
3967 struct mlx5_ifc_register_loopback_control_bits {
3969 u8 reserved_at_1[0x7];
3971 u8 reserved_at_10[0x10];
3973 u8 reserved_at_20[0x60];
3976 struct mlx5_ifc_vport_tc_element_bits {
3977 u8 traffic_class[0x4];
3978 u8 reserved_at_4[0xc];
3979 u8 vport_number[0x10];
3982 struct mlx5_ifc_vport_element_bits {
3983 u8 reserved_at_0[0x10];
3984 u8 vport_number[0x10];
3988 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3989 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3990 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3993 struct mlx5_ifc_tsar_element_bits {
3994 u8 reserved_at_0[0x8];
3996 u8 reserved_at_10[0x10];
4000 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4001 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4004 struct mlx5_ifc_teardown_hca_out_bits {
4006 u8 reserved_at_8[0x18];
4010 u8 reserved_at_40[0x3f];
4016 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
4017 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
4018 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4021 struct mlx5_ifc_teardown_hca_in_bits {
4023 u8 reserved_at_10[0x10];
4025 u8 reserved_at_20[0x10];
4028 u8 reserved_at_40[0x10];
4031 u8 reserved_at_60[0x20];
4034 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4036 u8 reserved_at_8[0x18];
4040 u8 reserved_at_40[0x40];
4043 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4047 u8 reserved_at_20[0x10];
4050 u8 reserved_at_40[0x8];
4053 u8 reserved_at_60[0x20];
4055 u8 opt_param_mask[0x20];
4057 u8 reserved_at_a0[0x20];
4059 struct mlx5_ifc_qpc_bits qpc;
4061 u8 reserved_at_800[0x80];
4064 struct mlx5_ifc_sqd2rts_qp_out_bits {
4066 u8 reserved_at_8[0x18];
4070 u8 reserved_at_40[0x40];
4073 struct mlx5_ifc_sqd2rts_qp_in_bits {
4077 u8 reserved_at_20[0x10];
4080 u8 reserved_at_40[0x8];
4083 u8 reserved_at_60[0x20];
4085 u8 opt_param_mask[0x20];
4087 u8 reserved_at_a0[0x20];
4089 struct mlx5_ifc_qpc_bits qpc;
4091 u8 reserved_at_800[0x80];
4094 struct mlx5_ifc_set_roce_address_out_bits {
4096 u8 reserved_at_8[0x18];
4100 u8 reserved_at_40[0x40];
4103 struct mlx5_ifc_set_roce_address_in_bits {
4105 u8 reserved_at_10[0x10];
4107 u8 reserved_at_20[0x10];
4110 u8 roce_address_index[0x10];
4111 u8 reserved_at_50[0xc];
4112 u8 vhca_port_num[0x4];
4114 u8 reserved_at_60[0x20];
4116 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4119 struct mlx5_ifc_set_mad_demux_out_bits {
4121 u8 reserved_at_8[0x18];
4125 u8 reserved_at_40[0x40];
4129 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
4130 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
4133 struct mlx5_ifc_set_mad_demux_in_bits {
4135 u8 reserved_at_10[0x10];
4137 u8 reserved_at_20[0x10];
4140 u8 reserved_at_40[0x20];
4142 u8 reserved_at_60[0x6];
4144 u8 reserved_at_68[0x18];
4147 struct mlx5_ifc_set_l2_table_entry_out_bits {
4149 u8 reserved_at_8[0x18];
4153 u8 reserved_at_40[0x40];
4156 struct mlx5_ifc_set_l2_table_entry_in_bits {
4158 u8 reserved_at_10[0x10];
4160 u8 reserved_at_20[0x10];
4163 u8 reserved_at_40[0x60];
4165 u8 reserved_at_a0[0x8];
4166 u8 table_index[0x18];
4168 u8 reserved_at_c0[0x20];
4170 u8 reserved_at_e0[0x13];
4174 struct mlx5_ifc_mac_address_layout_bits mac_address;
4176 u8 reserved_at_140[0xc0];
4179 struct mlx5_ifc_set_issi_out_bits {
4181 u8 reserved_at_8[0x18];
4185 u8 reserved_at_40[0x40];
4188 struct mlx5_ifc_set_issi_in_bits {
4190 u8 reserved_at_10[0x10];
4192 u8 reserved_at_20[0x10];
4195 u8 reserved_at_40[0x10];
4196 u8 current_issi[0x10];
4198 u8 reserved_at_60[0x20];
4201 struct mlx5_ifc_set_hca_cap_out_bits {
4203 u8 reserved_at_8[0x18];
4207 u8 reserved_at_40[0x40];
4210 struct mlx5_ifc_set_hca_cap_in_bits {
4212 u8 reserved_at_10[0x10];
4214 u8 reserved_at_20[0x10];
4217 u8 reserved_at_40[0x40];
4219 union mlx5_ifc_hca_cap_union_bits capability;
4223 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
4224 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
4225 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
4226 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3,
4227 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4
4230 struct mlx5_ifc_set_fte_out_bits {
4232 u8 reserved_at_8[0x18];
4236 u8 reserved_at_40[0x40];
4239 struct mlx5_ifc_set_fte_in_bits {
4241 u8 reserved_at_10[0x10];
4243 u8 reserved_at_20[0x10];
4246 u8 other_vport[0x1];
4247 u8 reserved_at_41[0xf];
4248 u8 vport_number[0x10];
4250 u8 reserved_at_60[0x20];
4253 u8 reserved_at_88[0x18];
4255 u8 reserved_at_a0[0x8];
4258 u8 ignore_flow_level[0x1];
4259 u8 reserved_at_c1[0x17];
4260 u8 modify_enable_mask[0x8];
4262 u8 reserved_at_e0[0x20];
4264 u8 flow_index[0x20];
4266 u8 reserved_at_120[0xe0];
4268 struct mlx5_ifc_flow_context_bits flow_context;
4271 struct mlx5_ifc_rts2rts_qp_out_bits {
4273 u8 reserved_at_8[0x18];
4277 u8 reserved_at_40[0x20];
4281 struct mlx5_ifc_rts2rts_qp_in_bits {
4285 u8 reserved_at_20[0x10];
4288 u8 reserved_at_40[0x8];
4291 u8 reserved_at_60[0x20];
4293 u8 opt_param_mask[0x20];
4297 struct mlx5_ifc_qpc_bits qpc;
4299 u8 reserved_at_800[0x80];
4302 struct mlx5_ifc_rtr2rts_qp_out_bits {
4304 u8 reserved_at_8[0x18];
4308 u8 reserved_at_40[0x20];
4312 struct mlx5_ifc_rtr2rts_qp_in_bits {
4316 u8 reserved_at_20[0x10];
4319 u8 reserved_at_40[0x8];
4322 u8 reserved_at_60[0x20];
4324 u8 opt_param_mask[0x20];
4328 struct mlx5_ifc_qpc_bits qpc;
4330 u8 reserved_at_800[0x80];
4333 struct mlx5_ifc_rst2init_qp_out_bits {
4335 u8 reserved_at_8[0x18];
4339 u8 reserved_at_40[0x20];
4343 struct mlx5_ifc_rst2init_qp_in_bits {
4347 u8 reserved_at_20[0x10];
4350 u8 reserved_at_40[0x8];
4353 u8 reserved_at_60[0x20];
4355 u8 opt_param_mask[0x20];
4359 struct mlx5_ifc_qpc_bits qpc;
4361 u8 reserved_at_800[0x80];
4364 struct mlx5_ifc_query_xrq_out_bits {
4366 u8 reserved_at_8[0x18];
4370 u8 reserved_at_40[0x40];
4372 struct mlx5_ifc_xrqc_bits xrq_context;
4375 struct mlx5_ifc_query_xrq_in_bits {
4377 u8 reserved_at_10[0x10];
4379 u8 reserved_at_20[0x10];
4382 u8 reserved_at_40[0x8];
4385 u8 reserved_at_60[0x20];
4388 struct mlx5_ifc_query_xrc_srq_out_bits {
4390 u8 reserved_at_8[0x18];
4394 u8 reserved_at_40[0x40];
4396 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4398 u8 reserved_at_280[0x600];
4403 struct mlx5_ifc_query_xrc_srq_in_bits {
4405 u8 reserved_at_10[0x10];
4407 u8 reserved_at_20[0x10];
4410 u8 reserved_at_40[0x8];
4413 u8 reserved_at_60[0x20];
4417 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
4418 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
4421 struct mlx5_ifc_query_vport_state_out_bits {
4423 u8 reserved_at_8[0x18];
4427 u8 reserved_at_40[0x20];
4429 u8 reserved_at_60[0x18];
4430 u8 admin_state[0x4];
4435 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
4436 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
4437 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2,
4440 struct mlx5_ifc_arm_monitor_counter_in_bits {
4444 u8 reserved_at_20[0x10];
4447 u8 reserved_at_40[0x20];
4449 u8 reserved_at_60[0x20];
4452 struct mlx5_ifc_arm_monitor_counter_out_bits {
4454 u8 reserved_at_8[0x18];
4458 u8 reserved_at_40[0x40];
4462 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
4463 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4466 enum mlx5_monitor_counter_ppcnt {
4467 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
4468 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
4469 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
4470 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4471 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
4472 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
4476 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
4479 struct mlx5_ifc_monitor_counter_output_bits {
4480 u8 reserved_at_0[0x4];
4482 u8 reserved_at_8[0x8];
4485 u8 counter_group_id[0x20];
4488 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4489 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
4490 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4491 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4493 struct mlx5_ifc_set_monitor_counter_in_bits {
4497 u8 reserved_at_20[0x10];
4500 u8 reserved_at_40[0x10];
4501 u8 num_of_counters[0x10];
4503 u8 reserved_at_60[0x20];
4505 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4508 struct mlx5_ifc_set_monitor_counter_out_bits {
4510 u8 reserved_at_8[0x18];
4514 u8 reserved_at_40[0x40];
4517 struct mlx5_ifc_query_vport_state_in_bits {
4519 u8 reserved_at_10[0x10];
4521 u8 reserved_at_20[0x10];
4524 u8 other_vport[0x1];
4525 u8 reserved_at_41[0xf];
4526 u8 vport_number[0x10];
4528 u8 reserved_at_60[0x20];
4531 struct mlx5_ifc_query_vnic_env_out_bits {
4533 u8 reserved_at_8[0x18];
4537 u8 reserved_at_40[0x40];
4539 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4543 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
4546 struct mlx5_ifc_query_vnic_env_in_bits {
4548 u8 reserved_at_10[0x10];
4550 u8 reserved_at_20[0x10];
4553 u8 other_vport[0x1];
4554 u8 reserved_at_41[0xf];
4555 u8 vport_number[0x10];
4557 u8 reserved_at_60[0x20];
4560 struct mlx5_ifc_query_vport_counter_out_bits {
4562 u8 reserved_at_8[0x18];
4566 u8 reserved_at_40[0x40];
4568 struct mlx5_ifc_traffic_counter_bits received_errors;
4570 struct mlx5_ifc_traffic_counter_bits transmit_errors;
4572 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4574 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4576 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4578 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4580 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4582 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4584 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4586 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4588 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4590 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4592 u8 reserved_at_680[0xa00];
4596 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4599 struct mlx5_ifc_query_vport_counter_in_bits {
4601 u8 reserved_at_10[0x10];
4603 u8 reserved_at_20[0x10];
4606 u8 other_vport[0x1];
4607 u8 reserved_at_41[0xb];
4609 u8 vport_number[0x10];
4611 u8 reserved_at_60[0x60];
4614 u8 reserved_at_c1[0x1f];
4616 u8 reserved_at_e0[0x20];
4619 struct mlx5_ifc_query_tis_out_bits {
4621 u8 reserved_at_8[0x18];
4625 u8 reserved_at_40[0x40];
4627 struct mlx5_ifc_tisc_bits tis_context;
4630 struct mlx5_ifc_query_tis_in_bits {
4632 u8 reserved_at_10[0x10];
4634 u8 reserved_at_20[0x10];
4637 u8 reserved_at_40[0x8];
4640 u8 reserved_at_60[0x20];
4643 struct mlx5_ifc_query_tir_out_bits {
4645 u8 reserved_at_8[0x18];
4649 u8 reserved_at_40[0xc0];
4651 struct mlx5_ifc_tirc_bits tir_context;
4654 struct mlx5_ifc_query_tir_in_bits {
4656 u8 reserved_at_10[0x10];
4658 u8 reserved_at_20[0x10];
4661 u8 reserved_at_40[0x8];
4664 u8 reserved_at_60[0x20];
4667 struct mlx5_ifc_query_srq_out_bits {
4669 u8 reserved_at_8[0x18];
4673 u8 reserved_at_40[0x40];
4675 struct mlx5_ifc_srqc_bits srq_context_entry;
4677 u8 reserved_at_280[0x600];
4682 struct mlx5_ifc_query_srq_in_bits {
4684 u8 reserved_at_10[0x10];
4686 u8 reserved_at_20[0x10];
4689 u8 reserved_at_40[0x8];
4692 u8 reserved_at_60[0x20];
4695 struct mlx5_ifc_query_sq_out_bits {
4697 u8 reserved_at_8[0x18];
4701 u8 reserved_at_40[0xc0];
4703 struct mlx5_ifc_sqc_bits sq_context;
4706 struct mlx5_ifc_query_sq_in_bits {
4708 u8 reserved_at_10[0x10];
4710 u8 reserved_at_20[0x10];
4713 u8 reserved_at_40[0x8];
4716 u8 reserved_at_60[0x20];
4719 struct mlx5_ifc_query_special_contexts_out_bits {
4721 u8 reserved_at_8[0x18];
4725 u8 dump_fill_mkey[0x20];
4731 u8 reserved_at_a0[0x60];
4734 struct mlx5_ifc_query_special_contexts_in_bits {
4736 u8 reserved_at_10[0x10];
4738 u8 reserved_at_20[0x10];
4741 u8 reserved_at_40[0x40];
4744 struct mlx5_ifc_query_scheduling_element_out_bits {
4746 u8 reserved_at_10[0x10];
4748 u8 reserved_at_20[0x10];
4751 u8 reserved_at_40[0xc0];
4753 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4755 u8 reserved_at_300[0x100];
4759 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4762 struct mlx5_ifc_query_scheduling_element_in_bits {
4764 u8 reserved_at_10[0x10];
4766 u8 reserved_at_20[0x10];
4769 u8 scheduling_hierarchy[0x8];
4770 u8 reserved_at_48[0x18];
4772 u8 scheduling_element_id[0x20];
4774 u8 reserved_at_80[0x180];
4777 struct mlx5_ifc_query_rqt_out_bits {
4779 u8 reserved_at_8[0x18];
4783 u8 reserved_at_40[0xc0];
4785 struct mlx5_ifc_rqtc_bits rqt_context;
4788 struct mlx5_ifc_query_rqt_in_bits {
4790 u8 reserved_at_10[0x10];
4792 u8 reserved_at_20[0x10];
4795 u8 reserved_at_40[0x8];
4798 u8 reserved_at_60[0x20];
4801 struct mlx5_ifc_query_rq_out_bits {
4803 u8 reserved_at_8[0x18];
4807 u8 reserved_at_40[0xc0];
4809 struct mlx5_ifc_rqc_bits rq_context;
4812 struct mlx5_ifc_query_rq_in_bits {
4814 u8 reserved_at_10[0x10];
4816 u8 reserved_at_20[0x10];
4819 u8 reserved_at_40[0x8];
4822 u8 reserved_at_60[0x20];
4825 struct mlx5_ifc_query_roce_address_out_bits {
4827 u8 reserved_at_8[0x18];
4831 u8 reserved_at_40[0x40];
4833 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4836 struct mlx5_ifc_query_roce_address_in_bits {
4838 u8 reserved_at_10[0x10];
4840 u8 reserved_at_20[0x10];
4843 u8 roce_address_index[0x10];
4844 u8 reserved_at_50[0xc];
4845 u8 vhca_port_num[0x4];
4847 u8 reserved_at_60[0x20];
4850 struct mlx5_ifc_query_rmp_out_bits {
4852 u8 reserved_at_8[0x18];
4856 u8 reserved_at_40[0xc0];
4858 struct mlx5_ifc_rmpc_bits rmp_context;
4861 struct mlx5_ifc_query_rmp_in_bits {
4863 u8 reserved_at_10[0x10];
4865 u8 reserved_at_20[0x10];
4868 u8 reserved_at_40[0x8];
4871 u8 reserved_at_60[0x20];
4874 struct mlx5_ifc_query_qp_out_bits {
4876 u8 reserved_at_8[0x18];
4880 u8 reserved_at_40[0x40];
4882 u8 opt_param_mask[0x20];
4886 struct mlx5_ifc_qpc_bits qpc;
4888 u8 reserved_at_800[0x80];
4893 struct mlx5_ifc_query_qp_in_bits {
4895 u8 reserved_at_10[0x10];
4897 u8 reserved_at_20[0x10];
4900 u8 reserved_at_40[0x8];
4903 u8 reserved_at_60[0x20];
4906 struct mlx5_ifc_query_q_counter_out_bits {
4908 u8 reserved_at_8[0x18];
4912 u8 reserved_at_40[0x40];
4914 u8 rx_write_requests[0x20];
4916 u8 reserved_at_a0[0x20];
4918 u8 rx_read_requests[0x20];
4920 u8 reserved_at_e0[0x20];
4922 u8 rx_atomic_requests[0x20];
4924 u8 reserved_at_120[0x20];
4926 u8 rx_dct_connect[0x20];
4928 u8 reserved_at_160[0x20];
4930 u8 out_of_buffer[0x20];
4932 u8 reserved_at_1a0[0x20];
4934 u8 out_of_sequence[0x20];
4936 u8 reserved_at_1e0[0x20];
4938 u8 duplicate_request[0x20];
4940 u8 reserved_at_220[0x20];
4942 u8 rnr_nak_retry_err[0x20];
4944 u8 reserved_at_260[0x20];
4946 u8 packet_seq_err[0x20];
4948 u8 reserved_at_2a0[0x20];
4950 u8 implied_nak_seq_err[0x20];
4952 u8 reserved_at_2e0[0x20];
4954 u8 local_ack_timeout_err[0x20];
4956 u8 reserved_at_320[0xa0];
4958 u8 resp_local_length_error[0x20];
4960 u8 req_local_length_error[0x20];
4962 u8 resp_local_qp_error[0x20];
4964 u8 local_operation_error[0x20];
4966 u8 resp_local_protection[0x20];
4968 u8 req_local_protection[0x20];
4970 u8 resp_cqe_error[0x20];
4972 u8 req_cqe_error[0x20];
4974 u8 req_mw_binding[0x20];
4976 u8 req_bad_response[0x20];
4978 u8 req_remote_invalid_request[0x20];
4980 u8 resp_remote_invalid_request[0x20];
4982 u8 req_remote_access_errors[0x20];
4984 u8 resp_remote_access_errors[0x20];
4986 u8 req_remote_operation_errors[0x20];
4988 u8 req_transport_retries_exceeded[0x20];
4990 u8 cq_overflow[0x20];
4992 u8 resp_cqe_flush_error[0x20];
4994 u8 req_cqe_flush_error[0x20];
4996 u8 reserved_at_620[0x20];
4998 u8 roce_adp_retrans[0x20];
5000 u8 roce_adp_retrans_to[0x20];
5002 u8 roce_slow_restart[0x20];
5004 u8 roce_slow_restart_cnps[0x20];
5006 u8 roce_slow_restart_trans[0x20];
5008 u8 reserved_at_6e0[0x120];
5011 struct mlx5_ifc_query_q_counter_in_bits {
5013 u8 reserved_at_10[0x10];
5015 u8 reserved_at_20[0x10];
5018 u8 reserved_at_40[0x80];
5021 u8 reserved_at_c1[0x1f];
5023 u8 reserved_at_e0[0x18];
5024 u8 counter_set_id[0x8];
5027 struct mlx5_ifc_query_pages_out_bits {
5029 u8 reserved_at_8[0x18];
5033 u8 embedded_cpu_function[0x1];
5034 u8 reserved_at_41[0xf];
5035 u8 function_id[0x10];
5041 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
5042 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
5043 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
5046 struct mlx5_ifc_query_pages_in_bits {
5048 u8 reserved_at_10[0x10];
5050 u8 reserved_at_20[0x10];
5053 u8 embedded_cpu_function[0x1];
5054 u8 reserved_at_41[0xf];
5055 u8 function_id[0x10];
5057 u8 reserved_at_60[0x20];
5060 struct mlx5_ifc_query_nic_vport_context_out_bits {
5062 u8 reserved_at_8[0x18];
5066 u8 reserved_at_40[0x40];
5068 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5071 struct mlx5_ifc_query_nic_vport_context_in_bits {
5073 u8 reserved_at_10[0x10];
5075 u8 reserved_at_20[0x10];
5078 u8 other_vport[0x1];
5079 u8 reserved_at_41[0xf];
5080 u8 vport_number[0x10];
5082 u8 reserved_at_60[0x5];
5083 u8 allowed_list_type[0x3];
5084 u8 reserved_at_68[0x18];
5087 struct mlx5_ifc_query_mkey_out_bits {
5089 u8 reserved_at_8[0x18];
5093 u8 reserved_at_40[0x40];
5095 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5097 u8 reserved_at_280[0x600];
5099 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
5101 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
5104 struct mlx5_ifc_query_mkey_in_bits {
5106 u8 reserved_at_10[0x10];
5108 u8 reserved_at_20[0x10];
5111 u8 reserved_at_40[0x8];
5112 u8 mkey_index[0x18];
5115 u8 reserved_at_61[0x1f];
5118 struct mlx5_ifc_query_mad_demux_out_bits {
5120 u8 reserved_at_8[0x18];
5124 u8 reserved_at_40[0x40];
5126 u8 mad_dumux_parameters_block[0x20];
5129 struct mlx5_ifc_query_mad_demux_in_bits {
5131 u8 reserved_at_10[0x10];
5133 u8 reserved_at_20[0x10];
5136 u8 reserved_at_40[0x40];
5139 struct mlx5_ifc_query_l2_table_entry_out_bits {
5141 u8 reserved_at_8[0x18];
5145 u8 reserved_at_40[0xa0];
5147 u8 reserved_at_e0[0x13];
5151 struct mlx5_ifc_mac_address_layout_bits mac_address;
5153 u8 reserved_at_140[0xc0];
5156 struct mlx5_ifc_query_l2_table_entry_in_bits {
5158 u8 reserved_at_10[0x10];
5160 u8 reserved_at_20[0x10];
5163 u8 reserved_at_40[0x60];
5165 u8 reserved_at_a0[0x8];
5166 u8 table_index[0x18];
5168 u8 reserved_at_c0[0x140];
5171 struct mlx5_ifc_query_issi_out_bits {
5173 u8 reserved_at_8[0x18];
5177 u8 reserved_at_40[0x10];
5178 u8 current_issi[0x10];
5180 u8 reserved_at_60[0xa0];
5182 u8 reserved_at_100[76][0x8];
5183 u8 supported_issi_dw0[0x20];
5186 struct mlx5_ifc_query_issi_in_bits {
5188 u8 reserved_at_10[0x10];
5190 u8 reserved_at_20[0x10];
5193 u8 reserved_at_40[0x40];
5196 struct mlx5_ifc_set_driver_version_out_bits {
5198 u8 reserved_0[0x18];
5201 u8 reserved_1[0x40];
5204 struct mlx5_ifc_set_driver_version_in_bits {
5206 u8 reserved_0[0x10];
5208 u8 reserved_1[0x10];
5211 u8 reserved_2[0x40];
5212 u8 driver_version[64][0x8];
5215 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5217 u8 reserved_at_8[0x18];
5221 u8 reserved_at_40[0x40];
5223 struct mlx5_ifc_pkey_bits pkey[];
5226 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5228 u8 reserved_at_10[0x10];
5230 u8 reserved_at_20[0x10];
5233 u8 other_vport[0x1];
5234 u8 reserved_at_41[0xb];
5236 u8 vport_number[0x10];
5238 u8 reserved_at_60[0x10];
5239 u8 pkey_index[0x10];
5243 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
5244 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
5245 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5248 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5250 u8 reserved_at_8[0x18];
5254 u8 reserved_at_40[0x20];
5257 u8 reserved_at_70[0x10];
5259 struct mlx5_ifc_array128_auto_bits gid[];
5262 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5264 u8 reserved_at_10[0x10];
5266 u8 reserved_at_20[0x10];
5269 u8 other_vport[0x1];
5270 u8 reserved_at_41[0xb];
5272 u8 vport_number[0x10];
5274 u8 reserved_at_60[0x10];
5278 struct mlx5_ifc_query_hca_vport_context_out_bits {
5280 u8 reserved_at_8[0x18];
5284 u8 reserved_at_40[0x40];
5286 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5289 struct mlx5_ifc_query_hca_vport_context_in_bits {
5291 u8 reserved_at_10[0x10];
5293 u8 reserved_at_20[0x10];
5296 u8 other_vport[0x1];
5297 u8 reserved_at_41[0xb];
5299 u8 vport_number[0x10];
5301 u8 reserved_at_60[0x20];
5304 struct mlx5_ifc_query_hca_cap_out_bits {
5306 u8 reserved_at_8[0x18];
5310 u8 reserved_at_40[0x40];
5312 union mlx5_ifc_hca_cap_union_bits capability;
5315 struct mlx5_ifc_query_hca_cap_in_bits {
5317 u8 reserved_at_10[0x10];
5319 u8 reserved_at_20[0x10];
5322 u8 other_function[0x1];
5323 u8 reserved_at_41[0xf];
5324 u8 function_id[0x10];
5326 u8 reserved_at_60[0x20];
5329 struct mlx5_ifc_other_hca_cap_bits {
5331 u8 reserved_at_1[0x27f];
5334 struct mlx5_ifc_query_other_hca_cap_out_bits {
5336 u8 reserved_at_8[0x18];
5340 u8 reserved_at_40[0x40];
5342 struct mlx5_ifc_other_hca_cap_bits other_capability;
5345 struct mlx5_ifc_query_other_hca_cap_in_bits {
5347 u8 reserved_at_10[0x10];
5349 u8 reserved_at_20[0x10];
5352 u8 reserved_at_40[0x10];
5353 u8 function_id[0x10];
5355 u8 reserved_at_60[0x20];
5358 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5360 u8 reserved_at_8[0x18];
5364 u8 reserved_at_40[0x40];
5367 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5369 u8 reserved_at_10[0x10];
5371 u8 reserved_at_20[0x10];
5374 u8 reserved_at_40[0x10];
5375 u8 function_id[0x10];
5376 u8 field_select[0x20];
5378 struct mlx5_ifc_other_hca_cap_bits other_capability;
5381 struct mlx5_ifc_flow_table_context_bits {
5382 u8 reformat_en[0x1];
5385 u8 termination_table[0x1];
5386 u8 table_miss_action[0x4];
5388 u8 reserved_at_10[0x8];
5391 u8 reserved_at_20[0x8];
5392 u8 table_miss_id[0x18];
5394 u8 reserved_at_40[0x8];
5395 u8 lag_master_next_table_id[0x18];
5397 u8 reserved_at_60[0x60];
5399 u8 sw_owner_icm_root_1[0x40];
5401 u8 sw_owner_icm_root_0[0x40];
5405 struct mlx5_ifc_query_flow_table_out_bits {
5407 u8 reserved_at_8[0x18];
5411 u8 reserved_at_40[0x80];
5413 struct mlx5_ifc_flow_table_context_bits flow_table_context;
5416 struct mlx5_ifc_query_flow_table_in_bits {
5418 u8 reserved_at_10[0x10];
5420 u8 reserved_at_20[0x10];
5423 u8 reserved_at_40[0x40];
5426 u8 reserved_at_88[0x18];
5428 u8 reserved_at_a0[0x8];
5431 u8 reserved_at_c0[0x140];
5434 struct mlx5_ifc_query_fte_out_bits {
5436 u8 reserved_at_8[0x18];
5440 u8 reserved_at_40[0x1c0];
5442 struct mlx5_ifc_flow_context_bits flow_context;
5445 struct mlx5_ifc_query_fte_in_bits {
5447 u8 reserved_at_10[0x10];
5449 u8 reserved_at_20[0x10];
5452 u8 reserved_at_40[0x40];
5455 u8 reserved_at_88[0x18];
5457 u8 reserved_at_a0[0x8];
5460 u8 reserved_at_c0[0x40];
5462 u8 flow_index[0x20];
5464 u8 reserved_at_120[0xe0];
5468 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5469 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5470 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5471 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5472 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5475 struct mlx5_ifc_query_flow_group_out_bits {
5477 u8 reserved_at_8[0x18];
5481 u8 reserved_at_40[0xa0];
5483 u8 start_flow_index[0x20];
5485 u8 reserved_at_100[0x20];
5487 u8 end_flow_index[0x20];
5489 u8 reserved_at_140[0xa0];
5491 u8 reserved_at_1e0[0x18];
5492 u8 match_criteria_enable[0x8];
5494 struct mlx5_ifc_fte_match_param_bits match_criteria;
5496 u8 reserved_at_1200[0xe00];
5499 struct mlx5_ifc_query_flow_group_in_bits {
5501 u8 reserved_at_10[0x10];
5503 u8 reserved_at_20[0x10];
5506 u8 reserved_at_40[0x40];
5509 u8 reserved_at_88[0x18];
5511 u8 reserved_at_a0[0x8];
5516 u8 reserved_at_e0[0x120];
5519 struct mlx5_ifc_query_flow_counter_out_bits {
5521 u8 reserved_at_8[0x18];
5525 u8 reserved_at_40[0x40];
5527 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
5530 struct mlx5_ifc_query_flow_counter_in_bits {
5532 u8 reserved_at_10[0x10];
5534 u8 reserved_at_20[0x10];
5537 u8 reserved_at_40[0x80];
5540 u8 reserved_at_c1[0xf];
5541 u8 num_of_counters[0x10];
5543 u8 flow_counter_id[0x20];
5546 struct mlx5_ifc_query_esw_vport_context_out_bits {
5548 u8 reserved_at_8[0x18];
5552 u8 reserved_at_40[0x40];
5554 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5557 struct mlx5_ifc_query_esw_vport_context_in_bits {
5559 u8 reserved_at_10[0x10];
5561 u8 reserved_at_20[0x10];
5564 u8 other_vport[0x1];
5565 u8 reserved_at_41[0xf];
5566 u8 vport_number[0x10];
5568 u8 reserved_at_60[0x20];
5571 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5573 u8 reserved_at_8[0x18];
5577 u8 reserved_at_40[0x40];
5580 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5581 u8 reserved_at_0[0x1b];
5582 u8 fdb_to_vport_reg_c_id[0x1];
5583 u8 vport_cvlan_insert[0x1];
5584 u8 vport_svlan_insert[0x1];
5585 u8 vport_cvlan_strip[0x1];
5586 u8 vport_svlan_strip[0x1];
5589 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5591 u8 reserved_at_10[0x10];
5593 u8 reserved_at_20[0x10];
5596 u8 other_vport[0x1];
5597 u8 reserved_at_41[0xf];
5598 u8 vport_number[0x10];
5600 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5602 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5605 struct mlx5_ifc_query_eq_out_bits {
5607 u8 reserved_at_8[0x18];
5611 u8 reserved_at_40[0x40];
5613 struct mlx5_ifc_eqc_bits eq_context_entry;
5615 u8 reserved_at_280[0x40];
5617 u8 event_bitmask[0x40];
5619 u8 reserved_at_300[0x580];
5624 struct mlx5_ifc_query_eq_in_bits {
5626 u8 reserved_at_10[0x10];
5628 u8 reserved_at_20[0x10];
5631 u8 reserved_at_40[0x18];
5634 u8 reserved_at_60[0x20];
5637 struct mlx5_ifc_packet_reformat_context_in_bits {
5638 u8 reserved_at_0[0x5];
5639 u8 reformat_type[0x3];
5640 u8 reserved_at_8[0xe];
5641 u8 reformat_data_size[0xa];
5643 u8 reserved_at_20[0x10];
5644 u8 reformat_data[2][0x8];
5646 u8 more_reformat_data[][0x8];
5649 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5651 u8 reserved_at_8[0x18];
5655 u8 reserved_at_40[0xa0];
5657 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
5660 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5662 u8 reserved_at_10[0x10];
5664 u8 reserved_at_20[0x10];
5667 u8 packet_reformat_id[0x20];
5669 u8 reserved_at_60[0xa0];
5672 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5674 u8 reserved_at_8[0x18];
5678 u8 packet_reformat_id[0x20];
5680 u8 reserved_at_60[0x20];
5683 enum mlx5_reformat_ctx_type {
5684 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5685 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5686 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5687 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5688 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5691 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5693 u8 reserved_at_10[0x10];
5695 u8 reserved_at_20[0x10];
5698 u8 reserved_at_40[0xa0];
5700 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5703 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5705 u8 reserved_at_8[0x18];
5709 u8 reserved_at_40[0x40];
5712 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5714 u8 reserved_at_10[0x10];
5716 u8 reserved_20[0x10];
5719 u8 packet_reformat_id[0x20];
5721 u8 reserved_60[0x20];
5724 struct mlx5_ifc_set_action_in_bits {
5725 u8 action_type[0x4];
5727 u8 reserved_at_10[0x3];
5729 u8 reserved_at_18[0x3];
5735 struct mlx5_ifc_add_action_in_bits {
5736 u8 action_type[0x4];
5738 u8 reserved_at_10[0x10];
5743 struct mlx5_ifc_copy_action_in_bits {
5744 u8 action_type[0x4];
5746 u8 reserved_at_10[0x3];
5748 u8 reserved_at_18[0x3];
5751 u8 reserved_at_20[0x4];
5753 u8 reserved_at_30[0x3];
5755 u8 reserved_at_38[0x8];
5758 union mlx5_ifc_set_add_copy_action_in_auto_bits {
5759 struct mlx5_ifc_set_action_in_bits set_action_in;
5760 struct mlx5_ifc_add_action_in_bits add_action_in;
5761 struct mlx5_ifc_copy_action_in_bits copy_action_in;
5762 u8 reserved_at_0[0x40];
5766 MLX5_ACTION_TYPE_SET = 0x1,
5767 MLX5_ACTION_TYPE_ADD = 0x2,
5768 MLX5_ACTION_TYPE_COPY = 0x3,
5772 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
5773 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
5774 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
5775 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
5776 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
5777 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
5778 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
5779 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
5780 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
5781 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
5782 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
5783 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
5784 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
5785 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
5786 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
5787 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
5788 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
5789 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
5790 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
5791 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
5792 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
5793 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
5794 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
5795 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5796 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
5797 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
5798 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
5799 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
5800 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
5801 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
5802 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
5803 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
5804 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57,
5805 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58,
5806 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
5807 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
5808 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D,
5811 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5813 u8 reserved_at_8[0x18];
5817 u8 modify_header_id[0x20];
5819 u8 reserved_at_60[0x20];
5822 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5824 u8 reserved_at_10[0x10];
5826 u8 reserved_at_20[0x10];
5829 u8 reserved_at_40[0x20];
5832 u8 reserved_at_68[0x10];
5833 u8 num_of_actions[0x8];
5835 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
5838 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5840 u8 reserved_at_8[0x18];
5844 u8 reserved_at_40[0x40];
5847 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5849 u8 reserved_at_10[0x10];
5851 u8 reserved_at_20[0x10];
5854 u8 modify_header_id[0x20];
5856 u8 reserved_at_60[0x20];
5859 struct mlx5_ifc_query_dct_out_bits {
5861 u8 reserved_at_8[0x18];
5865 u8 reserved_at_40[0x40];
5867 struct mlx5_ifc_dctc_bits dct_context_entry;
5869 u8 reserved_at_280[0x180];
5872 struct mlx5_ifc_query_dct_in_bits {
5874 u8 reserved_at_10[0x10];
5876 u8 reserved_at_20[0x10];
5879 u8 reserved_at_40[0x8];
5882 u8 reserved_at_60[0x20];
5885 struct mlx5_ifc_query_cq_out_bits {
5887 u8 reserved_at_8[0x18];
5891 u8 reserved_at_40[0x40];
5893 struct mlx5_ifc_cqc_bits cq_context;
5895 u8 reserved_at_280[0x600];
5900 struct mlx5_ifc_query_cq_in_bits {
5902 u8 reserved_at_10[0x10];
5904 u8 reserved_at_20[0x10];
5907 u8 reserved_at_40[0x8];
5910 u8 reserved_at_60[0x20];
5913 struct mlx5_ifc_query_cong_status_out_bits {
5915 u8 reserved_at_8[0x18];
5919 u8 reserved_at_40[0x20];
5923 u8 reserved_at_62[0x1e];
5926 struct mlx5_ifc_query_cong_status_in_bits {
5928 u8 reserved_at_10[0x10];
5930 u8 reserved_at_20[0x10];
5933 u8 reserved_at_40[0x18];
5935 u8 cong_protocol[0x4];
5937 u8 reserved_at_60[0x20];
5940 struct mlx5_ifc_query_cong_statistics_out_bits {
5942 u8 reserved_at_8[0x18];
5946 u8 reserved_at_40[0x40];
5948 u8 rp_cur_flows[0x20];
5952 u8 rp_cnp_ignored_high[0x20];
5954 u8 rp_cnp_ignored_low[0x20];
5956 u8 rp_cnp_handled_high[0x20];
5958 u8 rp_cnp_handled_low[0x20];
5960 u8 reserved_at_140[0x100];
5962 u8 time_stamp_high[0x20];
5964 u8 time_stamp_low[0x20];
5966 u8 accumulators_period[0x20];
5968 u8 np_ecn_marked_roce_packets_high[0x20];
5970 u8 np_ecn_marked_roce_packets_low[0x20];
5972 u8 np_cnp_sent_high[0x20];
5974 u8 np_cnp_sent_low[0x20];
5976 u8 reserved_at_320[0x560];
5979 struct mlx5_ifc_query_cong_statistics_in_bits {
5981 u8 reserved_at_10[0x10];
5983 u8 reserved_at_20[0x10];
5987 u8 reserved_at_41[0x1f];
5989 u8 reserved_at_60[0x20];
5992 struct mlx5_ifc_query_cong_params_out_bits {
5994 u8 reserved_at_8[0x18];
5998 u8 reserved_at_40[0x40];
6000 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6003 struct mlx5_ifc_query_cong_params_in_bits {
6005 u8 reserved_at_10[0x10];
6007 u8 reserved_at_20[0x10];
6010 u8 reserved_at_40[0x1c];
6011 u8 cong_protocol[0x4];
6013 u8 reserved_at_60[0x20];
6016 struct mlx5_ifc_query_adapter_out_bits {
6018 u8 reserved_at_8[0x18];
6022 u8 reserved_at_40[0x40];
6024 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6027 struct mlx5_ifc_query_adapter_in_bits {
6029 u8 reserved_at_10[0x10];
6031 u8 reserved_at_20[0x10];
6034 u8 reserved_at_40[0x40];
6037 struct mlx5_ifc_qp_2rst_out_bits {
6039 u8 reserved_at_8[0x18];
6043 u8 reserved_at_40[0x40];
6046 struct mlx5_ifc_qp_2rst_in_bits {
6050 u8 reserved_at_20[0x10];
6053 u8 reserved_at_40[0x8];
6056 u8 reserved_at_60[0x20];
6059 struct mlx5_ifc_qp_2err_out_bits {
6061 u8 reserved_at_8[0x18];
6065 u8 reserved_at_40[0x40];
6068 struct mlx5_ifc_qp_2err_in_bits {
6072 u8 reserved_at_20[0x10];
6075 u8 reserved_at_40[0x8];
6078 u8 reserved_at_60[0x20];
6081 struct mlx5_ifc_page_fault_resume_out_bits {
6083 u8 reserved_at_8[0x18];
6087 u8 reserved_at_40[0x40];
6090 struct mlx5_ifc_page_fault_resume_in_bits {
6092 u8 reserved_at_10[0x10];
6094 u8 reserved_at_20[0x10];
6098 u8 reserved_at_41[0x4];
6099 u8 page_fault_type[0x3];
6102 u8 reserved_at_60[0x8];
6106 struct mlx5_ifc_nop_out_bits {
6108 u8 reserved_at_8[0x18];
6112 u8 reserved_at_40[0x40];
6115 struct mlx5_ifc_nop_in_bits {
6117 u8 reserved_at_10[0x10];
6119 u8 reserved_at_20[0x10];
6122 u8 reserved_at_40[0x40];
6125 struct mlx5_ifc_modify_vport_state_out_bits {
6127 u8 reserved_at_8[0x18];
6131 u8 reserved_at_40[0x40];
6134 struct mlx5_ifc_modify_vport_state_in_bits {
6136 u8 reserved_at_10[0x10];
6138 u8 reserved_at_20[0x10];
6141 u8 other_vport[0x1];
6142 u8 reserved_at_41[0xf];
6143 u8 vport_number[0x10];
6145 u8 reserved_at_60[0x18];
6146 u8 admin_state[0x4];
6147 u8 reserved_at_7c[0x4];
6150 struct mlx5_ifc_modify_tis_out_bits {
6152 u8 reserved_at_8[0x18];
6156 u8 reserved_at_40[0x40];
6159 struct mlx5_ifc_modify_tis_bitmask_bits {
6160 u8 reserved_at_0[0x20];
6162 u8 reserved_at_20[0x1d];
6163 u8 lag_tx_port_affinity[0x1];
6164 u8 strict_lag_tx_port_affinity[0x1];
6168 struct mlx5_ifc_modify_tis_in_bits {
6172 u8 reserved_at_20[0x10];
6175 u8 reserved_at_40[0x8];
6178 u8 reserved_at_60[0x20];
6180 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
6182 u8 reserved_at_c0[0x40];
6184 struct mlx5_ifc_tisc_bits ctx;
6187 struct mlx5_ifc_modify_tir_bitmask_bits {
6188 u8 reserved_at_0[0x20];
6190 u8 reserved_at_20[0x1b];
6192 u8 reserved_at_3c[0x1];
6194 u8 reserved_at_3e[0x1];
6198 struct mlx5_ifc_modify_tir_out_bits {
6200 u8 reserved_at_8[0x18];
6204 u8 reserved_at_40[0x40];
6207 struct mlx5_ifc_modify_tir_in_bits {
6211 u8 reserved_at_20[0x10];
6214 u8 reserved_at_40[0x8];
6217 u8 reserved_at_60[0x20];
6219 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
6221 u8 reserved_at_c0[0x40];
6223 struct mlx5_ifc_tirc_bits ctx;
6226 struct mlx5_ifc_modify_sq_out_bits {
6228 u8 reserved_at_8[0x18];
6232 u8 reserved_at_40[0x40];
6235 struct mlx5_ifc_modify_sq_in_bits {
6239 u8 reserved_at_20[0x10];
6243 u8 reserved_at_44[0x4];
6246 u8 reserved_at_60[0x20];
6248 u8 modify_bitmask[0x40];
6250 u8 reserved_at_c0[0x40];
6252 struct mlx5_ifc_sqc_bits ctx;
6255 struct mlx5_ifc_modify_scheduling_element_out_bits {
6257 u8 reserved_at_8[0x18];
6261 u8 reserved_at_40[0x1c0];
6265 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6266 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6269 struct mlx5_ifc_modify_scheduling_element_in_bits {
6271 u8 reserved_at_10[0x10];
6273 u8 reserved_at_20[0x10];
6276 u8 scheduling_hierarchy[0x8];
6277 u8 reserved_at_48[0x18];
6279 u8 scheduling_element_id[0x20];
6281 u8 reserved_at_80[0x20];
6283 u8 modify_bitmask[0x20];
6285 u8 reserved_at_c0[0x40];
6287 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6289 u8 reserved_at_300[0x100];
6292 struct mlx5_ifc_modify_rqt_out_bits {
6294 u8 reserved_at_8[0x18];
6298 u8 reserved_at_40[0x40];
6301 struct mlx5_ifc_rqt_bitmask_bits {
6302 u8 reserved_at_0[0x20];
6304 u8 reserved_at_20[0x1f];
6308 struct mlx5_ifc_modify_rqt_in_bits {
6312 u8 reserved_at_20[0x10];
6315 u8 reserved_at_40[0x8];
6318 u8 reserved_at_60[0x20];
6320 struct mlx5_ifc_rqt_bitmask_bits bitmask;
6322 u8 reserved_at_c0[0x40];
6324 struct mlx5_ifc_rqtc_bits ctx;
6327 struct mlx5_ifc_modify_rq_out_bits {
6329 u8 reserved_at_8[0x18];
6333 u8 reserved_at_40[0x40];
6337 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6338 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
6339 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
6342 struct mlx5_ifc_modify_rq_in_bits {
6346 u8 reserved_at_20[0x10];
6350 u8 reserved_at_44[0x4];
6353 u8 reserved_at_60[0x20];
6355 u8 modify_bitmask[0x40];
6357 u8 reserved_at_c0[0x40];
6359 struct mlx5_ifc_rqc_bits ctx;
6362 struct mlx5_ifc_modify_rmp_out_bits {
6364 u8 reserved_at_8[0x18];
6368 u8 reserved_at_40[0x40];
6371 struct mlx5_ifc_rmp_bitmask_bits {
6372 u8 reserved_at_0[0x20];
6374 u8 reserved_at_20[0x1f];
6378 struct mlx5_ifc_modify_rmp_in_bits {
6382 u8 reserved_at_20[0x10];
6386 u8 reserved_at_44[0x4];
6389 u8 reserved_at_60[0x20];
6391 struct mlx5_ifc_rmp_bitmask_bits bitmask;
6393 u8 reserved_at_c0[0x40];
6395 struct mlx5_ifc_rmpc_bits ctx;
6398 struct mlx5_ifc_modify_nic_vport_context_out_bits {
6400 u8 reserved_at_8[0x18];
6404 u8 reserved_at_40[0x40];
6407 struct mlx5_ifc_modify_nic_vport_field_select_bits {
6408 u8 reserved_at_0[0x12];
6409 u8 affiliation[0x1];
6410 u8 reserved_at_13[0x1];
6411 u8 disable_uc_local_lb[0x1];
6412 u8 disable_mc_local_lb[0x1];
6417 u8 change_event[0x1];
6419 u8 permanent_address[0x1];
6420 u8 addresses_list[0x1];
6422 u8 reserved_at_1f[0x1];
6425 struct mlx5_ifc_modify_nic_vport_context_in_bits {
6427 u8 reserved_at_10[0x10];
6429 u8 reserved_at_20[0x10];
6432 u8 other_vport[0x1];
6433 u8 reserved_at_41[0xf];
6434 u8 vport_number[0x10];
6436 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6438 u8 reserved_at_80[0x780];
6440 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6443 struct mlx5_ifc_modify_hca_vport_context_out_bits {
6445 u8 reserved_at_8[0x18];
6449 u8 reserved_at_40[0x40];
6452 struct mlx5_ifc_modify_hca_vport_context_in_bits {
6454 u8 reserved_at_10[0x10];
6456 u8 reserved_at_20[0x10];
6459 u8 other_vport[0x1];
6460 u8 reserved_at_41[0xb];
6462 u8 vport_number[0x10];
6464 u8 reserved_at_60[0x20];
6466 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6469 struct mlx5_ifc_modify_cq_out_bits {
6471 u8 reserved_at_8[0x18];
6475 u8 reserved_at_40[0x40];
6479 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
6480 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
6483 struct mlx5_ifc_modify_cq_in_bits {
6487 u8 reserved_at_20[0x10];
6490 u8 reserved_at_40[0x8];
6493 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6495 struct mlx5_ifc_cqc_bits cq_context;
6497 u8 reserved_at_280[0x60];
6499 u8 cq_umem_valid[0x1];
6500 u8 reserved_at_2e1[0x1f];
6502 u8 reserved_at_300[0x580];
6507 struct mlx5_ifc_modify_cong_status_out_bits {
6509 u8 reserved_at_8[0x18];
6513 u8 reserved_at_40[0x40];
6516 struct mlx5_ifc_modify_cong_status_in_bits {
6518 u8 reserved_at_10[0x10];
6520 u8 reserved_at_20[0x10];
6523 u8 reserved_at_40[0x18];
6525 u8 cong_protocol[0x4];
6529 u8 reserved_at_62[0x1e];
6532 struct mlx5_ifc_modify_cong_params_out_bits {
6534 u8 reserved_at_8[0x18];
6538 u8 reserved_at_40[0x40];
6541 struct mlx5_ifc_modify_cong_params_in_bits {
6543 u8 reserved_at_10[0x10];
6545 u8 reserved_at_20[0x10];
6548 u8 reserved_at_40[0x1c];
6549 u8 cong_protocol[0x4];
6551 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6553 u8 reserved_at_80[0x80];
6555 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6558 struct mlx5_ifc_manage_pages_out_bits {
6560 u8 reserved_at_8[0x18];
6564 u8 output_num_entries[0x20];
6566 u8 reserved_at_60[0x20];
6572 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
6573 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
6574 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
6577 struct mlx5_ifc_manage_pages_in_bits {
6579 u8 reserved_at_10[0x10];
6581 u8 reserved_at_20[0x10];
6584 u8 embedded_cpu_function[0x1];
6585 u8 reserved_at_41[0xf];
6586 u8 function_id[0x10];
6588 u8 input_num_entries[0x20];
6593 struct mlx5_ifc_mad_ifc_out_bits {
6595 u8 reserved_at_8[0x18];
6599 u8 reserved_at_40[0x40];
6601 u8 response_mad_packet[256][0x8];
6604 struct mlx5_ifc_mad_ifc_in_bits {
6606 u8 reserved_at_10[0x10];
6608 u8 reserved_at_20[0x10];
6611 u8 remote_lid[0x10];
6612 u8 reserved_at_50[0x8];
6615 u8 reserved_at_60[0x20];
6620 struct mlx5_ifc_init_hca_out_bits {
6622 u8 reserved_at_8[0x18];
6626 u8 reserved_at_40[0x40];
6629 struct mlx5_ifc_init_hca_in_bits {
6631 u8 reserved_at_10[0x10];
6633 u8 reserved_at_20[0x10];
6636 u8 reserved_at_40[0x40];
6637 u8 sw_owner_id[4][0x20];
6640 struct mlx5_ifc_init2rtr_qp_out_bits {
6642 u8 reserved_at_8[0x18];
6646 u8 reserved_at_40[0x20];
6650 struct mlx5_ifc_init2rtr_qp_in_bits {
6654 u8 reserved_at_20[0x10];
6657 u8 reserved_at_40[0x8];
6660 u8 reserved_at_60[0x20];
6662 u8 opt_param_mask[0x20];
6666 struct mlx5_ifc_qpc_bits qpc;
6668 u8 reserved_at_800[0x80];
6671 struct mlx5_ifc_init2init_qp_out_bits {
6673 u8 reserved_at_8[0x18];
6677 u8 reserved_at_40[0x20];
6681 struct mlx5_ifc_init2init_qp_in_bits {
6685 u8 reserved_at_20[0x10];
6688 u8 reserved_at_40[0x8];
6691 u8 reserved_at_60[0x20];
6693 u8 opt_param_mask[0x20];
6697 struct mlx5_ifc_qpc_bits qpc;
6699 u8 reserved_at_800[0x80];
6702 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6704 u8 reserved_at_8[0x18];
6708 u8 reserved_at_40[0x40];
6710 u8 packet_headers_log[128][0x8];
6712 u8 packet_syndrome[64][0x8];
6715 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6717 u8 reserved_at_10[0x10];
6719 u8 reserved_at_20[0x10];
6722 u8 reserved_at_40[0x40];
6725 struct mlx5_ifc_gen_eqe_in_bits {
6727 u8 reserved_at_10[0x10];
6729 u8 reserved_at_20[0x10];
6732 u8 reserved_at_40[0x18];
6735 u8 reserved_at_60[0x20];
6740 struct mlx5_ifc_gen_eq_out_bits {
6742 u8 reserved_at_8[0x18];
6746 u8 reserved_at_40[0x40];
6749 struct mlx5_ifc_enable_hca_out_bits {
6751 u8 reserved_at_8[0x18];
6755 u8 reserved_at_40[0x20];
6758 struct mlx5_ifc_enable_hca_in_bits {
6760 u8 reserved_at_10[0x10];
6762 u8 reserved_at_20[0x10];
6765 u8 embedded_cpu_function[0x1];
6766 u8 reserved_at_41[0xf];
6767 u8 function_id[0x10];
6769 u8 reserved_at_60[0x20];
6772 struct mlx5_ifc_drain_dct_out_bits {
6774 u8 reserved_at_8[0x18];
6778 u8 reserved_at_40[0x40];
6781 struct mlx5_ifc_drain_dct_in_bits {
6785 u8 reserved_at_20[0x10];
6788 u8 reserved_at_40[0x8];
6791 u8 reserved_at_60[0x20];
6794 struct mlx5_ifc_disable_hca_out_bits {
6796 u8 reserved_at_8[0x18];
6800 u8 reserved_at_40[0x20];
6803 struct mlx5_ifc_disable_hca_in_bits {
6805 u8 reserved_at_10[0x10];
6807 u8 reserved_at_20[0x10];
6810 u8 embedded_cpu_function[0x1];
6811 u8 reserved_at_41[0xf];
6812 u8 function_id[0x10];
6814 u8 reserved_at_60[0x20];
6817 struct mlx5_ifc_detach_from_mcg_out_bits {
6819 u8 reserved_at_8[0x18];
6823 u8 reserved_at_40[0x40];
6826 struct mlx5_ifc_detach_from_mcg_in_bits {
6830 u8 reserved_at_20[0x10];
6833 u8 reserved_at_40[0x8];
6836 u8 reserved_at_60[0x20];
6838 u8 multicast_gid[16][0x8];
6841 struct mlx5_ifc_destroy_xrq_out_bits {
6843 u8 reserved_at_8[0x18];
6847 u8 reserved_at_40[0x40];
6850 struct mlx5_ifc_destroy_xrq_in_bits {
6854 u8 reserved_at_20[0x10];
6857 u8 reserved_at_40[0x8];
6860 u8 reserved_at_60[0x20];
6863 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6865 u8 reserved_at_8[0x18];
6869 u8 reserved_at_40[0x40];
6872 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6876 u8 reserved_at_20[0x10];
6879 u8 reserved_at_40[0x8];
6882 u8 reserved_at_60[0x20];
6885 struct mlx5_ifc_destroy_tis_out_bits {
6887 u8 reserved_at_8[0x18];
6891 u8 reserved_at_40[0x40];
6894 struct mlx5_ifc_destroy_tis_in_bits {
6898 u8 reserved_at_20[0x10];
6901 u8 reserved_at_40[0x8];
6904 u8 reserved_at_60[0x20];
6907 struct mlx5_ifc_destroy_tir_out_bits {
6909 u8 reserved_at_8[0x18];
6913 u8 reserved_at_40[0x40];
6916 struct mlx5_ifc_destroy_tir_in_bits {
6920 u8 reserved_at_20[0x10];
6923 u8 reserved_at_40[0x8];
6926 u8 reserved_at_60[0x20];
6929 struct mlx5_ifc_destroy_srq_out_bits {
6931 u8 reserved_at_8[0x18];
6935 u8 reserved_at_40[0x40];
6938 struct mlx5_ifc_destroy_srq_in_bits {
6942 u8 reserved_at_20[0x10];
6945 u8 reserved_at_40[0x8];
6948 u8 reserved_at_60[0x20];
6951 struct mlx5_ifc_destroy_sq_out_bits {
6953 u8 reserved_at_8[0x18];
6957 u8 reserved_at_40[0x40];
6960 struct mlx5_ifc_destroy_sq_in_bits {
6964 u8 reserved_at_20[0x10];
6967 u8 reserved_at_40[0x8];
6970 u8 reserved_at_60[0x20];
6973 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6975 u8 reserved_at_8[0x18];
6979 u8 reserved_at_40[0x1c0];
6982 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6984 u8 reserved_at_10[0x10];
6986 u8 reserved_at_20[0x10];
6989 u8 scheduling_hierarchy[0x8];
6990 u8 reserved_at_48[0x18];
6992 u8 scheduling_element_id[0x20];
6994 u8 reserved_at_80[0x180];
6997 struct mlx5_ifc_destroy_rqt_out_bits {
6999 u8 reserved_at_8[0x18];
7003 u8 reserved_at_40[0x40];
7006 struct mlx5_ifc_destroy_rqt_in_bits {
7010 u8 reserved_at_20[0x10];
7013 u8 reserved_at_40[0x8];
7016 u8 reserved_at_60[0x20];
7019 struct mlx5_ifc_destroy_rq_out_bits {
7021 u8 reserved_at_8[0x18];
7025 u8 reserved_at_40[0x40];
7028 struct mlx5_ifc_destroy_rq_in_bits {
7032 u8 reserved_at_20[0x10];
7035 u8 reserved_at_40[0x8];
7038 u8 reserved_at_60[0x20];
7041 struct mlx5_ifc_set_delay_drop_params_in_bits {
7043 u8 reserved_at_10[0x10];
7045 u8 reserved_at_20[0x10];
7048 u8 reserved_at_40[0x20];
7050 u8 reserved_at_60[0x10];
7051 u8 delay_drop_timeout[0x10];
7054 struct mlx5_ifc_set_delay_drop_params_out_bits {
7056 u8 reserved_at_8[0x18];
7060 u8 reserved_at_40[0x40];
7063 struct mlx5_ifc_destroy_rmp_out_bits {
7065 u8 reserved_at_8[0x18];
7069 u8 reserved_at_40[0x40];
7072 struct mlx5_ifc_destroy_rmp_in_bits {
7076 u8 reserved_at_20[0x10];
7079 u8 reserved_at_40[0x8];
7082 u8 reserved_at_60[0x20];
7085 struct mlx5_ifc_destroy_qp_out_bits {
7087 u8 reserved_at_8[0x18];
7091 u8 reserved_at_40[0x40];
7094 struct mlx5_ifc_destroy_qp_in_bits {
7098 u8 reserved_at_20[0x10];
7101 u8 reserved_at_40[0x8];
7104 u8 reserved_at_60[0x20];
7107 struct mlx5_ifc_destroy_psv_out_bits {
7109 u8 reserved_at_8[0x18];
7113 u8 reserved_at_40[0x40];
7116 struct mlx5_ifc_destroy_psv_in_bits {
7118 u8 reserved_at_10[0x10];
7120 u8 reserved_at_20[0x10];
7123 u8 reserved_at_40[0x8];
7126 u8 reserved_at_60[0x20];
7129 struct mlx5_ifc_destroy_mkey_out_bits {
7131 u8 reserved_at_8[0x18];
7135 u8 reserved_at_40[0x40];
7138 struct mlx5_ifc_destroy_mkey_in_bits {
7142 u8 reserved_at_20[0x10];
7145 u8 reserved_at_40[0x8];
7146 u8 mkey_index[0x18];
7148 u8 reserved_at_60[0x20];
7151 struct mlx5_ifc_destroy_flow_table_out_bits {
7153 u8 reserved_at_8[0x18];
7157 u8 reserved_at_40[0x40];
7160 struct mlx5_ifc_destroy_flow_table_in_bits {
7162 u8 reserved_at_10[0x10];
7164 u8 reserved_at_20[0x10];
7167 u8 other_vport[0x1];
7168 u8 reserved_at_41[0xf];
7169 u8 vport_number[0x10];
7171 u8 reserved_at_60[0x20];
7174 u8 reserved_at_88[0x18];
7176 u8 reserved_at_a0[0x8];
7179 u8 reserved_at_c0[0x140];
7182 struct mlx5_ifc_destroy_flow_group_out_bits {
7184 u8 reserved_at_8[0x18];
7188 u8 reserved_at_40[0x40];
7191 struct mlx5_ifc_destroy_flow_group_in_bits {
7193 u8 reserved_at_10[0x10];
7195 u8 reserved_at_20[0x10];
7198 u8 other_vport[0x1];
7199 u8 reserved_at_41[0xf];
7200 u8 vport_number[0x10];
7202 u8 reserved_at_60[0x20];
7205 u8 reserved_at_88[0x18];
7207 u8 reserved_at_a0[0x8];
7212 u8 reserved_at_e0[0x120];
7215 struct mlx5_ifc_destroy_eq_out_bits {
7217 u8 reserved_at_8[0x18];
7221 u8 reserved_at_40[0x40];
7224 struct mlx5_ifc_destroy_eq_in_bits {
7226 u8 reserved_at_10[0x10];
7228 u8 reserved_at_20[0x10];
7231 u8 reserved_at_40[0x18];
7234 u8 reserved_at_60[0x20];
7237 struct mlx5_ifc_destroy_dct_out_bits {
7239 u8 reserved_at_8[0x18];
7243 u8 reserved_at_40[0x40];
7246 struct mlx5_ifc_destroy_dct_in_bits {
7250 u8 reserved_at_20[0x10];
7253 u8 reserved_at_40[0x8];
7256 u8 reserved_at_60[0x20];
7259 struct mlx5_ifc_destroy_cq_out_bits {
7261 u8 reserved_at_8[0x18];
7265 u8 reserved_at_40[0x40];
7268 struct mlx5_ifc_destroy_cq_in_bits {
7272 u8 reserved_at_20[0x10];
7275 u8 reserved_at_40[0x8];
7278 u8 reserved_at_60[0x20];
7281 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7283 u8 reserved_at_8[0x18];
7287 u8 reserved_at_40[0x40];
7290 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7292 u8 reserved_at_10[0x10];
7294 u8 reserved_at_20[0x10];
7297 u8 reserved_at_40[0x20];
7299 u8 reserved_at_60[0x10];
7300 u8 vxlan_udp_port[0x10];
7303 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7305 u8 reserved_at_8[0x18];
7309 u8 reserved_at_40[0x40];
7312 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7314 u8 reserved_at_10[0x10];
7316 u8 reserved_at_20[0x10];
7319 u8 reserved_at_40[0x60];
7321 u8 reserved_at_a0[0x8];
7322 u8 table_index[0x18];
7324 u8 reserved_at_c0[0x140];
7327 struct mlx5_ifc_delete_fte_out_bits {
7329 u8 reserved_at_8[0x18];
7333 u8 reserved_at_40[0x40];
7336 struct mlx5_ifc_delete_fte_in_bits {
7338 u8 reserved_at_10[0x10];
7340 u8 reserved_at_20[0x10];
7343 u8 other_vport[0x1];
7344 u8 reserved_at_41[0xf];
7345 u8 vport_number[0x10];
7347 u8 reserved_at_60[0x20];
7350 u8 reserved_at_88[0x18];
7352 u8 reserved_at_a0[0x8];
7355 u8 reserved_at_c0[0x40];
7357 u8 flow_index[0x20];
7359 u8 reserved_at_120[0xe0];
7362 struct mlx5_ifc_dealloc_xrcd_out_bits {
7364 u8 reserved_at_8[0x18];
7368 u8 reserved_at_40[0x40];
7371 struct mlx5_ifc_dealloc_xrcd_in_bits {
7375 u8 reserved_at_20[0x10];
7378 u8 reserved_at_40[0x8];
7381 u8 reserved_at_60[0x20];
7384 struct mlx5_ifc_dealloc_uar_out_bits {
7386 u8 reserved_at_8[0x18];
7390 u8 reserved_at_40[0x40];
7393 struct mlx5_ifc_dealloc_uar_in_bits {
7395 u8 reserved_at_10[0x10];
7397 u8 reserved_at_20[0x10];
7400 u8 reserved_at_40[0x8];
7403 u8 reserved_at_60[0x20];
7406 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7408 u8 reserved_at_8[0x18];
7412 u8 reserved_at_40[0x40];
7415 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7419 u8 reserved_at_20[0x10];
7422 u8 reserved_at_40[0x8];
7423 u8 transport_domain[0x18];
7425 u8 reserved_at_60[0x20];
7428 struct mlx5_ifc_dealloc_q_counter_out_bits {
7430 u8 reserved_at_8[0x18];
7434 u8 reserved_at_40[0x40];
7437 struct mlx5_ifc_dealloc_q_counter_in_bits {
7439 u8 reserved_at_10[0x10];
7441 u8 reserved_at_20[0x10];
7444 u8 reserved_at_40[0x18];
7445 u8 counter_set_id[0x8];
7447 u8 reserved_at_60[0x20];
7450 struct mlx5_ifc_dealloc_pd_out_bits {
7452 u8 reserved_at_8[0x18];
7456 u8 reserved_at_40[0x40];
7459 struct mlx5_ifc_dealloc_pd_in_bits {
7463 u8 reserved_at_20[0x10];
7466 u8 reserved_at_40[0x8];
7469 u8 reserved_at_60[0x20];
7472 struct mlx5_ifc_dealloc_flow_counter_out_bits {
7474 u8 reserved_at_8[0x18];
7478 u8 reserved_at_40[0x40];
7481 struct mlx5_ifc_dealloc_flow_counter_in_bits {
7483 u8 reserved_at_10[0x10];
7485 u8 reserved_at_20[0x10];
7488 u8 flow_counter_id[0x20];
7490 u8 reserved_at_60[0x20];
7493 struct mlx5_ifc_create_xrq_out_bits {
7495 u8 reserved_at_8[0x18];
7499 u8 reserved_at_40[0x8];
7502 u8 reserved_at_60[0x20];
7505 struct mlx5_ifc_create_xrq_in_bits {
7509 u8 reserved_at_20[0x10];
7512 u8 reserved_at_40[0x40];
7514 struct mlx5_ifc_xrqc_bits xrq_context;
7517 struct mlx5_ifc_create_xrc_srq_out_bits {
7519 u8 reserved_at_8[0x18];
7523 u8 reserved_at_40[0x8];
7526 u8 reserved_at_60[0x20];
7529 struct mlx5_ifc_create_xrc_srq_in_bits {
7533 u8 reserved_at_20[0x10];
7536 u8 reserved_at_40[0x40];
7538 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7540 u8 reserved_at_280[0x60];
7542 u8 xrc_srq_umem_valid[0x1];
7543 u8 reserved_at_2e1[0x1f];
7545 u8 reserved_at_300[0x580];
7550 struct mlx5_ifc_create_tis_out_bits {
7552 u8 reserved_at_8[0x18];
7556 u8 reserved_at_40[0x8];
7559 u8 reserved_at_60[0x20];
7562 struct mlx5_ifc_create_tis_in_bits {
7566 u8 reserved_at_20[0x10];
7569 u8 reserved_at_40[0xc0];
7571 struct mlx5_ifc_tisc_bits ctx;
7574 struct mlx5_ifc_create_tir_out_bits {
7576 u8 icm_address_63_40[0x18];
7580 u8 icm_address_39_32[0x8];
7583 u8 icm_address_31_0[0x20];
7586 struct mlx5_ifc_create_tir_in_bits {
7590 u8 reserved_at_20[0x10];
7593 u8 reserved_at_40[0xc0];
7595 struct mlx5_ifc_tirc_bits ctx;
7598 struct mlx5_ifc_create_srq_out_bits {
7600 u8 reserved_at_8[0x18];
7604 u8 reserved_at_40[0x8];
7607 u8 reserved_at_60[0x20];
7610 struct mlx5_ifc_create_srq_in_bits {
7614 u8 reserved_at_20[0x10];
7617 u8 reserved_at_40[0x40];
7619 struct mlx5_ifc_srqc_bits srq_context_entry;
7621 u8 reserved_at_280[0x600];
7626 struct mlx5_ifc_create_sq_out_bits {
7628 u8 reserved_at_8[0x18];
7632 u8 reserved_at_40[0x8];
7635 u8 reserved_at_60[0x20];
7638 struct mlx5_ifc_create_sq_in_bits {
7642 u8 reserved_at_20[0x10];
7645 u8 reserved_at_40[0xc0];
7647 struct mlx5_ifc_sqc_bits ctx;
7650 struct mlx5_ifc_create_scheduling_element_out_bits {
7652 u8 reserved_at_8[0x18];
7656 u8 reserved_at_40[0x40];
7658 u8 scheduling_element_id[0x20];
7660 u8 reserved_at_a0[0x160];
7663 struct mlx5_ifc_create_scheduling_element_in_bits {
7665 u8 reserved_at_10[0x10];
7667 u8 reserved_at_20[0x10];
7670 u8 scheduling_hierarchy[0x8];
7671 u8 reserved_at_48[0x18];
7673 u8 reserved_at_60[0xa0];
7675 struct mlx5_ifc_scheduling_context_bits scheduling_context;
7677 u8 reserved_at_300[0x100];
7680 struct mlx5_ifc_create_rqt_out_bits {
7682 u8 reserved_at_8[0x18];
7686 u8 reserved_at_40[0x8];
7689 u8 reserved_at_60[0x20];
7692 struct mlx5_ifc_create_rqt_in_bits {
7696 u8 reserved_at_20[0x10];
7699 u8 reserved_at_40[0xc0];
7701 struct mlx5_ifc_rqtc_bits rqt_context;
7704 struct mlx5_ifc_create_rq_out_bits {
7706 u8 reserved_at_8[0x18];
7710 u8 reserved_at_40[0x8];
7713 u8 reserved_at_60[0x20];
7716 struct mlx5_ifc_create_rq_in_bits {
7720 u8 reserved_at_20[0x10];
7723 u8 reserved_at_40[0xc0];
7725 struct mlx5_ifc_rqc_bits ctx;
7728 struct mlx5_ifc_create_rmp_out_bits {
7730 u8 reserved_at_8[0x18];
7734 u8 reserved_at_40[0x8];
7737 u8 reserved_at_60[0x20];
7740 struct mlx5_ifc_create_rmp_in_bits {
7744 u8 reserved_at_20[0x10];
7747 u8 reserved_at_40[0xc0];
7749 struct mlx5_ifc_rmpc_bits ctx;
7752 struct mlx5_ifc_create_qp_out_bits {
7754 u8 reserved_at_8[0x18];
7758 u8 reserved_at_40[0x8];
7764 struct mlx5_ifc_create_qp_in_bits {
7768 u8 reserved_at_20[0x10];
7771 u8 reserved_at_40[0x8];
7774 u8 reserved_at_60[0x20];
7775 u8 opt_param_mask[0x20];
7779 struct mlx5_ifc_qpc_bits qpc;
7781 u8 reserved_at_800[0x60];
7783 u8 wq_umem_valid[0x1];
7784 u8 reserved_at_861[0x1f];
7789 struct mlx5_ifc_create_psv_out_bits {
7791 u8 reserved_at_8[0x18];
7795 u8 reserved_at_40[0x40];
7797 u8 reserved_at_80[0x8];
7798 u8 psv0_index[0x18];
7800 u8 reserved_at_a0[0x8];
7801 u8 psv1_index[0x18];
7803 u8 reserved_at_c0[0x8];
7804 u8 psv2_index[0x18];
7806 u8 reserved_at_e0[0x8];
7807 u8 psv3_index[0x18];
7810 struct mlx5_ifc_create_psv_in_bits {
7812 u8 reserved_at_10[0x10];
7814 u8 reserved_at_20[0x10];
7818 u8 reserved_at_44[0x4];
7821 u8 reserved_at_60[0x20];
7824 struct mlx5_ifc_create_mkey_out_bits {
7826 u8 reserved_at_8[0x18];
7830 u8 reserved_at_40[0x8];
7831 u8 mkey_index[0x18];
7833 u8 reserved_at_60[0x20];
7836 struct mlx5_ifc_create_mkey_in_bits {
7840 u8 reserved_at_20[0x10];
7843 u8 reserved_at_40[0x20];
7846 u8 mkey_umem_valid[0x1];
7847 u8 reserved_at_62[0x1e];
7849 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7851 u8 reserved_at_280[0x80];
7853 u8 translations_octword_actual_size[0x20];
7855 u8 reserved_at_320[0x560];
7857 u8 klm_pas_mtt[][0x20];
7861 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
7862 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
7863 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
7864 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
7865 MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
7866 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
7867 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
7870 struct mlx5_ifc_create_flow_table_out_bits {
7872 u8 icm_address_63_40[0x18];
7876 u8 icm_address_39_32[0x8];
7879 u8 icm_address_31_0[0x20];
7882 struct mlx5_ifc_create_flow_table_in_bits {
7884 u8 reserved_at_10[0x10];
7886 u8 reserved_at_20[0x10];
7889 u8 other_vport[0x1];
7890 u8 reserved_at_41[0xf];
7891 u8 vport_number[0x10];
7893 u8 reserved_at_60[0x20];
7896 u8 reserved_at_88[0x18];
7898 u8 reserved_at_a0[0x20];
7900 struct mlx5_ifc_flow_table_context_bits flow_table_context;
7903 struct mlx5_ifc_create_flow_group_out_bits {
7905 u8 reserved_at_8[0x18];
7909 u8 reserved_at_40[0x8];
7912 u8 reserved_at_60[0x20];
7916 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7917 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7918 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7919 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7922 struct mlx5_ifc_create_flow_group_in_bits {
7924 u8 reserved_at_10[0x10];
7926 u8 reserved_at_20[0x10];
7929 u8 other_vport[0x1];
7930 u8 reserved_at_41[0xf];
7931 u8 vport_number[0x10];
7933 u8 reserved_at_60[0x20];
7936 u8 reserved_at_88[0x18];
7938 u8 reserved_at_a0[0x8];
7941 u8 source_eswitch_owner_vhca_id_valid[0x1];
7943 u8 reserved_at_c1[0x1f];
7945 u8 start_flow_index[0x20];
7947 u8 reserved_at_100[0x20];
7949 u8 end_flow_index[0x20];
7951 u8 reserved_at_140[0xa0];
7953 u8 reserved_at_1e0[0x18];
7954 u8 match_criteria_enable[0x8];
7956 struct mlx5_ifc_fte_match_param_bits match_criteria;
7958 u8 reserved_at_1200[0xe00];
7961 struct mlx5_ifc_create_eq_out_bits {
7963 u8 reserved_at_8[0x18];
7967 u8 reserved_at_40[0x18];
7970 u8 reserved_at_60[0x20];
7973 struct mlx5_ifc_create_eq_in_bits {
7977 u8 reserved_at_20[0x10];
7980 u8 reserved_at_40[0x40];
7982 struct mlx5_ifc_eqc_bits eq_context_entry;
7984 u8 reserved_at_280[0x40];
7986 u8 event_bitmask[4][0x40];
7988 u8 reserved_at_3c0[0x4c0];
7993 struct mlx5_ifc_create_dct_out_bits {
7995 u8 reserved_at_8[0x18];
7999 u8 reserved_at_40[0x8];
8005 struct mlx5_ifc_create_dct_in_bits {
8009 u8 reserved_at_20[0x10];
8012 u8 reserved_at_40[0x40];
8014 struct mlx5_ifc_dctc_bits dct_context_entry;
8016 u8 reserved_at_280[0x180];
8019 struct mlx5_ifc_create_cq_out_bits {
8021 u8 reserved_at_8[0x18];
8025 u8 reserved_at_40[0x8];
8028 u8 reserved_at_60[0x20];
8031 struct mlx5_ifc_create_cq_in_bits {
8035 u8 reserved_at_20[0x10];
8038 u8 reserved_at_40[0x40];
8040 struct mlx5_ifc_cqc_bits cq_context;
8042 u8 reserved_at_280[0x60];
8044 u8 cq_umem_valid[0x1];
8045 u8 reserved_at_2e1[0x59f];
8050 struct mlx5_ifc_config_int_moderation_out_bits {
8052 u8 reserved_at_8[0x18];
8056 u8 reserved_at_40[0x4];
8058 u8 int_vector[0x10];
8060 u8 reserved_at_60[0x20];
8064 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
8065 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
8068 struct mlx5_ifc_config_int_moderation_in_bits {
8070 u8 reserved_at_10[0x10];
8072 u8 reserved_at_20[0x10];
8075 u8 reserved_at_40[0x4];
8077 u8 int_vector[0x10];
8079 u8 reserved_at_60[0x20];
8082 struct mlx5_ifc_attach_to_mcg_out_bits {
8084 u8 reserved_at_8[0x18];
8088 u8 reserved_at_40[0x40];
8091 struct mlx5_ifc_attach_to_mcg_in_bits {
8095 u8 reserved_at_20[0x10];
8098 u8 reserved_at_40[0x8];
8101 u8 reserved_at_60[0x20];
8103 u8 multicast_gid[16][0x8];
8106 struct mlx5_ifc_arm_xrq_out_bits {
8108 u8 reserved_at_8[0x18];
8112 u8 reserved_at_40[0x40];
8115 struct mlx5_ifc_arm_xrq_in_bits {
8117 u8 reserved_at_10[0x10];
8119 u8 reserved_at_20[0x10];
8122 u8 reserved_at_40[0x8];
8125 u8 reserved_at_60[0x10];
8129 struct mlx5_ifc_arm_xrc_srq_out_bits {
8131 u8 reserved_at_8[0x18];
8135 u8 reserved_at_40[0x40];
8139 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
8142 struct mlx5_ifc_arm_xrc_srq_in_bits {
8146 u8 reserved_at_20[0x10];
8149 u8 reserved_at_40[0x8];
8152 u8 reserved_at_60[0x10];
8156 struct mlx5_ifc_arm_rq_out_bits {
8158 u8 reserved_at_8[0x18];
8162 u8 reserved_at_40[0x40];
8166 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8167 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
8170 struct mlx5_ifc_arm_rq_in_bits {
8174 u8 reserved_at_20[0x10];
8177 u8 reserved_at_40[0x8];
8178 u8 srq_number[0x18];
8180 u8 reserved_at_60[0x10];
8184 struct mlx5_ifc_arm_dct_out_bits {
8186 u8 reserved_at_8[0x18];
8190 u8 reserved_at_40[0x40];
8193 struct mlx5_ifc_arm_dct_in_bits {
8195 u8 reserved_at_10[0x10];
8197 u8 reserved_at_20[0x10];
8200 u8 reserved_at_40[0x8];
8201 u8 dct_number[0x18];
8203 u8 reserved_at_60[0x20];
8206 struct mlx5_ifc_alloc_xrcd_out_bits {
8208 u8 reserved_at_8[0x18];
8212 u8 reserved_at_40[0x8];
8215 u8 reserved_at_60[0x20];
8218 struct mlx5_ifc_alloc_xrcd_in_bits {
8222 u8 reserved_at_20[0x10];
8225 u8 reserved_at_40[0x40];
8228 struct mlx5_ifc_alloc_uar_out_bits {
8230 u8 reserved_at_8[0x18];
8234 u8 reserved_at_40[0x8];
8237 u8 reserved_at_60[0x20];
8240 struct mlx5_ifc_alloc_uar_in_bits {
8242 u8 reserved_at_10[0x10];
8244 u8 reserved_at_20[0x10];
8247 u8 reserved_at_40[0x40];
8250 struct mlx5_ifc_alloc_transport_domain_out_bits {
8252 u8 reserved_at_8[0x18];
8256 u8 reserved_at_40[0x8];
8257 u8 transport_domain[0x18];
8259 u8 reserved_at_60[0x20];
8262 struct mlx5_ifc_alloc_transport_domain_in_bits {
8266 u8 reserved_at_20[0x10];
8269 u8 reserved_at_40[0x40];
8272 struct mlx5_ifc_alloc_q_counter_out_bits {
8274 u8 reserved_at_8[0x18];
8278 u8 reserved_at_40[0x18];
8279 u8 counter_set_id[0x8];
8281 u8 reserved_at_60[0x20];
8284 struct mlx5_ifc_alloc_q_counter_in_bits {
8288 u8 reserved_at_20[0x10];
8291 u8 reserved_at_40[0x40];
8294 struct mlx5_ifc_alloc_pd_out_bits {
8296 u8 reserved_at_8[0x18];
8300 u8 reserved_at_40[0x8];
8303 u8 reserved_at_60[0x20];
8306 struct mlx5_ifc_alloc_pd_in_bits {
8310 u8 reserved_at_20[0x10];
8313 u8 reserved_at_40[0x40];
8316 struct mlx5_ifc_alloc_flow_counter_out_bits {
8318 u8 reserved_at_8[0x18];
8322 u8 flow_counter_id[0x20];
8324 u8 reserved_at_60[0x20];
8327 struct mlx5_ifc_alloc_flow_counter_in_bits {
8329 u8 reserved_at_10[0x10];
8331 u8 reserved_at_20[0x10];
8334 u8 reserved_at_40[0x33];
8335 u8 flow_counter_bulk_log_size[0x5];
8336 u8 flow_counter_bulk[0x8];
8339 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8341 u8 reserved_at_8[0x18];
8345 u8 reserved_at_40[0x40];
8348 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8350 u8 reserved_at_10[0x10];
8352 u8 reserved_at_20[0x10];
8355 u8 reserved_at_40[0x20];
8357 u8 reserved_at_60[0x10];
8358 u8 vxlan_udp_port[0x10];
8361 struct mlx5_ifc_set_pp_rate_limit_out_bits {
8363 u8 reserved_at_8[0x18];
8367 u8 reserved_at_40[0x40];
8370 struct mlx5_ifc_set_pp_rate_limit_context_bits {
8371 u8 rate_limit[0x20];
8373 u8 burst_upper_bound[0x20];
8375 u8 reserved_at_40[0x10];
8376 u8 typical_packet_size[0x10];
8378 u8 reserved_at_60[0x120];
8381 struct mlx5_ifc_set_pp_rate_limit_in_bits {
8385 u8 reserved_at_20[0x10];
8388 u8 reserved_at_40[0x10];
8389 u8 rate_limit_index[0x10];
8391 u8 reserved_at_60[0x20];
8393 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
8396 struct mlx5_ifc_access_register_out_bits {
8398 u8 reserved_at_8[0x18];
8402 u8 reserved_at_40[0x40];
8404 u8 register_data[][0x20];
8408 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
8409 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
8412 struct mlx5_ifc_access_register_in_bits {
8414 u8 reserved_at_10[0x10];
8416 u8 reserved_at_20[0x10];
8419 u8 reserved_at_40[0x10];
8420 u8 register_id[0x10];
8424 u8 register_data[][0x20];
8427 struct mlx5_ifc_sltp_reg_bits {
8432 u8 reserved_at_12[0x2];
8434 u8 reserved_at_18[0x8];
8436 u8 reserved_at_20[0x20];
8438 u8 reserved_at_40[0x7];
8444 u8 reserved_at_60[0xc];
8445 u8 ob_preemp_mode[0x4];
8449 u8 reserved_at_80[0x20];
8452 struct mlx5_ifc_slrg_reg_bits {
8457 u8 reserved_at_12[0x2];
8459 u8 reserved_at_18[0x8];
8461 u8 time_to_link_up[0x10];
8462 u8 reserved_at_30[0xc];
8463 u8 grade_lane_speed[0x4];
8465 u8 grade_version[0x8];
8468 u8 reserved_at_60[0x4];
8469 u8 height_grade_type[0x4];
8470 u8 height_grade[0x18];
8475 u8 reserved_at_a0[0x10];
8476 u8 height_sigma[0x10];
8478 u8 reserved_at_c0[0x20];
8480 u8 reserved_at_e0[0x4];
8481 u8 phase_grade_type[0x4];
8482 u8 phase_grade[0x18];
8484 u8 reserved_at_100[0x8];
8485 u8 phase_eo_pos[0x8];
8486 u8 reserved_at_110[0x8];
8487 u8 phase_eo_neg[0x8];
8489 u8 ffe_set_tested[0x10];
8490 u8 test_errors_per_lane[0x10];
8493 struct mlx5_ifc_pvlc_reg_bits {
8494 u8 reserved_at_0[0x8];
8496 u8 reserved_at_10[0x10];
8498 u8 reserved_at_20[0x1c];
8501 u8 reserved_at_40[0x1c];
8504 u8 reserved_at_60[0x1c];
8505 u8 vl_operational[0x4];
8508 struct mlx5_ifc_pude_reg_bits {
8511 u8 reserved_at_10[0x4];
8512 u8 admin_status[0x4];
8513 u8 reserved_at_18[0x4];
8514 u8 oper_status[0x4];
8516 u8 reserved_at_20[0x60];
8519 struct mlx5_ifc_ptys_reg_bits {
8520 u8 reserved_at_0[0x1];
8521 u8 an_disable_admin[0x1];
8522 u8 an_disable_cap[0x1];
8523 u8 reserved_at_3[0x5];
8525 u8 reserved_at_10[0xd];
8529 u8 reserved_at_24[0xc];
8530 u8 data_rate_oper[0x10];
8532 u8 ext_eth_proto_capability[0x20];
8534 u8 eth_proto_capability[0x20];
8536 u8 ib_link_width_capability[0x10];
8537 u8 ib_proto_capability[0x10];
8539 u8 ext_eth_proto_admin[0x20];
8541 u8 eth_proto_admin[0x20];
8543 u8 ib_link_width_admin[0x10];
8544 u8 ib_proto_admin[0x10];
8546 u8 ext_eth_proto_oper[0x20];
8548 u8 eth_proto_oper[0x20];
8550 u8 ib_link_width_oper[0x10];
8551 u8 ib_proto_oper[0x10];
8553 u8 reserved_at_160[0x1c];
8554 u8 connector_type[0x4];
8556 u8 eth_proto_lp_advertise[0x20];
8558 u8 reserved_at_1a0[0x60];
8561 struct mlx5_ifc_mlcr_reg_bits {
8562 u8 reserved_at_0[0x8];
8564 u8 reserved_at_10[0x20];
8566 u8 beacon_duration[0x10];
8567 u8 reserved_at_40[0x10];
8569 u8 beacon_remain[0x10];
8572 struct mlx5_ifc_ptas_reg_bits {
8573 u8 reserved_at_0[0x20];
8575 u8 algorithm_options[0x10];
8576 u8 reserved_at_30[0x4];
8577 u8 repetitions_mode[0x4];
8578 u8 num_of_repetitions[0x8];
8580 u8 grade_version[0x8];
8581 u8 height_grade_type[0x4];
8582 u8 phase_grade_type[0x4];
8583 u8 height_grade_weight[0x8];
8584 u8 phase_grade_weight[0x8];
8586 u8 gisim_measure_bits[0x10];
8587 u8 adaptive_tap_measure_bits[0x10];
8589 u8 ber_bath_high_error_threshold[0x10];
8590 u8 ber_bath_mid_error_threshold[0x10];
8592 u8 ber_bath_low_error_threshold[0x10];
8593 u8 one_ratio_high_threshold[0x10];
8595 u8 one_ratio_high_mid_threshold[0x10];
8596 u8 one_ratio_low_mid_threshold[0x10];
8598 u8 one_ratio_low_threshold[0x10];
8599 u8 ndeo_error_threshold[0x10];
8601 u8 mixer_offset_step_size[0x10];
8602 u8 reserved_at_110[0x8];
8603 u8 mix90_phase_for_voltage_bath[0x8];
8605 u8 mixer_offset_start[0x10];
8606 u8 mixer_offset_end[0x10];
8608 u8 reserved_at_140[0x15];
8609 u8 ber_test_time[0xb];
8612 struct mlx5_ifc_pspa_reg_bits {
8616 u8 reserved_at_18[0x8];
8618 u8 reserved_at_20[0x20];
8621 struct mlx5_ifc_pqdr_reg_bits {
8622 u8 reserved_at_0[0x8];
8624 u8 reserved_at_10[0x5];
8626 u8 reserved_at_18[0x6];
8629 u8 reserved_at_20[0x20];
8631 u8 reserved_at_40[0x10];
8632 u8 min_threshold[0x10];
8634 u8 reserved_at_60[0x10];
8635 u8 max_threshold[0x10];
8637 u8 reserved_at_80[0x10];
8638 u8 mark_probability_denominator[0x10];
8640 u8 reserved_at_a0[0x60];
8643 struct mlx5_ifc_ppsc_reg_bits {
8644 u8 reserved_at_0[0x8];
8646 u8 reserved_at_10[0x10];
8648 u8 reserved_at_20[0x60];
8650 u8 reserved_at_80[0x1c];
8653 u8 reserved_at_a0[0x1c];
8654 u8 wrps_status[0x4];
8656 u8 reserved_at_c0[0x8];
8657 u8 up_threshold[0x8];
8658 u8 reserved_at_d0[0x8];
8659 u8 down_threshold[0x8];
8661 u8 reserved_at_e0[0x20];
8663 u8 reserved_at_100[0x1c];
8666 u8 reserved_at_120[0x1c];
8667 u8 srps_status[0x4];
8669 u8 reserved_at_140[0x40];
8672 struct mlx5_ifc_pplr_reg_bits {
8673 u8 reserved_at_0[0x8];
8675 u8 reserved_at_10[0x10];
8677 u8 reserved_at_20[0x8];
8679 u8 reserved_at_30[0x8];
8683 struct mlx5_ifc_pplm_reg_bits {
8684 u8 reserved_at_0[0x8];
8686 u8 reserved_at_10[0x10];
8688 u8 reserved_at_20[0x20];
8690 u8 port_profile_mode[0x8];
8691 u8 static_port_profile[0x8];
8692 u8 active_port_profile[0x8];
8693 u8 reserved_at_58[0x8];
8695 u8 retransmission_active[0x8];
8696 u8 fec_mode_active[0x18];
8698 u8 rs_fec_correction_bypass_cap[0x4];
8699 u8 reserved_at_84[0x8];
8700 u8 fec_override_cap_56g[0x4];
8701 u8 fec_override_cap_100g[0x4];
8702 u8 fec_override_cap_50g[0x4];
8703 u8 fec_override_cap_25g[0x4];
8704 u8 fec_override_cap_10g_40g[0x4];
8706 u8 rs_fec_correction_bypass_admin[0x4];
8707 u8 reserved_at_a4[0x8];
8708 u8 fec_override_admin_56g[0x4];
8709 u8 fec_override_admin_100g[0x4];
8710 u8 fec_override_admin_50g[0x4];
8711 u8 fec_override_admin_25g[0x4];
8712 u8 fec_override_admin_10g_40g[0x4];
8714 u8 fec_override_cap_400g_8x[0x10];
8715 u8 fec_override_cap_200g_4x[0x10];
8717 u8 fec_override_cap_100g_2x[0x10];
8718 u8 fec_override_cap_50g_1x[0x10];
8720 u8 fec_override_admin_400g_8x[0x10];
8721 u8 fec_override_admin_200g_4x[0x10];
8723 u8 fec_override_admin_100g_2x[0x10];
8724 u8 fec_override_admin_50g_1x[0x10];
8726 u8 reserved_at_140[0x140];
8729 struct mlx5_ifc_ppcnt_reg_bits {
8733 u8 reserved_at_12[0x8];
8737 u8 reserved_at_21[0x1c];
8740 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8743 struct mlx5_ifc_mpein_reg_bits {
8744 u8 reserved_at_0[0x2];
8748 u8 reserved_at_18[0x8];
8750 u8 capability_mask[0x20];
8752 u8 reserved_at_40[0x8];
8753 u8 link_width_enabled[0x8];
8754 u8 link_speed_enabled[0x10];
8756 u8 lane0_physical_position[0x8];
8757 u8 link_width_active[0x8];
8758 u8 link_speed_active[0x10];
8760 u8 num_of_pfs[0x10];
8761 u8 num_of_vfs[0x10];
8764 u8 reserved_at_b0[0x10];
8766 u8 max_read_request_size[0x4];
8767 u8 max_payload_size[0x4];
8768 u8 reserved_at_c8[0x5];
8771 u8 reserved_at_d4[0xb];
8772 u8 lane_reversal[0x1];
8774 u8 reserved_at_e0[0x14];
8777 u8 reserved_at_100[0x20];
8779 u8 device_status[0x10];
8781 u8 reserved_at_138[0x8];
8783 u8 reserved_at_140[0x10];
8784 u8 receiver_detect_result[0x10];
8786 u8 reserved_at_160[0x20];
8789 struct mlx5_ifc_mpcnt_reg_bits {
8790 u8 reserved_at_0[0x8];
8792 u8 reserved_at_10[0xa];
8796 u8 reserved_at_21[0x1f];
8798 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8801 struct mlx5_ifc_ppad_reg_bits {
8802 u8 reserved_at_0[0x3];
8804 u8 reserved_at_4[0x4];
8810 u8 reserved_at_40[0x40];
8813 struct mlx5_ifc_pmtu_reg_bits {
8814 u8 reserved_at_0[0x8];
8816 u8 reserved_at_10[0x10];
8819 u8 reserved_at_30[0x10];
8822 u8 reserved_at_50[0x10];
8825 u8 reserved_at_70[0x10];
8828 struct mlx5_ifc_pmpr_reg_bits {
8829 u8 reserved_at_0[0x8];
8831 u8 reserved_at_10[0x10];
8833 u8 reserved_at_20[0x18];
8834 u8 attenuation_5g[0x8];
8836 u8 reserved_at_40[0x18];
8837 u8 attenuation_7g[0x8];
8839 u8 reserved_at_60[0x18];
8840 u8 attenuation_12g[0x8];
8843 struct mlx5_ifc_pmpe_reg_bits {
8844 u8 reserved_at_0[0x8];
8846 u8 reserved_at_10[0xc];
8847 u8 module_status[0x4];
8849 u8 reserved_at_20[0x60];
8852 struct mlx5_ifc_pmpc_reg_bits {
8853 u8 module_state_updated[32][0x8];
8856 struct mlx5_ifc_pmlpn_reg_bits {
8857 u8 reserved_at_0[0x4];
8858 u8 mlpn_status[0x4];
8860 u8 reserved_at_10[0x10];
8863 u8 reserved_at_21[0x1f];
8866 struct mlx5_ifc_pmlp_reg_bits {
8868 u8 reserved_at_1[0x7];
8870 u8 reserved_at_10[0x8];
8873 u8 lane0_module_mapping[0x20];
8875 u8 lane1_module_mapping[0x20];
8877 u8 lane2_module_mapping[0x20];
8879 u8 lane3_module_mapping[0x20];
8881 u8 reserved_at_a0[0x160];
8884 struct mlx5_ifc_pmaos_reg_bits {
8885 u8 reserved_at_0[0x8];
8887 u8 reserved_at_10[0x4];
8888 u8 admin_status[0x4];
8889 u8 reserved_at_18[0x4];
8890 u8 oper_status[0x4];
8894 u8 reserved_at_22[0x1c];
8897 u8 reserved_at_40[0x40];
8900 struct mlx5_ifc_plpc_reg_bits {
8901 u8 reserved_at_0[0x4];
8903 u8 reserved_at_10[0x4];
8905 u8 reserved_at_18[0x8];
8907 u8 reserved_at_20[0x10];
8908 u8 lane_speed[0x10];
8910 u8 reserved_at_40[0x17];
8912 u8 fec_mode_policy[0x8];
8914 u8 retransmission_capability[0x8];
8915 u8 fec_mode_capability[0x18];
8917 u8 retransmission_support_admin[0x8];
8918 u8 fec_mode_support_admin[0x18];
8920 u8 retransmission_request_admin[0x8];
8921 u8 fec_mode_request_admin[0x18];
8923 u8 reserved_at_c0[0x80];
8926 struct mlx5_ifc_plib_reg_bits {
8927 u8 reserved_at_0[0x8];
8929 u8 reserved_at_10[0x8];
8932 u8 reserved_at_20[0x60];
8935 struct mlx5_ifc_plbf_reg_bits {
8936 u8 reserved_at_0[0x8];
8938 u8 reserved_at_10[0xd];
8941 u8 reserved_at_20[0x20];
8944 struct mlx5_ifc_pipg_reg_bits {
8945 u8 reserved_at_0[0x8];
8947 u8 reserved_at_10[0x10];
8950 u8 reserved_at_21[0x19];
8952 u8 reserved_at_3e[0x2];
8955 struct mlx5_ifc_pifr_reg_bits {
8956 u8 reserved_at_0[0x8];
8958 u8 reserved_at_10[0x10];
8960 u8 reserved_at_20[0xe0];
8962 u8 port_filter[8][0x20];
8964 u8 port_filter_update_en[8][0x20];
8967 struct mlx5_ifc_pfcc_reg_bits {
8968 u8 reserved_at_0[0x8];
8970 u8 reserved_at_10[0xb];
8971 u8 ppan_mask_n[0x1];
8972 u8 minor_stall_mask[0x1];
8973 u8 critical_stall_mask[0x1];
8974 u8 reserved_at_1e[0x2];
8977 u8 reserved_at_24[0x4];
8978 u8 prio_mask_tx[0x8];
8979 u8 reserved_at_30[0x8];
8980 u8 prio_mask_rx[0x8];
8984 u8 pptx_mask_n[0x1];
8985 u8 reserved_at_43[0x5];
8987 u8 reserved_at_50[0x10];
8991 u8 pprx_mask_n[0x1];
8992 u8 reserved_at_63[0x5];
8994 u8 reserved_at_70[0x10];
8996 u8 device_stall_minor_watermark[0x10];
8997 u8 device_stall_critical_watermark[0x10];
8999 u8 reserved_at_a0[0x60];
9002 struct mlx5_ifc_pelc_reg_bits {
9004 u8 reserved_at_4[0x4];
9006 u8 reserved_at_10[0x10];
9009 u8 op_capability[0x8];
9015 u8 capability[0x40];
9021 u8 reserved_at_140[0x80];
9024 struct mlx5_ifc_peir_reg_bits {
9025 u8 reserved_at_0[0x8];
9027 u8 reserved_at_10[0x10];
9029 u8 reserved_at_20[0xc];
9030 u8 error_count[0x4];
9031 u8 reserved_at_30[0x10];
9033 u8 reserved_at_40[0xc];
9035 u8 reserved_at_50[0x8];
9039 struct mlx5_ifc_mpegc_reg_bits {
9040 u8 reserved_at_0[0x30];
9041 u8 field_select[0x10];
9043 u8 tx_overflow_sense[0x1];
9046 u8 reserved_at_43[0x1b];
9047 u8 tx_lossy_overflow_oper[0x2];
9049 u8 reserved_at_60[0x100];
9052 struct mlx5_ifc_pcam_enhanced_features_bits {
9053 u8 reserved_at_0[0x68];
9054 u8 fec_50G_per_lane_in_pplm[0x1];
9055 u8 reserved_at_69[0x4];
9056 u8 rx_icrc_encapsulated_counter[0x1];
9057 u8 reserved_at_6e[0x4];
9058 u8 ptys_extended_ethernet[0x1];
9059 u8 reserved_at_73[0x3];
9061 u8 reserved_at_77[0x3];
9062 u8 per_lane_error_counters[0x1];
9063 u8 rx_buffer_fullness_counters[0x1];
9064 u8 ptys_connector_type[0x1];
9065 u8 reserved_at_7d[0x1];
9066 u8 ppcnt_discard_group[0x1];
9067 u8 ppcnt_statistical_group[0x1];
9070 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9071 u8 port_access_reg_cap_mask_127_to_96[0x20];
9072 u8 port_access_reg_cap_mask_95_to_64[0x20];
9074 u8 port_access_reg_cap_mask_63_to_36[0x1c];
9076 u8 port_access_reg_cap_mask_34_to_32[0x3];
9078 u8 port_access_reg_cap_mask_31_to_13[0x13];
9081 u8 port_access_reg_cap_mask_10_to_09[0x2];
9083 u8 port_access_reg_cap_mask_07_to_00[0x8];
9086 struct mlx5_ifc_pcam_reg_bits {
9087 u8 reserved_at_0[0x8];
9088 u8 feature_group[0x8];
9089 u8 reserved_at_10[0x8];
9090 u8 access_reg_group[0x8];
9092 u8 reserved_at_20[0x20];
9095 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
9096 u8 reserved_at_0[0x80];
9097 } port_access_reg_cap_mask;
9099 u8 reserved_at_c0[0x80];
9102 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9103 u8 reserved_at_0[0x80];
9106 u8 reserved_at_1c0[0xc0];
9109 struct mlx5_ifc_mcam_enhanced_features_bits {
9110 u8 reserved_at_0[0x6e];
9111 u8 pci_status_and_power[0x1];
9112 u8 reserved_at_6f[0x5];
9113 u8 mark_tx_action_cnp[0x1];
9114 u8 mark_tx_action_cqe[0x1];
9115 u8 dynamic_tx_overflow[0x1];
9116 u8 reserved_at_77[0x4];
9117 u8 pcie_outbound_stalled[0x1];
9118 u8 tx_overflow_buffer_pkt[0x1];
9119 u8 mtpps_enh_out_per_adj[0x1];
9121 u8 pcie_performance_group[0x1];
9124 struct mlx5_ifc_mcam_access_reg_bits {
9125 u8 reserved_at_0[0x1c];
9131 u8 regs_95_to_87[0x9];
9133 u8 regs_85_to_68[0x12];
9134 u8 tracer_registers[0x4];
9136 u8 regs_63_to_32[0x20];
9137 u8 regs_31_to_0[0x20];
9140 struct mlx5_ifc_mcam_access_reg_bits1 {
9141 u8 regs_127_to_96[0x20];
9143 u8 regs_95_to_64[0x20];
9145 u8 regs_63_to_32[0x20];
9147 u8 regs_31_to_0[0x20];
9150 struct mlx5_ifc_mcam_access_reg_bits2 {
9151 u8 regs_127_to_99[0x1d];
9153 u8 regs_97_to_96[0x2];
9155 u8 regs_95_to_64[0x20];
9157 u8 regs_63_to_32[0x20];
9159 u8 regs_31_to_0[0x20];
9162 struct mlx5_ifc_mcam_reg_bits {
9163 u8 reserved_at_0[0x8];
9164 u8 feature_group[0x8];
9165 u8 reserved_at_10[0x8];
9166 u8 access_reg_group[0x8];
9168 u8 reserved_at_20[0x20];
9171 struct mlx5_ifc_mcam_access_reg_bits access_regs;
9172 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9173 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
9174 u8 reserved_at_0[0x80];
9175 } mng_access_reg_cap_mask;
9177 u8 reserved_at_c0[0x80];
9180 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9181 u8 reserved_at_0[0x80];
9182 } mng_feature_cap_mask;
9184 u8 reserved_at_1c0[0x80];
9187 struct mlx5_ifc_qcam_access_reg_cap_mask {
9188 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
9190 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
9194 u8 qcam_access_reg_cap_mask_0[0x1];
9197 struct mlx5_ifc_qcam_qos_feature_cap_mask {
9198 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
9199 u8 qpts_trust_both[0x1];
9202 struct mlx5_ifc_qcam_reg_bits {
9203 u8 reserved_at_0[0x8];
9204 u8 feature_group[0x8];
9205 u8 reserved_at_10[0x8];
9206 u8 access_reg_group[0x8];
9207 u8 reserved_at_20[0x20];
9210 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9211 u8 reserved_at_0[0x80];
9212 } qos_access_reg_cap_mask;
9214 u8 reserved_at_c0[0x80];
9217 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9218 u8 reserved_at_0[0x80];
9219 } qos_feature_cap_mask;
9221 u8 reserved_at_1c0[0x80];
9224 struct mlx5_ifc_core_dump_reg_bits {
9225 u8 reserved_at_0[0x18];
9226 u8 core_dump_type[0x8];
9228 u8 reserved_at_20[0x30];
9231 u8 reserved_at_60[0x8];
9233 u8 reserved_at_80[0x180];
9236 struct mlx5_ifc_pcap_reg_bits {
9237 u8 reserved_at_0[0x8];
9239 u8 reserved_at_10[0x10];
9241 u8 port_capability_mask[4][0x20];
9244 struct mlx5_ifc_paos_reg_bits {
9247 u8 reserved_at_10[0x4];
9248 u8 admin_status[0x4];
9249 u8 reserved_at_18[0x4];
9250 u8 oper_status[0x4];
9254 u8 reserved_at_22[0x1c];
9257 u8 reserved_at_40[0x40];
9260 struct mlx5_ifc_pamp_reg_bits {
9261 u8 reserved_at_0[0x8];
9262 u8 opamp_group[0x8];
9263 u8 reserved_at_10[0xc];
9264 u8 opamp_group_type[0x4];
9266 u8 start_index[0x10];
9267 u8 reserved_at_30[0x4];
9268 u8 num_of_indices[0xc];
9270 u8 index_data[18][0x10];
9273 struct mlx5_ifc_pcmr_reg_bits {
9274 u8 reserved_at_0[0x8];
9276 u8 reserved_at_10[0x10];
9278 u8 entropy_force_cap[0x1];
9279 u8 entropy_calc_cap[0x1];
9280 u8 entropy_gre_calc_cap[0x1];
9281 u8 reserved_at_23[0xf];
9282 u8 rx_ts_over_crc_cap[0x1];
9283 u8 reserved_at_33[0xb];
9285 u8 reserved_at_3f[0x1];
9287 u8 entropy_force[0x1];
9288 u8 entropy_calc[0x1];
9289 u8 entropy_gre_calc[0x1];
9290 u8 reserved_at_43[0xf];
9291 u8 rx_ts_over_crc[0x1];
9292 u8 reserved_at_53[0xb];
9294 u8 reserved_at_5f[0x1];
9297 struct mlx5_ifc_lane_2_module_mapping_bits {
9298 u8 reserved_at_0[0x6];
9300 u8 reserved_at_8[0x6];
9302 u8 reserved_at_10[0x8];
9306 struct mlx5_ifc_bufferx_reg_bits {
9307 u8 reserved_at_0[0x6];
9310 u8 reserved_at_8[0x8];
9313 u8 xoff_threshold[0x10];
9314 u8 xon_threshold[0x10];
9317 struct mlx5_ifc_set_node_in_bits {
9318 u8 node_description[64][0x8];
9321 struct mlx5_ifc_register_power_settings_bits {
9322 u8 reserved_at_0[0x18];
9323 u8 power_settings_level[0x8];
9325 u8 reserved_at_20[0x60];
9328 struct mlx5_ifc_register_host_endianness_bits {
9330 u8 reserved_at_1[0x1f];
9332 u8 reserved_at_20[0x60];
9335 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9336 u8 reserved_at_0[0x20];
9340 u8 addressh_63_32[0x20];
9342 u8 addressl_31_0[0x20];
9345 struct mlx5_ifc_ud_adrs_vector_bits {
9349 u8 reserved_at_41[0x7];
9350 u8 destination_qp_dct[0x18];
9352 u8 static_rate[0x4];
9353 u8 sl_eth_prio[0x4];
9356 u8 rlid_udp_sport[0x10];
9358 u8 reserved_at_80[0x20];
9360 u8 rmac_47_16[0x20];
9366 u8 reserved_at_e0[0x1];
9368 u8 reserved_at_e2[0x2];
9369 u8 src_addr_index[0x8];
9370 u8 flow_label[0x14];
9372 u8 rgid_rip[16][0x8];
9375 struct mlx5_ifc_pages_req_event_bits {
9376 u8 reserved_at_0[0x10];
9377 u8 function_id[0x10];
9381 u8 reserved_at_40[0xa0];
9384 struct mlx5_ifc_eqe_bits {
9385 u8 reserved_at_0[0x8];
9387 u8 reserved_at_10[0x8];
9388 u8 event_sub_type[0x8];
9390 u8 reserved_at_20[0xe0];
9392 union mlx5_ifc_event_auto_bits event_data;
9394 u8 reserved_at_1e0[0x10];
9396 u8 reserved_at_1f8[0x7];
9401 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
9404 struct mlx5_ifc_cmd_queue_entry_bits {
9406 u8 reserved_at_8[0x18];
9408 u8 input_length[0x20];
9410 u8 input_mailbox_pointer_63_32[0x20];
9412 u8 input_mailbox_pointer_31_9[0x17];
9413 u8 reserved_at_77[0x9];
9415 u8 command_input_inline_data[16][0x8];
9417 u8 command_output_inline_data[16][0x8];
9419 u8 output_mailbox_pointer_63_32[0x20];
9421 u8 output_mailbox_pointer_31_9[0x17];
9422 u8 reserved_at_1b7[0x9];
9424 u8 output_length[0x20];
9428 u8 reserved_at_1f0[0x8];
9433 struct mlx5_ifc_cmd_out_bits {
9435 u8 reserved_at_8[0x18];
9439 u8 command_output[0x20];
9442 struct mlx5_ifc_cmd_in_bits {
9444 u8 reserved_at_10[0x10];
9446 u8 reserved_at_20[0x10];
9452 struct mlx5_ifc_cmd_if_box_bits {
9453 u8 mailbox_data[512][0x8];
9455 u8 reserved_at_1000[0x180];
9457 u8 next_pointer_63_32[0x20];
9459 u8 next_pointer_31_10[0x16];
9460 u8 reserved_at_11b6[0xa];
9462 u8 block_number[0x20];
9464 u8 reserved_at_11e0[0x8];
9466 u8 ctrl_signature[0x8];
9470 struct mlx5_ifc_mtt_bits {
9471 u8 ptag_63_32[0x20];
9474 u8 reserved_at_38[0x6];
9479 struct mlx5_ifc_query_wol_rol_out_bits {
9481 u8 reserved_at_8[0x18];
9485 u8 reserved_at_40[0x10];
9489 u8 reserved_at_60[0x20];
9492 struct mlx5_ifc_query_wol_rol_in_bits {
9494 u8 reserved_at_10[0x10];
9496 u8 reserved_at_20[0x10];
9499 u8 reserved_at_40[0x40];
9502 struct mlx5_ifc_set_wol_rol_out_bits {
9504 u8 reserved_at_8[0x18];
9508 u8 reserved_at_40[0x40];
9511 struct mlx5_ifc_set_wol_rol_in_bits {
9513 u8 reserved_at_10[0x10];
9515 u8 reserved_at_20[0x10];
9518 u8 rol_mode_valid[0x1];
9519 u8 wol_mode_valid[0x1];
9520 u8 reserved_at_42[0xe];
9524 u8 reserved_at_60[0x20];
9528 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
9529 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
9530 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
9534 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
9535 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
9536 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
9540 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
9541 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
9542 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
9543 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
9544 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
9545 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
9546 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
9547 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
9548 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
9549 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
9550 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
9553 struct mlx5_ifc_initial_seg_bits {
9554 u8 fw_rev_minor[0x10];
9555 u8 fw_rev_major[0x10];
9557 u8 cmd_interface_rev[0x10];
9558 u8 fw_rev_subminor[0x10];
9560 u8 reserved_at_40[0x40];
9562 u8 cmdq_phy_addr_63_32[0x20];
9564 u8 cmdq_phy_addr_31_12[0x14];
9565 u8 reserved_at_b4[0x2];
9566 u8 nic_interface[0x2];
9567 u8 log_cmdq_size[0x4];
9568 u8 log_cmdq_stride[0x4];
9570 u8 command_doorbell_vector[0x20];
9572 u8 reserved_at_e0[0xf00];
9574 u8 initializing[0x1];
9575 u8 reserved_at_fe1[0x4];
9576 u8 nic_interface_supported[0x3];
9577 u8 embedded_cpu[0x1];
9578 u8 reserved_at_fe9[0x17];
9580 struct mlx5_ifc_health_buffer_bits health_buffer;
9582 u8 no_dram_nic_offset[0x20];
9584 u8 reserved_at_1220[0x6e40];
9586 u8 reserved_at_8060[0x1f];
9589 u8 health_syndrome[0x8];
9590 u8 health_counter[0x18];
9592 u8 reserved_at_80a0[0x17fc0];
9595 struct mlx5_ifc_mtpps_reg_bits {
9596 u8 reserved_at_0[0xc];
9597 u8 cap_number_of_pps_pins[0x4];
9598 u8 reserved_at_10[0x4];
9599 u8 cap_max_num_of_pps_in_pins[0x4];
9600 u8 reserved_at_18[0x4];
9601 u8 cap_max_num_of_pps_out_pins[0x4];
9603 u8 reserved_at_20[0x24];
9604 u8 cap_pin_3_mode[0x4];
9605 u8 reserved_at_48[0x4];
9606 u8 cap_pin_2_mode[0x4];
9607 u8 reserved_at_50[0x4];
9608 u8 cap_pin_1_mode[0x4];
9609 u8 reserved_at_58[0x4];
9610 u8 cap_pin_0_mode[0x4];
9612 u8 reserved_at_60[0x4];
9613 u8 cap_pin_7_mode[0x4];
9614 u8 reserved_at_68[0x4];
9615 u8 cap_pin_6_mode[0x4];
9616 u8 reserved_at_70[0x4];
9617 u8 cap_pin_5_mode[0x4];
9618 u8 reserved_at_78[0x4];
9619 u8 cap_pin_4_mode[0x4];
9621 u8 field_select[0x20];
9622 u8 reserved_at_a0[0x60];
9625 u8 reserved_at_101[0xb];
9627 u8 reserved_at_110[0x4];
9631 u8 reserved_at_120[0x20];
9633 u8 time_stamp[0x40];
9635 u8 out_pulse_duration[0x10];
9636 u8 out_periodic_adjustment[0x10];
9637 u8 enhanced_out_periodic_adjustment[0x20];
9639 u8 reserved_at_1c0[0x20];
9642 struct mlx5_ifc_mtppse_reg_bits {
9643 u8 reserved_at_0[0x18];
9646 u8 reserved_at_21[0x1b];
9647 u8 event_generation_mode[0x4];
9648 u8 reserved_at_40[0x40];
9651 struct mlx5_ifc_mcqs_reg_bits {
9652 u8 last_index_flag[0x1];
9653 u8 reserved_at_1[0x7];
9655 u8 component_index[0x10];
9657 u8 reserved_at_20[0x10];
9658 u8 identifier[0x10];
9660 u8 reserved_at_40[0x17];
9661 u8 component_status[0x5];
9662 u8 component_update_state[0x4];
9664 u8 last_update_state_changer_type[0x4];
9665 u8 last_update_state_changer_host_id[0x4];
9666 u8 reserved_at_68[0x18];
9669 struct mlx5_ifc_mcqi_cap_bits {
9670 u8 supported_info_bitmask[0x20];
9672 u8 component_size[0x20];
9674 u8 max_component_size[0x20];
9676 u8 log_mcda_word_size[0x4];
9677 u8 reserved_at_64[0xc];
9678 u8 mcda_max_write_size[0x10];
9681 u8 reserved_at_81[0x1];
9682 u8 match_chip_id[0x1];
9684 u8 check_user_timestamp[0x1];
9685 u8 match_base_guid_mac[0x1];
9686 u8 reserved_at_86[0x1a];
9689 struct mlx5_ifc_mcqi_version_bits {
9690 u8 reserved_at_0[0x2];
9691 u8 build_time_valid[0x1];
9692 u8 user_defined_time_valid[0x1];
9693 u8 reserved_at_4[0x14];
9694 u8 version_string_length[0x8];
9698 u8 build_time[0x40];
9700 u8 user_defined_time[0x40];
9702 u8 build_tool_version[0x20];
9704 u8 reserved_at_e0[0x20];
9706 u8 version_string[92][0x8];
9709 struct mlx5_ifc_mcqi_activation_method_bits {
9710 u8 pending_server_ac_power_cycle[0x1];
9711 u8 pending_server_dc_power_cycle[0x1];
9712 u8 pending_server_reboot[0x1];
9713 u8 pending_fw_reset[0x1];
9714 u8 auto_activate[0x1];
9715 u8 all_hosts_sync[0x1];
9716 u8 device_hw_reset[0x1];
9717 u8 reserved_at_7[0x19];
9720 union mlx5_ifc_mcqi_reg_data_bits {
9721 struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
9722 struct mlx5_ifc_mcqi_version_bits mcqi_version;
9723 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9726 struct mlx5_ifc_mcqi_reg_bits {
9727 u8 read_pending_component[0x1];
9728 u8 reserved_at_1[0xf];
9729 u8 component_index[0x10];
9731 u8 reserved_at_20[0x20];
9733 u8 reserved_at_40[0x1b];
9740 u8 reserved_at_a0[0x10];
9743 union mlx5_ifc_mcqi_reg_data_bits data[];
9746 struct mlx5_ifc_mcc_reg_bits {
9747 u8 reserved_at_0[0x4];
9748 u8 time_elapsed_since_last_cmd[0xc];
9749 u8 reserved_at_10[0x8];
9750 u8 instruction[0x8];
9752 u8 reserved_at_20[0x10];
9753 u8 component_index[0x10];
9755 u8 reserved_at_40[0x8];
9756 u8 update_handle[0x18];
9758 u8 handle_owner_type[0x4];
9759 u8 handle_owner_host_id[0x4];
9760 u8 reserved_at_68[0x1];
9761 u8 control_progress[0x7];
9763 u8 reserved_at_78[0x4];
9764 u8 control_state[0x4];
9766 u8 component_size[0x20];
9768 u8 reserved_at_a0[0x60];
9771 struct mlx5_ifc_mcda_reg_bits {
9772 u8 reserved_at_0[0x8];
9773 u8 update_handle[0x18];
9777 u8 reserved_at_40[0x10];
9780 u8 reserved_at_60[0x20];
9786 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
9787 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
9791 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
9792 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
9793 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
9796 struct mlx5_ifc_mfrl_reg_bits {
9797 u8 reserved_at_0[0x20];
9799 u8 reserved_at_20[0x2];
9800 u8 pci_sync_for_fw_update_start[0x1];
9801 u8 pci_sync_for_fw_update_resp[0x2];
9802 u8 rst_type_sel[0x3];
9803 u8 reserved_at_28[0x8];
9805 u8 reset_level[0x8];
9808 struct mlx5_ifc_mirc_reg_bits {
9809 u8 reserved_at_0[0x18];
9810 u8 status_code[0x8];
9812 u8 reserved_at_20[0x20];
9815 union mlx5_ifc_ports_control_registers_document_bits {
9816 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9817 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9818 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9819 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9820 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9821 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9822 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9823 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
9824 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
9825 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9826 struct mlx5_ifc_pamp_reg_bits pamp_reg;
9827 struct mlx5_ifc_paos_reg_bits paos_reg;
9828 struct mlx5_ifc_pcap_reg_bits pcap_reg;
9829 struct mlx5_ifc_peir_reg_bits peir_reg;
9830 struct mlx5_ifc_pelc_reg_bits pelc_reg;
9831 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9832 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
9833 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9834 struct mlx5_ifc_pifr_reg_bits pifr_reg;
9835 struct mlx5_ifc_pipg_reg_bits pipg_reg;
9836 struct mlx5_ifc_plbf_reg_bits plbf_reg;
9837 struct mlx5_ifc_plib_reg_bits plib_reg;
9838 struct mlx5_ifc_plpc_reg_bits plpc_reg;
9839 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9840 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9841 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9842 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9843 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9844 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9845 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9846 struct mlx5_ifc_ppad_reg_bits ppad_reg;
9847 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9848 struct mlx5_ifc_mpein_reg_bits mpein_reg;
9849 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
9850 struct mlx5_ifc_pplm_reg_bits pplm_reg;
9851 struct mlx5_ifc_pplr_reg_bits pplr_reg;
9852 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9853 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9854 struct mlx5_ifc_pspa_reg_bits pspa_reg;
9855 struct mlx5_ifc_ptas_reg_bits ptas_reg;
9856 struct mlx5_ifc_ptys_reg_bits ptys_reg;
9857 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
9858 struct mlx5_ifc_pude_reg_bits pude_reg;
9859 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9860 struct mlx5_ifc_slrg_reg_bits slrg_reg;
9861 struct mlx5_ifc_sltp_reg_bits sltp_reg;
9862 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9863 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
9864 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
9865 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9866 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
9867 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9868 struct mlx5_ifc_mcc_reg_bits mcc_reg;
9869 struct mlx5_ifc_mcda_reg_bits mcda_reg;
9870 struct mlx5_ifc_mirc_reg_bits mirc_reg;
9871 struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
9872 u8 reserved_at_0[0x60e0];
9875 union mlx5_ifc_debug_enhancements_document_bits {
9876 struct mlx5_ifc_health_buffer_bits health_buffer;
9877 u8 reserved_at_0[0x200];
9880 union mlx5_ifc_uplink_pci_interface_document_bits {
9881 struct mlx5_ifc_initial_seg_bits initial_seg;
9882 u8 reserved_at_0[0x20060];
9885 struct mlx5_ifc_set_flow_table_root_out_bits {
9887 u8 reserved_at_8[0x18];
9891 u8 reserved_at_40[0x40];
9894 struct mlx5_ifc_set_flow_table_root_in_bits {
9896 u8 reserved_at_10[0x10];
9898 u8 reserved_at_20[0x10];
9901 u8 other_vport[0x1];
9902 u8 reserved_at_41[0xf];
9903 u8 vport_number[0x10];
9905 u8 reserved_at_60[0x20];
9908 u8 reserved_at_88[0x18];
9910 u8 reserved_at_a0[0x8];
9913 u8 reserved_at_c0[0x8];
9914 u8 underlay_qpn[0x18];
9915 u8 reserved_at_e0[0x120];
9919 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
9920 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
9923 struct mlx5_ifc_modify_flow_table_out_bits {
9925 u8 reserved_at_8[0x18];
9929 u8 reserved_at_40[0x40];
9932 struct mlx5_ifc_modify_flow_table_in_bits {
9934 u8 reserved_at_10[0x10];
9936 u8 reserved_at_20[0x10];
9939 u8 other_vport[0x1];
9940 u8 reserved_at_41[0xf];
9941 u8 vport_number[0x10];
9943 u8 reserved_at_60[0x10];
9944 u8 modify_field_select[0x10];
9947 u8 reserved_at_88[0x18];
9949 u8 reserved_at_a0[0x8];
9952 struct mlx5_ifc_flow_table_context_bits flow_table_context;
9955 struct mlx5_ifc_ets_tcn_config_reg_bits {
9959 u8 reserved_at_3[0x9];
9961 u8 reserved_at_10[0x9];
9962 u8 bw_allocation[0x7];
9964 u8 reserved_at_20[0xc];
9965 u8 max_bw_units[0x4];
9966 u8 reserved_at_30[0x8];
9967 u8 max_bw_value[0x8];
9970 struct mlx5_ifc_ets_global_config_reg_bits {
9971 u8 reserved_at_0[0x2];
9973 u8 reserved_at_3[0x1d];
9975 u8 reserved_at_20[0xc];
9976 u8 max_bw_units[0x4];
9977 u8 reserved_at_30[0x8];
9978 u8 max_bw_value[0x8];
9981 struct mlx5_ifc_qetc_reg_bits {
9982 u8 reserved_at_0[0x8];
9983 u8 port_number[0x8];
9984 u8 reserved_at_10[0x30];
9986 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
9987 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9990 struct mlx5_ifc_qpdpm_dscp_reg_bits {
9992 u8 reserved_at_01[0x0b];
9996 struct mlx5_ifc_qpdpm_reg_bits {
9997 u8 reserved_at_0[0x8];
9999 u8 reserved_at_10[0x10];
10000 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
10003 struct mlx5_ifc_qpts_reg_bits {
10004 u8 reserved_at_0[0x8];
10005 u8 local_port[0x8];
10006 u8 reserved_at_10[0x2d];
10007 u8 trust_state[0x3];
10010 struct mlx5_ifc_pptb_reg_bits {
10011 u8 reserved_at_0[0x2];
10013 u8 reserved_at_4[0x4];
10014 u8 local_port[0x8];
10015 u8 reserved_at_10[0x6];
10020 u8 prio_x_buff[0x20];
10023 u8 reserved_at_48[0x10];
10025 u8 untagged_buff[0x4];
10028 struct mlx5_ifc_sbcam_reg_bits {
10029 u8 reserved_at_0[0x8];
10030 u8 feature_group[0x8];
10031 u8 reserved_at_10[0x8];
10032 u8 access_reg_group[0x8];
10034 u8 reserved_at_20[0x20];
10036 u8 sb_access_reg_cap_mask[4][0x20];
10038 u8 reserved_at_c0[0x80];
10040 u8 sb_feature_cap_mask[4][0x20];
10042 u8 reserved_at_1c0[0x40];
10044 u8 cap_total_buffer_size[0x20];
10046 u8 cap_cell_size[0x10];
10047 u8 cap_max_pg_buffers[0x8];
10048 u8 cap_num_pool_supported[0x8];
10050 u8 reserved_at_240[0x8];
10051 u8 cap_sbsr_stat_size[0x8];
10052 u8 cap_max_tclass_data[0x8];
10053 u8 cap_max_cpu_ingress_tclass_sb[0x8];
10056 struct mlx5_ifc_pbmc_reg_bits {
10057 u8 reserved_at_0[0x8];
10058 u8 local_port[0x8];
10059 u8 reserved_at_10[0x10];
10061 u8 xoff_timer_value[0x10];
10062 u8 xoff_refresh[0x10];
10064 u8 reserved_at_40[0x9];
10065 u8 fullness_threshold[0x7];
10066 u8 port_buffer_size[0x10];
10068 struct mlx5_ifc_bufferx_reg_bits buffer[10];
10070 u8 reserved_at_2e0[0x80];
10073 struct mlx5_ifc_qtct_reg_bits {
10074 u8 reserved_at_0[0x8];
10075 u8 port_number[0x8];
10076 u8 reserved_at_10[0xd];
10079 u8 reserved_at_20[0x1d];
10083 struct mlx5_ifc_mcia_reg_bits {
10085 u8 reserved_at_1[0x7];
10087 u8 reserved_at_10[0x8];
10090 u8 i2c_device_address[0x8];
10091 u8 page_number[0x8];
10092 u8 device_address[0x10];
10094 u8 reserved_at_40[0x10];
10097 u8 reserved_at_60[0x20];
10113 struct mlx5_ifc_dcbx_param_bits {
10114 u8 dcbx_cee_cap[0x1];
10115 u8 dcbx_ieee_cap[0x1];
10116 u8 dcbx_standby_cap[0x1];
10117 u8 reserved_at_3[0x5];
10118 u8 port_number[0x8];
10119 u8 reserved_at_10[0xa];
10120 u8 max_application_table_size[6];
10121 u8 reserved_at_20[0x15];
10122 u8 version_oper[0x3];
10123 u8 reserved_at_38[5];
10124 u8 version_admin[0x3];
10125 u8 willing_admin[0x1];
10126 u8 reserved_at_41[0x3];
10127 u8 pfc_cap_oper[0x4];
10128 u8 reserved_at_48[0x4];
10129 u8 pfc_cap_admin[0x4];
10130 u8 reserved_at_50[0x4];
10131 u8 num_of_tc_oper[0x4];
10132 u8 reserved_at_58[0x4];
10133 u8 num_of_tc_admin[0x4];
10134 u8 remote_willing[0x1];
10135 u8 reserved_at_61[3];
10136 u8 remote_pfc_cap[4];
10137 u8 reserved_at_68[0x14];
10138 u8 remote_num_of_tc[0x4];
10139 u8 reserved_at_80[0x18];
10141 u8 reserved_at_a0[0x160];
10144 struct mlx5_ifc_lagc_bits {
10145 u8 reserved_at_0[0x1d];
10148 u8 reserved_at_20[0x14];
10149 u8 tx_remap_affinity_2[0x4];
10150 u8 reserved_at_38[0x4];
10151 u8 tx_remap_affinity_1[0x4];
10154 struct mlx5_ifc_create_lag_out_bits {
10156 u8 reserved_at_8[0x18];
10160 u8 reserved_at_40[0x40];
10163 struct mlx5_ifc_create_lag_in_bits {
10165 u8 reserved_at_10[0x10];
10167 u8 reserved_at_20[0x10];
10170 struct mlx5_ifc_lagc_bits ctx;
10173 struct mlx5_ifc_modify_lag_out_bits {
10175 u8 reserved_at_8[0x18];
10179 u8 reserved_at_40[0x40];
10182 struct mlx5_ifc_modify_lag_in_bits {
10184 u8 reserved_at_10[0x10];
10186 u8 reserved_at_20[0x10];
10189 u8 reserved_at_40[0x20];
10190 u8 field_select[0x20];
10192 struct mlx5_ifc_lagc_bits ctx;
10195 struct mlx5_ifc_query_lag_out_bits {
10197 u8 reserved_at_8[0x18];
10201 struct mlx5_ifc_lagc_bits ctx;
10204 struct mlx5_ifc_query_lag_in_bits {
10206 u8 reserved_at_10[0x10];
10208 u8 reserved_at_20[0x10];
10211 u8 reserved_at_40[0x40];
10214 struct mlx5_ifc_destroy_lag_out_bits {
10216 u8 reserved_at_8[0x18];
10220 u8 reserved_at_40[0x40];
10223 struct mlx5_ifc_destroy_lag_in_bits {
10225 u8 reserved_at_10[0x10];
10227 u8 reserved_at_20[0x10];
10230 u8 reserved_at_40[0x40];
10233 struct mlx5_ifc_create_vport_lag_out_bits {
10235 u8 reserved_at_8[0x18];
10239 u8 reserved_at_40[0x40];
10242 struct mlx5_ifc_create_vport_lag_in_bits {
10244 u8 reserved_at_10[0x10];
10246 u8 reserved_at_20[0x10];
10249 u8 reserved_at_40[0x40];
10252 struct mlx5_ifc_destroy_vport_lag_out_bits {
10254 u8 reserved_at_8[0x18];
10258 u8 reserved_at_40[0x40];
10261 struct mlx5_ifc_destroy_vport_lag_in_bits {
10263 u8 reserved_at_10[0x10];
10265 u8 reserved_at_20[0x10];
10268 u8 reserved_at_40[0x40];
10271 struct mlx5_ifc_alloc_memic_in_bits {
10273 u8 reserved_at_10[0x10];
10275 u8 reserved_at_20[0x10];
10278 u8 reserved_at_30[0x20];
10280 u8 reserved_at_40[0x18];
10281 u8 log_memic_addr_alignment[0x8];
10283 u8 range_start_addr[0x40];
10285 u8 range_size[0x20];
10287 u8 memic_size[0x20];
10290 struct mlx5_ifc_alloc_memic_out_bits {
10292 u8 reserved_at_8[0x18];
10296 u8 memic_start_addr[0x40];
10299 struct mlx5_ifc_dealloc_memic_in_bits {
10301 u8 reserved_at_10[0x10];
10303 u8 reserved_at_20[0x10];
10306 u8 reserved_at_40[0x40];
10308 u8 memic_start_addr[0x40];
10310 u8 memic_size[0x20];
10312 u8 reserved_at_e0[0x20];
10315 struct mlx5_ifc_dealloc_memic_out_bits {
10317 u8 reserved_at_8[0x18];
10321 u8 reserved_at_40[0x40];
10324 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
10328 u8 vhca_tunnel_id[0x10];
10333 u8 reserved_at_60[0x20];
10336 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
10338 u8 reserved_at_8[0x18];
10344 u8 reserved_at_60[0x20];
10347 struct mlx5_ifc_umem_bits {
10348 u8 reserved_at_0[0x80];
10350 u8 reserved_at_80[0x1b];
10351 u8 log_page_size[0x5];
10353 u8 page_offset[0x20];
10355 u8 num_of_mtt[0x40];
10357 struct mlx5_ifc_mtt_bits mtt[];
10360 struct mlx5_ifc_uctx_bits {
10363 u8 reserved_at_20[0x160];
10366 struct mlx5_ifc_sw_icm_bits {
10367 u8 modify_field_select[0x40];
10369 u8 reserved_at_40[0x18];
10370 u8 log_sw_icm_size[0x8];
10372 u8 reserved_at_60[0x20];
10374 u8 sw_icm_start_addr[0x40];
10376 u8 reserved_at_c0[0x140];
10379 struct mlx5_ifc_geneve_tlv_option_bits {
10380 u8 modify_field_select[0x40];
10382 u8 reserved_at_40[0x18];
10383 u8 geneve_option_fte_index[0x8];
10385 u8 option_class[0x10];
10386 u8 option_type[0x8];
10387 u8 reserved_at_78[0x3];
10388 u8 option_data_length[0x5];
10390 u8 reserved_at_80[0x180];
10393 struct mlx5_ifc_create_umem_in_bits {
10397 u8 reserved_at_20[0x10];
10400 u8 reserved_at_40[0x40];
10402 struct mlx5_ifc_umem_bits umem;
10405 struct mlx5_ifc_create_umem_out_bits {
10407 u8 reserved_at_8[0x18];
10411 u8 reserved_at_40[0x8];
10414 u8 reserved_at_60[0x20];
10417 struct mlx5_ifc_destroy_umem_in_bits {
10421 u8 reserved_at_20[0x10];
10424 u8 reserved_at_40[0x8];
10427 u8 reserved_at_60[0x20];
10430 struct mlx5_ifc_destroy_umem_out_bits {
10432 u8 reserved_at_8[0x18];
10436 u8 reserved_at_40[0x40];
10439 struct mlx5_ifc_create_uctx_in_bits {
10441 u8 reserved_at_10[0x10];
10443 u8 reserved_at_20[0x10];
10446 u8 reserved_at_40[0x40];
10448 struct mlx5_ifc_uctx_bits uctx;
10451 struct mlx5_ifc_create_uctx_out_bits {
10453 u8 reserved_at_8[0x18];
10457 u8 reserved_at_40[0x10];
10460 u8 reserved_at_60[0x20];
10463 struct mlx5_ifc_destroy_uctx_in_bits {
10465 u8 reserved_at_10[0x10];
10467 u8 reserved_at_20[0x10];
10470 u8 reserved_at_40[0x10];
10473 u8 reserved_at_60[0x20];
10476 struct mlx5_ifc_destroy_uctx_out_bits {
10478 u8 reserved_at_8[0x18];
10482 u8 reserved_at_40[0x40];
10485 struct mlx5_ifc_create_sw_icm_in_bits {
10486 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
10487 struct mlx5_ifc_sw_icm_bits sw_icm;
10490 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
10491 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
10492 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
10495 struct mlx5_ifc_mtrc_string_db_param_bits {
10496 u8 string_db_base_address[0x20];
10498 u8 reserved_at_20[0x8];
10499 u8 string_db_size[0x18];
10502 struct mlx5_ifc_mtrc_cap_bits {
10503 u8 trace_owner[0x1];
10504 u8 trace_to_memory[0x1];
10505 u8 reserved_at_2[0x4];
10507 u8 reserved_at_8[0x14];
10508 u8 num_string_db[0x4];
10510 u8 first_string_trace[0x8];
10511 u8 num_string_trace[0x8];
10512 u8 reserved_at_30[0x28];
10514 u8 log_max_trace_buffer_size[0x8];
10516 u8 reserved_at_60[0x20];
10518 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
10520 u8 reserved_at_280[0x180];
10523 struct mlx5_ifc_mtrc_conf_bits {
10524 u8 reserved_at_0[0x1c];
10525 u8 trace_mode[0x4];
10526 u8 reserved_at_20[0x18];
10527 u8 log_trace_buffer_size[0x8];
10528 u8 trace_mkey[0x20];
10529 u8 reserved_at_60[0x3a0];
10532 struct mlx5_ifc_mtrc_stdb_bits {
10533 u8 string_db_index[0x4];
10534 u8 reserved_at_4[0x4];
10535 u8 read_size[0x18];
10536 u8 start_offset[0x20];
10537 u8 string_db_data[];
10540 struct mlx5_ifc_mtrc_ctrl_bits {
10541 u8 trace_status[0x2];
10542 u8 reserved_at_2[0x2];
10544 u8 reserved_at_5[0xb];
10545 u8 modify_field_select[0x10];
10546 u8 reserved_at_20[0x2b];
10547 u8 current_timestamp52_32[0x15];
10548 u8 current_timestamp31_0[0x20];
10549 u8 reserved_at_80[0x180];
10552 struct mlx5_ifc_host_params_context_bits {
10553 u8 host_number[0x8];
10554 u8 reserved_at_8[0x7];
10555 u8 host_pf_disabled[0x1];
10556 u8 host_num_of_vfs[0x10];
10558 u8 host_total_vfs[0x10];
10559 u8 host_pci_bus[0x10];
10561 u8 reserved_at_40[0x10];
10562 u8 host_pci_device[0x10];
10564 u8 reserved_at_60[0x10];
10565 u8 host_pci_function[0x10];
10567 u8 reserved_at_80[0x180];
10570 struct mlx5_ifc_query_esw_functions_in_bits {
10572 u8 reserved_at_10[0x10];
10574 u8 reserved_at_20[0x10];
10577 u8 reserved_at_40[0x40];
10580 struct mlx5_ifc_query_esw_functions_out_bits {
10582 u8 reserved_at_8[0x18];
10586 u8 reserved_at_40[0x40];
10588 struct mlx5_ifc_host_params_context_bits host_params_context;
10590 u8 reserved_at_280[0x180];
10591 u8 host_sf_enable[][0x40];
10594 struct mlx5_ifc_sf_partition_bits {
10595 u8 reserved_at_0[0x10];
10596 u8 log_num_sf[0x8];
10597 u8 log_sf_bar_size[0x8];
10600 struct mlx5_ifc_query_sf_partitions_out_bits {
10602 u8 reserved_at_8[0x18];
10606 u8 reserved_at_40[0x18];
10607 u8 num_sf_partitions[0x8];
10609 u8 reserved_at_60[0x20];
10611 struct mlx5_ifc_sf_partition_bits sf_partition[];
10614 struct mlx5_ifc_query_sf_partitions_in_bits {
10616 u8 reserved_at_10[0x10];
10618 u8 reserved_at_20[0x10];
10621 u8 reserved_at_40[0x40];
10624 struct mlx5_ifc_dealloc_sf_out_bits {
10626 u8 reserved_at_8[0x18];
10630 u8 reserved_at_40[0x40];
10633 struct mlx5_ifc_dealloc_sf_in_bits {
10635 u8 reserved_at_10[0x10];
10637 u8 reserved_at_20[0x10];
10640 u8 reserved_at_40[0x10];
10641 u8 function_id[0x10];
10643 u8 reserved_at_60[0x20];
10646 struct mlx5_ifc_alloc_sf_out_bits {
10648 u8 reserved_at_8[0x18];
10652 u8 reserved_at_40[0x40];
10655 struct mlx5_ifc_alloc_sf_in_bits {
10657 u8 reserved_at_10[0x10];
10659 u8 reserved_at_20[0x10];
10662 u8 reserved_at_40[0x10];
10663 u8 function_id[0x10];
10665 u8 reserved_at_60[0x20];
10668 struct mlx5_ifc_affiliated_event_header_bits {
10669 u8 reserved_at_0[0x10];
10676 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
10677 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT(0x13),
10681 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10682 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
10686 MLX5_IPSEC_OBJECT_ICV_LEN_16B,
10687 MLX5_IPSEC_OBJECT_ICV_LEN_12B,
10688 MLX5_IPSEC_OBJECT_ICV_LEN_8B,
10691 struct mlx5_ifc_ipsec_obj_bits {
10692 u8 modify_field_select[0x40];
10693 u8 full_offload[0x1];
10694 u8 reserved_at_41[0x1];
10696 u8 esn_overlap[0x1];
10697 u8 reserved_at_44[0x2];
10698 u8 icv_length[0x2];
10699 u8 reserved_at_48[0x4];
10700 u8 aso_return_reg[0x4];
10701 u8 reserved_at_50[0x10];
10705 u8 reserved_at_80[0x8];
10710 u8 implicit_iv[0x40];
10712 u8 reserved_at_100[0x700];
10715 struct mlx5_ifc_create_ipsec_obj_in_bits {
10716 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10717 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
10721 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
10722 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
10725 struct mlx5_ifc_query_ipsec_obj_out_bits {
10726 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
10727 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
10730 struct mlx5_ifc_modify_ipsec_obj_in_bits {
10731 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10732 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
10735 struct mlx5_ifc_encryption_key_obj_bits {
10736 u8 modify_field_select[0x40];
10738 u8 reserved_at_40[0x14];
10740 u8 reserved_at_58[0x4];
10743 u8 reserved_at_60[0x8];
10746 u8 reserved_at_80[0x180];
10749 u8 reserved_at_300[0x500];
10752 struct mlx5_ifc_create_encryption_key_in_bits {
10753 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10754 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10758 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10759 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10763 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
10764 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
10767 struct mlx5_ifc_tls_static_params_bits {
10769 u8 tls_version[0x4];
10771 u8 reserved_at_8[0x14];
10772 u8 encryption_standard[0x4];
10774 u8 reserved_at_20[0x20];
10776 u8 initial_record_number[0x40];
10778 u8 resync_tcp_sn[0x20];
10782 u8 implicit_iv[0x40];
10784 u8 reserved_at_100[0x8];
10785 u8 dek_index[0x18];
10787 u8 reserved_at_120[0xe0];
10790 struct mlx5_ifc_tls_progress_params_bits {
10791 u8 next_record_tcp_sn[0x20];
10793 u8 hw_resync_tcp_sn[0x20];
10795 u8 record_tracker_state[0x2];
10796 u8 auth_state[0x2];
10797 u8 reserved_at_44[0x4];
10798 u8 hw_offset_record_number[0x18];
10802 MLX5_MTT_PERM_READ = 1 << 0,
10803 MLX5_MTT_PERM_WRITE = 1 << 1,
10804 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
10807 #endif /* MLX5_IFC_H */