include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 enum {
  36         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  37         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  38         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  39         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  40         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  41         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  42         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  43         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  44         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  45         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  46         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  47         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  48         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  49         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  50         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  51         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  52         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  53         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  54         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  56         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  57         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  58         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  59         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
  60 };
  61
  62 enum {
  63         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  64         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  65         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  66         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  67 };
  68
  69 enum {
  70         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  71         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  72 };
  73
  74 enum {
  75         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  76         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  77         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  78         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  79         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  80         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  81         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  82         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  83         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  84         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  85         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  86         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  87         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  88         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  89         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  90         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  91         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  92         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  93         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  94         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  95         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
  96         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
  97         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
  98         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
  99         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 100         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 101         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 102         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 103         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 104         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 105         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 106         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 107         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 108         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 109         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 110         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 111         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 112         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 113         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 114         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 115         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 116         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 117         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 118         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 119         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 120         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 121         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 122         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 123         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 124         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 125         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 126         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 127         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 128         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 129         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 130         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 131         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 132         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 133         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 134         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 135         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 136         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 137         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 138         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 139         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 140         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 141         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 142         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 143         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 144         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 145         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 146         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 147         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 148         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 149         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 150         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 151         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 152         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 153         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 154         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 155         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 156         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 157         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 158         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 159         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 160         MLX5_CMD_OP_NOP                           = 0x80d,
 161         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 162         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 163         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 164         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 165         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 166         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 167         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 168         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 169         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 170         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 171         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 172         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 173         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 174         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 175         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 176         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 177         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 178         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 179         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 180         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 181         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 182         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 183         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 184         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 185         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 186         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 187         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 188         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 189         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 190         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 191         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 192         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 193         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 194         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 195         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 196         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 197         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 198         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 199         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 200         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 201         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 202         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 203         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 204         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 205         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 206         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 207         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 208         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 209         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 210         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 211         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 212         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 213         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 214         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 215         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 216         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 217         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 218         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 219         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 220         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 221         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 222         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 223         MLX5_CMD_OP_MAX
 224 };
 225
 226 struct mlx5_ifc_flow_table_fields_supported_bits {
 227         u8         outer_dmac[0x1];
 228         u8         outer_smac[0x1];
 229         u8         outer_ether_type[0x1];
 230         u8         reserved_at_3[0x1];
 231         u8         outer_first_prio[0x1];
 232         u8         outer_first_cfi[0x1];
 233         u8         outer_first_vid[0x1];
 234         u8         reserved_at_7[0x1];
 235         u8         outer_second_prio[0x1];
 236         u8         outer_second_cfi[0x1];
 237         u8         outer_second_vid[0x1];
 238         u8         reserved_at_b[0x1];
 239         u8         outer_sip[0x1];
 240         u8         outer_dip[0x1];
 241         u8         outer_frag[0x1];
 242         u8         outer_ip_protocol[0x1];
 243         u8         outer_ip_ecn[0x1];
 244         u8         outer_ip_dscp[0x1];
 245         u8         outer_udp_sport[0x1];
 246         u8         outer_udp_dport[0x1];
 247         u8         outer_tcp_sport[0x1];
 248         u8         outer_tcp_dport[0x1];
 249         u8         outer_tcp_flags[0x1];
 250         u8         outer_gre_protocol[0x1];
 251         u8         outer_gre_key[0x1];
 252         u8         outer_vxlan_vni[0x1];
 253         u8         reserved_at_1a[0x5];
 254         u8         source_eswitch_port[0x1];
 255
 256         u8         inner_dmac[0x1];
 257         u8         inner_smac[0x1];
 258         u8         inner_ether_type[0x1];
 259         u8         reserved_at_23[0x1];
 260         u8         inner_first_prio[0x1];
 261         u8         inner_first_cfi[0x1];
 262         u8         inner_first_vid[0x1];
 263         u8         reserved_at_27[0x1];
 264         u8         inner_second_prio[0x1];
 265         u8         inner_second_cfi[0x1];
 266         u8         inner_second_vid[0x1];
 267         u8         reserved_at_2b[0x1];
 268         u8         inner_sip[0x1];
 269         u8         inner_dip[0x1];
 270         u8         inner_frag[0x1];
 271         u8         inner_ip_protocol[0x1];
 272         u8         inner_ip_ecn[0x1];
 273         u8         inner_ip_dscp[0x1];
 274         u8         inner_udp_sport[0x1];
 275         u8         inner_udp_dport[0x1];
 276         u8         inner_tcp_sport[0x1];
 277         u8         inner_tcp_dport[0x1];
 278         u8         inner_tcp_flags[0x1];
 279         u8         reserved_at_37[0x9];
 280
 281         u8         reserved_at_40[0x40];
 282 };
 283
 284 struct mlx5_ifc_flow_table_prop_layout_bits {
 285         u8         ft_support[0x1];
 286         u8         reserved_at_1[0x1];
 287         u8         flow_counter[0x1];
 288         u8         flow_modify_en[0x1];
 289         u8         modify_root[0x1];
 290         u8         identified_miss_table_mode[0x1];
 291         u8         flow_table_modify[0x1];
 292         u8         encap[0x1];
 293         u8         decap[0x1];
 294         u8         reserved_at_9[0x17];
 295
 296         u8         reserved_at_20[0x2];
 297         u8         log_max_ft_size[0x6];
 298         u8         reserved_at_28[0x10];
 299         u8         max_ft_level[0x8];
 300
 301         u8         reserved_at_40[0x20];
 302
 303         u8         reserved_at_60[0x18];
 304         u8         log_max_ft_num[0x8];
 305
 306         u8         reserved_at_80[0x18];
 307         u8         log_max_destination[0x8];
 308
 309         u8         reserved_at_a0[0x18];
 310         u8         log_max_flow[0x8];
 311
 312         u8         reserved_at_c0[0x40];
 313
 314         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 315
 316         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 317 };
 318
 319 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 320         u8         send[0x1];
 321         u8         receive[0x1];
 322         u8         write[0x1];
 323         u8         read[0x1];
 324         u8         reserved_at_4[0x1];
 325         u8         srq_receive[0x1];
 326         u8         reserved_at_6[0x1a];
 327 };
 328
 329 struct mlx5_ifc_ipv4_layout_bits {
 330         u8         reserved_at_0[0x60];
 331
 332         u8         ipv4[0x20];
 333 };
 334
 335 struct mlx5_ifc_ipv6_layout_bits {
 336         u8         ipv6[16][0x8];
 337 };
 338
 339 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 340         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 341         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 342         u8         reserved_at_0[0x80];
 343 };
 344
 345 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 346         u8         smac_47_16[0x20];
 347
 348         u8         smac_15_0[0x10];
 349         u8         ethertype[0x10];
 350
 351         u8         dmac_47_16[0x20];
 352
 353         u8         dmac_15_0[0x10];
 354         u8         first_prio[0x3];
 355         u8         first_cfi[0x1];
 356         u8         first_vid[0xc];
 357
 358         u8         ip_protocol[0x8];
 359         u8         ip_dscp[0x6];
 360         u8         ip_ecn[0x2];
 361         u8         vlan_tag[0x1];
 362         u8         reserved_at_91[0x1];
 363         u8         frag[0x1];
 364         u8         reserved_at_93[0x4];
 365         u8         tcp_flags[0x9];
 366
 367         u8         tcp_sport[0x10];
 368         u8         tcp_dport[0x10];
 369
 370         u8         reserved_at_c0[0x20];
 371
 372         u8         udp_sport[0x10];
 373         u8         udp_dport[0x10];
 374
 375         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 376
 377         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 378 };
 379
 380 struct mlx5_ifc_fte_match_set_misc_bits {
 381         u8         reserved_at_0[0x8];
 382         u8         source_sqn[0x18];
 383
 384         u8         reserved_at_20[0x10];
 385         u8         source_port[0x10];
 386
 387         u8         outer_second_prio[0x3];
 388         u8         outer_second_cfi[0x1];
 389         u8         outer_second_vid[0xc];
 390         u8         inner_second_prio[0x3];
 391         u8         inner_second_cfi[0x1];
 392         u8         inner_second_vid[0xc];
 393
 394         u8         outer_second_vlan_tag[0x1];
 395         u8         inner_second_vlan_tag[0x1];
 396         u8         reserved_at_62[0xe];
 397         u8         gre_protocol[0x10];
 398
 399         u8         gre_key_h[0x18];
 400         u8         gre_key_l[0x8];
 401
 402         u8         vxlan_vni[0x18];
 403         u8         reserved_at_b8[0x8];
 404
 405         u8         reserved_at_c0[0x20];
 406
 407         u8         reserved_at_e0[0xc];
 408         u8         outer_ipv6_flow_label[0x14];
 409
 410         u8         reserved_at_100[0xc];
 411         u8         inner_ipv6_flow_label[0x14];
 412
 413         u8         reserved_at_120[0xe0];
 414 };
 415
 416 struct mlx5_ifc_cmd_pas_bits {
 417         u8         pa_h[0x20];
 418
 419         u8         pa_l[0x14];
 420         u8         reserved_at_34[0xc];
 421 };
 422
 423 struct mlx5_ifc_uint64_bits {
 424         u8         hi[0x20];
 425
 426         u8         lo[0x20];
 427 };
 428
 429 enum {
 430         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 431         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 432         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 433         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 434         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 435         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 436         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 437         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 438         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 439         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 440 };
 441
 442 struct mlx5_ifc_ads_bits {
 443         u8         fl[0x1];
 444         u8         free_ar[0x1];
 445         u8         reserved_at_2[0xe];
 446         u8         pkey_index[0x10];
 447
 448         u8         reserved_at_20[0x8];
 449         u8         grh[0x1];
 450         u8         mlid[0x7];
 451         u8         rlid[0x10];
 452
 453         u8         ack_timeout[0x5];
 454         u8         reserved_at_45[0x3];
 455         u8         src_addr_index[0x8];
 456         u8         reserved_at_50[0x4];
 457         u8         stat_rate[0x4];
 458         u8         hop_limit[0x8];
 459
 460         u8         reserved_at_60[0x4];
 461         u8         tclass[0x8];
 462         u8         flow_label[0x14];
 463
 464         u8         rgid_rip[16][0x8];
 465
 466         u8         reserved_at_100[0x4];
 467         u8         f_dscp[0x1];
 468         u8         f_ecn[0x1];
 469         u8         reserved_at_106[0x1];
 470         u8         f_eth_prio[0x1];
 471         u8         ecn[0x2];
 472         u8         dscp[0x6];
 473         u8         udp_sport[0x10];
 474
 475         u8         dei_cfi[0x1];
 476         u8         eth_prio[0x3];
 477         u8         sl[0x4];
 478         u8         port[0x8];
 479         u8         rmac_47_32[0x10];
 480
 481         u8         rmac_31_0[0x20];
 482 };
 483
 484 struct mlx5_ifc_flow_table_nic_cap_bits {
 485         u8         nic_rx_multi_path_tirs[0x1];
 486         u8         nic_rx_multi_path_tirs_fts[0x1];
 487         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 488         u8         reserved_at_3[0x1fd];
 489
 490         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 491
 492         u8         reserved_at_400[0x200];
 493
 494         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 495
 496         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 497
 498         u8         reserved_at_a00[0x200];
 499
 500         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 501
 502         u8         reserved_at_e00[0x7200];
 503 };
 504
 505 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 506         u8     reserved_at_0[0x200];
 507
 508         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 509
 510         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 511
 512         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 513
 514         u8      reserved_at_800[0x7800];
 515 };
 516
 517 struct mlx5_ifc_e_switch_cap_bits {
 518         u8         vport_svlan_strip[0x1];
 519         u8         vport_cvlan_strip[0x1];
 520         u8         vport_svlan_insert[0x1];
 521         u8         vport_cvlan_insert_if_not_exist[0x1];
 522         u8         vport_cvlan_insert_overwrite[0x1];
 523         u8         reserved_at_5[0x19];
 524         u8         nic_vport_node_guid_modify[0x1];
 525         u8         nic_vport_port_guid_modify[0x1];
 526
 527         u8         vxlan_encap_decap[0x1];
 528         u8         nvgre_encap_decap[0x1];
 529         u8         reserved_at_22[0x9];
 530         u8         log_max_encap_headers[0x5];
 531         u8         reserved_2b[0x6];
 532         u8         max_encap_header_size[0xa];
 533
 534         u8         reserved_40[0x7c0];
 535
 536 };
 537
 538 struct mlx5_ifc_qos_cap_bits {
 539         u8         packet_pacing[0x1];
 540         u8         reserved_0[0x1f];
 541         u8         reserved_1[0x20];
 542         u8         packet_pacing_max_rate[0x20];
 543         u8         packet_pacing_min_rate[0x20];
 544         u8         reserved_2[0x10];
 545         u8         packet_pacing_rate_table_size[0x10];
 546         u8         reserved_3[0x760];
 547 };
 548
 549 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 550         u8         csum_cap[0x1];
 551         u8         vlan_cap[0x1];
 552         u8         lro_cap[0x1];
 553         u8         lro_psh_flag[0x1];
 554         u8         lro_time_stamp[0x1];
 555         u8         reserved_at_5[0x3];
 556         u8         self_lb_en_modifiable[0x1];
 557         u8         reserved_at_9[0x2];
 558         u8         max_lso_cap[0x5];
 559         u8         reserved_at_10[0x2];
 560         u8         wqe_inline_mode[0x2];
 561         u8         rss_ind_tbl_cap[0x4];
 562         u8         reg_umr_sq[0x1];
 563         u8         scatter_fcs[0x1];
 564         u8         reserved_at_1a[0x1];
 565         u8         tunnel_lso_const_out_ip_id[0x1];
 566         u8         reserved_at_1c[0x2];
 567         u8         tunnel_statless_gre[0x1];
 568         u8         tunnel_stateless_vxlan[0x1];
 569
 570         u8         reserved_at_20[0x20];
 571
 572         u8         reserved_at_40[0x10];
 573         u8         lro_min_mss_size[0x10];
 574
 575         u8         reserved_at_60[0x120];
 576
 577         u8         lro_timer_supported_periods[4][0x20];
 578
 579         u8         reserved_at_200[0x600];
 580 };
 581
 582 struct mlx5_ifc_roce_cap_bits {
 583         u8         roce_apm[0x1];
 584         u8         reserved_at_1[0x1f];
 585
 586         u8         reserved_at_20[0x60];
 587
 588         u8         reserved_at_80[0xc];
 589         u8         l3_type[0x4];
 590         u8         reserved_at_90[0x8];
 591         u8         roce_version[0x8];
 592
 593         u8         reserved_at_a0[0x10];
 594         u8         r_roce_dest_udp_port[0x10];
 595
 596         u8         r_roce_max_src_udp_port[0x10];
 597         u8         r_roce_min_src_udp_port[0x10];
 598
 599         u8         reserved_at_e0[0x10];
 600         u8         roce_address_table_size[0x10];
 601
 602         u8         reserved_at_100[0x700];
 603 };
 604
 605 enum {
 606         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 607         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 608         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 609         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 610         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 611         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 612         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 613         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 614         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 615 };
 616
 617 enum {
 618         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 619         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 620         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 621         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 622         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 623         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 624         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 625         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 626         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 627 };
 628
 629 struct mlx5_ifc_atomic_caps_bits {
 630         u8         reserved_at_0[0x40];
 631
 632         u8         atomic_req_8B_endianess_mode[0x2];
 633         u8         reserved_at_42[0x4];
 634         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 635
 636         u8         reserved_at_47[0x19];
 637
 638         u8         reserved_at_60[0x20];
 639
 640         u8         reserved_at_80[0x10];
 641         u8         atomic_operations[0x10];
 642
 643         u8         reserved_at_a0[0x10];
 644         u8         atomic_size_qp[0x10];
 645
 646         u8         reserved_at_c0[0x10];
 647         u8         atomic_size_dc[0x10];
 648
 649         u8         reserved_at_e0[0x720];
 650 };
 651
 652 struct mlx5_ifc_odp_cap_bits {
 653         u8         reserved_at_0[0x40];
 654
 655         u8         sig[0x1];
 656         u8         reserved_at_41[0x1f];
 657
 658         u8         reserved_at_60[0x20];
 659
 660         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 661
 662         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 663
 664         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 665
 666         u8         reserved_at_e0[0x720];
 667 };
 668
 669 struct mlx5_ifc_calc_op {
 670         u8        reserved_at_0[0x10];
 671         u8        reserved_at_10[0x9];
 672         u8        op_swap_endianness[0x1];
 673         u8        op_min[0x1];
 674         u8        op_xor[0x1];
 675         u8        op_or[0x1];
 676         u8        op_and[0x1];
 677         u8        op_max[0x1];
 678         u8        op_add[0x1];
 679 };
 680
 681 struct mlx5_ifc_vector_calc_cap_bits {
 682         u8         calc_matrix[0x1];
 683         u8         reserved_at_1[0x1f];
 684         u8         reserved_at_20[0x8];
 685         u8         max_vec_count[0x8];
 686         u8         reserved_at_30[0xd];
 687         u8         max_chunk_size[0x3];
 688         struct mlx5_ifc_calc_op calc0;
 689         struct mlx5_ifc_calc_op calc1;
 690         struct mlx5_ifc_calc_op calc2;
 691         struct mlx5_ifc_calc_op calc3;
 692
 693         u8         reserved_at_e0[0x720];
 694 };
 695
 696 enum {
 697         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 698         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 699         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 700 };
 701
 702 enum {
 703         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 704         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 705 };
 706
 707 enum {
 708         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 709         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 710         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 711         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 712         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 713 };
 714
 715 enum {
 716         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 717         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 718         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 719         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 720         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 721         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 722 };
 723
 724 enum {
 725         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 726         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 727 };
 728
 729 enum {
 730         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 731         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 732         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 733 };
 734
 735 enum {
 736         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 737         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 738 };
 739
 740 enum {
 741         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
 742         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
 743         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
 744 };
 745
 746 struct mlx5_ifc_cmd_hca_cap_bits {
 747         u8         reserved_at_0[0x80];
 748
 749         u8         log_max_srq_sz[0x8];
 750         u8         log_max_qp_sz[0x8];
 751         u8         reserved_at_90[0xb];
 752         u8         log_max_qp[0x5];
 753
 754         u8         reserved_at_a0[0xb];
 755         u8         log_max_srq[0x5];
 756         u8         reserved_at_b0[0x10];
 757
 758         u8         reserved_at_c0[0x8];
 759         u8         log_max_cq_sz[0x8];
 760         u8         reserved_at_d0[0xb];
 761         u8         log_max_cq[0x5];
 762
 763         u8         log_max_eq_sz[0x8];
 764         u8         reserved_at_e8[0x2];
 765         u8         log_max_mkey[0x6];
 766         u8         reserved_at_f0[0xc];
 767         u8         log_max_eq[0x4];
 768
 769         u8         max_indirection[0x8];
 770         u8         reserved_at_108[0x1];
 771         u8         log_max_mrw_sz[0x7];
 772         u8         reserved_at_110[0x2];
 773         u8         log_max_bsf_list_size[0x6];
 774         u8         reserved_at_118[0x2];
 775         u8         log_max_klm_list_size[0x6];
 776
 777         u8         reserved_at_120[0xa];
 778         u8         log_max_ra_req_dc[0x6];
 779         u8         reserved_at_130[0xa];
 780         u8         log_max_ra_res_dc[0x6];
 781
 782         u8         reserved_at_140[0xa];
 783         u8         log_max_ra_req_qp[0x6];
 784         u8         reserved_at_150[0xa];
 785         u8         log_max_ra_res_qp[0x6];
 786
 787         u8         pad_cap[0x1];
 788         u8         cc_query_allowed[0x1];
 789         u8         cc_modify_allowed[0x1];
 790         u8         reserved_at_163[0xd];
 791         u8         gid_table_size[0x10];
 792
 793         u8         out_of_seq_cnt[0x1];
 794         u8         vport_counters[0x1];
 795         u8         retransmission_q_counters[0x1];
 796         u8         reserved_at_183[0x1];
 797         u8         modify_rq_counter_set_id[0x1];
 798         u8         reserved_at_185[0x1];
 799         u8         max_qp_cnt[0xa];
 800         u8         pkey_table_size[0x10];
 801
 802         u8         vport_group_manager[0x1];
 803         u8         vhca_group_manager[0x1];
 804         u8         ib_virt[0x1];
 805         u8         eth_virt[0x1];
 806         u8         reserved_at_1a4[0x1];
 807         u8         ets[0x1];
 808         u8         nic_flow_table[0x1];
 809         u8         eswitch_flow_table[0x1];
 810         u8         early_vf_enable[0x1];
 811         u8         reserved_at_1a9[0x2];
 812         u8         local_ca_ack_delay[0x5];
 813         u8         reserved_at_1af[0x2];
 814         u8         ports_check[0x1];
 815         u8         reserved_at_1b2[0x1];
 816         u8         disable_link_up[0x1];
 817         u8         beacon_led[0x1];
 818         u8         port_type[0x2];
 819         u8         num_ports[0x8];
 820
 821         u8         reserved_at_1c0[0x3];
 822         u8         log_max_msg[0x5];
 823         u8         reserved_at_1c8[0x4];
 824         u8         max_tc[0x4];
 825         u8         reserved_at_1d0[0x1];
 826         u8         dcbx[0x1];
 827         u8         reserved_at_1d2[0x4];
 828         u8         rol_s[0x1];
 829         u8         rol_g[0x1];
 830         u8         reserved_at_1d8[0x1];
 831         u8         wol_s[0x1];
 832         u8         wol_g[0x1];
 833         u8         wol_a[0x1];
 834         u8         wol_b[0x1];
 835         u8         wol_m[0x1];
 836         u8         wol_u[0x1];
 837         u8         wol_p[0x1];
 838
 839         u8         stat_rate_support[0x10];
 840         u8         reserved_at_1f0[0xc];
 841         u8         cqe_version[0x4];
 842
 843         u8         compact_address_vector[0x1];
 844         u8         striding_rq[0x1];
 845         u8         reserved_at_201[0x2];
 846         u8         ipoib_basic_offloads[0x1];
 847         u8         reserved_at_205[0x5];
 848         u8         umr_fence[0x2];
 849         u8         reserved_at_20c[0x3];
 850         u8         drain_sigerr[0x1];
 851         u8         cmdif_checksum[0x2];
 852         u8         sigerr_cqe[0x1];
 853         u8         reserved_at_213[0x1];
 854         u8         wq_signature[0x1];
 855         u8         sctr_data_cqe[0x1];
 856         u8         reserved_at_216[0x1];
 857         u8         sho[0x1];
 858         u8         tph[0x1];
 859         u8         rf[0x1];
 860         u8         dct[0x1];
 861         u8         qos[0x1];
 862         u8         eth_net_offloads[0x1];
 863         u8         roce[0x1];
 864         u8         atomic[0x1];
 865         u8         reserved_at_21f[0x1];
 866
 867         u8         cq_oi[0x1];
 868         u8         cq_resize[0x1];
 869         u8         cq_moderation[0x1];
 870         u8         reserved_at_223[0x3];
 871         u8         cq_eq_remap[0x1];
 872         u8         pg[0x1];
 873         u8         block_lb_mc[0x1];
 874         u8         reserved_at_229[0x1];
 875         u8         scqe_break_moderation[0x1];
 876         u8         cq_period_start_from_cqe[0x1];
 877         u8         cd[0x1];
 878         u8         reserved_at_22d[0x1];
 879         u8         apm[0x1];
 880         u8         vector_calc[0x1];
 881         u8         umr_ptr_rlky[0x1];
 882         u8         imaicl[0x1];
 883         u8         reserved_at_232[0x4];
 884         u8         qkv[0x1];
 885         u8         pkv[0x1];
 886         u8         set_deth_sqpn[0x1];
 887         u8         reserved_at_239[0x3];
 888         u8         xrc[0x1];
 889         u8         ud[0x1];
 890         u8         uc[0x1];
 891         u8         rc[0x1];
 892
 893         u8         reserved_at_240[0xa];
 894         u8         uar_sz[0x6];
 895         u8         reserved_at_250[0x8];
 896         u8         log_pg_sz[0x8];
 897
 898         u8         bf[0x1];
 899         u8         reserved_at_261[0x1];
 900         u8         pad_tx_eth_packet[0x1];
 901         u8         reserved_at_263[0x8];
 902         u8         log_bf_reg_size[0x5];
 903
 904         u8         reserved_at_270[0xb];
 905         u8         lag_master[0x1];
 906         u8         num_lag_ports[0x4];
 907
 908         u8         reserved_at_280[0x10];
 909         u8         max_wqe_sz_sq[0x10];
 910
 911         u8         reserved_at_2a0[0x10];
 912         u8         max_wqe_sz_rq[0x10];
 913
 914         u8         reserved_at_2c0[0x10];
 915         u8         max_wqe_sz_sq_dc[0x10];
 916
 917         u8         reserved_at_2e0[0x7];
 918         u8         max_qp_mcg[0x19];
 919
 920         u8         reserved_at_300[0x18];
 921         u8         log_max_mcg[0x8];
 922
 923         u8         reserved_at_320[0x3];
 924         u8         log_max_transport_domain[0x5];
 925         u8         reserved_at_328[0x3];
 926         u8         log_max_pd[0x5];
 927         u8         reserved_at_330[0xb];
 928         u8         log_max_xrcd[0x5];
 929
 930         u8         reserved_at_340[0x8];
 931         u8         log_max_flow_counter_bulk[0x8];
 932         u8         max_flow_counter[0x10];
 933
 934
 935         u8         reserved_at_360[0x3];
 936         u8         log_max_rq[0x5];
 937         u8         reserved_at_368[0x3];
 938         u8         log_max_sq[0x5];
 939         u8         reserved_at_370[0x3];
 940         u8         log_max_tir[0x5];
 941         u8         reserved_at_378[0x3];
 942         u8         log_max_tis[0x5];
 943
 944         u8         basic_cyclic_rcv_wqe[0x1];
 945         u8         reserved_at_381[0x2];
 946         u8         log_max_rmp[0x5];
 947         u8         reserved_at_388[0x3];
 948         u8         log_max_rqt[0x5];
 949         u8         reserved_at_390[0x3];
 950         u8         log_max_rqt_size[0x5];
 951         u8         reserved_at_398[0x3];
 952         u8         log_max_tis_per_sq[0x5];
 953
 954         u8         reserved_at_3a0[0x3];
 955         u8         log_max_stride_sz_rq[0x5];
 956         u8         reserved_at_3a8[0x3];
 957         u8         log_min_stride_sz_rq[0x5];
 958         u8         reserved_at_3b0[0x3];
 959         u8         log_max_stride_sz_sq[0x5];
 960         u8         reserved_at_3b8[0x3];
 961         u8         log_min_stride_sz_sq[0x5];
 962
 963         u8         reserved_at_3c0[0x1b];
 964         u8         log_max_wq_sz[0x5];
 965
 966         u8         nic_vport_change_event[0x1];
 967         u8         reserved_at_3e1[0xa];
 968         u8         log_max_vlan_list[0x5];
 969         u8         reserved_at_3f0[0x3];
 970         u8         log_max_current_mc_list[0x5];
 971         u8         reserved_at_3f8[0x3];
 972         u8         log_max_current_uc_list[0x5];
 973
 974         u8         reserved_at_400[0x80];
 975
 976         u8         reserved_at_480[0x3];
 977         u8         log_max_l2_table[0x5];
 978         u8         reserved_at_488[0x8];
 979         u8         log_uar_page_sz[0x10];
 980
 981         u8         reserved_at_4a0[0x20];
 982         u8         device_frequency_mhz[0x20];
 983         u8         device_frequency_khz[0x20];
 984
 985         u8         reserved_at_500[0x80];
 986
 987         u8         reserved_at_580[0x3f];
 988         u8         cqe_compression[0x1];
 989
 990         u8         cqe_compression_timeout[0x10];
 991         u8         cqe_compression_max_num[0x10];
 992
 993         u8         reserved_at_5e0[0x10];
 994         u8         tag_matching[0x1];
 995         u8         rndv_offload_rc[0x1];
 996         u8         rndv_offload_dc[0x1];
 997         u8         log_tag_matching_list_sz[0x5];
 998         u8         reserved_at_5e8[0x3];
 999         u8         log_max_xrq[0x5];
1000
1001         u8         reserved_at_5f0[0x200];
1002 };
1003
1004 enum mlx5_flow_destination_type {
1005         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1006         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1007         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1008
1009         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1010 };
1011
1012 struct mlx5_ifc_dest_format_struct_bits {
1013         u8         destination_type[0x8];
1014         u8         destination_id[0x18];
1015
1016         u8         reserved_at_20[0x20];
1017 };
1018
1019 struct mlx5_ifc_flow_counter_list_bits {
1020         u8         clear[0x1];
1021         u8         num_of_counters[0xf];
1022         u8         flow_counter_id[0x10];
1023
1024         u8         reserved_at_20[0x20];
1025 };
1026
1027 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1028         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1029         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1030         u8         reserved_at_0[0x40];
1031 };
1032
1033 struct mlx5_ifc_fte_match_param_bits {
1034         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1035
1036         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1037
1038         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1039
1040         u8         reserved_at_600[0xa00];
1041 };
1042
1043 enum {
1044         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1045         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1046         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1047         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1048         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1049 };
1050
1051 struct mlx5_ifc_rx_hash_field_select_bits {
1052         u8         l3_prot_type[0x1];
1053         u8         l4_prot_type[0x1];
1054         u8         selected_fields[0x1e];
1055 };
1056
1057 enum {
1058         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1059         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1060 };
1061
1062 enum {
1063         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1064         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1065 };
1066
1067 struct mlx5_ifc_wq_bits {
1068         u8         wq_type[0x4];
1069         u8         wq_signature[0x1];
1070         u8         end_padding_mode[0x2];
1071         u8         cd_slave[0x1];
1072         u8         reserved_at_8[0x18];
1073
1074         u8         hds_skip_first_sge[0x1];
1075         u8         log2_hds_buf_size[0x3];
1076         u8         reserved_at_24[0x7];
1077         u8         page_offset[0x5];
1078         u8         lwm[0x10];
1079
1080         u8         reserved_at_40[0x8];
1081         u8         pd[0x18];
1082
1083         u8         reserved_at_60[0x8];
1084         u8         uar_page[0x18];
1085
1086         u8         dbr_addr[0x40];
1087
1088         u8         hw_counter[0x20];
1089
1090         u8         sw_counter[0x20];
1091
1092         u8         reserved_at_100[0xc];
1093         u8         log_wq_stride[0x4];
1094         u8         reserved_at_110[0x3];
1095         u8         log_wq_pg_sz[0x5];
1096         u8         reserved_at_118[0x3];
1097         u8         log_wq_sz[0x5];
1098
1099         u8         reserved_at_120[0x15];
1100         u8         log_wqe_num_of_strides[0x3];
1101         u8         two_byte_shift_en[0x1];
1102         u8         reserved_at_139[0x4];
1103         u8         log_wqe_stride_size[0x3];
1104
1105         u8         reserved_at_140[0x4c0];
1106
1107         struct mlx5_ifc_cmd_pas_bits pas[0];
1108 };
1109
1110 struct mlx5_ifc_rq_num_bits {
1111         u8         reserved_at_0[0x8];
1112         u8         rq_num[0x18];
1113 };
1114
1115 struct mlx5_ifc_mac_address_layout_bits {
1116         u8         reserved_at_0[0x10];
1117         u8         mac_addr_47_32[0x10];
1118
1119         u8         mac_addr_31_0[0x20];
1120 };
1121
1122 struct mlx5_ifc_vlan_layout_bits {
1123         u8         reserved_at_0[0x14];
1124         u8         vlan[0x0c];
1125
1126         u8         reserved_at_20[0x20];
1127 };
1128
1129 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1130         u8         reserved_at_0[0xa0];
1131
1132         u8         min_time_between_cnps[0x20];
1133
1134         u8         reserved_at_c0[0x12];
1135         u8         cnp_dscp[0x6];
1136         u8         reserved_at_d8[0x5];
1137         u8         cnp_802p_prio[0x3];
1138
1139         u8         reserved_at_e0[0x720];
1140 };
1141
1142 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1143         u8         reserved_at_0[0x60];
1144
1145         u8         reserved_at_60[0x4];
1146         u8         clamp_tgt_rate[0x1];
1147         u8         reserved_at_65[0x3];
1148         u8         clamp_tgt_rate_after_time_inc[0x1];
1149         u8         reserved_at_69[0x17];
1150
1151         u8         reserved_at_80[0x20];
1152
1153         u8         rpg_time_reset[0x20];
1154
1155         u8         rpg_byte_reset[0x20];
1156
1157         u8         rpg_threshold[0x20];
1158
1159         u8         rpg_max_rate[0x20];
1160
1161         u8         rpg_ai_rate[0x20];
1162
1163         u8         rpg_hai_rate[0x20];
1164
1165         u8         rpg_gd[0x20];
1166
1167         u8         rpg_min_dec_fac[0x20];
1168
1169         u8         rpg_min_rate[0x20];
1170
1171         u8         reserved_at_1c0[0xe0];
1172
1173         u8         rate_to_set_on_first_cnp[0x20];
1174
1175         u8         dce_tcp_g[0x20];
1176
1177         u8         dce_tcp_rtt[0x20];
1178
1179         u8         rate_reduce_monitor_period[0x20];
1180
1181         u8         reserved_at_320[0x20];
1182
1183         u8         initial_alpha_value[0x20];
1184
1185         u8         reserved_at_360[0x4a0];
1186 };
1187
1188 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1189         u8         reserved_at_0[0x80];
1190
1191         u8         rppp_max_rps[0x20];
1192
1193         u8         rpg_time_reset[0x20];
1194
1195         u8         rpg_byte_reset[0x20];
1196
1197         u8         rpg_threshold[0x20];
1198
1199         u8         rpg_max_rate[0x20];
1200
1201         u8         rpg_ai_rate[0x20];
1202
1203         u8         rpg_hai_rate[0x20];
1204
1205         u8         rpg_gd[0x20];
1206
1207         u8         rpg_min_dec_fac[0x20];
1208
1209         u8         rpg_min_rate[0x20];
1210
1211         u8         reserved_at_1c0[0x640];
1212 };
1213
1214 enum {
1215         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1216         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1217         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1218 };
1219
1220 struct mlx5_ifc_resize_field_select_bits {
1221         u8         resize_field_select[0x20];
1222 };
1223
1224 enum {
1225         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1226         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1227         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1228         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1229 };
1230
1231 struct mlx5_ifc_modify_field_select_bits {
1232         u8         modify_field_select[0x20];
1233 };
1234
1235 struct mlx5_ifc_field_select_r_roce_np_bits {
1236         u8         field_select_r_roce_np[0x20];
1237 };
1238
1239 struct mlx5_ifc_field_select_r_roce_rp_bits {
1240         u8         field_select_r_roce_rp[0x20];
1241 };
1242
1243 enum {
1244         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1245         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1246         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1247         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1248         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1249         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1250         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1251         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1252         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1253         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1254 };
1255
1256 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1257         u8         field_select_8021qaurp[0x20];
1258 };
1259
1260 struct mlx5_ifc_phys_layer_cntrs_bits {
1261         u8         time_since_last_clear_high[0x20];
1262
1263         u8         time_since_last_clear_low[0x20];
1264
1265         u8         symbol_errors_high[0x20];
1266
1267         u8         symbol_errors_low[0x20];
1268
1269         u8         sync_headers_errors_high[0x20];
1270
1271         u8         sync_headers_errors_low[0x20];
1272
1273         u8         edpl_bip_errors_lane0_high[0x20];
1274
1275         u8         edpl_bip_errors_lane0_low[0x20];
1276
1277         u8         edpl_bip_errors_lane1_high[0x20];
1278
1279         u8         edpl_bip_errors_lane1_low[0x20];
1280
1281         u8         edpl_bip_errors_lane2_high[0x20];
1282
1283         u8         edpl_bip_errors_lane2_low[0x20];
1284
1285         u8         edpl_bip_errors_lane3_high[0x20];
1286
1287         u8         edpl_bip_errors_lane3_low[0x20];
1288
1289         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1290
1291         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1292
1293         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1294
1295         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1296
1297         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1298
1299         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1300
1301         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1302
1303         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1304
1305         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1306
1307         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1308
1309         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1310
1311         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1312
1313         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1314
1315         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1316
1317         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1318
1319         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1320
1321         u8         rs_fec_corrected_blocks_high[0x20];
1322
1323         u8         rs_fec_corrected_blocks_low[0x20];
1324
1325         u8         rs_fec_uncorrectable_blocks_high[0x20];
1326
1327         u8         rs_fec_uncorrectable_blocks_low[0x20];
1328
1329         u8         rs_fec_no_errors_blocks_high[0x20];
1330
1331         u8         rs_fec_no_errors_blocks_low[0x20];
1332
1333         u8         rs_fec_single_error_blocks_high[0x20];
1334
1335         u8         rs_fec_single_error_blocks_low[0x20];
1336
1337         u8         rs_fec_corrected_symbols_total_high[0x20];
1338
1339         u8         rs_fec_corrected_symbols_total_low[0x20];
1340
1341         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1342
1343         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1344
1345         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1346
1347         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1348
1349         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1350
1351         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1352
1353         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1354
1355         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1356
1357         u8         link_down_events[0x20];
1358
1359         u8         successful_recovery_events[0x20];
1360
1361         u8         reserved_at_640[0x180];
1362 };
1363
1364 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1365         u8         symbol_error_counter[0x10];
1366
1367         u8         link_error_recovery_counter[0x8];
1368
1369         u8         link_downed_counter[0x8];
1370
1371         u8         port_rcv_errors[0x10];
1372
1373         u8         port_rcv_remote_physical_errors[0x10];
1374
1375         u8         port_rcv_switch_relay_errors[0x10];
1376
1377         u8         port_xmit_discards[0x10];
1378
1379         u8         port_xmit_constraint_errors[0x8];
1380
1381         u8         port_rcv_constraint_errors[0x8];
1382
1383         u8         reserved_at_70[0x8];
1384
1385         u8         link_overrun_errors[0x8];
1386
1387         u8         reserved_at_80[0x10];
1388
1389         u8         vl_15_dropped[0x10];
1390
1391         u8         reserved_at_a0[0xa0];
1392 };
1393
1394 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1395         u8         transmit_queue_high[0x20];
1396
1397         u8         transmit_queue_low[0x20];
1398
1399         u8         reserved_at_40[0x780];
1400 };
1401
1402 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1403         u8         rx_octets_high[0x20];
1404
1405         u8         rx_octets_low[0x20];
1406
1407         u8         reserved_at_40[0xc0];
1408
1409         u8         rx_frames_high[0x20];
1410
1411         u8         rx_frames_low[0x20];
1412
1413         u8         tx_octets_high[0x20];
1414
1415         u8         tx_octets_low[0x20];
1416
1417         u8         reserved_at_180[0xc0];
1418
1419         u8         tx_frames_high[0x20];
1420
1421         u8         tx_frames_low[0x20];
1422
1423         u8         rx_pause_high[0x20];
1424
1425         u8         rx_pause_low[0x20];
1426
1427         u8         rx_pause_duration_high[0x20];
1428
1429         u8         rx_pause_duration_low[0x20];
1430
1431         u8         tx_pause_high[0x20];
1432
1433         u8         tx_pause_low[0x20];
1434
1435         u8         tx_pause_duration_high[0x20];
1436
1437         u8         tx_pause_duration_low[0x20];
1438
1439         u8         rx_pause_transition_high[0x20];
1440
1441         u8         rx_pause_transition_low[0x20];
1442
1443         u8         reserved_at_3c0[0x400];
1444 };
1445
1446 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1447         u8         port_transmit_wait_high[0x20];
1448
1449         u8         port_transmit_wait_low[0x20];
1450
1451         u8         reserved_at_40[0x780];
1452 };
1453
1454 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1455         u8         dot3stats_alignment_errors_high[0x20];
1456
1457         u8         dot3stats_alignment_errors_low[0x20];
1458
1459         u8         dot3stats_fcs_errors_high[0x20];
1460
1461         u8         dot3stats_fcs_errors_low[0x20];
1462
1463         u8         dot3stats_single_collision_frames_high[0x20];
1464
1465         u8         dot3stats_single_collision_frames_low[0x20];
1466
1467         u8         dot3stats_multiple_collision_frames_high[0x20];
1468
1469         u8         dot3stats_multiple_collision_frames_low[0x20];
1470
1471         u8         dot3stats_sqe_test_errors_high[0x20];
1472
1473         u8         dot3stats_sqe_test_errors_low[0x20];
1474
1475         u8         dot3stats_deferred_transmissions_high[0x20];
1476
1477         u8         dot3stats_deferred_transmissions_low[0x20];
1478
1479         u8         dot3stats_late_collisions_high[0x20];
1480
1481         u8         dot3stats_late_collisions_low[0x20];
1482
1483         u8         dot3stats_excessive_collisions_high[0x20];
1484
1485         u8         dot3stats_excessive_collisions_low[0x20];
1486
1487         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1488
1489         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1490
1491         u8         dot3stats_carrier_sense_errors_high[0x20];
1492
1493         u8         dot3stats_carrier_sense_errors_low[0x20];
1494
1495         u8         dot3stats_frame_too_longs_high[0x20];
1496
1497         u8         dot3stats_frame_too_longs_low[0x20];
1498
1499         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1500
1501         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1502
1503         u8         dot3stats_symbol_errors_high[0x20];
1504
1505         u8         dot3stats_symbol_errors_low[0x20];
1506
1507         u8         dot3control_in_unknown_opcodes_high[0x20];
1508
1509         u8         dot3control_in_unknown_opcodes_low[0x20];
1510
1511         u8         dot3in_pause_frames_high[0x20];
1512
1513         u8         dot3in_pause_frames_low[0x20];
1514
1515         u8         dot3out_pause_frames_high[0x20];
1516
1517         u8         dot3out_pause_frames_low[0x20];
1518
1519         u8         reserved_at_400[0x3c0];
1520 };
1521
1522 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1523         u8         ether_stats_drop_events_high[0x20];
1524
1525         u8         ether_stats_drop_events_low[0x20];
1526
1527         u8         ether_stats_octets_high[0x20];
1528
1529         u8         ether_stats_octets_low[0x20];
1530
1531         u8         ether_stats_pkts_high[0x20];
1532
1533         u8         ether_stats_pkts_low[0x20];
1534
1535         u8         ether_stats_broadcast_pkts_high[0x20];
1536
1537         u8         ether_stats_broadcast_pkts_low[0x20];
1538
1539         u8         ether_stats_multicast_pkts_high[0x20];
1540
1541         u8         ether_stats_multicast_pkts_low[0x20];
1542
1543         u8         ether_stats_crc_align_errors_high[0x20];
1544
1545         u8         ether_stats_crc_align_errors_low[0x20];
1546
1547         u8         ether_stats_undersize_pkts_high[0x20];
1548
1549         u8         ether_stats_undersize_pkts_low[0x20];
1550
1551         u8         ether_stats_oversize_pkts_high[0x20];
1552
1553         u8         ether_stats_oversize_pkts_low[0x20];
1554
1555         u8         ether_stats_fragments_high[0x20];
1556
1557         u8         ether_stats_fragments_low[0x20];
1558
1559         u8         ether_stats_jabbers_high[0x20];
1560
1561         u8         ether_stats_jabbers_low[0x20];
1562
1563         u8         ether_stats_collisions_high[0x20];
1564
1565         u8         ether_stats_collisions_low[0x20];
1566
1567         u8         ether_stats_pkts64octets_high[0x20];
1568
1569         u8         ether_stats_pkts64octets_low[0x20];
1570
1571         u8         ether_stats_pkts65to127octets_high[0x20];
1572
1573         u8         ether_stats_pkts65to127octets_low[0x20];
1574
1575         u8         ether_stats_pkts128to255octets_high[0x20];
1576
1577         u8         ether_stats_pkts128to255octets_low[0x20];
1578
1579         u8         ether_stats_pkts256to511octets_high[0x20];
1580
1581         u8         ether_stats_pkts256to511octets_low[0x20];
1582
1583         u8         ether_stats_pkts512to1023octets_high[0x20];
1584
1585         u8         ether_stats_pkts512to1023octets_low[0x20];
1586
1587         u8         ether_stats_pkts1024to1518octets_high[0x20];
1588
1589         u8         ether_stats_pkts1024to1518octets_low[0x20];
1590
1591         u8         ether_stats_pkts1519to2047octets_high[0x20];
1592
1593         u8         ether_stats_pkts1519to2047octets_low[0x20];
1594
1595         u8         ether_stats_pkts2048to4095octets_high[0x20];
1596
1597         u8         ether_stats_pkts2048to4095octets_low[0x20];
1598
1599         u8         ether_stats_pkts4096to8191octets_high[0x20];
1600
1601         u8         ether_stats_pkts4096to8191octets_low[0x20];
1602
1603         u8         ether_stats_pkts8192to10239octets_high[0x20];
1604
1605         u8         ether_stats_pkts8192to10239octets_low[0x20];
1606
1607         u8         reserved_at_540[0x280];
1608 };
1609
1610 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1611         u8         if_in_octets_high[0x20];
1612
1613         u8         if_in_octets_low[0x20];
1614
1615         u8         if_in_ucast_pkts_high[0x20];
1616
1617         u8         if_in_ucast_pkts_low[0x20];
1618
1619         u8         if_in_discards_high[0x20];
1620
1621         u8         if_in_discards_low[0x20];
1622
1623         u8         if_in_errors_high[0x20];
1624
1625         u8         if_in_errors_low[0x20];
1626
1627         u8         if_in_unknown_protos_high[0x20];
1628
1629         u8         if_in_unknown_protos_low[0x20];
1630
1631         u8         if_out_octets_high[0x20];
1632
1633         u8         if_out_octets_low[0x20];
1634
1635         u8         if_out_ucast_pkts_high[0x20];
1636
1637         u8         if_out_ucast_pkts_low[0x20];
1638
1639         u8         if_out_discards_high[0x20];
1640
1641         u8         if_out_discards_low[0x20];
1642
1643         u8         if_out_errors_high[0x20];
1644
1645         u8         if_out_errors_low[0x20];
1646
1647         u8         if_in_multicast_pkts_high[0x20];
1648
1649         u8         if_in_multicast_pkts_low[0x20];
1650
1651         u8         if_in_broadcast_pkts_high[0x20];
1652
1653         u8         if_in_broadcast_pkts_low[0x20];
1654
1655         u8         if_out_multicast_pkts_high[0x20];
1656
1657         u8         if_out_multicast_pkts_low[0x20];
1658
1659         u8         if_out_broadcast_pkts_high[0x20];
1660
1661         u8         if_out_broadcast_pkts_low[0x20];
1662
1663         u8         reserved_at_340[0x480];
1664 };
1665
1666 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1667         u8         a_frames_transmitted_ok_high[0x20];
1668
1669         u8         a_frames_transmitted_ok_low[0x20];
1670
1671         u8         a_frames_received_ok_high[0x20];
1672
1673         u8         a_frames_received_ok_low[0x20];
1674
1675         u8         a_frame_check_sequence_errors_high[0x20];
1676
1677         u8         a_frame_check_sequence_errors_low[0x20];
1678
1679         u8         a_alignment_errors_high[0x20];
1680
1681         u8         a_alignment_errors_low[0x20];
1682
1683         u8         a_octets_transmitted_ok_high[0x20];
1684
1685         u8         a_octets_transmitted_ok_low[0x20];
1686
1687         u8         a_octets_received_ok_high[0x20];
1688
1689         u8         a_octets_received_ok_low[0x20];
1690
1691         u8         a_multicast_frames_xmitted_ok_high[0x20];
1692
1693         u8         a_multicast_frames_xmitted_ok_low[0x20];
1694
1695         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1696
1697         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1698
1699         u8         a_multicast_frames_received_ok_high[0x20];
1700
1701         u8         a_multicast_frames_received_ok_low[0x20];
1702
1703         u8         a_broadcast_frames_received_ok_high[0x20];
1704
1705         u8         a_broadcast_frames_received_ok_low[0x20];
1706
1707         u8         a_in_range_length_errors_high[0x20];
1708
1709         u8         a_in_range_length_errors_low[0x20];
1710
1711         u8         a_out_of_range_length_field_high[0x20];
1712
1713         u8         a_out_of_range_length_field_low[0x20];
1714
1715         u8         a_frame_too_long_errors_high[0x20];
1716
1717         u8         a_frame_too_long_errors_low[0x20];
1718
1719         u8         a_symbol_error_during_carrier_high[0x20];
1720
1721         u8         a_symbol_error_during_carrier_low[0x20];
1722
1723         u8         a_mac_control_frames_transmitted_high[0x20];
1724
1725         u8         a_mac_control_frames_transmitted_low[0x20];
1726
1727         u8         a_mac_control_frames_received_high[0x20];
1728
1729         u8         a_mac_control_frames_received_low[0x20];
1730
1731         u8         a_unsupported_opcodes_received_high[0x20];
1732
1733         u8         a_unsupported_opcodes_received_low[0x20];
1734
1735         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1736
1737         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1738
1739         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1740
1741         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1742
1743         u8         reserved_at_4c0[0x300];
1744 };
1745
1746 struct mlx5_ifc_cmd_inter_comp_event_bits {
1747         u8         command_completion_vector[0x20];
1748
1749         u8         reserved_at_20[0xc0];
1750 };
1751
1752 struct mlx5_ifc_stall_vl_event_bits {
1753         u8         reserved_at_0[0x18];
1754         u8         port_num[0x1];
1755         u8         reserved_at_19[0x3];
1756         u8         vl[0x4];
1757
1758         u8         reserved_at_20[0xa0];
1759 };
1760
1761 struct mlx5_ifc_db_bf_congestion_event_bits {
1762         u8         event_subtype[0x8];
1763         u8         reserved_at_8[0x8];
1764         u8         congestion_level[0x8];
1765         u8         reserved_at_18[0x8];
1766
1767         u8         reserved_at_20[0xa0];
1768 };
1769
1770 struct mlx5_ifc_gpio_event_bits {
1771         u8         reserved_at_0[0x60];
1772
1773         u8         gpio_event_hi[0x20];
1774
1775         u8         gpio_event_lo[0x20];
1776
1777         u8         reserved_at_a0[0x40];
1778 };
1779
1780 struct mlx5_ifc_port_state_change_event_bits {
1781         u8         reserved_at_0[0x40];
1782
1783         u8         port_num[0x4];
1784         u8         reserved_at_44[0x1c];
1785
1786         u8         reserved_at_60[0x80];
1787 };
1788
1789 struct mlx5_ifc_dropped_packet_logged_bits {
1790         u8         reserved_at_0[0xe0];
1791 };
1792
1793 enum {
1794         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1795         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1796 };
1797
1798 struct mlx5_ifc_cq_error_bits {
1799         u8         reserved_at_0[0x8];
1800         u8         cqn[0x18];
1801
1802         u8         reserved_at_20[0x20];
1803
1804         u8         reserved_at_40[0x18];
1805         u8         syndrome[0x8];
1806
1807         u8         reserved_at_60[0x80];
1808 };
1809
1810 struct mlx5_ifc_rdma_page_fault_event_bits {
1811         u8         bytes_committed[0x20];
1812
1813         u8         r_key[0x20];
1814
1815         u8         reserved_at_40[0x10];
1816         u8         packet_len[0x10];
1817
1818         u8         rdma_op_len[0x20];
1819
1820         u8         rdma_va[0x40];
1821
1822         u8         reserved_at_c0[0x5];
1823         u8         rdma[0x1];
1824         u8         write[0x1];
1825         u8         requestor[0x1];
1826         u8         qp_number[0x18];
1827 };
1828
1829 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1830         u8         bytes_committed[0x20];
1831
1832         u8         reserved_at_20[0x10];
1833         u8         wqe_index[0x10];
1834
1835         u8         reserved_at_40[0x10];
1836         u8         len[0x10];
1837
1838         u8         reserved_at_60[0x60];
1839
1840         u8         reserved_at_c0[0x5];
1841         u8         rdma[0x1];
1842         u8         write_read[0x1];
1843         u8         requestor[0x1];
1844         u8         qpn[0x18];
1845 };
1846
1847 struct mlx5_ifc_qp_events_bits {
1848         u8         reserved_at_0[0xa0];
1849
1850         u8         type[0x8];
1851         u8         reserved_at_a8[0x18];
1852
1853         u8         reserved_at_c0[0x8];
1854         u8         qpn_rqn_sqn[0x18];
1855 };
1856
1857 struct mlx5_ifc_dct_events_bits {
1858         u8         reserved_at_0[0xc0];
1859
1860         u8         reserved_at_c0[0x8];
1861         u8         dct_number[0x18];
1862 };
1863
1864 struct mlx5_ifc_comp_event_bits {
1865         u8         reserved_at_0[0xc0];
1866
1867         u8         reserved_at_c0[0x8];
1868         u8         cq_number[0x18];
1869 };
1870
1871 enum {
1872         MLX5_QPC_STATE_RST        = 0x0,
1873         MLX5_QPC_STATE_INIT       = 0x1,
1874         MLX5_QPC_STATE_RTR        = 0x2,
1875         MLX5_QPC_STATE_RTS        = 0x3,
1876         MLX5_QPC_STATE_SQER       = 0x4,
1877         MLX5_QPC_STATE_ERR        = 0x6,
1878         MLX5_QPC_STATE_SQD        = 0x7,
1879         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1880 };
1881
1882 enum {
1883         MLX5_QPC_ST_RC            = 0x0,
1884         MLX5_QPC_ST_UC            = 0x1,
1885         MLX5_QPC_ST_UD            = 0x2,
1886         MLX5_QPC_ST_XRC           = 0x3,
1887         MLX5_QPC_ST_DCI           = 0x5,
1888         MLX5_QPC_ST_QP0           = 0x7,
1889         MLX5_QPC_ST_QP1           = 0x8,
1890         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1891         MLX5_QPC_ST_REG_UMR       = 0xc,
1892 };
1893
1894 enum {
1895         MLX5_QPC_PM_STATE_ARMED     = 0x0,
1896         MLX5_QPC_PM_STATE_REARM     = 0x1,
1897         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1898         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
1899 };
1900
1901 enum {
1902         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1903         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1904 };
1905
1906 enum {
1907         MLX5_QPC_MTU_256_BYTES        = 0x1,
1908         MLX5_QPC_MTU_512_BYTES        = 0x2,
1909         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1910         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1911         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1912         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1913 };
1914
1915 enum {
1916         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1917         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1918         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1919         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1920         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1921         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1922         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1923         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1924 };
1925
1926 enum {
1927         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1928         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1929         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1930 };
1931
1932 enum {
1933         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1934         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1935         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1936 };
1937
1938 struct mlx5_ifc_qpc_bits {
1939         u8         state[0x4];
1940         u8         lag_tx_port_affinity[0x4];
1941         u8         st[0x8];
1942         u8         reserved_at_10[0x3];
1943         u8         pm_state[0x2];
1944         u8         reserved_at_15[0x7];
1945         u8         end_padding_mode[0x2];
1946         u8         reserved_at_1e[0x2];
1947
1948         u8         wq_signature[0x1];
1949         u8         block_lb_mc[0x1];
1950         u8         atomic_like_write_en[0x1];
1951         u8         latency_sensitive[0x1];
1952         u8         reserved_at_24[0x1];
1953         u8         drain_sigerr[0x1];
1954         u8         reserved_at_26[0x2];
1955         u8         pd[0x18];
1956
1957         u8         mtu[0x3];
1958         u8         log_msg_max[0x5];
1959         u8         reserved_at_48[0x1];
1960         u8         log_rq_size[0x4];
1961         u8         log_rq_stride[0x3];
1962         u8         no_sq[0x1];
1963         u8         log_sq_size[0x4];
1964         u8         reserved_at_55[0x6];
1965         u8         rlky[0x1];
1966         u8         ulp_stateless_offload_mode[0x4];
1967
1968         u8         counter_set_id[0x8];
1969         u8         uar_page[0x18];
1970
1971         u8         reserved_at_80[0x8];
1972         u8         user_index[0x18];
1973
1974         u8         reserved_at_a0[0x3];
1975         u8         log_page_size[0x5];
1976         u8         remote_qpn[0x18];
1977
1978         struct mlx5_ifc_ads_bits primary_address_path;
1979
1980         struct mlx5_ifc_ads_bits secondary_address_path;
1981
1982         u8         log_ack_req_freq[0x4];
1983         u8         reserved_at_384[0x4];
1984         u8         log_sra_max[0x3];
1985         u8         reserved_at_38b[0x2];
1986         u8         retry_count[0x3];
1987         u8         rnr_retry[0x3];
1988         u8         reserved_at_393[0x1];
1989         u8         fre[0x1];
1990         u8         cur_rnr_retry[0x3];
1991         u8         cur_retry_count[0x3];
1992         u8         reserved_at_39b[0x5];
1993
1994         u8         reserved_at_3a0[0x20];
1995
1996         u8         reserved_at_3c0[0x8];
1997         u8         next_send_psn[0x18];
1998
1999         u8         reserved_at_3e0[0x8];
2000         u8         cqn_snd[0x18];
2001
2002         u8         reserved_at_400[0x8];
2003         u8         deth_sqpn[0x18];
2004
2005         u8         reserved_at_420[0x20];
2006
2007         u8         reserved_at_440[0x8];
2008         u8         last_acked_psn[0x18];
2009
2010         u8         reserved_at_460[0x8];
2011         u8         ssn[0x18];
2012
2013         u8         reserved_at_480[0x8];
2014         u8         log_rra_max[0x3];
2015         u8         reserved_at_48b[0x1];
2016         u8         atomic_mode[0x4];
2017         u8         rre[0x1];
2018         u8         rwe[0x1];
2019         u8         rae[0x1];
2020         u8         reserved_at_493[0x1];
2021         u8         page_offset[0x6];
2022         u8         reserved_at_49a[0x3];
2023         u8         cd_slave_receive[0x1];
2024         u8         cd_slave_send[0x1];
2025         u8         cd_master[0x1];
2026
2027         u8         reserved_at_4a0[0x3];
2028         u8         min_rnr_nak[0x5];
2029         u8         next_rcv_psn[0x18];
2030
2031         u8         reserved_at_4c0[0x8];
2032         u8         xrcd[0x18];
2033
2034         u8         reserved_at_4e0[0x8];
2035         u8         cqn_rcv[0x18];
2036
2037         u8         dbr_addr[0x40];
2038
2039         u8         q_key[0x20];
2040
2041         u8         reserved_at_560[0x5];
2042         u8         rq_type[0x3];
2043         u8         srqn_rmpn_xrqn[0x18];
2044
2045         u8         reserved_at_580[0x8];
2046         u8         rmsn[0x18];
2047
2048         u8         hw_sq_wqebb_counter[0x10];
2049         u8         sw_sq_wqebb_counter[0x10];
2050
2051         u8         hw_rq_counter[0x20];
2052
2053         u8         sw_rq_counter[0x20];
2054
2055         u8         reserved_at_600[0x20];
2056
2057         u8         reserved_at_620[0xf];
2058         u8         cgs[0x1];
2059         u8         cs_req[0x8];
2060         u8         cs_res[0x8];
2061
2062         u8         dc_access_key[0x40];
2063
2064         u8         reserved_at_680[0xc0];
2065 };
2066
2067 struct mlx5_ifc_roce_addr_layout_bits {
2068         u8         source_l3_address[16][0x8];
2069
2070         u8         reserved_at_80[0x3];
2071         u8         vlan_valid[0x1];
2072         u8         vlan_id[0xc];
2073         u8         source_mac_47_32[0x10];
2074
2075         u8         source_mac_31_0[0x20];
2076
2077         u8         reserved_at_c0[0x14];
2078         u8         roce_l3_type[0x4];
2079         u8         roce_version[0x8];
2080
2081         u8         reserved_at_e0[0x20];
2082 };
2083
2084 union mlx5_ifc_hca_cap_union_bits {
2085         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2086         struct mlx5_ifc_odp_cap_bits odp_cap;
2087         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2088         struct mlx5_ifc_roce_cap_bits roce_cap;
2089         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2090         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2091         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2092         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2093         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2094         struct mlx5_ifc_qos_cap_bits qos_cap;
2095         u8         reserved_at_0[0x8000];
2096 };
2097
2098 enum {
2099         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2100         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2101         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2102         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2103         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2104         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2105 };
2106
2107 struct mlx5_ifc_flow_context_bits {
2108         u8         reserved_at_0[0x20];
2109
2110         u8         group_id[0x20];
2111
2112         u8         reserved_at_40[0x8];
2113         u8         flow_tag[0x18];
2114
2115         u8         reserved_at_60[0x10];
2116         u8         action[0x10];
2117
2118         u8         reserved_at_80[0x8];
2119         u8         destination_list_size[0x18];
2120
2121         u8         reserved_at_a0[0x8];
2122         u8         flow_counter_list_size[0x18];
2123
2124         u8         encap_id[0x20];
2125
2126         u8         reserved_at_e0[0x120];
2127
2128         struct mlx5_ifc_fte_match_param_bits match_value;
2129
2130         u8         reserved_at_1200[0x600];
2131
2132         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2133 };
2134
2135 enum {
2136         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2137         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2138 };
2139
2140 struct mlx5_ifc_xrc_srqc_bits {
2141         u8         state[0x4];
2142         u8         log_xrc_srq_size[0x4];
2143         u8         reserved_at_8[0x18];
2144
2145         u8         wq_signature[0x1];
2146         u8         cont_srq[0x1];
2147         u8         reserved_at_22[0x1];
2148         u8         rlky[0x1];
2149         u8         basic_cyclic_rcv_wqe[0x1];
2150         u8         log_rq_stride[0x3];
2151         u8         xrcd[0x18];
2152
2153         u8         page_offset[0x6];
2154         u8         reserved_at_46[0x2];
2155         u8         cqn[0x18];
2156
2157         u8         reserved_at_60[0x20];
2158
2159         u8         user_index_equal_xrc_srqn[0x1];
2160         u8         reserved_at_81[0x1];
2161         u8         log_page_size[0x6];
2162         u8         user_index[0x18];
2163
2164         u8         reserved_at_a0[0x20];
2165
2166         u8         reserved_at_c0[0x8];
2167         u8         pd[0x18];
2168
2169         u8         lwm[0x10];
2170         u8         wqe_cnt[0x10];
2171
2172         u8         reserved_at_100[0x40];
2173
2174         u8         db_record_addr_h[0x20];
2175
2176         u8         db_record_addr_l[0x1e];
2177         u8         reserved_at_17e[0x2];
2178
2179         u8         reserved_at_180[0x80];
2180 };
2181
2182 struct mlx5_ifc_traffic_counter_bits {
2183         u8         packets[0x40];
2184
2185         u8         octets[0x40];
2186 };
2187
2188 struct mlx5_ifc_tisc_bits {
2189         u8         strict_lag_tx_port_affinity[0x1];
2190         u8         reserved_at_1[0x3];
2191         u8         lag_tx_port_affinity[0x04];
2192
2193         u8         reserved_at_8[0x4];
2194         u8         prio[0x4];
2195         u8         reserved_at_10[0x10];
2196
2197         u8         reserved_at_20[0x100];
2198
2199         u8         reserved_at_120[0x8];
2200         u8         transport_domain[0x18];
2201
2202         u8         reserved_at_140[0x3c0];
2203 };
2204
2205 enum {
2206         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2207         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2208 };
2209
2210 enum {
2211         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2212         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2213 };
2214
2215 enum {
2216         MLX5_RX_HASH_FN_NONE           = 0x0,
2217         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2218         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2219 };
2220
2221 enum {
2222         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2223         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2224 };
2225
2226 struct mlx5_ifc_tirc_bits {
2227         u8         reserved_at_0[0x20];
2228
2229         u8         disp_type[0x4];
2230         u8         reserved_at_24[0x1c];
2231
2232         u8         reserved_at_40[0x40];
2233
2234         u8         reserved_at_80[0x4];
2235         u8         lro_timeout_period_usecs[0x10];
2236         u8         lro_enable_mask[0x4];
2237         u8         lro_max_ip_payload_size[0x8];
2238
2239         u8         reserved_at_a0[0x40];
2240
2241         u8         reserved_at_e0[0x8];
2242         u8         inline_rqn[0x18];
2243
2244         u8         rx_hash_symmetric[0x1];
2245         u8         reserved_at_101[0x1];
2246         u8         tunneled_offload_en[0x1];
2247         u8         reserved_at_103[0x5];
2248         u8         indirect_table[0x18];
2249
2250         u8         rx_hash_fn[0x4];
2251         u8         reserved_at_124[0x2];
2252         u8         self_lb_block[0x2];
2253         u8         transport_domain[0x18];
2254
2255         u8         rx_hash_toeplitz_key[10][0x20];
2256
2257         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2258
2259         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2260
2261         u8         reserved_at_2c0[0x4c0];
2262 };
2263
2264 enum {
2265         MLX5_SRQC_STATE_GOOD   = 0x0,
2266         MLX5_SRQC_STATE_ERROR  = 0x1,
2267 };
2268
2269 struct mlx5_ifc_srqc_bits {
2270         u8         state[0x4];
2271         u8         log_srq_size[0x4];
2272         u8         reserved_at_8[0x18];
2273
2274         u8         wq_signature[0x1];
2275         u8         cont_srq[0x1];
2276         u8         reserved_at_22[0x1];
2277         u8         rlky[0x1];
2278         u8         reserved_at_24[0x1];
2279         u8         log_rq_stride[0x3];
2280         u8         xrcd[0x18];
2281
2282         u8         page_offset[0x6];
2283         u8         reserved_at_46[0x2];
2284         u8         cqn[0x18];
2285
2286         u8         reserved_at_60[0x20];
2287
2288         u8         reserved_at_80[0x2];
2289         u8         log_page_size[0x6];
2290         u8         reserved_at_88[0x18];
2291
2292         u8         reserved_at_a0[0x20];
2293
2294         u8         reserved_at_c0[0x8];
2295         u8         pd[0x18];
2296
2297         u8         lwm[0x10];
2298         u8         wqe_cnt[0x10];
2299
2300         u8         reserved_at_100[0x40];
2301
2302         u8         dbr_addr[0x40];
2303
2304         u8         reserved_at_180[0x80];
2305 };
2306
2307 enum {
2308         MLX5_SQC_STATE_RST  = 0x0,
2309         MLX5_SQC_STATE_RDY  = 0x1,
2310         MLX5_SQC_STATE_ERR  = 0x3,
2311 };
2312
2313 struct mlx5_ifc_sqc_bits {
2314         u8         rlky[0x1];
2315         u8         cd_master[0x1];
2316         u8         fre[0x1];
2317         u8         flush_in_error_en[0x1];
2318         u8         reserved_at_4[0x1];
2319         u8         min_wqe_inline_mode[0x3];
2320         u8         state[0x4];
2321         u8         reg_umr[0x1];
2322         u8         reserved_at_d[0x13];
2323
2324         u8         reserved_at_20[0x8];
2325         u8         user_index[0x18];
2326
2327         u8         reserved_at_40[0x8];
2328         u8         cqn[0x18];
2329
2330         u8         reserved_at_60[0x90];
2331
2332         u8         packet_pacing_rate_limit_index[0x10];
2333         u8         tis_lst_sz[0x10];
2334         u8         reserved_at_110[0x10];
2335
2336         u8         reserved_at_120[0x40];
2337
2338         u8         reserved_at_160[0x8];
2339         u8         tis_num_0[0x18];
2340
2341         struct mlx5_ifc_wq_bits wq;
2342 };
2343
2344 struct mlx5_ifc_rqtc_bits {
2345         u8         reserved_at_0[0xa0];
2346
2347         u8         reserved_at_a0[0x10];
2348         u8         rqt_max_size[0x10];
2349
2350         u8         reserved_at_c0[0x10];
2351         u8         rqt_actual_size[0x10];
2352
2353         u8         reserved_at_e0[0x6a0];
2354
2355         struct mlx5_ifc_rq_num_bits rq_num[0];
2356 };
2357
2358 enum {
2359         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2360         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2361 };
2362
2363 enum {
2364         MLX5_RQC_STATE_RST  = 0x0,
2365         MLX5_RQC_STATE_RDY  = 0x1,
2366         MLX5_RQC_STATE_ERR  = 0x3,
2367 };
2368
2369 struct mlx5_ifc_rqc_bits {
2370         u8         rlky[0x1];
2371         u8         reserved_at_1[0x1];
2372         u8         scatter_fcs[0x1];
2373         u8         vsd[0x1];
2374         u8         mem_rq_type[0x4];
2375         u8         state[0x4];
2376         u8         reserved_at_c[0x1];
2377         u8         flush_in_error_en[0x1];
2378         u8         reserved_at_e[0x12];
2379
2380         u8         reserved_at_20[0x8];
2381         u8         user_index[0x18];
2382
2383         u8         reserved_at_40[0x8];
2384         u8         cqn[0x18];
2385
2386         u8         counter_set_id[0x8];
2387         u8         reserved_at_68[0x18];
2388
2389         u8         reserved_at_80[0x8];
2390         u8         rmpn[0x18];
2391
2392         u8         reserved_at_a0[0xe0];
2393
2394         struct mlx5_ifc_wq_bits wq;
2395 };
2396
2397 enum {
2398         MLX5_RMPC_STATE_RDY  = 0x1,
2399         MLX5_RMPC_STATE_ERR  = 0x3,
2400 };
2401
2402 struct mlx5_ifc_rmpc_bits {
2403         u8         reserved_at_0[0x8];
2404         u8         state[0x4];
2405         u8         reserved_at_c[0x14];
2406
2407         u8         basic_cyclic_rcv_wqe[0x1];
2408         u8         reserved_at_21[0x1f];
2409
2410         u8         reserved_at_40[0x140];
2411
2412         struct mlx5_ifc_wq_bits wq;
2413 };
2414
2415 struct mlx5_ifc_nic_vport_context_bits {
2416         u8         reserved_at_0[0x5];
2417         u8         min_wqe_inline_mode[0x3];
2418         u8         reserved_at_8[0x17];
2419         u8         roce_en[0x1];
2420
2421         u8         arm_change_event[0x1];
2422         u8         reserved_at_21[0x1a];
2423         u8         event_on_mtu[0x1];
2424         u8         event_on_promisc_change[0x1];
2425         u8         event_on_vlan_change[0x1];
2426         u8         event_on_mc_address_change[0x1];
2427         u8         event_on_uc_address_change[0x1];
2428
2429         u8         reserved_at_40[0xf0];
2430
2431         u8         mtu[0x10];
2432
2433         u8         system_image_guid[0x40];
2434         u8         port_guid[0x40];
2435         u8         node_guid[0x40];
2436
2437         u8         reserved_at_200[0x140];
2438         u8         qkey_violation_counter[0x10];
2439         u8         reserved_at_350[0x430];
2440
2441         u8         promisc_uc[0x1];
2442         u8         promisc_mc[0x1];
2443         u8         promisc_all[0x1];
2444         u8         reserved_at_783[0x2];
2445         u8         allowed_list_type[0x3];
2446         u8         reserved_at_788[0xc];
2447         u8         allowed_list_size[0xc];
2448
2449         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2450
2451         u8         reserved_at_7e0[0x20];
2452
2453         u8         current_uc_mac_address[0][0x40];
2454 };
2455
2456 enum {
2457         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2458         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2459         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2460 };
2461
2462 struct mlx5_ifc_mkc_bits {
2463         u8         reserved_at_0[0x1];
2464         u8         free[0x1];
2465         u8         reserved_at_2[0xd];
2466         u8         small_fence_on_rdma_read_response[0x1];
2467         u8         umr_en[0x1];
2468         u8         a[0x1];
2469         u8         rw[0x1];
2470         u8         rr[0x1];
2471         u8         lw[0x1];
2472         u8         lr[0x1];
2473         u8         access_mode[0x2];
2474         u8         reserved_at_18[0x8];
2475
2476         u8         qpn[0x18];
2477         u8         mkey_7_0[0x8];
2478
2479         u8         reserved_at_40[0x20];
2480
2481         u8         length64[0x1];
2482         u8         bsf_en[0x1];
2483         u8         sync_umr[0x1];
2484         u8         reserved_at_63[0x2];
2485         u8         expected_sigerr_count[0x1];
2486         u8         reserved_at_66[0x1];
2487         u8         en_rinval[0x1];
2488         u8         pd[0x18];
2489
2490         u8         start_addr[0x40];
2491
2492         u8         len[0x40];
2493
2494         u8         bsf_octword_size[0x20];
2495
2496         u8         reserved_at_120[0x80];
2497
2498         u8         translations_octword_size[0x20];
2499
2500         u8         reserved_at_1c0[0x1b];
2501         u8         log_page_size[0x5];
2502
2503         u8         reserved_at_1e0[0x20];
2504 };
2505
2506 struct mlx5_ifc_pkey_bits {
2507         u8         reserved_at_0[0x10];
2508         u8         pkey[0x10];
2509 };
2510
2511 struct mlx5_ifc_array128_auto_bits {
2512         u8         array128_auto[16][0x8];
2513 };
2514
2515 struct mlx5_ifc_hca_vport_context_bits {
2516         u8         field_select[0x20];
2517
2518         u8         reserved_at_20[0xe0];
2519
2520         u8         sm_virt_aware[0x1];
2521         u8         has_smi[0x1];
2522         u8         has_raw[0x1];
2523         u8         grh_required[0x1];
2524         u8         reserved_at_104[0xc];
2525         u8         port_physical_state[0x4];
2526         u8         vport_state_policy[0x4];
2527         u8         port_state[0x4];
2528         u8         vport_state[0x4];
2529
2530         u8         reserved_at_120[0x20];
2531
2532         u8         system_image_guid[0x40];
2533
2534         u8         port_guid[0x40];
2535
2536         u8         node_guid[0x40];
2537
2538         u8         cap_mask1[0x20];
2539
2540         u8         cap_mask1_field_select[0x20];
2541
2542         u8         cap_mask2[0x20];
2543
2544         u8         cap_mask2_field_select[0x20];
2545
2546         u8         reserved_at_280[0x80];
2547
2548         u8         lid[0x10];
2549         u8         reserved_at_310[0x4];
2550         u8         init_type_reply[0x4];
2551         u8         lmc[0x3];
2552         u8         subnet_timeout[0x5];
2553
2554         u8         sm_lid[0x10];
2555         u8         sm_sl[0x4];
2556         u8         reserved_at_334[0xc];
2557
2558         u8         qkey_violation_counter[0x10];
2559         u8         pkey_violation_counter[0x10];
2560
2561         u8         reserved_at_360[0xca0];
2562 };
2563
2564 struct mlx5_ifc_esw_vport_context_bits {
2565         u8         reserved_at_0[0x3];
2566         u8         vport_svlan_strip[0x1];
2567         u8         vport_cvlan_strip[0x1];
2568         u8         vport_svlan_insert[0x1];
2569         u8         vport_cvlan_insert[0x2];
2570         u8         reserved_at_8[0x18];
2571
2572         u8         reserved_at_20[0x20];
2573
2574         u8         svlan_cfi[0x1];
2575         u8         svlan_pcp[0x3];
2576         u8         svlan_id[0xc];
2577         u8         cvlan_cfi[0x1];
2578         u8         cvlan_pcp[0x3];
2579         u8         cvlan_id[0xc];
2580
2581         u8         reserved_at_60[0x7a0];
2582 };
2583
2584 enum {
2585         MLX5_EQC_STATUS_OK                = 0x0,
2586         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2587 };
2588
2589 enum {
2590         MLX5_EQC_ST_ARMED  = 0x9,
2591         MLX5_EQC_ST_FIRED  = 0xa,
2592 };
2593
2594 struct mlx5_ifc_eqc_bits {
2595         u8         status[0x4];
2596         u8         reserved_at_4[0x9];
2597         u8         ec[0x1];
2598         u8         oi[0x1];
2599         u8         reserved_at_f[0x5];
2600         u8         st[0x4];
2601         u8         reserved_at_18[0x8];
2602
2603         u8         reserved_at_20[0x20];
2604
2605         u8         reserved_at_40[0x14];
2606         u8         page_offset[0x6];
2607         u8         reserved_at_5a[0x6];
2608
2609         u8         reserved_at_60[0x3];
2610         u8         log_eq_size[0x5];
2611         u8         uar_page[0x18];
2612
2613         u8         reserved_at_80[0x20];
2614
2615         u8         reserved_at_a0[0x18];
2616         u8         intr[0x8];
2617
2618         u8         reserved_at_c0[0x3];
2619         u8         log_page_size[0x5];
2620         u8         reserved_at_c8[0x18];
2621
2622         u8         reserved_at_e0[0x60];
2623
2624         u8         reserved_at_140[0x8];
2625         u8         consumer_counter[0x18];
2626
2627         u8         reserved_at_160[0x8];
2628         u8         producer_counter[0x18];
2629
2630         u8         reserved_at_180[0x80];
2631 };
2632
2633 enum {
2634         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2635         MLX5_DCTC_STATE_DRAINING  = 0x1,
2636         MLX5_DCTC_STATE_DRAINED   = 0x2,
2637 };
2638
2639 enum {
2640         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2641         MLX5_DCTC_CS_RES_NA         = 0x1,
2642         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2643 };
2644
2645 enum {
2646         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2647         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2648         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2649         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2650         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2651 };
2652
2653 struct mlx5_ifc_dctc_bits {
2654         u8         reserved_at_0[0x4];
2655         u8         state[0x4];
2656         u8         reserved_at_8[0x18];
2657
2658         u8         reserved_at_20[0x8];
2659         u8         user_index[0x18];
2660
2661         u8         reserved_at_40[0x8];
2662         u8         cqn[0x18];
2663
2664         u8         counter_set_id[0x8];
2665         u8         atomic_mode[0x4];
2666         u8         rre[0x1];
2667         u8         rwe[0x1];
2668         u8         rae[0x1];
2669         u8         atomic_like_write_en[0x1];
2670         u8         latency_sensitive[0x1];
2671         u8         rlky[0x1];
2672         u8         free_ar[0x1];
2673         u8         reserved_at_73[0xd];
2674
2675         u8         reserved_at_80[0x8];
2676         u8         cs_res[0x8];
2677         u8         reserved_at_90[0x3];
2678         u8         min_rnr_nak[0x5];
2679         u8         reserved_at_98[0x8];
2680
2681         u8         reserved_at_a0[0x8];
2682         u8         srqn_xrqn[0x18];
2683
2684         u8         reserved_at_c0[0x8];
2685         u8         pd[0x18];
2686
2687         u8         tclass[0x8];
2688         u8         reserved_at_e8[0x4];
2689         u8         flow_label[0x14];
2690
2691         u8         dc_access_key[0x40];
2692
2693         u8         reserved_at_140[0x5];
2694         u8         mtu[0x3];
2695         u8         port[0x8];
2696         u8         pkey_index[0x10];
2697
2698         u8         reserved_at_160[0x8];
2699         u8         my_addr_index[0x8];
2700         u8         reserved_at_170[0x8];
2701         u8         hop_limit[0x8];
2702
2703         u8         dc_access_key_violation_count[0x20];
2704
2705         u8         reserved_at_1a0[0x14];
2706         u8         dei_cfi[0x1];
2707         u8         eth_prio[0x3];
2708         u8         ecn[0x2];
2709         u8         dscp[0x6];
2710
2711         u8         reserved_at_1c0[0x40];
2712 };
2713
2714 enum {
2715         MLX5_CQC_STATUS_OK             = 0x0,
2716         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2717         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2718 };
2719
2720 enum {
2721         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2722         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2723 };
2724
2725 enum {
2726         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2727         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2728         MLX5_CQC_ST_FIRED                                 = 0xa,
2729 };
2730
2731 enum {
2732         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2733         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2734         MLX5_CQ_PERIOD_NUM_MODES
2735 };
2736
2737 struct mlx5_ifc_cqc_bits {
2738         u8         status[0x4];
2739         u8         reserved_at_4[0x4];
2740         u8         cqe_sz[0x3];
2741         u8         cc[0x1];
2742         u8         reserved_at_c[0x1];
2743         u8         scqe_break_moderation_en[0x1];
2744         u8         oi[0x1];
2745         u8         cq_period_mode[0x2];
2746         u8         cqe_comp_en[0x1];
2747         u8         mini_cqe_res_format[0x2];
2748         u8         st[0x4];
2749         u8         reserved_at_18[0x8];
2750
2751         u8         reserved_at_20[0x20];
2752
2753         u8         reserved_at_40[0x14];
2754         u8         page_offset[0x6];
2755         u8         reserved_at_5a[0x6];
2756
2757         u8         reserved_at_60[0x3];
2758         u8         log_cq_size[0x5];
2759         u8         uar_page[0x18];
2760
2761         u8         reserved_at_80[0x4];
2762         u8         cq_period[0xc];
2763         u8         cq_max_count[0x10];
2764
2765         u8         reserved_at_a0[0x18];
2766         u8         c_eqn[0x8];
2767
2768         u8         reserved_at_c0[0x3];
2769         u8         log_page_size[0x5];
2770         u8         reserved_at_c8[0x18];
2771
2772         u8         reserved_at_e0[0x20];
2773
2774         u8         reserved_at_100[0x8];
2775         u8         last_notified_index[0x18];
2776
2777         u8         reserved_at_120[0x8];
2778         u8         last_solicit_index[0x18];
2779
2780         u8         reserved_at_140[0x8];
2781         u8         consumer_counter[0x18];
2782
2783         u8         reserved_at_160[0x8];
2784         u8         producer_counter[0x18];
2785
2786         u8         reserved_at_180[0x40];
2787
2788         u8         dbr_addr[0x40];
2789 };
2790
2791 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2792         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2793         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2794         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2795         u8         reserved_at_0[0x800];
2796 };
2797
2798 struct mlx5_ifc_query_adapter_param_block_bits {
2799         u8         reserved_at_0[0xc0];
2800
2801         u8         reserved_at_c0[0x8];
2802         u8         ieee_vendor_id[0x18];
2803
2804         u8         reserved_at_e0[0x10];
2805         u8         vsd_vendor_id[0x10];
2806
2807         u8         vsd[208][0x8];
2808
2809         u8         vsd_contd_psid[16][0x8];
2810 };
2811
2812 enum {
2813         MLX5_XRQC_STATE_GOOD   = 0x0,
2814         MLX5_XRQC_STATE_ERROR  = 0x1,
2815 };
2816
2817 enum {
2818         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2819         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
2820 };
2821
2822 enum {
2823         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2824 };
2825
2826 struct mlx5_ifc_tag_matching_topology_context_bits {
2827         u8         log_matching_list_sz[0x4];
2828         u8         reserved_at_4[0xc];
2829         u8         append_next_index[0x10];
2830
2831         u8         sw_phase_cnt[0x10];
2832         u8         hw_phase_cnt[0x10];
2833
2834         u8         reserved_at_40[0x40];
2835 };
2836
2837 struct mlx5_ifc_xrqc_bits {
2838         u8         state[0x4];
2839         u8         rlkey[0x1];
2840         u8         reserved_at_5[0xf];
2841         u8         topology[0x4];
2842         u8         reserved_at_18[0x4];
2843         u8         offload[0x4];
2844
2845         u8         reserved_at_20[0x8];
2846         u8         user_index[0x18];
2847
2848         u8         reserved_at_40[0x8];
2849         u8         cqn[0x18];
2850
2851         u8         reserved_at_60[0xa0];
2852
2853         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2854
2855         u8         reserved_at_180[0x200];
2856
2857         struct mlx5_ifc_wq_bits wq;
2858 };
2859
2860 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2861         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2862         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2863         u8         reserved_at_0[0x20];
2864 };
2865
2866 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2867         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2868         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2869         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2870         u8         reserved_at_0[0x20];
2871 };
2872
2873 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2874         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2875         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2876         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2877         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2878         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2879         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2880         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2881         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2882         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2883         u8         reserved_at_0[0x7c0];
2884 };
2885
2886 union mlx5_ifc_event_auto_bits {
2887         struct mlx5_ifc_comp_event_bits comp_event;
2888         struct mlx5_ifc_dct_events_bits dct_events;
2889         struct mlx5_ifc_qp_events_bits qp_events;
2890         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2891         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2892         struct mlx5_ifc_cq_error_bits cq_error;
2893         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2894         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2895         struct mlx5_ifc_gpio_event_bits gpio_event;
2896         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2897         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2898         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2899         u8         reserved_at_0[0xe0];
2900 };
2901
2902 struct mlx5_ifc_health_buffer_bits {
2903         u8         reserved_at_0[0x100];
2904
2905         u8         assert_existptr[0x20];
2906
2907         u8         assert_callra[0x20];
2908
2909         u8         reserved_at_140[0x40];
2910
2911         u8         fw_version[0x20];
2912
2913         u8         hw_id[0x20];
2914
2915         u8         reserved_at_1c0[0x20];
2916
2917         u8         irisc_index[0x8];
2918         u8         synd[0x8];
2919         u8         ext_synd[0x10];
2920 };
2921
2922 struct mlx5_ifc_register_loopback_control_bits {
2923         u8         no_lb[0x1];
2924         u8         reserved_at_1[0x7];
2925         u8         port[0x8];
2926         u8         reserved_at_10[0x10];
2927
2928         u8         reserved_at_20[0x60];
2929 };
2930
2931 struct mlx5_ifc_teardown_hca_out_bits {
2932         u8         status[0x8];
2933         u8         reserved_at_8[0x18];
2934
2935         u8         syndrome[0x20];
2936
2937         u8         reserved_at_40[0x40];
2938 };
2939
2940 enum {
2941         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
2942         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
2943 };
2944
2945 struct mlx5_ifc_teardown_hca_in_bits {
2946         u8         opcode[0x10];
2947         u8         reserved_at_10[0x10];
2948
2949         u8         reserved_at_20[0x10];
2950         u8         op_mod[0x10];
2951
2952         u8         reserved_at_40[0x10];
2953         u8         profile[0x10];
2954
2955         u8         reserved_at_60[0x20];
2956 };
2957
2958 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2959         u8         status[0x8];
2960         u8         reserved_at_8[0x18];
2961
2962         u8         syndrome[0x20];
2963
2964         u8         reserved_at_40[0x40];
2965 };
2966
2967 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2968         u8         opcode[0x10];
2969         u8         reserved_at_10[0x10];
2970
2971         u8         reserved_at_20[0x10];
2972         u8         op_mod[0x10];
2973
2974         u8         reserved_at_40[0x8];
2975         u8         qpn[0x18];
2976
2977         u8         reserved_at_60[0x20];
2978
2979         u8         opt_param_mask[0x20];
2980
2981         u8         reserved_at_a0[0x20];
2982
2983         struct mlx5_ifc_qpc_bits qpc;
2984
2985         u8         reserved_at_800[0x80];
2986 };
2987
2988 struct mlx5_ifc_sqd2rts_qp_out_bits {
2989         u8         status[0x8];
2990         u8         reserved_at_8[0x18];
2991
2992         u8         syndrome[0x20];
2993
2994         u8         reserved_at_40[0x40];
2995 };
2996
2997 struct mlx5_ifc_sqd2rts_qp_in_bits {
2998         u8         opcode[0x10];
2999         u8         reserved_at_10[0x10];
3000
3001         u8         reserved_at_20[0x10];
3002         u8         op_mod[0x10];
3003
3004         u8         reserved_at_40[0x8];
3005         u8         qpn[0x18];
3006
3007         u8         reserved_at_60[0x20];
3008
3009         u8         opt_param_mask[0x20];
3010
3011         u8         reserved_at_a0[0x20];
3012
3013         struct mlx5_ifc_qpc_bits qpc;
3014
3015         u8         reserved_at_800[0x80];
3016 };
3017
3018 struct mlx5_ifc_set_roce_address_out_bits {
3019         u8         status[0x8];
3020         u8         reserved_at_8[0x18];
3021
3022         u8         syndrome[0x20];
3023
3024         u8         reserved_at_40[0x40];
3025 };
3026
3027 struct mlx5_ifc_set_roce_address_in_bits {
3028         u8         opcode[0x10];
3029         u8         reserved_at_10[0x10];
3030
3031         u8         reserved_at_20[0x10];
3032         u8         op_mod[0x10];
3033
3034         u8         roce_address_index[0x10];
3035         u8         reserved_at_50[0x10];
3036
3037         u8         reserved_at_60[0x20];
3038
3039         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3040 };
3041
3042 struct mlx5_ifc_set_mad_demux_out_bits {
3043         u8         status[0x8];
3044         u8         reserved_at_8[0x18];
3045
3046         u8         syndrome[0x20];
3047
3048         u8         reserved_at_40[0x40];
3049 };
3050
3051 enum {
3052         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3053         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3054 };
3055
3056 struct mlx5_ifc_set_mad_demux_in_bits {
3057         u8         opcode[0x10];
3058         u8         reserved_at_10[0x10];
3059
3060         u8         reserved_at_20[0x10];
3061         u8         op_mod[0x10];
3062
3063         u8         reserved_at_40[0x20];
3064
3065         u8         reserved_at_60[0x6];
3066         u8         demux_mode[0x2];
3067         u8         reserved_at_68[0x18];
3068 };
3069
3070 struct mlx5_ifc_set_l2_table_entry_out_bits {
3071         u8         status[0x8];
3072         u8         reserved_at_8[0x18];
3073
3074         u8         syndrome[0x20];
3075
3076         u8         reserved_at_40[0x40];
3077 };
3078
3079 struct mlx5_ifc_set_l2_table_entry_in_bits {
3080         u8         opcode[0x10];
3081         u8         reserved_at_10[0x10];
3082
3083         u8         reserved_at_20[0x10];
3084         u8         op_mod[0x10];
3085
3086         u8         reserved_at_40[0x60];
3087
3088         u8         reserved_at_a0[0x8];
3089         u8         table_index[0x18];
3090
3091         u8         reserved_at_c0[0x20];
3092
3093         u8         reserved_at_e0[0x13];
3094         u8         vlan_valid[0x1];
3095         u8         vlan[0xc];
3096
3097         struct mlx5_ifc_mac_address_layout_bits mac_address;
3098
3099         u8         reserved_at_140[0xc0];
3100 };
3101
3102 struct mlx5_ifc_set_issi_out_bits {
3103         u8         status[0x8];
3104         u8         reserved_at_8[0x18];
3105
3106         u8         syndrome[0x20];
3107
3108         u8         reserved_at_40[0x40];
3109 };
3110
3111 struct mlx5_ifc_set_issi_in_bits {
3112         u8         opcode[0x10];
3113         u8         reserved_at_10[0x10];
3114
3115         u8         reserved_at_20[0x10];
3116         u8         op_mod[0x10];
3117
3118         u8         reserved_at_40[0x10];
3119         u8         current_issi[0x10];
3120
3121         u8         reserved_at_60[0x20];
3122 };
3123
3124 struct mlx5_ifc_set_hca_cap_out_bits {
3125         u8         status[0x8];
3126         u8         reserved_at_8[0x18];
3127
3128         u8         syndrome[0x20];
3129
3130         u8         reserved_at_40[0x40];
3131 };
3132
3133 struct mlx5_ifc_set_hca_cap_in_bits {
3134         u8         opcode[0x10];
3135         u8         reserved_at_10[0x10];
3136
3137         u8         reserved_at_20[0x10];
3138         u8         op_mod[0x10];
3139
3140         u8         reserved_at_40[0x40];
3141
3142         union mlx5_ifc_hca_cap_union_bits capability;
3143 };
3144
3145 enum {
3146         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3147         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3148         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3149         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3150 };
3151
3152 struct mlx5_ifc_set_fte_out_bits {
3153         u8         status[0x8];
3154         u8         reserved_at_8[0x18];
3155
3156         u8         syndrome[0x20];
3157
3158         u8         reserved_at_40[0x40];
3159 };
3160
3161 struct mlx5_ifc_set_fte_in_bits {
3162         u8         opcode[0x10];
3163         u8         reserved_at_10[0x10];
3164
3165         u8         reserved_at_20[0x10];
3166         u8         op_mod[0x10];
3167
3168         u8         other_vport[0x1];
3169         u8         reserved_at_41[0xf];
3170         u8         vport_number[0x10];
3171
3172         u8         reserved_at_60[0x20];
3173
3174         u8         table_type[0x8];
3175         u8         reserved_at_88[0x18];
3176
3177         u8         reserved_at_a0[0x8];
3178         u8         table_id[0x18];
3179
3180         u8         reserved_at_c0[0x18];
3181         u8         modify_enable_mask[0x8];
3182
3183         u8         reserved_at_e0[0x20];
3184
3185         u8         flow_index[0x20];
3186
3187         u8         reserved_at_120[0xe0];
3188
3189         struct mlx5_ifc_flow_context_bits flow_context;
3190 };
3191
3192 struct mlx5_ifc_rts2rts_qp_out_bits {
3193         u8         status[0x8];
3194         u8         reserved_at_8[0x18];
3195
3196         u8         syndrome[0x20];
3197
3198         u8         reserved_at_40[0x40];
3199 };
3200
3201 struct mlx5_ifc_rts2rts_qp_in_bits {
3202         u8         opcode[0x10];
3203         u8         reserved_at_10[0x10];
3204
3205         u8         reserved_at_20[0x10];
3206         u8         op_mod[0x10];
3207
3208         u8         reserved_at_40[0x8];
3209         u8         qpn[0x18];
3210
3211         u8         reserved_at_60[0x20];
3212
3213         u8         opt_param_mask[0x20];
3214
3215         u8         reserved_at_a0[0x20];
3216
3217         struct mlx5_ifc_qpc_bits qpc;
3218
3219         u8         reserved_at_800[0x80];
3220 };
3221
3222 struct mlx5_ifc_rtr2rts_qp_out_bits {
3223         u8         status[0x8];
3224         u8         reserved_at_8[0x18];
3225
3226         u8         syndrome[0x20];
3227
3228         u8         reserved_at_40[0x40];
3229 };
3230
3231 struct mlx5_ifc_rtr2rts_qp_in_bits {
3232         u8         opcode[0x10];
3233         u8         reserved_at_10[0x10];
3234
3235         u8         reserved_at_20[0x10];
3236         u8         op_mod[0x10];
3237
3238         u8         reserved_at_40[0x8];
3239         u8         qpn[0x18];
3240
3241         u8         reserved_at_60[0x20];
3242
3243         u8         opt_param_mask[0x20];
3244
3245         u8         reserved_at_a0[0x20];
3246
3247         struct mlx5_ifc_qpc_bits qpc;
3248
3249         u8         reserved_at_800[0x80];
3250 };
3251
3252 struct mlx5_ifc_rst2init_qp_out_bits {
3253         u8         status[0x8];
3254         u8         reserved_at_8[0x18];
3255
3256         u8         syndrome[0x20];
3257
3258         u8         reserved_at_40[0x40];
3259 };
3260
3261 struct mlx5_ifc_rst2init_qp_in_bits {
3262         u8         opcode[0x10];
3263         u8         reserved_at_10[0x10];
3264
3265         u8         reserved_at_20[0x10];
3266         u8         op_mod[0x10];
3267
3268         u8         reserved_at_40[0x8];
3269         u8         qpn[0x18];
3270
3271         u8         reserved_at_60[0x20];
3272
3273         u8         opt_param_mask[0x20];
3274
3275         u8         reserved_at_a0[0x20];
3276
3277         struct mlx5_ifc_qpc_bits qpc;
3278
3279         u8         reserved_at_800[0x80];
3280 };
3281
3282 struct mlx5_ifc_query_xrq_out_bits {
3283         u8         status[0x8];
3284         u8         reserved_at_8[0x18];
3285
3286         u8         syndrome[0x20];
3287
3288         u8         reserved_at_40[0x40];
3289
3290         struct mlx5_ifc_xrqc_bits xrq_context;
3291 };
3292
3293 struct mlx5_ifc_query_xrq_in_bits {
3294         u8         opcode[0x10];
3295         u8         reserved_at_10[0x10];
3296
3297         u8         reserved_at_20[0x10];
3298         u8         op_mod[0x10];
3299
3300         u8         reserved_at_40[0x8];
3301         u8         xrqn[0x18];
3302
3303         u8         reserved_at_60[0x20];
3304 };
3305
3306 struct mlx5_ifc_query_xrc_srq_out_bits {
3307         u8         status[0x8];
3308         u8         reserved_at_8[0x18];
3309
3310         u8         syndrome[0x20];
3311
3312         u8         reserved_at_40[0x40];
3313
3314         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3315
3316         u8         reserved_at_280[0x600];
3317
3318         u8         pas[0][0x40];
3319 };
3320
3321 struct mlx5_ifc_query_xrc_srq_in_bits {
3322         u8         opcode[0x10];
3323         u8         reserved_at_10[0x10];
3324
3325         u8         reserved_at_20[0x10];
3326         u8         op_mod[0x10];
3327
3328         u8         reserved_at_40[0x8];
3329         u8         xrc_srqn[0x18];
3330
3331         u8         reserved_at_60[0x20];
3332 };
3333
3334 enum {
3335         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3336         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3337 };
3338
3339 struct mlx5_ifc_query_vport_state_out_bits {
3340         u8         status[0x8];
3341         u8         reserved_at_8[0x18];
3342
3343         u8         syndrome[0x20];
3344
3345         u8         reserved_at_40[0x20];
3346
3347         u8         reserved_at_60[0x18];
3348         u8         admin_state[0x4];
3349         u8         state[0x4];
3350 };
3351
3352 enum {
3353         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3354         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3355 };
3356
3357 struct mlx5_ifc_query_vport_state_in_bits {
3358         u8         opcode[0x10];
3359         u8         reserved_at_10[0x10];
3360
3361         u8         reserved_at_20[0x10];
3362         u8         op_mod[0x10];
3363
3364         u8         other_vport[0x1];
3365         u8         reserved_at_41[0xf];
3366         u8         vport_number[0x10];
3367
3368         u8         reserved_at_60[0x20];
3369 };
3370
3371 struct mlx5_ifc_query_vport_counter_out_bits {
3372         u8         status[0x8];
3373         u8         reserved_at_8[0x18];
3374
3375         u8         syndrome[0x20];
3376
3377         u8         reserved_at_40[0x40];
3378
3379         struct mlx5_ifc_traffic_counter_bits received_errors;
3380
3381         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3382
3383         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3384
3385         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3386
3387         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3388
3389         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3390
3391         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3392
3393         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3394
3395         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3396
3397         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3398
3399         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3400
3401         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3402
3403         u8         reserved_at_680[0xa00];
3404 };
3405
3406 enum {
3407         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3408 };
3409
3410 struct mlx5_ifc_query_vport_counter_in_bits {
3411         u8         opcode[0x10];
3412         u8         reserved_at_10[0x10];
3413
3414         u8         reserved_at_20[0x10];
3415         u8         op_mod[0x10];
3416
3417         u8         other_vport[0x1];
3418         u8         reserved_at_41[0xb];
3419         u8         port_num[0x4];
3420         u8         vport_number[0x10];
3421
3422         u8         reserved_at_60[0x60];
3423
3424         u8         clear[0x1];
3425         u8         reserved_at_c1[0x1f];
3426
3427         u8         reserved_at_e0[0x20];
3428 };
3429
3430 struct mlx5_ifc_query_tis_out_bits {
3431         u8         status[0x8];
3432         u8         reserved_at_8[0x18];
3433
3434         u8         syndrome[0x20];
3435
3436         u8         reserved_at_40[0x40];
3437
3438         struct mlx5_ifc_tisc_bits tis_context;
3439 };
3440
3441 struct mlx5_ifc_query_tis_in_bits {
3442         u8         opcode[0x10];
3443         u8         reserved_at_10[0x10];
3444
3445         u8         reserved_at_20[0x10];
3446         u8         op_mod[0x10];
3447
3448         u8         reserved_at_40[0x8];
3449         u8         tisn[0x18];
3450
3451         u8         reserved_at_60[0x20];
3452 };
3453
3454 struct mlx5_ifc_query_tir_out_bits {
3455         u8         status[0x8];
3456         u8         reserved_at_8[0x18];
3457
3458         u8         syndrome[0x20];
3459
3460         u8         reserved_at_40[0xc0];
3461
3462         struct mlx5_ifc_tirc_bits tir_context;
3463 };
3464
3465 struct mlx5_ifc_query_tir_in_bits {
3466         u8         opcode[0x10];
3467         u8         reserved_at_10[0x10];
3468
3469         u8         reserved_at_20[0x10];
3470         u8         op_mod[0x10];
3471
3472         u8         reserved_at_40[0x8];
3473         u8         tirn[0x18];
3474
3475         u8         reserved_at_60[0x20];
3476 };
3477
3478 struct mlx5_ifc_query_srq_out_bits {
3479         u8         status[0x8];
3480         u8         reserved_at_8[0x18];
3481
3482         u8         syndrome[0x20];
3483
3484         u8         reserved_at_40[0x40];
3485
3486         struct mlx5_ifc_srqc_bits srq_context_entry;
3487
3488         u8         reserved_at_280[0x600];
3489
3490         u8         pas[0][0x40];
3491 };
3492
3493 struct mlx5_ifc_query_srq_in_bits {
3494         u8         opcode[0x10];
3495         u8         reserved_at_10[0x10];
3496
3497         u8         reserved_at_20[0x10];
3498         u8         op_mod[0x10];
3499
3500         u8         reserved_at_40[0x8];
3501         u8         srqn[0x18];
3502
3503         u8         reserved_at_60[0x20];
3504 };
3505
3506 struct mlx5_ifc_query_sq_out_bits {
3507         u8         status[0x8];
3508         u8         reserved_at_8[0x18];
3509
3510         u8         syndrome[0x20];
3511
3512         u8         reserved_at_40[0xc0];
3513
3514         struct mlx5_ifc_sqc_bits sq_context;
3515 };
3516
3517 struct mlx5_ifc_query_sq_in_bits {
3518         u8         opcode[0x10];
3519         u8         reserved_at_10[0x10];
3520
3521         u8         reserved_at_20[0x10];
3522         u8         op_mod[0x10];
3523
3524         u8         reserved_at_40[0x8];
3525         u8         sqn[0x18];
3526
3527         u8         reserved_at_60[0x20];
3528 };
3529
3530 struct mlx5_ifc_query_special_contexts_out_bits {
3531         u8         status[0x8];
3532         u8         reserved_at_8[0x18];
3533
3534         u8         syndrome[0x20];
3535
3536         u8         dump_fill_mkey[0x20];
3537
3538         u8         resd_lkey[0x20];
3539 };
3540
3541 struct mlx5_ifc_query_special_contexts_in_bits {
3542         u8         opcode[0x10];
3543         u8         reserved_at_10[0x10];
3544
3545         u8         reserved_at_20[0x10];
3546         u8         op_mod[0x10];
3547
3548         u8         reserved_at_40[0x40];
3549 };
3550
3551 struct mlx5_ifc_query_rqt_out_bits {
3552         u8         status[0x8];
3553         u8         reserved_at_8[0x18];
3554
3555         u8         syndrome[0x20];
3556
3557         u8         reserved_at_40[0xc0];
3558
3559         struct mlx5_ifc_rqtc_bits rqt_context;
3560 };
3561
3562 struct mlx5_ifc_query_rqt_in_bits {
3563         u8         opcode[0x10];
3564         u8         reserved_at_10[0x10];
3565
3566         u8         reserved_at_20[0x10];
3567         u8         op_mod[0x10];
3568
3569         u8         reserved_at_40[0x8];
3570         u8         rqtn[0x18];
3571
3572         u8         reserved_at_60[0x20];
3573 };
3574
3575 struct mlx5_ifc_query_rq_out_bits {
3576         u8         status[0x8];
3577         u8         reserved_at_8[0x18];
3578
3579         u8         syndrome[0x20];
3580
3581         u8         reserved_at_40[0xc0];
3582
3583         struct mlx5_ifc_rqc_bits rq_context;
3584 };
3585
3586 struct mlx5_ifc_query_rq_in_bits {
3587         u8         opcode[0x10];
3588         u8         reserved_at_10[0x10];
3589
3590         u8         reserved_at_20[0x10];
3591         u8         op_mod[0x10];
3592
3593         u8         reserved_at_40[0x8];
3594         u8         rqn[0x18];
3595
3596         u8         reserved_at_60[0x20];
3597 };
3598
3599 struct mlx5_ifc_query_roce_address_out_bits {
3600         u8         status[0x8];
3601         u8         reserved_at_8[0x18];
3602
3603         u8         syndrome[0x20];
3604
3605         u8         reserved_at_40[0x40];
3606
3607         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3608 };
3609
3610 struct mlx5_ifc_query_roce_address_in_bits {
3611         u8         opcode[0x10];
3612         u8         reserved_at_10[0x10];
3613
3614         u8         reserved_at_20[0x10];
3615         u8         op_mod[0x10];
3616
3617         u8         roce_address_index[0x10];
3618         u8         reserved_at_50[0x10];
3619
3620         u8         reserved_at_60[0x20];
3621 };
3622
3623 struct mlx5_ifc_query_rmp_out_bits {
3624         u8         status[0x8];
3625         u8         reserved_at_8[0x18];
3626
3627         u8         syndrome[0x20];
3628
3629         u8         reserved_at_40[0xc0];
3630
3631         struct mlx5_ifc_rmpc_bits rmp_context;
3632 };
3633
3634 struct mlx5_ifc_query_rmp_in_bits {
3635         u8         opcode[0x10];
3636         u8         reserved_at_10[0x10];
3637
3638         u8         reserved_at_20[0x10];
3639         u8         op_mod[0x10];
3640
3641         u8         reserved_at_40[0x8];
3642         u8         rmpn[0x18];
3643
3644         u8         reserved_at_60[0x20];
3645 };
3646
3647 struct mlx5_ifc_query_qp_out_bits {
3648         u8         status[0x8];
3649         u8         reserved_at_8[0x18];
3650
3651         u8         syndrome[0x20];
3652
3653         u8         reserved_at_40[0x40];
3654
3655         u8         opt_param_mask[0x20];
3656
3657         u8         reserved_at_a0[0x20];
3658
3659         struct mlx5_ifc_qpc_bits qpc;
3660
3661         u8         reserved_at_800[0x80];
3662
3663         u8         pas[0][0x40];
3664 };
3665
3666 struct mlx5_ifc_query_qp_in_bits {
3667         u8         opcode[0x10];
3668         u8         reserved_at_10[0x10];
3669
3670         u8         reserved_at_20[0x10];
3671         u8         op_mod[0x10];
3672
3673         u8         reserved_at_40[0x8];
3674         u8         qpn[0x18];
3675
3676         u8         reserved_at_60[0x20];
3677 };
3678
3679 struct mlx5_ifc_query_q_counter_out_bits {
3680         u8         status[0x8];
3681         u8         reserved_at_8[0x18];
3682
3683         u8         syndrome[0x20];
3684
3685         u8         reserved_at_40[0x40];
3686
3687         u8         rx_write_requests[0x20];
3688
3689         u8         reserved_at_a0[0x20];
3690
3691         u8         rx_read_requests[0x20];
3692
3693         u8         reserved_at_e0[0x20];
3694
3695         u8         rx_atomic_requests[0x20];
3696
3697         u8         reserved_at_120[0x20];
3698
3699         u8         rx_dct_connect[0x20];
3700
3701         u8         reserved_at_160[0x20];
3702
3703         u8         out_of_buffer[0x20];
3704
3705         u8         reserved_at_1a0[0x20];
3706
3707         u8         out_of_sequence[0x20];
3708
3709         u8         reserved_at_1e0[0x20];
3710
3711         u8         duplicate_request[0x20];
3712
3713         u8         reserved_at_220[0x20];
3714
3715         u8         rnr_nak_retry_err[0x20];
3716
3717         u8         reserved_at_260[0x20];
3718
3719         u8         packet_seq_err[0x20];
3720
3721         u8         reserved_at_2a0[0x20];
3722
3723         u8         implied_nak_seq_err[0x20];
3724
3725         u8         reserved_at_2e0[0x20];
3726
3727         u8         local_ack_timeout_err[0x20];
3728
3729         u8         reserved_at_320[0x4e0];
3730 };
3731
3732 struct mlx5_ifc_query_q_counter_in_bits {
3733         u8         opcode[0x10];
3734         u8         reserved_at_10[0x10];
3735
3736         u8         reserved_at_20[0x10];
3737         u8         op_mod[0x10];
3738
3739         u8         reserved_at_40[0x80];
3740
3741         u8         clear[0x1];
3742         u8         reserved_at_c1[0x1f];
3743
3744         u8         reserved_at_e0[0x18];
3745         u8         counter_set_id[0x8];
3746 };
3747
3748 struct mlx5_ifc_query_pages_out_bits {
3749         u8         status[0x8];
3750         u8         reserved_at_8[0x18];
3751
3752         u8         syndrome[0x20];
3753
3754         u8         reserved_at_40[0x10];
3755         u8         function_id[0x10];
3756
3757         u8         num_pages[0x20];
3758 };
3759
3760 enum {
3761         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3762         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3763         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3764 };
3765
3766 struct mlx5_ifc_query_pages_in_bits {
3767         u8         opcode[0x10];
3768         u8         reserved_at_10[0x10];
3769
3770         u8         reserved_at_20[0x10];
3771         u8         op_mod[0x10];
3772
3773         u8         reserved_at_40[0x10];
3774         u8         function_id[0x10];
3775
3776         u8         reserved_at_60[0x20];
3777 };
3778
3779 struct mlx5_ifc_query_nic_vport_context_out_bits {
3780         u8         status[0x8];
3781         u8         reserved_at_8[0x18];
3782
3783         u8         syndrome[0x20];
3784
3785         u8         reserved_at_40[0x40];
3786
3787         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3788 };
3789
3790 struct mlx5_ifc_query_nic_vport_context_in_bits {
3791         u8         opcode[0x10];
3792         u8         reserved_at_10[0x10];
3793
3794         u8         reserved_at_20[0x10];
3795         u8         op_mod[0x10];
3796
3797         u8         other_vport[0x1];
3798         u8         reserved_at_41[0xf];
3799         u8         vport_number[0x10];
3800
3801         u8         reserved_at_60[0x5];
3802         u8         allowed_list_type[0x3];
3803         u8         reserved_at_68[0x18];
3804 };
3805
3806 struct mlx5_ifc_query_mkey_out_bits {
3807         u8         status[0x8];
3808         u8         reserved_at_8[0x18];
3809
3810         u8         syndrome[0x20];
3811
3812         u8         reserved_at_40[0x40];
3813
3814         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3815
3816         u8         reserved_at_280[0x600];
3817
3818         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
3819
3820         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
3821 };
3822
3823 struct mlx5_ifc_query_mkey_in_bits {
3824         u8         opcode[0x10];
3825         u8         reserved_at_10[0x10];
3826
3827         u8         reserved_at_20[0x10];
3828         u8         op_mod[0x10];
3829
3830         u8         reserved_at_40[0x8];
3831         u8         mkey_index[0x18];
3832
3833         u8         pg_access[0x1];
3834         u8         reserved_at_61[0x1f];
3835 };
3836
3837 struct mlx5_ifc_query_mad_demux_out_bits {
3838         u8         status[0x8];
3839         u8         reserved_at_8[0x18];
3840
3841         u8         syndrome[0x20];
3842
3843         u8         reserved_at_40[0x40];
3844
3845         u8         mad_dumux_parameters_block[0x20];
3846 };
3847
3848 struct mlx5_ifc_query_mad_demux_in_bits {
3849         u8         opcode[0x10];
3850         u8         reserved_at_10[0x10];
3851
3852         u8         reserved_at_20[0x10];
3853         u8         op_mod[0x10];
3854
3855         u8         reserved_at_40[0x40];
3856 };
3857
3858 struct mlx5_ifc_query_l2_table_entry_out_bits {
3859         u8         status[0x8];
3860         u8         reserved_at_8[0x18];
3861
3862         u8         syndrome[0x20];
3863
3864         u8         reserved_at_40[0xa0];
3865
3866         u8         reserved_at_e0[0x13];
3867         u8         vlan_valid[0x1];
3868         u8         vlan[0xc];
3869
3870         struct mlx5_ifc_mac_address_layout_bits mac_address;
3871
3872         u8         reserved_at_140[0xc0];
3873 };
3874
3875 struct mlx5_ifc_query_l2_table_entry_in_bits {
3876         u8         opcode[0x10];
3877         u8         reserved_at_10[0x10];
3878
3879         u8         reserved_at_20[0x10];
3880         u8         op_mod[0x10];
3881
3882         u8         reserved_at_40[0x60];
3883
3884         u8         reserved_at_a0[0x8];
3885         u8         table_index[0x18];
3886
3887         u8         reserved_at_c0[0x140];
3888 };
3889
3890 struct mlx5_ifc_query_issi_out_bits {
3891         u8         status[0x8];
3892         u8         reserved_at_8[0x18];
3893
3894         u8         syndrome[0x20];
3895
3896         u8         reserved_at_40[0x10];
3897         u8         current_issi[0x10];
3898
3899         u8         reserved_at_60[0xa0];
3900
3901         u8         reserved_at_100[76][0x8];
3902         u8         supported_issi_dw0[0x20];
3903 };
3904
3905 struct mlx5_ifc_query_issi_in_bits {
3906         u8         opcode[0x10];
3907         u8         reserved_at_10[0x10];
3908
3909         u8         reserved_at_20[0x10];
3910         u8         op_mod[0x10];
3911
3912         u8         reserved_at_40[0x40];
3913 };
3914
3915 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3916         u8         status[0x8];
3917         u8         reserved_at_8[0x18];
3918
3919         u8         syndrome[0x20];
3920
3921         u8         reserved_at_40[0x40];
3922
3923         struct mlx5_ifc_pkey_bits pkey[0];
3924 };
3925
3926 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3927         u8         opcode[0x10];
3928         u8         reserved_at_10[0x10];
3929
3930         u8         reserved_at_20[0x10];
3931         u8         op_mod[0x10];
3932
3933         u8         other_vport[0x1];
3934         u8         reserved_at_41[0xb];
3935         u8         port_num[0x4];
3936         u8         vport_number[0x10];
3937
3938         u8         reserved_at_60[0x10];
3939         u8         pkey_index[0x10];
3940 };
3941
3942 enum {
3943         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
3944         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
3945         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
3946 };
3947
3948 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3949         u8         status[0x8];
3950         u8         reserved_at_8[0x18];
3951
3952         u8         syndrome[0x20];
3953
3954         u8         reserved_at_40[0x20];
3955
3956         u8         gids_num[0x10];
3957         u8         reserved_at_70[0x10];
3958
3959         struct mlx5_ifc_array128_auto_bits gid[0];
3960 };
3961
3962 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3963         u8         opcode[0x10];
3964         u8         reserved_at_10[0x10];
3965
3966         u8         reserved_at_20[0x10];
3967         u8         op_mod[0x10];
3968
3969         u8         other_vport[0x1];
3970         u8         reserved_at_41[0xb];
3971         u8         port_num[0x4];
3972         u8         vport_number[0x10];
3973
3974         u8         reserved_at_60[0x10];
3975         u8         gid_index[0x10];
3976 };
3977
3978 struct mlx5_ifc_query_hca_vport_context_out_bits {
3979         u8         status[0x8];
3980         u8         reserved_at_8[0x18];
3981
3982         u8         syndrome[0x20];
3983
3984         u8         reserved_at_40[0x40];
3985
3986         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3987 };
3988
3989 struct mlx5_ifc_query_hca_vport_context_in_bits {
3990         u8         opcode[0x10];
3991         u8         reserved_at_10[0x10];
3992
3993         u8         reserved_at_20[0x10];
3994         u8         op_mod[0x10];
3995
3996         u8         other_vport[0x1];
3997         u8         reserved_at_41[0xb];
3998         u8         port_num[0x4];
3999         u8         vport_number[0x10];
4000
4001         u8         reserved_at_60[0x20];
4002 };
4003
4004 struct mlx5_ifc_query_hca_cap_out_bits {
4005         u8         status[0x8];
4006         u8         reserved_at_8[0x18];
4007
4008         u8         syndrome[0x20];
4009
4010         u8         reserved_at_40[0x40];
4011
4012         union mlx5_ifc_hca_cap_union_bits capability;
4013 };
4014
4015 struct mlx5_ifc_query_hca_cap_in_bits {
4016         u8         opcode[0x10];
4017         u8         reserved_at_10[0x10];
4018
4019         u8         reserved_at_20[0x10];
4020         u8         op_mod[0x10];
4021
4022         u8         reserved_at_40[0x40];
4023 };
4024
4025 struct mlx5_ifc_query_flow_table_out_bits {
4026         u8         status[0x8];
4027         u8         reserved_at_8[0x18];
4028
4029         u8         syndrome[0x20];
4030
4031         u8         reserved_at_40[0x80];
4032
4033         u8         reserved_at_c0[0x8];
4034         u8         level[0x8];
4035         u8         reserved_at_d0[0x8];
4036         u8         log_size[0x8];
4037
4038         u8         reserved_at_e0[0x120];
4039 };
4040
4041 struct mlx5_ifc_query_flow_table_in_bits {
4042         u8         opcode[0x10];
4043         u8         reserved_at_10[0x10];
4044
4045         u8         reserved_at_20[0x10];
4046         u8         op_mod[0x10];
4047
4048         u8         reserved_at_40[0x40];
4049
4050         u8         table_type[0x8];
4051         u8         reserved_at_88[0x18];
4052
4053         u8         reserved_at_a0[0x8];
4054         u8         table_id[0x18];
4055
4056         u8         reserved_at_c0[0x140];
4057 };
4058
4059 struct mlx5_ifc_query_fte_out_bits {
4060         u8         status[0x8];
4061         u8         reserved_at_8[0x18];
4062
4063         u8         syndrome[0x20];
4064
4065         u8         reserved_at_40[0x1c0];
4066
4067         struct mlx5_ifc_flow_context_bits flow_context;
4068 };
4069
4070 struct mlx5_ifc_query_fte_in_bits {
4071         u8         opcode[0x10];
4072         u8         reserved_at_10[0x10];
4073
4074         u8         reserved_at_20[0x10];
4075         u8         op_mod[0x10];
4076
4077         u8         reserved_at_40[0x40];
4078
4079         u8         table_type[0x8];
4080         u8         reserved_at_88[0x18];
4081
4082         u8         reserved_at_a0[0x8];
4083         u8         table_id[0x18];
4084
4085         u8         reserved_at_c0[0x40];
4086
4087         u8         flow_index[0x20];
4088
4089         u8         reserved_at_120[0xe0];
4090 };
4091
4092 enum {
4093         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4094         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4095         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4096 };
4097
4098 struct mlx5_ifc_query_flow_group_out_bits {
4099         u8         status[0x8];
4100         u8         reserved_at_8[0x18];
4101
4102         u8         syndrome[0x20];
4103
4104         u8         reserved_at_40[0xa0];
4105
4106         u8         start_flow_index[0x20];
4107
4108         u8         reserved_at_100[0x20];
4109
4110         u8         end_flow_index[0x20];
4111
4112         u8         reserved_at_140[0xa0];
4113
4114         u8         reserved_at_1e0[0x18];
4115         u8         match_criteria_enable[0x8];
4116
4117         struct mlx5_ifc_fte_match_param_bits match_criteria;
4118
4119         u8         reserved_at_1200[0xe00];
4120 };
4121
4122 struct mlx5_ifc_query_flow_group_in_bits {
4123         u8         opcode[0x10];
4124         u8         reserved_at_10[0x10];
4125
4126         u8         reserved_at_20[0x10];
4127         u8         op_mod[0x10];
4128
4129         u8         reserved_at_40[0x40];
4130
4131         u8         table_type[0x8];
4132         u8         reserved_at_88[0x18];
4133
4134         u8         reserved_at_a0[0x8];
4135         u8         table_id[0x18];
4136
4137         u8         group_id[0x20];
4138
4139         u8         reserved_at_e0[0x120];
4140 };
4141
4142 struct mlx5_ifc_query_flow_counter_out_bits {
4143         u8         status[0x8];
4144         u8         reserved_at_8[0x18];
4145
4146         u8         syndrome[0x20];
4147
4148         u8         reserved_at_40[0x40];
4149
4150         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4151 };
4152
4153 struct mlx5_ifc_query_flow_counter_in_bits {
4154         u8         opcode[0x10];
4155         u8         reserved_at_10[0x10];
4156
4157         u8         reserved_at_20[0x10];
4158         u8         op_mod[0x10];
4159
4160         u8         reserved_at_40[0x80];
4161
4162         u8         clear[0x1];
4163         u8         reserved_at_c1[0xf];
4164         u8         num_of_counters[0x10];
4165
4166         u8         reserved_at_e0[0x10];
4167         u8         flow_counter_id[0x10];
4168 };
4169
4170 struct mlx5_ifc_query_esw_vport_context_out_bits {
4171         u8         status[0x8];
4172         u8         reserved_at_8[0x18];
4173
4174         u8         syndrome[0x20];
4175
4176         u8         reserved_at_40[0x40];
4177
4178         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4179 };
4180
4181 struct mlx5_ifc_query_esw_vport_context_in_bits {
4182         u8         opcode[0x10];
4183         u8         reserved_at_10[0x10];
4184
4185         u8         reserved_at_20[0x10];
4186         u8         op_mod[0x10];
4187
4188         u8         other_vport[0x1];
4189         u8         reserved_at_41[0xf];
4190         u8         vport_number[0x10];
4191
4192         u8         reserved_at_60[0x20];
4193 };
4194
4195 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4196         u8         status[0x8];
4197         u8         reserved_at_8[0x18];
4198
4199         u8         syndrome[0x20];
4200
4201         u8         reserved_at_40[0x40];
4202 };
4203
4204 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4205         u8         reserved_at_0[0x1c];
4206         u8         vport_cvlan_insert[0x1];
4207         u8         vport_svlan_insert[0x1];
4208         u8         vport_cvlan_strip[0x1];
4209         u8         vport_svlan_strip[0x1];
4210 };
4211
4212 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4213         u8         opcode[0x10];
4214         u8         reserved_at_10[0x10];
4215
4216         u8         reserved_at_20[0x10];
4217         u8         op_mod[0x10];
4218
4219         u8         other_vport[0x1];
4220         u8         reserved_at_41[0xf];
4221         u8         vport_number[0x10];
4222
4223         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4224
4225         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4226 };
4227
4228 struct mlx5_ifc_query_eq_out_bits {
4229         u8         status[0x8];
4230         u8         reserved_at_8[0x18];
4231
4232         u8         syndrome[0x20];
4233
4234         u8         reserved_at_40[0x40];
4235
4236         struct mlx5_ifc_eqc_bits eq_context_entry;
4237
4238         u8         reserved_at_280[0x40];
4239
4240         u8         event_bitmask[0x40];
4241
4242         u8         reserved_at_300[0x580];
4243
4244         u8         pas[0][0x40];
4245 };
4246
4247 struct mlx5_ifc_query_eq_in_bits {
4248         u8         opcode[0x10];
4249         u8         reserved_at_10[0x10];
4250
4251         u8         reserved_at_20[0x10];
4252         u8         op_mod[0x10];
4253
4254         u8         reserved_at_40[0x18];
4255         u8         eq_number[0x8];
4256
4257         u8         reserved_at_60[0x20];
4258 };
4259
4260 struct mlx5_ifc_encap_header_in_bits {
4261         u8         reserved_at_0[0x5];
4262         u8         header_type[0x3];
4263         u8         reserved_at_8[0xe];
4264         u8         encap_header_size[0xa];
4265
4266         u8         reserved_at_20[0x10];
4267         u8         encap_header[2][0x8];
4268
4269         u8         more_encap_header[0][0x8];
4270 };
4271
4272 struct mlx5_ifc_query_encap_header_out_bits {
4273         u8         status[0x8];
4274         u8         reserved_at_8[0x18];
4275
4276         u8         syndrome[0x20];
4277
4278         u8         reserved_at_40[0xa0];
4279
4280         struct mlx5_ifc_encap_header_in_bits encap_header[0];
4281 };
4282
4283 struct mlx5_ifc_query_encap_header_in_bits {
4284         u8         opcode[0x10];
4285         u8         reserved_at_10[0x10];
4286
4287         u8         reserved_at_20[0x10];
4288         u8         op_mod[0x10];
4289
4290         u8         encap_id[0x20];
4291
4292         u8         reserved_at_60[0xa0];
4293 };
4294
4295 struct mlx5_ifc_alloc_encap_header_out_bits {
4296         u8         status[0x8];
4297         u8         reserved_at_8[0x18];
4298
4299         u8         syndrome[0x20];
4300
4301         u8         encap_id[0x20];
4302
4303         u8         reserved_at_60[0x20];
4304 };
4305
4306 struct mlx5_ifc_alloc_encap_header_in_bits {
4307         u8         opcode[0x10];
4308         u8         reserved_at_10[0x10];
4309
4310         u8         reserved_at_20[0x10];
4311         u8         op_mod[0x10];
4312
4313         u8         reserved_at_40[0xa0];
4314
4315         struct mlx5_ifc_encap_header_in_bits encap_header;
4316 };
4317
4318 struct mlx5_ifc_dealloc_encap_header_out_bits {
4319         u8         status[0x8];
4320         u8         reserved_at_8[0x18];
4321
4322         u8         syndrome[0x20];
4323
4324         u8         reserved_at_40[0x40];
4325 };
4326
4327 struct mlx5_ifc_dealloc_encap_header_in_bits {
4328         u8         opcode[0x10];
4329         u8         reserved_at_10[0x10];
4330
4331         u8         reserved_20[0x10];
4332         u8         op_mod[0x10];
4333
4334         u8         encap_id[0x20];
4335
4336         u8         reserved_60[0x20];
4337 };
4338
4339 struct mlx5_ifc_query_dct_out_bits {
4340         u8         status[0x8];
4341         u8         reserved_at_8[0x18];
4342
4343         u8         syndrome[0x20];
4344
4345         u8         reserved_at_40[0x40];
4346
4347         struct mlx5_ifc_dctc_bits dct_context_entry;
4348
4349         u8         reserved_at_280[0x180];
4350 };
4351
4352 struct mlx5_ifc_query_dct_in_bits {
4353         u8         opcode[0x10];
4354         u8         reserved_at_10[0x10];
4355
4356         u8         reserved_at_20[0x10];
4357         u8         op_mod[0x10];
4358
4359         u8         reserved_at_40[0x8];
4360         u8         dctn[0x18];
4361
4362         u8         reserved_at_60[0x20];
4363 };
4364
4365 struct mlx5_ifc_query_cq_out_bits {
4366         u8         status[0x8];
4367         u8         reserved_at_8[0x18];
4368
4369         u8         syndrome[0x20];
4370
4371         u8         reserved_at_40[0x40];
4372
4373         struct mlx5_ifc_cqc_bits cq_context;
4374
4375         u8         reserved_at_280[0x600];
4376
4377         u8         pas[0][0x40];
4378 };
4379
4380 struct mlx5_ifc_query_cq_in_bits {
4381         u8         opcode[0x10];
4382         u8         reserved_at_10[0x10];
4383
4384         u8         reserved_at_20[0x10];
4385         u8         op_mod[0x10];
4386
4387         u8         reserved_at_40[0x8];
4388         u8         cqn[0x18];
4389
4390         u8         reserved_at_60[0x20];
4391 };
4392
4393 struct mlx5_ifc_query_cong_status_out_bits {
4394         u8         status[0x8];
4395         u8         reserved_at_8[0x18];
4396
4397         u8         syndrome[0x20];
4398
4399         u8         reserved_at_40[0x20];
4400
4401         u8         enable[0x1];
4402         u8         tag_enable[0x1];
4403         u8         reserved_at_62[0x1e];
4404 };
4405
4406 struct mlx5_ifc_query_cong_status_in_bits {
4407         u8         opcode[0x10];
4408         u8         reserved_at_10[0x10];
4409
4410         u8         reserved_at_20[0x10];
4411         u8         op_mod[0x10];
4412
4413         u8         reserved_at_40[0x18];
4414         u8         priority[0x4];
4415         u8         cong_protocol[0x4];
4416
4417         u8         reserved_at_60[0x20];
4418 };
4419
4420 struct mlx5_ifc_query_cong_statistics_out_bits {
4421         u8         status[0x8];
4422         u8         reserved_at_8[0x18];
4423
4424         u8         syndrome[0x20];
4425
4426         u8         reserved_at_40[0x40];
4427
4428         u8         cur_flows[0x20];
4429
4430         u8         sum_flows[0x20];
4431
4432         u8         cnp_ignored_high[0x20];
4433
4434         u8         cnp_ignored_low[0x20];
4435
4436         u8         cnp_handled_high[0x20];
4437
4438         u8         cnp_handled_low[0x20];
4439
4440         u8         reserved_at_140[0x100];
4441
4442         u8         time_stamp_high[0x20];
4443
4444         u8         time_stamp_low[0x20];
4445
4446         u8         accumulators_period[0x20];
4447
4448         u8         ecn_marked_roce_packets_high[0x20];
4449
4450         u8         ecn_marked_roce_packets_low[0x20];
4451
4452         u8         cnps_sent_high[0x20];
4453
4454         u8         cnps_sent_low[0x20];
4455
4456         u8         reserved_at_320[0x560];
4457 };
4458
4459 struct mlx5_ifc_query_cong_statistics_in_bits {
4460         u8         opcode[0x10];
4461         u8         reserved_at_10[0x10];
4462
4463         u8         reserved_at_20[0x10];
4464         u8         op_mod[0x10];
4465
4466         u8         clear[0x1];
4467         u8         reserved_at_41[0x1f];
4468
4469         u8         reserved_at_60[0x20];
4470 };
4471
4472 struct mlx5_ifc_query_cong_params_out_bits {
4473         u8         status[0x8];
4474         u8         reserved_at_8[0x18];
4475
4476         u8         syndrome[0x20];
4477
4478         u8         reserved_at_40[0x40];
4479
4480         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4481 };
4482
4483 struct mlx5_ifc_query_cong_params_in_bits {
4484         u8         opcode[0x10];
4485         u8         reserved_at_10[0x10];
4486
4487         u8         reserved_at_20[0x10];
4488         u8         op_mod[0x10];
4489
4490         u8         reserved_at_40[0x1c];
4491         u8         cong_protocol[0x4];
4492
4493         u8         reserved_at_60[0x20];
4494 };
4495
4496 struct mlx5_ifc_query_adapter_out_bits {
4497         u8         status[0x8];
4498         u8         reserved_at_8[0x18];
4499
4500         u8         syndrome[0x20];
4501
4502         u8         reserved_at_40[0x40];
4503
4504         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4505 };
4506
4507 struct mlx5_ifc_query_adapter_in_bits {
4508         u8         opcode[0x10];
4509         u8         reserved_at_10[0x10];
4510
4511         u8         reserved_at_20[0x10];
4512         u8         op_mod[0x10];
4513
4514         u8         reserved_at_40[0x40];
4515 };
4516
4517 struct mlx5_ifc_qp_2rst_out_bits {
4518         u8         status[0x8];
4519         u8         reserved_at_8[0x18];
4520
4521         u8         syndrome[0x20];
4522
4523         u8         reserved_at_40[0x40];
4524 };
4525
4526 struct mlx5_ifc_qp_2rst_in_bits {
4527         u8         opcode[0x10];
4528         u8         reserved_at_10[0x10];
4529
4530         u8         reserved_at_20[0x10];
4531         u8         op_mod[0x10];
4532
4533         u8         reserved_at_40[0x8];
4534         u8         qpn[0x18];
4535
4536         u8         reserved_at_60[0x20];
4537 };
4538
4539 struct mlx5_ifc_qp_2err_out_bits {
4540         u8         status[0x8];
4541         u8         reserved_at_8[0x18];
4542
4543         u8         syndrome[0x20];
4544
4545         u8         reserved_at_40[0x40];
4546 };
4547
4548 struct mlx5_ifc_qp_2err_in_bits {
4549         u8         opcode[0x10];
4550         u8         reserved_at_10[0x10];
4551
4552         u8         reserved_at_20[0x10];
4553         u8         op_mod[0x10];
4554
4555         u8         reserved_at_40[0x8];
4556         u8         qpn[0x18];
4557
4558         u8         reserved_at_60[0x20];
4559 };
4560
4561 struct mlx5_ifc_page_fault_resume_out_bits {
4562         u8         status[0x8];
4563         u8         reserved_at_8[0x18];
4564
4565         u8         syndrome[0x20];
4566
4567         u8         reserved_at_40[0x40];
4568 };
4569
4570 struct mlx5_ifc_page_fault_resume_in_bits {
4571         u8         opcode[0x10];
4572         u8         reserved_at_10[0x10];
4573
4574         u8         reserved_at_20[0x10];
4575         u8         op_mod[0x10];
4576
4577         u8         error[0x1];
4578         u8         reserved_at_41[0x4];
4579         u8         rdma[0x1];
4580         u8         read_write[0x1];
4581         u8         req_res[0x1];
4582         u8         qpn[0x18];
4583
4584         u8         reserved_at_60[0x20];
4585 };
4586
4587 struct mlx5_ifc_nop_out_bits {
4588         u8         status[0x8];
4589         u8         reserved_at_8[0x18];
4590
4591         u8         syndrome[0x20];
4592
4593         u8         reserved_at_40[0x40];
4594 };
4595
4596 struct mlx5_ifc_nop_in_bits {
4597         u8         opcode[0x10];
4598         u8         reserved_at_10[0x10];
4599
4600         u8         reserved_at_20[0x10];
4601         u8         op_mod[0x10];
4602
4603         u8         reserved_at_40[0x40];
4604 };
4605
4606 struct mlx5_ifc_modify_vport_state_out_bits {
4607         u8         status[0x8];
4608         u8         reserved_at_8[0x18];
4609
4610         u8         syndrome[0x20];
4611
4612         u8         reserved_at_40[0x40];
4613 };
4614
4615 struct mlx5_ifc_modify_vport_state_in_bits {
4616         u8         opcode[0x10];
4617         u8         reserved_at_10[0x10];
4618
4619         u8         reserved_at_20[0x10];
4620         u8         op_mod[0x10];
4621
4622         u8         other_vport[0x1];
4623         u8         reserved_at_41[0xf];
4624         u8         vport_number[0x10];
4625
4626         u8         reserved_at_60[0x18];
4627         u8         admin_state[0x4];
4628         u8         reserved_at_7c[0x4];
4629 };
4630
4631 struct mlx5_ifc_modify_tis_out_bits {
4632         u8         status[0x8];
4633         u8         reserved_at_8[0x18];
4634
4635         u8         syndrome[0x20];
4636
4637         u8         reserved_at_40[0x40];
4638 };
4639
4640 struct mlx5_ifc_modify_tis_bitmask_bits {
4641         u8         reserved_at_0[0x20];
4642
4643         u8         reserved_at_20[0x1d];
4644         u8         lag_tx_port_affinity[0x1];
4645         u8         strict_lag_tx_port_affinity[0x1];
4646         u8         prio[0x1];
4647 };
4648
4649 struct mlx5_ifc_modify_tis_in_bits {
4650         u8         opcode[0x10];
4651         u8         reserved_at_10[0x10];
4652
4653         u8         reserved_at_20[0x10];
4654         u8         op_mod[0x10];
4655
4656         u8         reserved_at_40[0x8];
4657         u8         tisn[0x18];
4658
4659         u8         reserved_at_60[0x20];
4660
4661         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4662
4663         u8         reserved_at_c0[0x40];
4664
4665         struct mlx5_ifc_tisc_bits ctx;
4666 };
4667
4668 struct mlx5_ifc_modify_tir_bitmask_bits {
4669         u8         reserved_at_0[0x20];
4670
4671         u8         reserved_at_20[0x1b];
4672         u8         self_lb_en[0x1];
4673         u8         reserved_at_3c[0x1];
4674         u8         hash[0x1];
4675         u8         reserved_at_3e[0x1];
4676         u8         lro[0x1];
4677 };
4678
4679 struct mlx5_ifc_modify_tir_out_bits {
4680         u8         status[0x8];
4681         u8         reserved_at_8[0x18];
4682
4683         u8         syndrome[0x20];
4684
4685         u8         reserved_at_40[0x40];
4686 };
4687
4688 struct mlx5_ifc_modify_tir_in_bits {
4689         u8         opcode[0x10];
4690         u8         reserved_at_10[0x10];
4691
4692         u8         reserved_at_20[0x10];
4693         u8         op_mod[0x10];
4694
4695         u8         reserved_at_40[0x8];
4696         u8         tirn[0x18];
4697
4698         u8         reserved_at_60[0x20];
4699
4700         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4701
4702         u8         reserved_at_c0[0x40];
4703
4704         struct mlx5_ifc_tirc_bits ctx;
4705 };
4706
4707 struct mlx5_ifc_modify_sq_out_bits {
4708         u8         status[0x8];
4709         u8         reserved_at_8[0x18];
4710
4711         u8         syndrome[0x20];
4712
4713         u8         reserved_at_40[0x40];
4714 };
4715
4716 struct mlx5_ifc_modify_sq_in_bits {
4717         u8         opcode[0x10];
4718         u8         reserved_at_10[0x10];
4719
4720         u8         reserved_at_20[0x10];
4721         u8         op_mod[0x10];
4722
4723         u8         sq_state[0x4];
4724         u8         reserved_at_44[0x4];
4725         u8         sqn[0x18];
4726
4727         u8         reserved_at_60[0x20];
4728
4729         u8         modify_bitmask[0x40];
4730
4731         u8         reserved_at_c0[0x40];
4732
4733         struct mlx5_ifc_sqc_bits ctx;
4734 };
4735
4736 struct mlx5_ifc_modify_rqt_out_bits {
4737         u8         status[0x8];
4738         u8         reserved_at_8[0x18];
4739
4740         u8         syndrome[0x20];
4741
4742         u8         reserved_at_40[0x40];
4743 };
4744
4745 struct mlx5_ifc_rqt_bitmask_bits {
4746         u8         reserved_at_0[0x20];
4747
4748         u8         reserved_at_20[0x1f];
4749         u8         rqn_list[0x1];
4750 };
4751
4752 struct mlx5_ifc_modify_rqt_in_bits {
4753         u8         opcode[0x10];
4754         u8         reserved_at_10[0x10];
4755
4756         u8         reserved_at_20[0x10];
4757         u8         op_mod[0x10];
4758
4759         u8         reserved_at_40[0x8];
4760         u8         rqtn[0x18];
4761
4762         u8         reserved_at_60[0x20];
4763
4764         struct mlx5_ifc_rqt_bitmask_bits bitmask;
4765
4766         u8         reserved_at_c0[0x40];
4767
4768         struct mlx5_ifc_rqtc_bits ctx;
4769 };
4770
4771 struct mlx5_ifc_modify_rq_out_bits {
4772         u8         status[0x8];
4773         u8         reserved_at_8[0x18];
4774
4775         u8         syndrome[0x20];
4776
4777         u8         reserved_at_40[0x40];
4778 };
4779
4780 enum {
4781         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
4782         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
4783 };
4784
4785 struct mlx5_ifc_modify_rq_in_bits {
4786         u8         opcode[0x10];
4787         u8         reserved_at_10[0x10];
4788
4789         u8         reserved_at_20[0x10];
4790         u8         op_mod[0x10];
4791
4792         u8         rq_state[0x4];
4793         u8         reserved_at_44[0x4];
4794         u8         rqn[0x18];
4795
4796         u8         reserved_at_60[0x20];
4797
4798         u8         modify_bitmask[0x40];
4799
4800         u8         reserved_at_c0[0x40];
4801
4802         struct mlx5_ifc_rqc_bits ctx;
4803 };
4804
4805 struct mlx5_ifc_modify_rmp_out_bits {
4806         u8         status[0x8];
4807         u8         reserved_at_8[0x18];
4808
4809         u8         syndrome[0x20];
4810
4811         u8         reserved_at_40[0x40];
4812 };
4813
4814 struct mlx5_ifc_rmp_bitmask_bits {
4815         u8         reserved_at_0[0x20];
4816
4817         u8         reserved_at_20[0x1f];
4818         u8         lwm[0x1];
4819 };
4820
4821 struct mlx5_ifc_modify_rmp_in_bits {
4822         u8         opcode[0x10];
4823         u8         reserved_at_10[0x10];
4824
4825         u8         reserved_at_20[0x10];
4826         u8         op_mod[0x10];
4827
4828         u8         rmp_state[0x4];
4829         u8         reserved_at_44[0x4];
4830         u8         rmpn[0x18];
4831
4832         u8         reserved_at_60[0x20];
4833
4834         struct mlx5_ifc_rmp_bitmask_bits bitmask;
4835
4836         u8         reserved_at_c0[0x40];
4837
4838         struct mlx5_ifc_rmpc_bits ctx;
4839 };
4840
4841 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4842         u8         status[0x8];
4843         u8         reserved_at_8[0x18];
4844
4845         u8         syndrome[0x20];
4846
4847         u8         reserved_at_40[0x40];
4848 };
4849
4850 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4851         u8         reserved_at_0[0x16];
4852         u8         node_guid[0x1];
4853         u8         port_guid[0x1];
4854         u8         min_inline[0x1];
4855         u8         mtu[0x1];
4856         u8         change_event[0x1];
4857         u8         promisc[0x1];
4858         u8         permanent_address[0x1];
4859         u8         addresses_list[0x1];
4860         u8         roce_en[0x1];
4861         u8         reserved_at_1f[0x1];
4862 };
4863
4864 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4865         u8         opcode[0x10];
4866         u8         reserved_at_10[0x10];
4867
4868         u8         reserved_at_20[0x10];
4869         u8         op_mod[0x10];
4870
4871         u8         other_vport[0x1];
4872         u8         reserved_at_41[0xf];
4873         u8         vport_number[0x10];
4874
4875         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4876
4877         u8         reserved_at_80[0x780];
4878
4879         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4880 };
4881
4882 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4883         u8         status[0x8];
4884         u8         reserved_at_8[0x18];
4885
4886         u8         syndrome[0x20];
4887
4888         u8         reserved_at_40[0x40];
4889 };
4890
4891 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4892         u8         opcode[0x10];
4893         u8         reserved_at_10[0x10];
4894
4895         u8         reserved_at_20[0x10];
4896         u8         op_mod[0x10];
4897
4898         u8         other_vport[0x1];
4899         u8         reserved_at_41[0xb];
4900         u8         port_num[0x4];
4901         u8         vport_number[0x10];
4902
4903         u8         reserved_at_60[0x20];
4904
4905         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4906 };
4907
4908 struct mlx5_ifc_modify_cq_out_bits {
4909         u8         status[0x8];
4910         u8         reserved_at_8[0x18];
4911
4912         u8         syndrome[0x20];
4913
4914         u8         reserved_at_40[0x40];
4915 };
4916
4917 enum {
4918         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
4919         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
4920 };
4921
4922 struct mlx5_ifc_modify_cq_in_bits {
4923         u8         opcode[0x10];
4924         u8         reserved_at_10[0x10];
4925
4926         u8         reserved_at_20[0x10];
4927         u8         op_mod[0x10];
4928
4929         u8         reserved_at_40[0x8];
4930         u8         cqn[0x18];
4931
4932         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4933
4934         struct mlx5_ifc_cqc_bits cq_context;
4935
4936         u8         reserved_at_280[0x600];
4937
4938         u8         pas[0][0x40];
4939 };
4940
4941 struct mlx5_ifc_modify_cong_status_out_bits {
4942         u8         status[0x8];
4943         u8         reserved_at_8[0x18];
4944
4945         u8         syndrome[0x20];
4946
4947         u8         reserved_at_40[0x40];
4948 };
4949
4950 struct mlx5_ifc_modify_cong_status_in_bits {
4951         u8         opcode[0x10];
4952         u8         reserved_at_10[0x10];
4953
4954         u8         reserved_at_20[0x10];
4955         u8         op_mod[0x10];
4956
4957         u8         reserved_at_40[0x18];
4958         u8         priority[0x4];
4959         u8         cong_protocol[0x4];
4960
4961         u8         enable[0x1];
4962         u8         tag_enable[0x1];
4963         u8         reserved_at_62[0x1e];
4964 };
4965
4966 struct mlx5_ifc_modify_cong_params_out_bits {
4967         u8         status[0x8];
4968         u8         reserved_at_8[0x18];
4969
4970         u8         syndrome[0x20];
4971
4972         u8         reserved_at_40[0x40];
4973 };
4974
4975 struct mlx5_ifc_modify_cong_params_in_bits {
4976         u8         opcode[0x10];
4977         u8         reserved_at_10[0x10];
4978
4979         u8         reserved_at_20[0x10];
4980         u8         op_mod[0x10];
4981
4982         u8         reserved_at_40[0x1c];
4983         u8         cong_protocol[0x4];
4984
4985         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4986
4987         u8         reserved_at_80[0x80];
4988
4989         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4990 };
4991
4992 struct mlx5_ifc_manage_pages_out_bits {
4993         u8         status[0x8];
4994         u8         reserved_at_8[0x18];
4995
4996         u8         syndrome[0x20];
4997
4998         u8         output_num_entries[0x20];
4999
5000         u8         reserved_at_60[0x20];
5001
5002         u8         pas[0][0x40];
5003 };
5004
5005 enum {
5006         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5007         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5008         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5009 };
5010
5011 struct mlx5_ifc_manage_pages_in_bits {
5012         u8         opcode[0x10];
5013         u8         reserved_at_10[0x10];
5014
5015         u8         reserved_at_20[0x10];
5016         u8         op_mod[0x10];
5017
5018         u8         reserved_at_40[0x10];
5019         u8         function_id[0x10];
5020
5021         u8         input_num_entries[0x20];
5022
5023         u8         pas[0][0x40];
5024 };
5025
5026 struct mlx5_ifc_mad_ifc_out_bits {
5027         u8         status[0x8];
5028         u8         reserved_at_8[0x18];
5029
5030         u8         syndrome[0x20];
5031
5032         u8         reserved_at_40[0x40];
5033
5034         u8         response_mad_packet[256][0x8];
5035 };
5036
5037 struct mlx5_ifc_mad_ifc_in_bits {
5038         u8         opcode[0x10];
5039         u8         reserved_at_10[0x10];
5040
5041         u8         reserved_at_20[0x10];
5042         u8         op_mod[0x10];
5043
5044         u8         remote_lid[0x10];
5045         u8         reserved_at_50[0x8];
5046         u8         port[0x8];
5047
5048         u8         reserved_at_60[0x20];
5049
5050         u8         mad[256][0x8];
5051 };
5052
5053 struct mlx5_ifc_init_hca_out_bits {
5054         u8         status[0x8];
5055         u8         reserved_at_8[0x18];
5056
5057         u8         syndrome[0x20];
5058
5059         u8         reserved_at_40[0x40];
5060 };
5061
5062 struct mlx5_ifc_init_hca_in_bits {
5063         u8         opcode[0x10];
5064         u8         reserved_at_10[0x10];
5065
5066         u8         reserved_at_20[0x10];
5067         u8         op_mod[0x10];
5068
5069         u8         reserved_at_40[0x40];
5070 };
5071
5072 struct mlx5_ifc_init2rtr_qp_out_bits {
5073         u8         status[0x8];
5074         u8         reserved_at_8[0x18];
5075
5076         u8         syndrome[0x20];
5077
5078         u8         reserved_at_40[0x40];
5079 };
5080
5081 struct mlx5_ifc_init2rtr_qp_in_bits {
5082         u8         opcode[0x10];
5083         u8         reserved_at_10[0x10];
5084
5085         u8         reserved_at_20[0x10];
5086         u8         op_mod[0x10];
5087
5088         u8         reserved_at_40[0x8];
5089         u8         qpn[0x18];
5090
5091         u8         reserved_at_60[0x20];
5092
5093         u8         opt_param_mask[0x20];
5094
5095         u8         reserved_at_a0[0x20];
5096
5097         struct mlx5_ifc_qpc_bits qpc;
5098
5099         u8         reserved_at_800[0x80];
5100 };
5101
5102 struct mlx5_ifc_init2init_qp_out_bits {
5103         u8         status[0x8];
5104         u8         reserved_at_8[0x18];
5105
5106         u8         syndrome[0x20];
5107
5108         u8         reserved_at_40[0x40];
5109 };
5110
5111 struct mlx5_ifc_init2init_qp_in_bits {
5112         u8         opcode[0x10];
5113         u8         reserved_at_10[0x10];
5114
5115         u8         reserved_at_20[0x10];
5116         u8         op_mod[0x10];
5117
5118         u8         reserved_at_40[0x8];
5119         u8         qpn[0x18];
5120
5121         u8         reserved_at_60[0x20];
5122
5123         u8         opt_param_mask[0x20];
5124
5125         u8         reserved_at_a0[0x20];
5126
5127         struct mlx5_ifc_qpc_bits qpc;
5128
5129         u8         reserved_at_800[0x80];
5130 };
5131
5132 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5133         u8         status[0x8];
5134         u8         reserved_at_8[0x18];
5135
5136         u8         syndrome[0x20];
5137
5138         u8         reserved_at_40[0x40];
5139
5140         u8         packet_headers_log[128][0x8];
5141
5142         u8         packet_syndrome[64][0x8];
5143 };
5144
5145 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5146         u8         opcode[0x10];
5147         u8         reserved_at_10[0x10];
5148
5149         u8         reserved_at_20[0x10];
5150         u8         op_mod[0x10];
5151
5152         u8         reserved_at_40[0x40];
5153 };
5154
5155 struct mlx5_ifc_gen_eqe_in_bits {
5156         u8         opcode[0x10];
5157         u8         reserved_at_10[0x10];
5158
5159         u8         reserved_at_20[0x10];
5160         u8         op_mod[0x10];
5161
5162         u8         reserved_at_40[0x18];
5163         u8         eq_number[0x8];
5164
5165         u8         reserved_at_60[0x20];
5166
5167         u8         eqe[64][0x8];
5168 };
5169
5170 struct mlx5_ifc_gen_eq_out_bits {
5171         u8         status[0x8];
5172         u8         reserved_at_8[0x18];
5173
5174         u8         syndrome[0x20];
5175
5176         u8         reserved_at_40[0x40];
5177 };
5178
5179 struct mlx5_ifc_enable_hca_out_bits {
5180         u8         status[0x8];
5181         u8         reserved_at_8[0x18];
5182
5183         u8         syndrome[0x20];
5184
5185         u8         reserved_at_40[0x20];
5186 };
5187
5188 struct mlx5_ifc_enable_hca_in_bits {
5189         u8         opcode[0x10];
5190         u8         reserved_at_10[0x10];
5191
5192         u8         reserved_at_20[0x10];
5193         u8         op_mod[0x10];
5194
5195         u8         reserved_at_40[0x10];
5196         u8         function_id[0x10];
5197
5198         u8         reserved_at_60[0x20];
5199 };
5200
5201 struct mlx5_ifc_drain_dct_out_bits {
5202         u8         status[0x8];
5203         u8         reserved_at_8[0x18];
5204
5205         u8         syndrome[0x20];
5206
5207         u8         reserved_at_40[0x40];
5208 };
5209
5210 struct mlx5_ifc_drain_dct_in_bits {
5211         u8         opcode[0x10];
5212         u8         reserved_at_10[0x10];
5213
5214         u8         reserved_at_20[0x10];
5215         u8         op_mod[0x10];
5216
5217         u8         reserved_at_40[0x8];
5218         u8         dctn[0x18];
5219
5220         u8         reserved_at_60[0x20];
5221 };
5222
5223 struct mlx5_ifc_disable_hca_out_bits {
5224         u8         status[0x8];
5225         u8         reserved_at_8[0x18];
5226
5227         u8         syndrome[0x20];
5228
5229         u8         reserved_at_40[0x20];
5230 };
5231
5232 struct mlx5_ifc_disable_hca_in_bits {
5233         u8         opcode[0x10];
5234         u8         reserved_at_10[0x10];
5235
5236         u8         reserved_at_20[0x10];
5237         u8         op_mod[0x10];
5238
5239         u8         reserved_at_40[0x10];
5240         u8         function_id[0x10];
5241
5242         u8         reserved_at_60[0x20];
5243 };
5244
5245 struct mlx5_ifc_detach_from_mcg_out_bits {
5246         u8         status[0x8];
5247         u8         reserved_at_8[0x18];
5248
5249         u8         syndrome[0x20];
5250
5251         u8         reserved_at_40[0x40];
5252 };
5253
5254 struct mlx5_ifc_detach_from_mcg_in_bits {
5255         u8         opcode[0x10];
5256         u8         reserved_at_10[0x10];
5257
5258         u8         reserved_at_20[0x10];
5259         u8         op_mod[0x10];
5260
5261         u8         reserved_at_40[0x8];
5262         u8         qpn[0x18];
5263
5264         u8         reserved_at_60[0x20];
5265
5266         u8         multicast_gid[16][0x8];
5267 };
5268
5269 struct mlx5_ifc_destroy_xrq_out_bits {
5270         u8         status[0x8];
5271         u8         reserved_at_8[0x18];
5272
5273         u8         syndrome[0x20];
5274
5275         u8         reserved_at_40[0x40];
5276 };
5277
5278 struct mlx5_ifc_destroy_xrq_in_bits {
5279         u8         opcode[0x10];
5280         u8         reserved_at_10[0x10];
5281
5282         u8         reserved_at_20[0x10];
5283         u8         op_mod[0x10];
5284
5285         u8         reserved_at_40[0x8];
5286         u8         xrqn[0x18];
5287
5288         u8         reserved_at_60[0x20];
5289 };
5290
5291 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5292         u8         status[0x8];
5293         u8         reserved_at_8[0x18];
5294
5295         u8         syndrome[0x20];
5296
5297         u8         reserved_at_40[0x40];
5298 };
5299
5300 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5301         u8         opcode[0x10];
5302         u8         reserved_at_10[0x10];
5303
5304         u8         reserved_at_20[0x10];
5305         u8         op_mod[0x10];
5306
5307         u8         reserved_at_40[0x8];
5308         u8         xrc_srqn[0x18];
5309
5310         u8         reserved_at_60[0x20];
5311 };
5312
5313 struct mlx5_ifc_destroy_tis_out_bits {
5314         u8         status[0x8];
5315         u8         reserved_at_8[0x18];
5316
5317         u8         syndrome[0x20];
5318
5319         u8         reserved_at_40[0x40];
5320 };
5321
5322 struct mlx5_ifc_destroy_tis_in_bits {
5323         u8         opcode[0x10];
5324         u8         reserved_at_10[0x10];
5325
5326         u8         reserved_at_20[0x10];
5327         u8         op_mod[0x10];
5328
5329         u8         reserved_at_40[0x8];
5330         u8         tisn[0x18];
5331
5332         u8         reserved_at_60[0x20];
5333 };
5334
5335 struct mlx5_ifc_destroy_tir_out_bits {
5336         u8         status[0x8];
5337         u8         reserved_at_8[0x18];
5338
5339         u8         syndrome[0x20];
5340
5341         u8         reserved_at_40[0x40];
5342 };
5343
5344 struct mlx5_ifc_destroy_tir_in_bits {
5345         u8         opcode[0x10];
5346         u8         reserved_at_10[0x10];
5347
5348         u8         reserved_at_20[0x10];
5349         u8         op_mod[0x10];
5350
5351         u8         reserved_at_40[0x8];
5352         u8         tirn[0x18];
5353
5354         u8         reserved_at_60[0x20];
5355 };
5356
5357 struct mlx5_ifc_destroy_srq_out_bits {
5358         u8         status[0x8];
5359         u8         reserved_at_8[0x18];
5360
5361         u8         syndrome[0x20];
5362
5363         u8         reserved_at_40[0x40];
5364 };
5365
5366 struct mlx5_ifc_destroy_srq_in_bits {
5367         u8         opcode[0x10];
5368         u8         reserved_at_10[0x10];
5369
5370         u8         reserved_at_20[0x10];
5371         u8         op_mod[0x10];
5372
5373         u8         reserved_at_40[0x8];
5374         u8         srqn[0x18];
5375
5376         u8         reserved_at_60[0x20];
5377 };
5378
5379 struct mlx5_ifc_destroy_sq_out_bits {
5380         u8         status[0x8];
5381         u8         reserved_at_8[0x18];
5382
5383         u8         syndrome[0x20];
5384
5385         u8         reserved_at_40[0x40];
5386 };
5387
5388 struct mlx5_ifc_destroy_sq_in_bits {
5389         u8         opcode[0x10];
5390         u8         reserved_at_10[0x10];
5391
5392         u8         reserved_at_20[0x10];
5393         u8         op_mod[0x10];
5394
5395         u8         reserved_at_40[0x8];
5396         u8         sqn[0x18];
5397
5398         u8         reserved_at_60[0x20];
5399 };
5400
5401 struct mlx5_ifc_destroy_rqt_out_bits {
5402         u8         status[0x8];
5403         u8         reserved_at_8[0x18];
5404
5405         u8         syndrome[0x20];
5406
5407         u8         reserved_at_40[0x40];
5408 };
5409
5410 struct mlx5_ifc_destroy_rqt_in_bits {
5411         u8         opcode[0x10];
5412         u8         reserved_at_10[0x10];
5413
5414         u8         reserved_at_20[0x10];
5415         u8         op_mod[0x10];
5416
5417         u8         reserved_at_40[0x8];
5418         u8         rqtn[0x18];
5419
5420         u8         reserved_at_60[0x20];
5421 };
5422
5423 struct mlx5_ifc_destroy_rq_out_bits {
5424         u8         status[0x8];
5425         u8         reserved_at_8[0x18];
5426
5427         u8         syndrome[0x20];
5428
5429         u8         reserved_at_40[0x40];
5430 };
5431
5432 struct mlx5_ifc_destroy_rq_in_bits {
5433         u8         opcode[0x10];
5434         u8         reserved_at_10[0x10];
5435
5436         u8         reserved_at_20[0x10];
5437         u8         op_mod[0x10];
5438
5439         u8         reserved_at_40[0x8];
5440         u8         rqn[0x18];
5441
5442         u8         reserved_at_60[0x20];
5443 };
5444
5445 struct mlx5_ifc_destroy_rmp_out_bits {
5446         u8         status[0x8];
5447         u8         reserved_at_8[0x18];
5448
5449         u8         syndrome[0x20];
5450
5451         u8         reserved_at_40[0x40];
5452 };
5453
5454 struct mlx5_ifc_destroy_rmp_in_bits {
5455         u8         opcode[0x10];
5456         u8         reserved_at_10[0x10];
5457
5458         u8         reserved_at_20[0x10];
5459         u8         op_mod[0x10];
5460
5461         u8         reserved_at_40[0x8];
5462         u8         rmpn[0x18];
5463
5464         u8         reserved_at_60[0x20];
5465 };
5466
5467 struct mlx5_ifc_destroy_qp_out_bits {
5468         u8         status[0x8];
5469         u8         reserved_at_8[0x18];
5470
5471         u8         syndrome[0x20];
5472
5473         u8         reserved_at_40[0x40];
5474 };
5475
5476 struct mlx5_ifc_destroy_qp_in_bits {
5477         u8         opcode[0x10];
5478         u8         reserved_at_10[0x10];
5479
5480         u8         reserved_at_20[0x10];
5481         u8         op_mod[0x10];
5482
5483         u8         reserved_at_40[0x8];
5484         u8         qpn[0x18];
5485
5486         u8         reserved_at_60[0x20];
5487 };
5488
5489 struct mlx5_ifc_destroy_psv_out_bits {
5490         u8         status[0x8];
5491         u8         reserved_at_8[0x18];
5492
5493         u8         syndrome[0x20];
5494
5495         u8         reserved_at_40[0x40];
5496 };
5497
5498 struct mlx5_ifc_destroy_psv_in_bits {
5499         u8         opcode[0x10];
5500         u8         reserved_at_10[0x10];
5501
5502         u8         reserved_at_20[0x10];
5503         u8         op_mod[0x10];
5504
5505         u8         reserved_at_40[0x8];
5506         u8         psvn[0x18];
5507
5508         u8         reserved_at_60[0x20];
5509 };
5510
5511 struct mlx5_ifc_destroy_mkey_out_bits {
5512         u8         status[0x8];
5513         u8         reserved_at_8[0x18];
5514
5515         u8         syndrome[0x20];
5516
5517         u8         reserved_at_40[0x40];
5518 };
5519
5520 struct mlx5_ifc_destroy_mkey_in_bits {
5521         u8         opcode[0x10];
5522         u8         reserved_at_10[0x10];
5523
5524         u8         reserved_at_20[0x10];
5525         u8         op_mod[0x10];
5526
5527         u8         reserved_at_40[0x8];
5528         u8         mkey_index[0x18];
5529
5530         u8         reserved_at_60[0x20];
5531 };
5532
5533 struct mlx5_ifc_destroy_flow_table_out_bits {
5534         u8         status[0x8];
5535         u8         reserved_at_8[0x18];
5536
5537         u8         syndrome[0x20];
5538
5539         u8         reserved_at_40[0x40];
5540 };
5541
5542 struct mlx5_ifc_destroy_flow_table_in_bits {
5543         u8         opcode[0x10];
5544         u8         reserved_at_10[0x10];
5545
5546         u8         reserved_at_20[0x10];
5547         u8         op_mod[0x10];
5548
5549         u8         other_vport[0x1];
5550         u8         reserved_at_41[0xf];
5551         u8         vport_number[0x10];
5552
5553         u8         reserved_at_60[0x20];
5554
5555         u8         table_type[0x8];
5556         u8         reserved_at_88[0x18];
5557
5558         u8         reserved_at_a0[0x8];
5559         u8         table_id[0x18];
5560
5561         u8         reserved_at_c0[0x140];
5562 };
5563
5564 struct mlx5_ifc_destroy_flow_group_out_bits {
5565         u8         status[0x8];
5566         u8         reserved_at_8[0x18];
5567
5568         u8         syndrome[0x20];
5569
5570         u8         reserved_at_40[0x40];
5571 };
5572
5573 struct mlx5_ifc_destroy_flow_group_in_bits {
5574         u8         opcode[0x10];
5575         u8         reserved_at_10[0x10];
5576
5577         u8         reserved_at_20[0x10];
5578         u8         op_mod[0x10];
5579
5580         u8         other_vport[0x1];
5581         u8         reserved_at_41[0xf];
5582         u8         vport_number[0x10];
5583
5584         u8         reserved_at_60[0x20];
5585
5586         u8         table_type[0x8];
5587         u8         reserved_at_88[0x18];
5588
5589         u8         reserved_at_a0[0x8];
5590         u8         table_id[0x18];
5591
5592         u8         group_id[0x20];
5593
5594         u8         reserved_at_e0[0x120];
5595 };
5596
5597 struct mlx5_ifc_destroy_eq_out_bits {
5598         u8         status[0x8];
5599         u8         reserved_at_8[0x18];
5600
5601         u8         syndrome[0x20];
5602
5603         u8         reserved_at_40[0x40];
5604 };
5605
5606 struct mlx5_ifc_destroy_eq_in_bits {
5607         u8         opcode[0x10];
5608         u8         reserved_at_10[0x10];
5609
5610         u8         reserved_at_20[0x10];
5611         u8         op_mod[0x10];
5612
5613         u8         reserved_at_40[0x18];
5614         u8         eq_number[0x8];
5615
5616         u8         reserved_at_60[0x20];
5617 };
5618
5619 struct mlx5_ifc_destroy_dct_out_bits {
5620         u8         status[0x8];
5621         u8         reserved_at_8[0x18];
5622
5623         u8         syndrome[0x20];
5624
5625         u8         reserved_at_40[0x40];
5626 };
5627
5628 struct mlx5_ifc_destroy_dct_in_bits {
5629         u8         opcode[0x10];
5630         u8         reserved_at_10[0x10];
5631
5632         u8         reserved_at_20[0x10];
5633         u8         op_mod[0x10];
5634
5635         u8         reserved_at_40[0x8];
5636         u8         dctn[0x18];
5637
5638         u8         reserved_at_60[0x20];
5639 };
5640
5641 struct mlx5_ifc_destroy_cq_out_bits {
5642         u8         status[0x8];
5643         u8         reserved_at_8[0x18];
5644
5645         u8         syndrome[0x20];
5646
5647         u8         reserved_at_40[0x40];
5648 };
5649
5650 struct mlx5_ifc_destroy_cq_in_bits {
5651         u8         opcode[0x10];
5652         u8         reserved_at_10[0x10];
5653
5654         u8         reserved_at_20[0x10];
5655         u8         op_mod[0x10];
5656
5657         u8         reserved_at_40[0x8];
5658         u8         cqn[0x18];
5659
5660         u8         reserved_at_60[0x20];
5661 };
5662
5663 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5664         u8         status[0x8];
5665         u8         reserved_at_8[0x18];
5666
5667         u8         syndrome[0x20];
5668
5669         u8         reserved_at_40[0x40];
5670 };
5671
5672 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5673         u8         opcode[0x10];
5674         u8         reserved_at_10[0x10];
5675
5676         u8         reserved_at_20[0x10];
5677         u8         op_mod[0x10];
5678
5679         u8         reserved_at_40[0x20];
5680
5681         u8         reserved_at_60[0x10];
5682         u8         vxlan_udp_port[0x10];
5683 };
5684
5685 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5686         u8         status[0x8];
5687         u8         reserved_at_8[0x18];
5688
5689         u8         syndrome[0x20];
5690
5691         u8         reserved_at_40[0x40];
5692 };
5693
5694 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5695         u8         opcode[0x10];
5696         u8         reserved_at_10[0x10];
5697
5698         u8         reserved_at_20[0x10];
5699         u8         op_mod[0x10];
5700
5701         u8         reserved_at_40[0x60];
5702
5703         u8         reserved_at_a0[0x8];
5704         u8         table_index[0x18];
5705
5706         u8         reserved_at_c0[0x140];
5707 };
5708
5709 struct mlx5_ifc_delete_fte_out_bits {
5710         u8         status[0x8];
5711         u8         reserved_at_8[0x18];
5712
5713         u8         syndrome[0x20];
5714
5715         u8         reserved_at_40[0x40];
5716 };
5717
5718 struct mlx5_ifc_delete_fte_in_bits {
5719         u8         opcode[0x10];
5720         u8         reserved_at_10[0x10];
5721
5722         u8         reserved_at_20[0x10];
5723         u8         op_mod[0x10];
5724
5725         u8         other_vport[0x1];
5726         u8         reserved_at_41[0xf];
5727         u8         vport_number[0x10];
5728
5729         u8         reserved_at_60[0x20];
5730
5731         u8         table_type[0x8];
5732         u8         reserved_at_88[0x18];
5733
5734         u8         reserved_at_a0[0x8];
5735         u8         table_id[0x18];
5736
5737         u8         reserved_at_c0[0x40];
5738
5739         u8         flow_index[0x20];
5740
5741         u8         reserved_at_120[0xe0];
5742 };
5743
5744 struct mlx5_ifc_dealloc_xrcd_out_bits {
5745         u8         status[0x8];
5746         u8         reserved_at_8[0x18];
5747
5748         u8         syndrome[0x20];
5749
5750         u8         reserved_at_40[0x40];
5751 };
5752
5753 struct mlx5_ifc_dealloc_xrcd_in_bits {
5754         u8         opcode[0x10];
5755         u8         reserved_at_10[0x10];
5756
5757         u8         reserved_at_20[0x10];
5758         u8         op_mod[0x10];
5759
5760         u8         reserved_at_40[0x8];
5761         u8         xrcd[0x18];
5762
5763         u8         reserved_at_60[0x20];
5764 };
5765
5766 struct mlx5_ifc_dealloc_uar_out_bits {
5767         u8         status[0x8];
5768         u8         reserved_at_8[0x18];
5769
5770         u8         syndrome[0x20];
5771
5772         u8         reserved_at_40[0x40];
5773 };
5774
5775 struct mlx5_ifc_dealloc_uar_in_bits {
5776         u8         opcode[0x10];
5777         u8         reserved_at_10[0x10];
5778
5779         u8         reserved_at_20[0x10];
5780         u8         op_mod[0x10];
5781
5782         u8         reserved_at_40[0x8];
5783         u8         uar[0x18];
5784
5785         u8         reserved_at_60[0x20];
5786 };
5787
5788 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5789         u8         status[0x8];
5790         u8         reserved_at_8[0x18];
5791
5792         u8         syndrome[0x20];
5793
5794         u8         reserved_at_40[0x40];
5795 };
5796
5797 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5798         u8         opcode[0x10];
5799         u8         reserved_at_10[0x10];
5800
5801         u8         reserved_at_20[0x10];
5802         u8         op_mod[0x10];
5803
5804         u8         reserved_at_40[0x8];
5805         u8         transport_domain[0x18];
5806
5807         u8         reserved_at_60[0x20];
5808 };
5809
5810 struct mlx5_ifc_dealloc_q_counter_out_bits {
5811         u8         status[0x8];
5812         u8         reserved_at_8[0x18];
5813
5814         u8         syndrome[0x20];
5815
5816         u8         reserved_at_40[0x40];
5817 };
5818
5819 struct mlx5_ifc_dealloc_q_counter_in_bits {
5820         u8         opcode[0x10];
5821         u8         reserved_at_10[0x10];
5822
5823         u8         reserved_at_20[0x10];
5824         u8         op_mod[0x10];
5825
5826         u8         reserved_at_40[0x18];
5827         u8         counter_set_id[0x8];
5828
5829         u8         reserved_at_60[0x20];
5830 };
5831
5832 struct mlx5_ifc_dealloc_pd_out_bits {
5833         u8         status[0x8];
5834         u8         reserved_at_8[0x18];
5835
5836         u8         syndrome[0x20];
5837
5838         u8         reserved_at_40[0x40];
5839 };
5840
5841 struct mlx5_ifc_dealloc_pd_in_bits {
5842         u8         opcode[0x10];
5843         u8         reserved_at_10[0x10];
5844
5845         u8         reserved_at_20[0x10];
5846         u8         op_mod[0x10];
5847
5848         u8         reserved_at_40[0x8];
5849         u8         pd[0x18];
5850
5851         u8         reserved_at_60[0x20];
5852 };
5853
5854 struct mlx5_ifc_dealloc_flow_counter_out_bits {
5855         u8         status[0x8];
5856         u8         reserved_at_8[0x18];
5857
5858         u8         syndrome[0x20];
5859
5860         u8         reserved_at_40[0x40];
5861 };
5862
5863 struct mlx5_ifc_dealloc_flow_counter_in_bits {
5864         u8         opcode[0x10];
5865         u8         reserved_at_10[0x10];
5866
5867         u8         reserved_at_20[0x10];
5868         u8         op_mod[0x10];
5869
5870         u8         reserved_at_40[0x10];
5871         u8         flow_counter_id[0x10];
5872
5873         u8         reserved_at_60[0x20];
5874 };
5875
5876 struct mlx5_ifc_create_xrq_out_bits {
5877         u8         status[0x8];
5878         u8         reserved_at_8[0x18];
5879
5880         u8         syndrome[0x20];
5881
5882         u8         reserved_at_40[0x8];
5883         u8         xrqn[0x18];
5884
5885         u8         reserved_at_60[0x20];
5886 };
5887
5888 struct mlx5_ifc_create_xrq_in_bits {
5889         u8         opcode[0x10];
5890         u8         reserved_at_10[0x10];
5891
5892         u8         reserved_at_20[0x10];
5893         u8         op_mod[0x10];
5894
5895         u8         reserved_at_40[0x40];
5896
5897         struct mlx5_ifc_xrqc_bits xrq_context;
5898 };
5899
5900 struct mlx5_ifc_create_xrc_srq_out_bits {
5901         u8         status[0x8];
5902         u8         reserved_at_8[0x18];
5903
5904         u8         syndrome[0x20];
5905
5906         u8         reserved_at_40[0x8];
5907         u8         xrc_srqn[0x18];
5908
5909         u8         reserved_at_60[0x20];
5910 };
5911
5912 struct mlx5_ifc_create_xrc_srq_in_bits {
5913         u8         opcode[0x10];
5914         u8         reserved_at_10[0x10];
5915
5916         u8         reserved_at_20[0x10];
5917         u8         op_mod[0x10];
5918
5919         u8         reserved_at_40[0x40];
5920
5921         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5922
5923         u8         reserved_at_280[0x600];
5924
5925         u8         pas[0][0x40];
5926 };
5927
5928 struct mlx5_ifc_create_tis_out_bits {
5929         u8         status[0x8];
5930         u8         reserved_at_8[0x18];
5931
5932         u8         syndrome[0x20];
5933
5934         u8         reserved_at_40[0x8];
5935         u8         tisn[0x18];
5936
5937         u8         reserved_at_60[0x20];
5938 };
5939
5940 struct mlx5_ifc_create_tis_in_bits {
5941         u8         opcode[0x10];
5942         u8         reserved_at_10[0x10];
5943
5944         u8         reserved_at_20[0x10];
5945         u8         op_mod[0x10];
5946
5947         u8         reserved_at_40[0xc0];
5948
5949         struct mlx5_ifc_tisc_bits ctx;
5950 };
5951
5952 struct mlx5_ifc_create_tir_out_bits {
5953         u8         status[0x8];
5954         u8         reserved_at_8[0x18];
5955
5956         u8         syndrome[0x20];
5957
5958         u8         reserved_at_40[0x8];
5959         u8         tirn[0x18];
5960
5961         u8         reserved_at_60[0x20];
5962 };
5963
5964 struct mlx5_ifc_create_tir_in_bits {
5965         u8         opcode[0x10];
5966         u8         reserved_at_10[0x10];
5967
5968         u8         reserved_at_20[0x10];
5969         u8         op_mod[0x10];
5970
5971         u8         reserved_at_40[0xc0];
5972
5973         struct mlx5_ifc_tirc_bits ctx;
5974 };
5975
5976 struct mlx5_ifc_create_srq_out_bits {
5977         u8         status[0x8];
5978         u8         reserved_at_8[0x18];
5979
5980         u8         syndrome[0x20];
5981
5982         u8         reserved_at_40[0x8];
5983         u8         srqn[0x18];
5984
5985         u8         reserved_at_60[0x20];
5986 };
5987
5988 struct mlx5_ifc_create_srq_in_bits {
5989         u8         opcode[0x10];
5990         u8         reserved_at_10[0x10];
5991
5992         u8         reserved_at_20[0x10];
5993         u8         op_mod[0x10];
5994
5995         u8         reserved_at_40[0x40];
5996
5997         struct mlx5_ifc_srqc_bits srq_context_entry;
5998
5999         u8         reserved_at_280[0x600];
6000
6001         u8         pas[0][0x40];
6002 };
6003
6004 struct mlx5_ifc_create_sq_out_bits {
6005         u8         status[0x8];
6006         u8         reserved_at_8[0x18];
6007
6008         u8         syndrome[0x20];
6009
6010         u8         reserved_at_40[0x8];
6011         u8         sqn[0x18];
6012
6013         u8         reserved_at_60[0x20];
6014 };
6015
6016 struct mlx5_ifc_create_sq_in_bits {
6017         u8         opcode[0x10];
6018         u8         reserved_at_10[0x10];
6019
6020         u8         reserved_at_20[0x10];
6021         u8         op_mod[0x10];
6022
6023         u8         reserved_at_40[0xc0];
6024
6025         struct mlx5_ifc_sqc_bits ctx;
6026 };
6027
6028 struct mlx5_ifc_create_rqt_out_bits {
6029         u8         status[0x8];
6030         u8         reserved_at_8[0x18];
6031
6032         u8         syndrome[0x20];
6033
6034         u8         reserved_at_40[0x8];
6035         u8         rqtn[0x18];
6036
6037         u8         reserved_at_60[0x20];
6038 };
6039
6040 struct mlx5_ifc_create_rqt_in_bits {
6041         u8         opcode[0x10];
6042         u8         reserved_at_10[0x10];
6043
6044         u8         reserved_at_20[0x10];
6045         u8         op_mod[0x10];
6046
6047         u8         reserved_at_40[0xc0];
6048
6049         struct mlx5_ifc_rqtc_bits rqt_context;
6050 };
6051
6052 struct mlx5_ifc_create_rq_out_bits {
6053         u8         status[0x8];
6054         u8         reserved_at_8[0x18];
6055
6056         u8         syndrome[0x20];
6057
6058         u8         reserved_at_40[0x8];
6059         u8         rqn[0x18];
6060
6061         u8         reserved_at_60[0x20];
6062 };
6063
6064 struct mlx5_ifc_create_rq_in_bits {
6065         u8         opcode[0x10];
6066         u8         reserved_at_10[0x10];
6067
6068         u8         reserved_at_20[0x10];
6069         u8         op_mod[0x10];
6070
6071         u8         reserved_at_40[0xc0];
6072
6073         struct mlx5_ifc_rqc_bits ctx;
6074 };
6075
6076 struct mlx5_ifc_create_rmp_out_bits {
6077         u8         status[0x8];
6078         u8         reserved_at_8[0x18];
6079
6080         u8         syndrome[0x20];
6081
6082         u8         reserved_at_40[0x8];
6083         u8         rmpn[0x18];
6084
6085         u8         reserved_at_60[0x20];
6086 };
6087
6088 struct mlx5_ifc_create_rmp_in_bits {
6089         u8         opcode[0x10];
6090         u8         reserved_at_10[0x10];
6091
6092         u8         reserved_at_20[0x10];
6093         u8         op_mod[0x10];
6094
6095         u8         reserved_at_40[0xc0];
6096
6097         struct mlx5_ifc_rmpc_bits ctx;
6098 };
6099
6100 struct mlx5_ifc_create_qp_out_bits {
6101         u8         status[0x8];
6102         u8         reserved_at_8[0x18];
6103
6104         u8         syndrome[0x20];
6105
6106         u8         reserved_at_40[0x8];
6107         u8         qpn[0x18];
6108
6109         u8         reserved_at_60[0x20];
6110 };
6111
6112 struct mlx5_ifc_create_qp_in_bits {
6113         u8         opcode[0x10];
6114         u8         reserved_at_10[0x10];
6115
6116         u8         reserved_at_20[0x10];
6117         u8         op_mod[0x10];
6118
6119         u8         reserved_at_40[0x40];
6120
6121         u8         opt_param_mask[0x20];
6122
6123         u8         reserved_at_a0[0x20];
6124
6125         struct mlx5_ifc_qpc_bits qpc;
6126
6127         u8         reserved_at_800[0x80];
6128
6129         u8         pas[0][0x40];
6130 };
6131
6132 struct mlx5_ifc_create_psv_out_bits {
6133         u8         status[0x8];
6134         u8         reserved_at_8[0x18];
6135
6136         u8         syndrome[0x20];
6137
6138         u8         reserved_at_40[0x40];
6139
6140         u8         reserved_at_80[0x8];
6141         u8         psv0_index[0x18];
6142
6143         u8         reserved_at_a0[0x8];
6144         u8         psv1_index[0x18];
6145
6146         u8         reserved_at_c0[0x8];
6147         u8         psv2_index[0x18];
6148
6149         u8         reserved_at_e0[0x8];
6150         u8         psv3_index[0x18];
6151 };
6152
6153 struct mlx5_ifc_create_psv_in_bits {
6154         u8         opcode[0x10];
6155         u8         reserved_at_10[0x10];
6156
6157         u8         reserved_at_20[0x10];
6158         u8         op_mod[0x10];
6159
6160         u8         num_psv[0x4];
6161         u8         reserved_at_44[0x4];
6162         u8         pd[0x18];
6163
6164         u8         reserved_at_60[0x20];
6165 };
6166
6167 struct mlx5_ifc_create_mkey_out_bits {
6168         u8         status[0x8];
6169         u8         reserved_at_8[0x18];
6170
6171         u8         syndrome[0x20];
6172
6173         u8         reserved_at_40[0x8];
6174         u8         mkey_index[0x18];
6175
6176         u8         reserved_at_60[0x20];
6177 };
6178
6179 struct mlx5_ifc_create_mkey_in_bits {
6180         u8         opcode[0x10];
6181         u8         reserved_at_10[0x10];
6182
6183         u8         reserved_at_20[0x10];
6184         u8         op_mod[0x10];
6185
6186         u8         reserved_at_40[0x20];
6187
6188         u8         pg_access[0x1];
6189         u8         reserved_at_61[0x1f];
6190
6191         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6192
6193         u8         reserved_at_280[0x80];
6194
6195         u8         translations_octword_actual_size[0x20];
6196
6197         u8         reserved_at_320[0x560];
6198
6199         u8         klm_pas_mtt[0][0x20];
6200 };
6201
6202 struct mlx5_ifc_create_flow_table_out_bits {
6203         u8         status[0x8];
6204         u8         reserved_at_8[0x18];
6205
6206         u8         syndrome[0x20];
6207
6208         u8         reserved_at_40[0x8];
6209         u8         table_id[0x18];
6210
6211         u8         reserved_at_60[0x20];
6212 };
6213
6214 struct mlx5_ifc_create_flow_table_in_bits {
6215         u8         opcode[0x10];
6216         u8         reserved_at_10[0x10];
6217
6218         u8         reserved_at_20[0x10];
6219         u8         op_mod[0x10];
6220
6221         u8         other_vport[0x1];
6222         u8         reserved_at_41[0xf];
6223         u8         vport_number[0x10];
6224
6225         u8         reserved_at_60[0x20];
6226
6227         u8         table_type[0x8];
6228         u8         reserved_at_88[0x18];
6229
6230         u8         reserved_at_a0[0x20];
6231
6232         u8         encap_en[0x1];
6233         u8         decap_en[0x1];
6234         u8         reserved_at_c2[0x2];
6235         u8         table_miss_mode[0x4];
6236         u8         level[0x8];
6237         u8         reserved_at_d0[0x8];
6238         u8         log_size[0x8];
6239
6240         u8         reserved_at_e0[0x8];
6241         u8         table_miss_id[0x18];
6242
6243         u8         reserved_at_100[0x8];
6244         u8         lag_master_next_table_id[0x18];
6245
6246         u8         reserved_at_120[0x80];
6247 };
6248
6249 struct mlx5_ifc_create_flow_group_out_bits {
6250         u8         status[0x8];
6251         u8         reserved_at_8[0x18];
6252
6253         u8         syndrome[0x20];
6254
6255         u8         reserved_at_40[0x8];
6256         u8         group_id[0x18];
6257
6258         u8         reserved_at_60[0x20];
6259 };
6260
6261 enum {
6262         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6263         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6264         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6265 };
6266
6267 struct mlx5_ifc_create_flow_group_in_bits {
6268         u8         opcode[0x10];
6269         u8         reserved_at_10[0x10];
6270
6271         u8         reserved_at_20[0x10];
6272         u8         op_mod[0x10];
6273
6274         u8         other_vport[0x1];
6275         u8         reserved_at_41[0xf];
6276         u8         vport_number[0x10];
6277
6278         u8         reserved_at_60[0x20];
6279
6280         u8         table_type[0x8];
6281         u8         reserved_at_88[0x18];
6282
6283         u8         reserved_at_a0[0x8];
6284         u8         table_id[0x18];
6285
6286         u8         reserved_at_c0[0x20];
6287
6288         u8         start_flow_index[0x20];
6289
6290         u8         reserved_at_100[0x20];
6291
6292         u8         end_flow_index[0x20];
6293
6294         u8         reserved_at_140[0xa0];
6295
6296         u8         reserved_at_1e0[0x18];
6297         u8         match_criteria_enable[0x8];
6298
6299         struct mlx5_ifc_fte_match_param_bits match_criteria;
6300
6301         u8         reserved_at_1200[0xe00];
6302 };
6303
6304 struct mlx5_ifc_create_eq_out_bits {
6305         u8         status[0x8];
6306         u8         reserved_at_8[0x18];
6307
6308         u8         syndrome[0x20];
6309
6310         u8         reserved_at_40[0x18];
6311         u8         eq_number[0x8];
6312
6313         u8         reserved_at_60[0x20];
6314 };
6315
6316 struct mlx5_ifc_create_eq_in_bits {
6317         u8         opcode[0x10];
6318         u8         reserved_at_10[0x10];
6319
6320         u8         reserved_at_20[0x10];
6321         u8         op_mod[0x10];
6322
6323         u8         reserved_at_40[0x40];
6324
6325         struct mlx5_ifc_eqc_bits eq_context_entry;
6326
6327         u8         reserved_at_280[0x40];
6328
6329         u8         event_bitmask[0x40];
6330
6331         u8         reserved_at_300[0x580];
6332
6333         u8         pas[0][0x40];
6334 };
6335
6336 struct mlx5_ifc_create_dct_out_bits {
6337         u8         status[0x8];
6338         u8         reserved_at_8[0x18];
6339
6340         u8         syndrome[0x20];
6341
6342         u8         reserved_at_40[0x8];
6343         u8         dctn[0x18];
6344
6345         u8         reserved_at_60[0x20];
6346 };
6347
6348 struct mlx5_ifc_create_dct_in_bits {
6349         u8         opcode[0x10];
6350         u8         reserved_at_10[0x10];
6351
6352         u8         reserved_at_20[0x10];
6353         u8         op_mod[0x10];
6354
6355         u8         reserved_at_40[0x40];
6356
6357         struct mlx5_ifc_dctc_bits dct_context_entry;
6358
6359         u8         reserved_at_280[0x180];
6360 };
6361
6362 struct mlx5_ifc_create_cq_out_bits {
6363         u8         status[0x8];
6364         u8         reserved_at_8[0x18];
6365
6366         u8         syndrome[0x20];
6367
6368         u8         reserved_at_40[0x8];
6369         u8         cqn[0x18];
6370
6371         u8         reserved_at_60[0x20];
6372 };
6373
6374 struct mlx5_ifc_create_cq_in_bits {
6375         u8         opcode[0x10];
6376         u8         reserved_at_10[0x10];
6377
6378         u8         reserved_at_20[0x10];
6379         u8         op_mod[0x10];
6380
6381         u8         reserved_at_40[0x40];
6382
6383         struct mlx5_ifc_cqc_bits cq_context;
6384
6385         u8         reserved_at_280[0x600];
6386
6387         u8         pas[0][0x40];
6388 };
6389
6390 struct mlx5_ifc_config_int_moderation_out_bits {
6391         u8         status[0x8];
6392         u8         reserved_at_8[0x18];
6393
6394         u8         syndrome[0x20];
6395
6396         u8         reserved_at_40[0x4];
6397         u8         min_delay[0xc];
6398         u8         int_vector[0x10];
6399
6400         u8         reserved_at_60[0x20];
6401 };
6402
6403 enum {
6404         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
6405         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
6406 };
6407
6408 struct mlx5_ifc_config_int_moderation_in_bits {
6409         u8         opcode[0x10];
6410         u8         reserved_at_10[0x10];
6411
6412         u8         reserved_at_20[0x10];
6413         u8         op_mod[0x10];
6414
6415         u8         reserved_at_40[0x4];
6416         u8         min_delay[0xc];
6417         u8         int_vector[0x10];
6418
6419         u8         reserved_at_60[0x20];
6420 };
6421
6422 struct mlx5_ifc_attach_to_mcg_out_bits {
6423         u8         status[0x8];
6424         u8         reserved_at_8[0x18];
6425
6426         u8         syndrome[0x20];
6427
6428         u8         reserved_at_40[0x40];
6429 };
6430
6431 struct mlx5_ifc_attach_to_mcg_in_bits {
6432         u8         opcode[0x10];
6433         u8         reserved_at_10[0x10];
6434
6435         u8         reserved_at_20[0x10];
6436         u8         op_mod[0x10];
6437
6438         u8         reserved_at_40[0x8];
6439         u8         qpn[0x18];
6440
6441         u8         reserved_at_60[0x20];
6442
6443         u8         multicast_gid[16][0x8];
6444 };
6445
6446 struct mlx5_ifc_arm_xrq_out_bits {
6447         u8         status[0x8];
6448         u8         reserved_at_8[0x18];
6449
6450         u8         syndrome[0x20];
6451
6452         u8         reserved_at_40[0x40];
6453 };
6454
6455 struct mlx5_ifc_arm_xrq_in_bits {
6456         u8         opcode[0x10];
6457         u8         reserved_at_10[0x10];
6458
6459         u8         reserved_at_20[0x10];
6460         u8         op_mod[0x10];
6461
6462         u8         reserved_at_40[0x8];
6463         u8         xrqn[0x18];
6464
6465         u8         reserved_at_60[0x10];
6466         u8         lwm[0x10];
6467 };
6468
6469 struct mlx5_ifc_arm_xrc_srq_out_bits {
6470         u8         status[0x8];
6471         u8         reserved_at_8[0x18];
6472
6473         u8         syndrome[0x20];
6474
6475         u8         reserved_at_40[0x40];
6476 };
6477
6478 enum {
6479         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
6480 };
6481
6482 struct mlx5_ifc_arm_xrc_srq_in_bits {
6483         u8         opcode[0x10];
6484         u8         reserved_at_10[0x10];
6485
6486         u8         reserved_at_20[0x10];
6487         u8         op_mod[0x10];
6488
6489         u8         reserved_at_40[0x8];
6490         u8         xrc_srqn[0x18];
6491
6492         u8         reserved_at_60[0x10];
6493         u8         lwm[0x10];
6494 };
6495
6496 struct mlx5_ifc_arm_rq_out_bits {
6497         u8         status[0x8];
6498         u8         reserved_at_8[0x18];
6499
6500         u8         syndrome[0x20];
6501
6502         u8         reserved_at_40[0x40];
6503 };
6504
6505 enum {
6506         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6507         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6508 };
6509
6510 struct mlx5_ifc_arm_rq_in_bits {
6511         u8         opcode[0x10];
6512         u8         reserved_at_10[0x10];
6513
6514         u8         reserved_at_20[0x10];
6515         u8         op_mod[0x10];
6516
6517         u8         reserved_at_40[0x8];
6518         u8         srq_number[0x18];
6519
6520         u8         reserved_at_60[0x10];
6521         u8         lwm[0x10];
6522 };
6523
6524 struct mlx5_ifc_arm_dct_out_bits {
6525         u8         status[0x8];
6526         u8         reserved_at_8[0x18];
6527
6528         u8         syndrome[0x20];
6529
6530         u8         reserved_at_40[0x40];
6531 };
6532
6533 struct mlx5_ifc_arm_dct_in_bits {
6534         u8         opcode[0x10];
6535         u8         reserved_at_10[0x10];
6536
6537         u8         reserved_at_20[0x10];
6538         u8         op_mod[0x10];
6539
6540         u8         reserved_at_40[0x8];
6541         u8         dct_number[0x18];
6542
6543         u8         reserved_at_60[0x20];
6544 };
6545
6546 struct mlx5_ifc_alloc_xrcd_out_bits {
6547         u8         status[0x8];
6548         u8         reserved_at_8[0x18];
6549
6550         u8         syndrome[0x20];
6551
6552         u8         reserved_at_40[0x8];
6553         u8         xrcd[0x18];
6554
6555         u8         reserved_at_60[0x20];
6556 };
6557
6558 struct mlx5_ifc_alloc_xrcd_in_bits {
6559         u8         opcode[0x10];
6560         u8         reserved_at_10[0x10];
6561
6562         u8         reserved_at_20[0x10];
6563         u8         op_mod[0x10];
6564
6565         u8         reserved_at_40[0x40];
6566 };
6567
6568 struct mlx5_ifc_alloc_uar_out_bits {
6569         u8         status[0x8];
6570         u8         reserved_at_8[0x18];
6571
6572         u8         syndrome[0x20];
6573
6574         u8         reserved_at_40[0x8];
6575         u8         uar[0x18];
6576
6577         u8         reserved_at_60[0x20];
6578 };
6579
6580 struct mlx5_ifc_alloc_uar_in_bits {
6581         u8         opcode[0x10];
6582         u8         reserved_at_10[0x10];
6583
6584         u8         reserved_at_20[0x10];
6585         u8         op_mod[0x10];
6586
6587         u8         reserved_at_40[0x40];
6588 };
6589
6590 struct mlx5_ifc_alloc_transport_domain_out_bits {
6591         u8         status[0x8];
6592         u8         reserved_at_8[0x18];
6593
6594         u8         syndrome[0x20];
6595
6596         u8         reserved_at_40[0x8];
6597         u8         transport_domain[0x18];
6598
6599         u8         reserved_at_60[0x20];
6600 };
6601
6602 struct mlx5_ifc_alloc_transport_domain_in_bits {
6603         u8         opcode[0x10];
6604         u8         reserved_at_10[0x10];
6605
6606         u8         reserved_at_20[0x10];
6607         u8         op_mod[0x10];
6608
6609         u8         reserved_at_40[0x40];
6610 };
6611
6612 struct mlx5_ifc_alloc_q_counter_out_bits {
6613         u8         status[0x8];
6614         u8         reserved_at_8[0x18];
6615
6616         u8         syndrome[0x20];
6617
6618         u8         reserved_at_40[0x18];
6619         u8         counter_set_id[0x8];
6620
6621         u8         reserved_at_60[0x20];
6622 };
6623
6624 struct mlx5_ifc_alloc_q_counter_in_bits {
6625         u8         opcode[0x10];
6626         u8         reserved_at_10[0x10];
6627
6628         u8         reserved_at_20[0x10];
6629         u8         op_mod[0x10];
6630
6631         u8         reserved_at_40[0x40];
6632 };
6633
6634 struct mlx5_ifc_alloc_pd_out_bits {
6635         u8         status[0x8];
6636         u8         reserved_at_8[0x18];
6637
6638         u8         syndrome[0x20];
6639
6640         u8         reserved_at_40[0x8];
6641         u8         pd[0x18];
6642
6643         u8         reserved_at_60[0x20];
6644 };
6645
6646 struct mlx5_ifc_alloc_pd_in_bits {
6647         u8         opcode[0x10];
6648         u8         reserved_at_10[0x10];
6649
6650         u8         reserved_at_20[0x10];
6651         u8         op_mod[0x10];
6652
6653         u8         reserved_at_40[0x40];
6654 };
6655
6656 struct mlx5_ifc_alloc_flow_counter_out_bits {
6657         u8         status[0x8];
6658         u8         reserved_at_8[0x18];
6659
6660         u8         syndrome[0x20];
6661
6662         u8         reserved_at_40[0x10];
6663         u8         flow_counter_id[0x10];
6664
6665         u8         reserved_at_60[0x20];
6666 };
6667
6668 struct mlx5_ifc_alloc_flow_counter_in_bits {
6669         u8         opcode[0x10];
6670         u8         reserved_at_10[0x10];
6671
6672         u8         reserved_at_20[0x10];
6673         u8         op_mod[0x10];
6674
6675         u8         reserved_at_40[0x40];
6676 };
6677
6678 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6679         u8         status[0x8];
6680         u8         reserved_at_8[0x18];
6681
6682         u8         syndrome[0x20];
6683
6684         u8         reserved_at_40[0x40];
6685 };
6686
6687 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6688         u8         opcode[0x10];
6689         u8         reserved_at_10[0x10];
6690
6691         u8         reserved_at_20[0x10];
6692         u8         op_mod[0x10];
6693
6694         u8         reserved_at_40[0x20];
6695
6696         u8         reserved_at_60[0x10];
6697         u8         vxlan_udp_port[0x10];
6698 };
6699
6700 struct mlx5_ifc_set_pp_rate_limit_out_bits {
6701         u8         status[0x8];
6702         u8         reserved_at_8[0x18];
6703
6704         u8         syndrome[0x20];
6705
6706         u8         reserved_at_40[0x40];
6707 };
6708
6709 struct mlx5_ifc_set_pp_rate_limit_in_bits {
6710         u8         opcode[0x10];
6711         u8         reserved_at_10[0x10];
6712
6713         u8         reserved_at_20[0x10];
6714         u8         op_mod[0x10];
6715
6716         u8         reserved_at_40[0x10];
6717         u8         rate_limit_index[0x10];
6718
6719         u8         reserved_at_60[0x20];
6720
6721         u8         rate_limit[0x20];
6722
6723         u8         reserved_at_a0[0x160];
6724 };
6725
6726 struct mlx5_ifc_access_register_out_bits {
6727         u8         status[0x8];
6728         u8         reserved_at_8[0x18];
6729
6730         u8         syndrome[0x20];
6731
6732         u8         reserved_at_40[0x40];
6733
6734         u8         register_data[0][0x20];
6735 };
6736
6737 enum {
6738         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
6739         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
6740 };
6741
6742 struct mlx5_ifc_access_register_in_bits {
6743         u8         opcode[0x10];
6744         u8         reserved_at_10[0x10];
6745
6746         u8         reserved_at_20[0x10];
6747         u8         op_mod[0x10];
6748
6749         u8         reserved_at_40[0x10];
6750         u8         register_id[0x10];
6751
6752         u8         argument[0x20];
6753
6754         u8         register_data[0][0x20];
6755 };
6756
6757 struct mlx5_ifc_sltp_reg_bits {
6758         u8         status[0x4];
6759         u8         version[0x4];
6760         u8         local_port[0x8];
6761         u8         pnat[0x2];
6762         u8         reserved_at_12[0x2];
6763         u8         lane[0x4];
6764         u8         reserved_at_18[0x8];
6765
6766         u8         reserved_at_20[0x20];
6767
6768         u8         reserved_at_40[0x7];
6769         u8         polarity[0x1];
6770         u8         ob_tap0[0x8];
6771         u8         ob_tap1[0x8];
6772         u8         ob_tap2[0x8];
6773
6774         u8         reserved_at_60[0xc];
6775         u8         ob_preemp_mode[0x4];
6776         u8         ob_reg[0x8];
6777         u8         ob_bias[0x8];
6778
6779         u8         reserved_at_80[0x20];
6780 };
6781
6782 struct mlx5_ifc_slrg_reg_bits {
6783         u8         status[0x4];
6784         u8         version[0x4];
6785         u8         local_port[0x8];
6786         u8         pnat[0x2];
6787         u8         reserved_at_12[0x2];
6788         u8         lane[0x4];
6789         u8         reserved_at_18[0x8];
6790
6791         u8         time_to_link_up[0x10];
6792         u8         reserved_at_30[0xc];
6793         u8         grade_lane_speed[0x4];
6794
6795         u8         grade_version[0x8];
6796         u8         grade[0x18];
6797
6798         u8         reserved_at_60[0x4];
6799         u8         height_grade_type[0x4];
6800         u8         height_grade[0x18];
6801
6802         u8         height_dz[0x10];
6803         u8         height_dv[0x10];
6804
6805         u8         reserved_at_a0[0x10];
6806         u8         height_sigma[0x10];
6807
6808         u8         reserved_at_c0[0x20];
6809
6810         u8         reserved_at_e0[0x4];
6811         u8         phase_grade_type[0x4];
6812         u8         phase_grade[0x18];
6813
6814         u8         reserved_at_100[0x8];
6815         u8         phase_eo_pos[0x8];
6816         u8         reserved_at_110[0x8];
6817         u8         phase_eo_neg[0x8];
6818
6819         u8         ffe_set_tested[0x10];
6820         u8         test_errors_per_lane[0x10];
6821 };
6822
6823 struct mlx5_ifc_pvlc_reg_bits {
6824         u8         reserved_at_0[0x8];
6825         u8         local_port[0x8];
6826         u8         reserved_at_10[0x10];
6827
6828         u8         reserved_at_20[0x1c];
6829         u8         vl_hw_cap[0x4];
6830
6831         u8         reserved_at_40[0x1c];
6832         u8         vl_admin[0x4];
6833
6834         u8         reserved_at_60[0x1c];
6835         u8         vl_operational[0x4];
6836 };
6837
6838 struct mlx5_ifc_pude_reg_bits {
6839         u8         swid[0x8];
6840         u8         local_port[0x8];
6841         u8         reserved_at_10[0x4];
6842         u8         admin_status[0x4];
6843         u8         reserved_at_18[0x4];
6844         u8         oper_status[0x4];
6845
6846         u8         reserved_at_20[0x60];
6847 };
6848
6849 struct mlx5_ifc_ptys_reg_bits {
6850         u8         reserved_at_0[0x1];
6851         u8         an_disable_admin[0x1];
6852         u8         an_disable_cap[0x1];
6853         u8         reserved_at_3[0x5];
6854         u8         local_port[0x8];
6855         u8         reserved_at_10[0xd];
6856         u8         proto_mask[0x3];
6857
6858         u8         an_status[0x4];
6859         u8         reserved_at_24[0x3c];
6860
6861         u8         eth_proto_capability[0x20];
6862
6863         u8         ib_link_width_capability[0x10];
6864         u8         ib_proto_capability[0x10];
6865
6866         u8         reserved_at_a0[0x20];
6867
6868         u8         eth_proto_admin[0x20];
6869
6870         u8         ib_link_width_admin[0x10];
6871         u8         ib_proto_admin[0x10];
6872
6873         u8         reserved_at_100[0x20];
6874
6875         u8         eth_proto_oper[0x20];
6876
6877         u8         ib_link_width_oper[0x10];
6878         u8         ib_proto_oper[0x10];
6879
6880         u8         reserved_at_160[0x20];
6881
6882         u8         eth_proto_lp_advertise[0x20];
6883
6884         u8         reserved_at_1a0[0x60];
6885 };
6886
6887 struct mlx5_ifc_mlcr_reg_bits {
6888         u8         reserved_at_0[0x8];
6889         u8         local_port[0x8];
6890         u8         reserved_at_10[0x20];
6891
6892         u8         beacon_duration[0x10];
6893         u8         reserved_at_40[0x10];
6894
6895         u8         beacon_remain[0x10];
6896 };
6897
6898 struct mlx5_ifc_ptas_reg_bits {
6899         u8         reserved_at_0[0x20];
6900
6901         u8         algorithm_options[0x10];
6902         u8         reserved_at_30[0x4];
6903         u8         repetitions_mode[0x4];
6904         u8         num_of_repetitions[0x8];
6905
6906         u8         grade_version[0x8];
6907         u8         height_grade_type[0x4];
6908         u8         phase_grade_type[0x4];
6909         u8         height_grade_weight[0x8];
6910         u8         phase_grade_weight[0x8];
6911
6912         u8         gisim_measure_bits[0x10];
6913         u8         adaptive_tap_measure_bits[0x10];
6914
6915         u8         ber_bath_high_error_threshold[0x10];
6916         u8         ber_bath_mid_error_threshold[0x10];
6917
6918         u8         ber_bath_low_error_threshold[0x10];
6919         u8         one_ratio_high_threshold[0x10];
6920
6921         u8         one_ratio_high_mid_threshold[0x10];
6922         u8         one_ratio_low_mid_threshold[0x10];
6923
6924         u8         one_ratio_low_threshold[0x10];
6925         u8         ndeo_error_threshold[0x10];
6926
6927         u8         mixer_offset_step_size[0x10];
6928         u8         reserved_at_110[0x8];
6929         u8         mix90_phase_for_voltage_bath[0x8];
6930
6931         u8         mixer_offset_start[0x10];
6932         u8         mixer_offset_end[0x10];
6933
6934         u8         reserved_at_140[0x15];
6935         u8         ber_test_time[0xb];
6936 };
6937
6938 struct mlx5_ifc_pspa_reg_bits {
6939         u8         swid[0x8];
6940         u8         local_port[0x8];
6941         u8         sub_port[0x8];
6942         u8         reserved_at_18[0x8];
6943
6944         u8         reserved_at_20[0x20];
6945 };
6946
6947 struct mlx5_ifc_pqdr_reg_bits {
6948         u8         reserved_at_0[0x8];
6949         u8         local_port[0x8];
6950         u8         reserved_at_10[0x5];
6951         u8         prio[0x3];
6952         u8         reserved_at_18[0x6];
6953         u8         mode[0x2];
6954
6955         u8         reserved_at_20[0x20];
6956
6957         u8         reserved_at_40[0x10];
6958         u8         min_threshold[0x10];
6959
6960         u8         reserved_at_60[0x10];
6961         u8         max_threshold[0x10];
6962
6963         u8         reserved_at_80[0x10];
6964         u8         mark_probability_denominator[0x10];
6965
6966         u8         reserved_at_a0[0x60];
6967 };
6968
6969 struct mlx5_ifc_ppsc_reg_bits {
6970         u8         reserved_at_0[0x8];
6971         u8         local_port[0x8];
6972         u8         reserved_at_10[0x10];
6973
6974         u8         reserved_at_20[0x60];
6975
6976         u8         reserved_at_80[0x1c];
6977         u8         wrps_admin[0x4];
6978
6979         u8         reserved_at_a0[0x1c];
6980         u8         wrps_status[0x4];
6981
6982         u8         reserved_at_c0[0x8];
6983         u8         up_threshold[0x8];
6984         u8         reserved_at_d0[0x8];
6985         u8         down_threshold[0x8];
6986
6987         u8         reserved_at_e0[0x20];
6988
6989         u8         reserved_at_100[0x1c];
6990         u8         srps_admin[0x4];
6991
6992         u8         reserved_at_120[0x1c];
6993         u8         srps_status[0x4];
6994
6995         u8         reserved_at_140[0x40];
6996 };
6997
6998 struct mlx5_ifc_pplr_reg_bits {
6999         u8         reserved_at_0[0x8];
7000         u8         local_port[0x8];
7001         u8         reserved_at_10[0x10];
7002
7003         u8         reserved_at_20[0x8];
7004         u8         lb_cap[0x8];
7005         u8         reserved_at_30[0x8];
7006         u8         lb_en[0x8];
7007 };
7008
7009 struct mlx5_ifc_pplm_reg_bits {
7010         u8         reserved_at_0[0x8];
7011         u8         local_port[0x8];
7012         u8         reserved_at_10[0x10];
7013
7014         u8         reserved_at_20[0x20];
7015
7016         u8         port_profile_mode[0x8];
7017         u8         static_port_profile[0x8];
7018         u8         active_port_profile[0x8];
7019         u8         reserved_at_58[0x8];
7020
7021         u8         retransmission_active[0x8];
7022         u8         fec_mode_active[0x18];
7023
7024         u8         reserved_at_80[0x20];
7025 };
7026
7027 struct mlx5_ifc_ppcnt_reg_bits {
7028         u8         swid[0x8];
7029         u8         local_port[0x8];
7030         u8         pnat[0x2];
7031         u8         reserved_at_12[0x8];
7032         u8         grp[0x6];
7033
7034         u8         clr[0x1];
7035         u8         reserved_at_21[0x1c];
7036         u8         prio_tc[0x3];
7037
7038         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7039 };
7040
7041 struct mlx5_ifc_ppad_reg_bits {
7042         u8         reserved_at_0[0x3];
7043         u8         single_mac[0x1];
7044         u8         reserved_at_4[0x4];
7045         u8         local_port[0x8];
7046         u8         mac_47_32[0x10];
7047
7048         u8         mac_31_0[0x20];
7049
7050         u8         reserved_at_40[0x40];
7051 };
7052
7053 struct mlx5_ifc_pmtu_reg_bits {
7054         u8         reserved_at_0[0x8];
7055         u8         local_port[0x8];
7056         u8         reserved_at_10[0x10];
7057
7058         u8         max_mtu[0x10];
7059         u8         reserved_at_30[0x10];
7060
7061         u8         admin_mtu[0x10];
7062         u8         reserved_at_50[0x10];
7063
7064         u8         oper_mtu[0x10];
7065         u8         reserved_at_70[0x10];
7066 };
7067
7068 struct mlx5_ifc_pmpr_reg_bits {
7069         u8         reserved_at_0[0x8];
7070         u8         module[0x8];
7071         u8         reserved_at_10[0x10];
7072
7073         u8         reserved_at_20[0x18];
7074         u8         attenuation_5g[0x8];
7075
7076         u8         reserved_at_40[0x18];
7077         u8         attenuation_7g[0x8];
7078
7079         u8         reserved_at_60[0x18];
7080         u8         attenuation_12g[0x8];
7081 };
7082
7083 struct mlx5_ifc_pmpe_reg_bits {
7084         u8         reserved_at_0[0x8];
7085         u8         module[0x8];
7086         u8         reserved_at_10[0xc];
7087         u8         module_status[0x4];
7088
7089         u8         reserved_at_20[0x60];
7090 };
7091
7092 struct mlx5_ifc_pmpc_reg_bits {
7093         u8         module_state_updated[32][0x8];
7094 };
7095
7096 struct mlx5_ifc_pmlpn_reg_bits {
7097         u8         reserved_at_0[0x4];
7098         u8         mlpn_status[0x4];
7099         u8         local_port[0x8];
7100         u8         reserved_at_10[0x10];
7101
7102         u8         e[0x1];
7103         u8         reserved_at_21[0x1f];
7104 };
7105
7106 struct mlx5_ifc_pmlp_reg_bits {
7107         u8         rxtx[0x1];
7108         u8         reserved_at_1[0x7];
7109         u8         local_port[0x8];
7110         u8         reserved_at_10[0x8];
7111         u8         width[0x8];
7112
7113         u8         lane0_module_mapping[0x20];
7114
7115         u8         lane1_module_mapping[0x20];
7116
7117         u8         lane2_module_mapping[0x20];
7118
7119         u8         lane3_module_mapping[0x20];
7120
7121         u8         reserved_at_a0[0x160];
7122 };
7123
7124 struct mlx5_ifc_pmaos_reg_bits {
7125         u8         reserved_at_0[0x8];
7126         u8         module[0x8];
7127         u8         reserved_at_10[0x4];
7128         u8         admin_status[0x4];
7129         u8         reserved_at_18[0x4];
7130         u8         oper_status[0x4];
7131
7132         u8         ase[0x1];
7133         u8         ee[0x1];
7134         u8         reserved_at_22[0x1c];
7135         u8         e[0x2];
7136
7137         u8         reserved_at_40[0x40];
7138 };
7139
7140 struct mlx5_ifc_plpc_reg_bits {
7141         u8         reserved_at_0[0x4];
7142         u8         profile_id[0xc];
7143         u8         reserved_at_10[0x4];
7144         u8         proto_mask[0x4];
7145         u8         reserved_at_18[0x8];
7146
7147         u8         reserved_at_20[0x10];
7148         u8         lane_speed[0x10];
7149
7150         u8         reserved_at_40[0x17];
7151         u8         lpbf[0x1];
7152         u8         fec_mode_policy[0x8];
7153
7154         u8         retransmission_capability[0x8];
7155         u8         fec_mode_capability[0x18];
7156
7157         u8         retransmission_support_admin[0x8];
7158         u8         fec_mode_support_admin[0x18];
7159
7160         u8         retransmission_request_admin[0x8];
7161         u8         fec_mode_request_admin[0x18];
7162
7163         u8         reserved_at_c0[0x80];
7164 };
7165
7166 struct mlx5_ifc_plib_reg_bits {
7167         u8         reserved_at_0[0x8];
7168         u8         local_port[0x8];
7169         u8         reserved_at_10[0x8];
7170         u8         ib_port[0x8];
7171
7172         u8         reserved_at_20[0x60];
7173 };
7174
7175 struct mlx5_ifc_plbf_reg_bits {
7176         u8         reserved_at_0[0x8];
7177         u8         local_port[0x8];
7178         u8         reserved_at_10[0xd];
7179         u8         lbf_mode[0x3];
7180
7181         u8         reserved_at_20[0x20];
7182 };
7183
7184 struct mlx5_ifc_pipg_reg_bits {
7185         u8         reserved_at_0[0x8];
7186         u8         local_port[0x8];
7187         u8         reserved_at_10[0x10];
7188
7189         u8         dic[0x1];
7190         u8         reserved_at_21[0x19];
7191         u8         ipg[0x4];
7192         u8         reserved_at_3e[0x2];
7193 };
7194
7195 struct mlx5_ifc_pifr_reg_bits {
7196         u8         reserved_at_0[0x8];
7197         u8         local_port[0x8];
7198         u8         reserved_at_10[0x10];
7199
7200         u8         reserved_at_20[0xe0];
7201
7202         u8         port_filter[8][0x20];
7203
7204         u8         port_filter_update_en[8][0x20];
7205 };
7206
7207 struct mlx5_ifc_pfcc_reg_bits {
7208         u8         reserved_at_0[0x8];
7209         u8         local_port[0x8];
7210         u8         reserved_at_10[0x10];
7211
7212         u8         ppan[0x4];
7213         u8         reserved_at_24[0x4];
7214         u8         prio_mask_tx[0x8];
7215         u8         reserved_at_30[0x8];
7216         u8         prio_mask_rx[0x8];
7217
7218         u8         pptx[0x1];
7219         u8         aptx[0x1];
7220         u8         reserved_at_42[0x6];
7221         u8         pfctx[0x8];
7222         u8         reserved_at_50[0x10];
7223
7224         u8         pprx[0x1];
7225         u8         aprx[0x1];
7226         u8         reserved_at_62[0x6];
7227         u8         pfcrx[0x8];
7228         u8         reserved_at_70[0x10];
7229
7230         u8         reserved_at_80[0x80];
7231 };
7232
7233 struct mlx5_ifc_pelc_reg_bits {
7234         u8         op[0x4];
7235         u8         reserved_at_4[0x4];
7236         u8         local_port[0x8];
7237         u8         reserved_at_10[0x10];
7238
7239         u8         op_admin[0x8];
7240         u8         op_capability[0x8];
7241         u8         op_request[0x8];
7242         u8         op_active[0x8];
7243
7244         u8         admin[0x40];
7245
7246         u8         capability[0x40];
7247
7248         u8         request[0x40];
7249
7250         u8         active[0x40];
7251
7252         u8         reserved_at_140[0x80];
7253 };
7254
7255 struct mlx5_ifc_peir_reg_bits {
7256         u8         reserved_at_0[0x8];
7257         u8         local_port[0x8];
7258         u8         reserved_at_10[0x10];
7259
7260         u8         reserved_at_20[0xc];
7261         u8         error_count[0x4];
7262         u8         reserved_at_30[0x10];
7263
7264         u8         reserved_at_40[0xc];
7265         u8         lane[0x4];
7266         u8         reserved_at_50[0x8];
7267         u8         error_type[0x8];
7268 };
7269
7270 struct mlx5_ifc_pcap_reg_bits {
7271         u8         reserved_at_0[0x8];
7272         u8         local_port[0x8];
7273         u8         reserved_at_10[0x10];
7274
7275         u8         port_capability_mask[4][0x20];
7276 };
7277
7278 struct mlx5_ifc_paos_reg_bits {
7279         u8         swid[0x8];
7280         u8         local_port[0x8];
7281         u8         reserved_at_10[0x4];
7282         u8         admin_status[0x4];
7283         u8         reserved_at_18[0x4];
7284         u8         oper_status[0x4];
7285
7286         u8         ase[0x1];
7287         u8         ee[0x1];
7288         u8         reserved_at_22[0x1c];
7289         u8         e[0x2];
7290
7291         u8         reserved_at_40[0x40];
7292 };
7293
7294 struct mlx5_ifc_pamp_reg_bits {
7295         u8         reserved_at_0[0x8];
7296         u8         opamp_group[0x8];
7297         u8         reserved_at_10[0xc];
7298         u8         opamp_group_type[0x4];
7299
7300         u8         start_index[0x10];
7301         u8         reserved_at_30[0x4];
7302         u8         num_of_indices[0xc];
7303
7304         u8         index_data[18][0x10];
7305 };
7306
7307 struct mlx5_ifc_pcmr_reg_bits {
7308         u8         reserved_at_0[0x8];
7309         u8         local_port[0x8];
7310         u8         reserved_at_10[0x2e];
7311         u8         fcs_cap[0x1];
7312         u8         reserved_at_3f[0x1f];
7313         u8         fcs_chk[0x1];
7314         u8         reserved_at_5f[0x1];
7315 };
7316
7317 struct mlx5_ifc_lane_2_module_mapping_bits {
7318         u8         reserved_at_0[0x6];
7319         u8         rx_lane[0x2];
7320         u8         reserved_at_8[0x6];
7321         u8         tx_lane[0x2];
7322         u8         reserved_at_10[0x8];
7323         u8         module[0x8];
7324 };
7325
7326 struct mlx5_ifc_bufferx_reg_bits {
7327         u8         reserved_at_0[0x6];
7328         u8         lossy[0x1];
7329         u8         epsb[0x1];
7330         u8         reserved_at_8[0x8];
7331         u8         size[0x10];
7332
7333         u8         xoff_threshold[0x10];
7334         u8         xon_threshold[0x10];
7335 };
7336
7337 struct mlx5_ifc_set_node_in_bits {
7338         u8         node_description[64][0x8];
7339 };
7340
7341 struct mlx5_ifc_register_power_settings_bits {
7342         u8         reserved_at_0[0x18];
7343         u8         power_settings_level[0x8];
7344
7345         u8         reserved_at_20[0x60];
7346 };
7347
7348 struct mlx5_ifc_register_host_endianness_bits {
7349         u8         he[0x1];
7350         u8         reserved_at_1[0x1f];
7351
7352         u8         reserved_at_20[0x60];
7353 };
7354
7355 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7356         u8         reserved_at_0[0x20];
7357
7358         u8         mkey[0x20];
7359
7360         u8         addressh_63_32[0x20];
7361
7362         u8         addressl_31_0[0x20];
7363 };
7364
7365 struct mlx5_ifc_ud_adrs_vector_bits {
7366         u8         dc_key[0x40];
7367
7368         u8         ext[0x1];
7369         u8         reserved_at_41[0x7];
7370         u8         destination_qp_dct[0x18];
7371
7372         u8         static_rate[0x4];
7373         u8         sl_eth_prio[0x4];
7374         u8         fl[0x1];
7375         u8         mlid[0x7];
7376         u8         rlid_udp_sport[0x10];
7377
7378         u8         reserved_at_80[0x20];
7379
7380         u8         rmac_47_16[0x20];
7381
7382         u8         rmac_15_0[0x10];
7383         u8         tclass[0x8];
7384         u8         hop_limit[0x8];
7385
7386         u8         reserved_at_e0[0x1];
7387         u8         grh[0x1];
7388         u8         reserved_at_e2[0x2];
7389         u8         src_addr_index[0x8];
7390         u8         flow_label[0x14];
7391
7392         u8         rgid_rip[16][0x8];
7393 };
7394
7395 struct mlx5_ifc_pages_req_event_bits {
7396         u8         reserved_at_0[0x10];
7397         u8         function_id[0x10];
7398
7399         u8         num_pages[0x20];
7400
7401         u8         reserved_at_40[0xa0];
7402 };
7403
7404 struct mlx5_ifc_eqe_bits {
7405         u8         reserved_at_0[0x8];
7406         u8         event_type[0x8];
7407         u8         reserved_at_10[0x8];
7408         u8         event_sub_type[0x8];
7409
7410         u8         reserved_at_20[0xe0];
7411
7412         union mlx5_ifc_event_auto_bits event_data;
7413
7414         u8         reserved_at_1e0[0x10];
7415         u8         signature[0x8];
7416         u8         reserved_at_1f8[0x7];
7417         u8         owner[0x1];
7418 };
7419
7420 enum {
7421         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
7422 };
7423
7424 struct mlx5_ifc_cmd_queue_entry_bits {
7425         u8         type[0x8];
7426         u8         reserved_at_8[0x18];
7427
7428         u8         input_length[0x20];
7429
7430         u8         input_mailbox_pointer_63_32[0x20];
7431
7432         u8         input_mailbox_pointer_31_9[0x17];
7433         u8         reserved_at_77[0x9];
7434
7435         u8         command_input_inline_data[16][0x8];
7436
7437         u8         command_output_inline_data[16][0x8];
7438
7439         u8         output_mailbox_pointer_63_32[0x20];
7440
7441         u8         output_mailbox_pointer_31_9[0x17];
7442         u8         reserved_at_1b7[0x9];
7443
7444         u8         output_length[0x20];
7445
7446         u8         token[0x8];
7447         u8         signature[0x8];
7448         u8         reserved_at_1f0[0x8];
7449         u8         status[0x7];
7450         u8         ownership[0x1];
7451 };
7452
7453 struct mlx5_ifc_cmd_out_bits {
7454         u8         status[0x8];
7455         u8         reserved_at_8[0x18];
7456
7457         u8         syndrome[0x20];
7458
7459         u8         command_output[0x20];
7460 };
7461
7462 struct mlx5_ifc_cmd_in_bits {
7463         u8         opcode[0x10];
7464         u8         reserved_at_10[0x10];
7465
7466         u8         reserved_at_20[0x10];
7467         u8         op_mod[0x10];
7468
7469         u8         command[0][0x20];
7470 };
7471
7472 struct mlx5_ifc_cmd_if_box_bits {
7473         u8         mailbox_data[512][0x8];
7474
7475         u8         reserved_at_1000[0x180];
7476
7477         u8         next_pointer_63_32[0x20];
7478
7479         u8         next_pointer_31_10[0x16];
7480         u8         reserved_at_11b6[0xa];
7481
7482         u8         block_number[0x20];
7483
7484         u8         reserved_at_11e0[0x8];
7485         u8         token[0x8];
7486         u8         ctrl_signature[0x8];
7487         u8         signature[0x8];
7488 };
7489
7490 struct mlx5_ifc_mtt_bits {
7491         u8         ptag_63_32[0x20];
7492
7493         u8         ptag_31_8[0x18];
7494         u8         reserved_at_38[0x6];
7495         u8         wr_en[0x1];
7496         u8         rd_en[0x1];
7497 };
7498
7499 struct mlx5_ifc_query_wol_rol_out_bits {
7500         u8         status[0x8];
7501         u8         reserved_at_8[0x18];
7502
7503         u8         syndrome[0x20];
7504
7505         u8         reserved_at_40[0x10];
7506         u8         rol_mode[0x8];
7507         u8         wol_mode[0x8];
7508
7509         u8         reserved_at_60[0x20];
7510 };
7511
7512 struct mlx5_ifc_query_wol_rol_in_bits {
7513         u8         opcode[0x10];
7514         u8         reserved_at_10[0x10];
7515
7516         u8         reserved_at_20[0x10];
7517         u8         op_mod[0x10];
7518
7519         u8         reserved_at_40[0x40];
7520 };
7521
7522 struct mlx5_ifc_set_wol_rol_out_bits {
7523         u8         status[0x8];
7524         u8         reserved_at_8[0x18];
7525
7526         u8         syndrome[0x20];
7527
7528         u8         reserved_at_40[0x40];
7529 };
7530
7531 struct mlx5_ifc_set_wol_rol_in_bits {
7532         u8         opcode[0x10];
7533         u8         reserved_at_10[0x10];
7534
7535         u8         reserved_at_20[0x10];
7536         u8         op_mod[0x10];
7537
7538         u8         rol_mode_valid[0x1];
7539         u8         wol_mode_valid[0x1];
7540         u8         reserved_at_42[0xe];
7541         u8         rol_mode[0x8];
7542         u8         wol_mode[0x8];
7543
7544         u8         reserved_at_60[0x20];
7545 };
7546
7547 enum {
7548         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
7549         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
7550         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
7551 };
7552
7553 enum {
7554         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
7555         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
7556         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
7557 };
7558
7559 enum {
7560         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
7561         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
7562         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
7563         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
7564         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
7565         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
7566         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
7567         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
7568         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
7569         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
7570         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
7571 };
7572
7573 struct mlx5_ifc_initial_seg_bits {
7574         u8         fw_rev_minor[0x10];
7575         u8         fw_rev_major[0x10];
7576
7577         u8         cmd_interface_rev[0x10];
7578         u8         fw_rev_subminor[0x10];
7579
7580         u8         reserved_at_40[0x40];
7581
7582         u8         cmdq_phy_addr_63_32[0x20];
7583
7584         u8         cmdq_phy_addr_31_12[0x14];
7585         u8         reserved_at_b4[0x2];
7586         u8         nic_interface[0x2];
7587         u8         log_cmdq_size[0x4];
7588         u8         log_cmdq_stride[0x4];
7589
7590         u8         command_doorbell_vector[0x20];
7591
7592         u8         reserved_at_e0[0xf00];
7593
7594         u8         initializing[0x1];
7595         u8         reserved_at_fe1[0x4];
7596         u8         nic_interface_supported[0x3];
7597         u8         reserved_at_fe8[0x18];
7598
7599         struct mlx5_ifc_health_buffer_bits health_buffer;
7600
7601         u8         no_dram_nic_offset[0x20];
7602
7603         u8         reserved_at_1220[0x6e40];
7604
7605         u8         reserved_at_8060[0x1f];
7606         u8         clear_int[0x1];
7607
7608         u8         health_syndrome[0x8];
7609         u8         health_counter[0x18];
7610
7611         u8         reserved_at_80a0[0x17fc0];
7612 };
7613
7614 union mlx5_ifc_ports_control_registers_document_bits {
7615         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7616         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7617         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7618         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7619         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7620         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7621         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7622         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7623         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7624         struct mlx5_ifc_pamp_reg_bits pamp_reg;
7625         struct mlx5_ifc_paos_reg_bits paos_reg;
7626         struct mlx5_ifc_pcap_reg_bits pcap_reg;
7627         struct mlx5_ifc_peir_reg_bits peir_reg;
7628         struct mlx5_ifc_pelc_reg_bits pelc_reg;
7629         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
7630         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
7631         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7632         struct mlx5_ifc_pifr_reg_bits pifr_reg;
7633         struct mlx5_ifc_pipg_reg_bits pipg_reg;
7634         struct mlx5_ifc_plbf_reg_bits plbf_reg;
7635         struct mlx5_ifc_plib_reg_bits plib_reg;
7636         struct mlx5_ifc_plpc_reg_bits plpc_reg;
7637         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7638         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7639         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7640         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7641         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7642         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7643         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7644         struct mlx5_ifc_ppad_reg_bits ppad_reg;
7645         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7646         struct mlx5_ifc_pplm_reg_bits pplm_reg;
7647         struct mlx5_ifc_pplr_reg_bits pplr_reg;
7648         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7649         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7650         struct mlx5_ifc_pspa_reg_bits pspa_reg;
7651         struct mlx5_ifc_ptas_reg_bits ptas_reg;
7652         struct mlx5_ifc_ptys_reg_bits ptys_reg;
7653         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
7654         struct mlx5_ifc_pude_reg_bits pude_reg;
7655         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7656         struct mlx5_ifc_slrg_reg_bits slrg_reg;
7657         struct mlx5_ifc_sltp_reg_bits sltp_reg;
7658         u8         reserved_at_0[0x60e0];
7659 };
7660
7661 union mlx5_ifc_debug_enhancements_document_bits {
7662         struct mlx5_ifc_health_buffer_bits health_buffer;
7663         u8         reserved_at_0[0x200];
7664 };
7665
7666 union mlx5_ifc_uplink_pci_interface_document_bits {
7667         struct mlx5_ifc_initial_seg_bits initial_seg;
7668         u8         reserved_at_0[0x20060];
7669 };
7670
7671 struct mlx5_ifc_set_flow_table_root_out_bits {
7672         u8         status[0x8];
7673         u8         reserved_at_8[0x18];
7674
7675         u8         syndrome[0x20];
7676
7677         u8         reserved_at_40[0x40];
7678 };
7679
7680 struct mlx5_ifc_set_flow_table_root_in_bits {
7681         u8         opcode[0x10];
7682         u8         reserved_at_10[0x10];
7683
7684         u8         reserved_at_20[0x10];
7685         u8         op_mod[0x10];
7686
7687         u8         other_vport[0x1];
7688         u8         reserved_at_41[0xf];
7689         u8         vport_number[0x10];
7690
7691         u8         reserved_at_60[0x20];
7692
7693         u8         table_type[0x8];
7694         u8         reserved_at_88[0x18];
7695
7696         u8         reserved_at_a0[0x8];
7697         u8         table_id[0x18];
7698
7699         u8         reserved_at_c0[0x140];
7700 };
7701
7702 enum {
7703         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
7704         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
7705 };
7706
7707 struct mlx5_ifc_modify_flow_table_out_bits {
7708         u8         status[0x8];
7709         u8         reserved_at_8[0x18];
7710
7711         u8         syndrome[0x20];
7712
7713         u8         reserved_at_40[0x40];
7714 };
7715
7716 struct mlx5_ifc_modify_flow_table_in_bits {
7717         u8         opcode[0x10];
7718         u8         reserved_at_10[0x10];
7719
7720         u8         reserved_at_20[0x10];
7721         u8         op_mod[0x10];
7722
7723         u8         other_vport[0x1];
7724         u8         reserved_at_41[0xf];
7725         u8         vport_number[0x10];
7726
7727         u8         reserved_at_60[0x10];
7728         u8         modify_field_select[0x10];
7729
7730         u8         table_type[0x8];
7731         u8         reserved_at_88[0x18];
7732
7733         u8         reserved_at_a0[0x8];
7734         u8         table_id[0x18];
7735
7736         u8         reserved_at_c0[0x4];
7737         u8         table_miss_mode[0x4];
7738         u8         reserved_at_c8[0x18];
7739
7740         u8         reserved_at_e0[0x8];
7741         u8         table_miss_id[0x18];
7742
7743         u8         reserved_at_100[0x8];
7744         u8         lag_master_next_table_id[0x18];
7745
7746         u8         reserved_at_120[0x80];
7747 };
7748
7749 struct mlx5_ifc_ets_tcn_config_reg_bits {
7750         u8         g[0x1];
7751         u8         b[0x1];
7752         u8         r[0x1];
7753         u8         reserved_at_3[0x9];
7754         u8         group[0x4];
7755         u8         reserved_at_10[0x9];
7756         u8         bw_allocation[0x7];
7757
7758         u8         reserved_at_20[0xc];
7759         u8         max_bw_units[0x4];
7760         u8         reserved_at_30[0x8];
7761         u8         max_bw_value[0x8];
7762 };
7763
7764 struct mlx5_ifc_ets_global_config_reg_bits {
7765         u8         reserved_at_0[0x2];
7766         u8         r[0x1];
7767         u8         reserved_at_3[0x1d];
7768
7769         u8         reserved_at_20[0xc];
7770         u8         max_bw_units[0x4];
7771         u8         reserved_at_30[0x8];
7772         u8         max_bw_value[0x8];
7773 };
7774
7775 struct mlx5_ifc_qetc_reg_bits {
7776         u8                                         reserved_at_0[0x8];
7777         u8                                         port_number[0x8];
7778         u8                                         reserved_at_10[0x30];
7779
7780         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
7781         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7782 };
7783
7784 struct mlx5_ifc_qtct_reg_bits {
7785         u8         reserved_at_0[0x8];
7786         u8         port_number[0x8];
7787         u8         reserved_at_10[0xd];
7788         u8         prio[0x3];
7789
7790         u8         reserved_at_20[0x1d];
7791         u8         tclass[0x3];
7792 };
7793
7794 struct mlx5_ifc_mcia_reg_bits {
7795         u8         l[0x1];
7796         u8         reserved_at_1[0x7];
7797         u8         module[0x8];
7798         u8         reserved_at_10[0x8];
7799         u8         status[0x8];
7800
7801         u8         i2c_device_address[0x8];
7802         u8         page_number[0x8];
7803         u8         device_address[0x10];
7804
7805         u8         reserved_at_40[0x10];
7806         u8         size[0x10];
7807
7808         u8         reserved_at_60[0x20];
7809
7810         u8         dword_0[0x20];
7811         u8         dword_1[0x20];
7812         u8         dword_2[0x20];
7813         u8         dword_3[0x20];
7814         u8         dword_4[0x20];
7815         u8         dword_5[0x20];
7816         u8         dword_6[0x20];
7817         u8         dword_7[0x20];
7818         u8         dword_8[0x20];
7819         u8         dword_9[0x20];
7820         u8         dword_10[0x20];
7821         u8         dword_11[0x20];
7822 };
7823
7824 struct mlx5_ifc_dcbx_param_bits {
7825         u8         dcbx_cee_cap[0x1];
7826         u8         dcbx_ieee_cap[0x1];
7827         u8         dcbx_standby_cap[0x1];
7828         u8         reserved_at_0[0x5];
7829         u8         port_number[0x8];
7830         u8         reserved_at_10[0xa];
7831         u8         max_application_table_size[6];
7832         u8         reserved_at_20[0x15];
7833         u8         version_oper[0x3];
7834         u8         reserved_at_38[5];
7835         u8         version_admin[0x3];
7836         u8         willing_admin[0x1];
7837         u8         reserved_at_41[0x3];
7838         u8         pfc_cap_oper[0x4];
7839         u8         reserved_at_48[0x4];
7840         u8         pfc_cap_admin[0x4];
7841         u8         reserved_at_50[0x4];
7842         u8         num_of_tc_oper[0x4];
7843         u8         reserved_at_58[0x4];
7844         u8         num_of_tc_admin[0x4];
7845         u8         remote_willing[0x1];
7846         u8         reserved_at_61[3];
7847         u8         remote_pfc_cap[4];
7848         u8         reserved_at_68[0x14];
7849         u8         remote_num_of_tc[0x4];
7850         u8         reserved_at_80[0x18];
7851         u8         error[0x8];
7852         u8         reserved_at_a0[0x160];
7853 };
7854
7855 struct mlx5_ifc_lagc_bits {
7856         u8         reserved_at_0[0x1d];
7857         u8         lag_state[0x3];
7858
7859         u8         reserved_at_20[0x14];
7860         u8         tx_remap_affinity_2[0x4];
7861         u8         reserved_at_38[0x4];
7862         u8         tx_remap_affinity_1[0x4];
7863 };
7864
7865 struct mlx5_ifc_create_lag_out_bits {
7866         u8         status[0x8];
7867         u8         reserved_at_8[0x18];
7868
7869         u8         syndrome[0x20];
7870
7871         u8         reserved_at_40[0x40];
7872 };
7873
7874 struct mlx5_ifc_create_lag_in_bits {
7875         u8         opcode[0x10];
7876         u8         reserved_at_10[0x10];
7877
7878         u8         reserved_at_20[0x10];
7879         u8         op_mod[0x10];
7880
7881         struct mlx5_ifc_lagc_bits ctx;
7882 };
7883
7884 struct mlx5_ifc_modify_lag_out_bits {
7885         u8         status[0x8];
7886         u8         reserved_at_8[0x18];
7887
7888         u8         syndrome[0x20];
7889
7890         u8         reserved_at_40[0x40];
7891 };
7892
7893 struct mlx5_ifc_modify_lag_in_bits {
7894         u8         opcode[0x10];
7895         u8         reserved_at_10[0x10];
7896
7897         u8         reserved_at_20[0x10];
7898         u8         op_mod[0x10];
7899
7900         u8         reserved_at_40[0x20];
7901         u8         field_select[0x20];
7902
7903         struct mlx5_ifc_lagc_bits ctx;
7904 };
7905
7906 struct mlx5_ifc_query_lag_out_bits {
7907         u8         status[0x8];
7908         u8         reserved_at_8[0x18];
7909
7910         u8         syndrome[0x20];
7911
7912         struct mlx5_ifc_lagc_bits ctx;
7913 };
7914
7915 struct mlx5_ifc_query_lag_in_bits {
7916         u8         opcode[0x10];
7917         u8         reserved_at_10[0x10];
7918
7919         u8         reserved_at_20[0x10];
7920         u8         op_mod[0x10];
7921
7922         u8         reserved_at_40[0x40];
7923 };
7924
7925 struct mlx5_ifc_destroy_lag_out_bits {
7926         u8         status[0x8];
7927         u8         reserved_at_8[0x18];
7928
7929         u8         syndrome[0x20];
7930
7931         u8         reserved_at_40[0x40];
7932 };
7933
7934 struct mlx5_ifc_destroy_lag_in_bits {
7935         u8         opcode[0x10];
7936         u8         reserved_at_10[0x10];
7937
7938         u8         reserved_at_20[0x10];
7939         u8         op_mod[0x10];
7940
7941         u8         reserved_at_40[0x40];
7942 };
7943
7944 struct mlx5_ifc_create_vport_lag_out_bits {
7945         u8         status[0x8];
7946         u8         reserved_at_8[0x18];
7947
7948         u8         syndrome[0x20];
7949
7950         u8         reserved_at_40[0x40];
7951 };
7952
7953 struct mlx5_ifc_create_vport_lag_in_bits {
7954         u8         opcode[0x10];
7955         u8         reserved_at_10[0x10];
7956
7957         u8         reserved_at_20[0x10];
7958         u8         op_mod[0x10];
7959
7960         u8         reserved_at_40[0x40];
7961 };
7962
7963 struct mlx5_ifc_destroy_vport_lag_out_bits {
7964         u8         status[0x8];
7965         u8         reserved_at_8[0x18];
7966
7967         u8         syndrome[0x20];
7968
7969         u8         reserved_at_40[0x40];
7970 };
7971
7972 struct mlx5_ifc_destroy_vport_lag_in_bits {
7973         u8         opcode[0x10];
7974         u8         reserved_at_10[0x10];
7975
7976         u8         reserved_at_20[0x10];
7977         u8         op_mod[0x10];
7978
7979         u8         reserved_at_40[0x40];
7980 };
7981
7982 #endif /* MLX5_IFC_H */