2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
71 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
72 MLX5_CMD_OP_INIT_HCA = 0x102,
73 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
74 MLX5_CMD_OP_ENABLE_HCA = 0x104,
75 MLX5_CMD_OP_DISABLE_HCA = 0x105,
76 MLX5_CMD_OP_QUERY_PAGES = 0x107,
77 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
78 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
79 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
80 MLX5_CMD_OP_SET_ISSI = 0x10b,
81 MLX5_CMD_OP_CREATE_MKEY = 0x200,
82 MLX5_CMD_OP_QUERY_MKEY = 0x201,
83 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
84 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
85 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
86 MLX5_CMD_OP_CREATE_EQ = 0x301,
87 MLX5_CMD_OP_DESTROY_EQ = 0x302,
88 MLX5_CMD_OP_QUERY_EQ = 0x303,
89 MLX5_CMD_OP_GEN_EQE = 0x304,
90 MLX5_CMD_OP_CREATE_CQ = 0x400,
91 MLX5_CMD_OP_DESTROY_CQ = 0x401,
92 MLX5_CMD_OP_QUERY_CQ = 0x402,
93 MLX5_CMD_OP_MODIFY_CQ = 0x403,
94 MLX5_CMD_OP_CREATE_QP = 0x500,
95 MLX5_CMD_OP_DESTROY_QP = 0x501,
96 MLX5_CMD_OP_RST2INIT_QP = 0x502,
97 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
98 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
99 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
100 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
101 MLX5_CMD_OP_2ERR_QP = 0x507,
102 MLX5_CMD_OP_2RST_QP = 0x50a,
103 MLX5_CMD_OP_QUERY_QP = 0x50b,
104 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
105 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
106 MLX5_CMD_OP_CREATE_PSV = 0x600,
107 MLX5_CMD_OP_DESTROY_PSV = 0x601,
108 MLX5_CMD_OP_CREATE_SRQ = 0x700,
109 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
110 MLX5_CMD_OP_QUERY_SRQ = 0x702,
111 MLX5_CMD_OP_ARM_RQ = 0x703,
112 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
113 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
114 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
115 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
116 MLX5_CMD_OP_CREATE_DCT = 0x710,
117 MLX5_CMD_OP_DESTROY_DCT = 0x711,
118 MLX5_CMD_OP_DRAIN_DCT = 0x712,
119 MLX5_CMD_OP_QUERY_DCT = 0x713,
120 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
121 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
122 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
123 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
124 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
125 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
126 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
127 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
128 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
129 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
130 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
131 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
132 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
133 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
134 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
135 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
136 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
137 MLX5_CMD_OP_ALLOC_PD = 0x800,
138 MLX5_CMD_OP_DEALLOC_PD = 0x801,
139 MLX5_CMD_OP_ALLOC_UAR = 0x802,
140 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
141 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
142 MLX5_CMD_OP_ACCESS_REG = 0x805,
143 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
144 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807,
145 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
146 MLX5_CMD_OP_MAD_IFC = 0x50d,
147 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
148 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
149 MLX5_CMD_OP_NOP = 0x80d,
150 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
151 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
152 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
153 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
154 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
155 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
156 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
157 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
158 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
159 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
160 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
161 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
162 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
163 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
164 MLX5_CMD_OP_CREATE_TIR = 0x900,
165 MLX5_CMD_OP_MODIFY_TIR = 0x901,
166 MLX5_CMD_OP_DESTROY_TIR = 0x902,
167 MLX5_CMD_OP_QUERY_TIR = 0x903,
168 MLX5_CMD_OP_CREATE_SQ = 0x904,
169 MLX5_CMD_OP_MODIFY_SQ = 0x905,
170 MLX5_CMD_OP_DESTROY_SQ = 0x906,
171 MLX5_CMD_OP_QUERY_SQ = 0x907,
172 MLX5_CMD_OP_CREATE_RQ = 0x908,
173 MLX5_CMD_OP_MODIFY_RQ = 0x909,
174 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
175 MLX5_CMD_OP_QUERY_RQ = 0x90b,
176 MLX5_CMD_OP_CREATE_RMP = 0x90c,
177 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
178 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
179 MLX5_CMD_OP_QUERY_RMP = 0x90f,
180 MLX5_CMD_OP_CREATE_TIS = 0x912,
181 MLX5_CMD_OP_MODIFY_TIS = 0x913,
182 MLX5_CMD_OP_DESTROY_TIS = 0x914,
183 MLX5_CMD_OP_QUERY_TIS = 0x915,
184 MLX5_CMD_OP_CREATE_RQT = 0x916,
185 MLX5_CMD_OP_MODIFY_RQT = 0x917,
186 MLX5_CMD_OP_DESTROY_RQT = 0x918,
187 MLX5_CMD_OP_QUERY_RQT = 0x919,
188 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
189 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
190 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
191 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
192 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
193 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
194 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
195 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
196 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938
199 struct mlx5_ifc_flow_table_fields_supported_bits {
202 u8 outer_ether_type[0x1];
204 u8 outer_first_prio[0x1];
205 u8 outer_first_cfi[0x1];
206 u8 outer_first_vid[0x1];
208 u8 outer_second_prio[0x1];
209 u8 outer_second_cfi[0x1];
210 u8 outer_second_vid[0x1];
215 u8 outer_ip_protocol[0x1];
216 u8 outer_ip_ecn[0x1];
217 u8 outer_ip_dscp[0x1];
218 u8 outer_udp_sport[0x1];
219 u8 outer_udp_dport[0x1];
220 u8 outer_tcp_sport[0x1];
221 u8 outer_tcp_dport[0x1];
222 u8 outer_tcp_flags[0x1];
223 u8 outer_gre_protocol[0x1];
224 u8 outer_gre_key[0x1];
225 u8 outer_vxlan_vni[0x1];
227 u8 source_eswitch_port[0x1];
231 u8 inner_ether_type[0x1];
233 u8 inner_first_prio[0x1];
234 u8 inner_first_cfi[0x1];
235 u8 inner_first_vid[0x1];
237 u8 inner_second_prio[0x1];
238 u8 inner_second_cfi[0x1];
239 u8 inner_second_vid[0x1];
244 u8 inner_ip_protocol[0x1];
245 u8 inner_ip_ecn[0x1];
246 u8 inner_ip_dscp[0x1];
247 u8 inner_udp_sport[0x1];
248 u8 inner_udp_dport[0x1];
249 u8 inner_tcp_sport[0x1];
250 u8 inner_tcp_dport[0x1];
251 u8 inner_tcp_flags[0x1];
257 struct mlx5_ifc_flow_table_prop_layout_bits {
262 u8 log_max_ft_size[0x6];
264 u8 max_ft_level[0x8];
269 u8 log_max_ft_num[0x8];
272 u8 log_max_destination[0x8];
275 u8 log_max_flow[0x8];
279 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
281 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
284 struct mlx5_ifc_odp_per_transport_service_cap_bits {
294 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
329 struct mlx5_ifc_fte_match_set_misc_bits {
333 u8 source_port[0x10];
335 u8 outer_second_prio[0x3];
336 u8 outer_second_cfi[0x1];
337 u8 outer_second_vid[0xc];
338 u8 inner_second_prio[0x3];
339 u8 inner_second_cfi[0x1];
340 u8 inner_second_vid[0xc];
342 u8 outer_second_vlan_tag[0x1];
343 u8 inner_second_vlan_tag[0x1];
345 u8 gre_protocol[0x10];
356 u8 outer_ipv6_flow_label[0x14];
359 u8 inner_ipv6_flow_label[0x14];
364 struct mlx5_ifc_cmd_pas_bits {
371 struct mlx5_ifc_uint64_bits {
378 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
379 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
380 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
381 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
382 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
383 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
384 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
385 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
386 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
387 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
390 struct mlx5_ifc_ads_bits {
403 u8 src_addr_index[0x8];
412 u8 rgid_rip[16][0x8];
432 struct mlx5_ifc_flow_table_nic_cap_bits {
433 u8 reserved_0[0x200];
435 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
437 u8 reserved_1[0x200];
439 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
441 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
443 u8 reserved_2[0x200];
445 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
447 u8 reserved_3[0x7200];
450 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
454 u8 lro_psh_flag[0x1];
455 u8 lro_time_stamp[0x1];
457 u8 self_lb_en_modifiable[0x1];
461 u8 rss_ind_tbl_cap[0x4];
463 u8 tunnel_lso_const_out_ip_id[0x1];
465 u8 tunnel_statless_gre[0x1];
466 u8 tunnel_stateless_vxlan[0x1];
471 u8 lro_min_mss_size[0x10];
473 u8 reserved_7[0x120];
475 u8 lro_timer_supported_periods[4][0x20];
477 u8 reserved_8[0x600];
480 struct mlx5_ifc_roce_cap_bits {
489 u8 roce_version[0x8];
492 u8 r_roce_dest_udp_port[0x10];
494 u8 r_roce_max_src_udp_port[0x10];
495 u8 r_roce_min_src_udp_port[0x10];
498 u8 roce_address_table_size[0x10];
500 u8 reserved_6[0x700];
504 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
505 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
506 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
507 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
508 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
509 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
510 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
511 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
512 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
516 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
517 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
518 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
519 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
520 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
521 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
522 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
523 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
524 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
527 struct mlx5_ifc_atomic_caps_bits {
530 u8 atomic_req_endianness[0x1];
536 u8 atomic_operations[0x10];
539 u8 atomic_size_qp[0x10];
542 u8 atomic_size_dc[0x10];
544 u8 reserved_6[0x720];
547 struct mlx5_ifc_odp_cap_bits {
555 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
557 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
559 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
561 u8 reserved_3[0x720];
565 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
566 MLX5_WQ_TYPE_CYCLIC = 0x1,
567 MLX5_WQ_TYPE_STRQ = 0x2,
571 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
572 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
576 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
577 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
578 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
579 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
580 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
584 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
585 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
586 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
587 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
588 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
589 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
593 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
594 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
598 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
599 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
600 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
604 MLX5_CAP_PORT_TYPE_IB = 0x0,
605 MLX5_CAP_PORT_TYPE_ETH = 0x1,
608 struct mlx5_ifc_cmd_hca_cap_bits {
611 u8 log_max_srq_sz[0x8];
612 u8 log_max_qp_sz[0x8];
621 u8 log_max_cq_sz[0x8];
625 u8 log_max_eq_sz[0x8];
627 u8 log_max_mkey[0x6];
631 u8 max_indirection[0x8];
633 u8 log_max_mrw_sz[0x7];
635 u8 log_max_bsf_list_size[0x6];
637 u8 log_max_klm_list_size[0x6];
640 u8 log_max_ra_req_dc[0x6];
642 u8 log_max_ra_res_dc[0x6];
645 u8 log_max_ra_req_qp[0x6];
647 u8 log_max_ra_res_qp[0x6];
650 u8 cc_query_allowed[0x1];
651 u8 cc_modify_allowed[0x1];
653 u8 gid_table_size[0x10];
655 u8 out_of_seq_cnt[0x1];
656 u8 vport_counters[0x1];
659 u8 pkey_table_size[0x10];
661 u8 vport_group_manager[0x1];
662 u8 vhca_group_manager[0x1];
667 u8 nic_flow_table[0x1];
669 u8 local_ca_ack_delay[0x5];
676 u8 reserved_21[0x18];
678 u8 stat_rate_support[0x10];
682 u8 compact_address_vector[0x1];
684 u8 drain_sigerr[0x1];
685 u8 cmdif_checksum[0x2];
688 u8 wq_signature[0x1];
689 u8 sctr_data_cqe[0x1];
696 u8 eth_net_offloads[0x1];
703 u8 cq_moderation[0x1];
709 u8 scqe_break_moderation[0x1];
730 u8 pad_tx_eth_packet[0x1];
732 u8 log_bf_reg_size[0x5];
733 u8 reserved_38[0x10];
735 u8 reserved_39[0x10];
736 u8 max_wqe_sz_sq[0x10];
738 u8 reserved_40[0x10];
739 u8 max_wqe_sz_rq[0x10];
741 u8 reserved_41[0x10];
742 u8 max_wqe_sz_sq_dc[0x10];
747 u8 reserved_43[0x18];
751 u8 log_max_transport_domain[0x5];
755 u8 log_max_xrcd[0x5];
757 u8 reserved_47[0x20];
768 u8 basic_cyclic_rcv_wqe[0x1];
774 u8 log_max_rqt_size[0x5];
776 u8 log_max_tis_per_sq[0x5];
779 u8 log_max_stride_sz_rq[0x5];
781 u8 log_min_stride_sz_rq[0x5];
783 u8 log_max_stride_sz_sq[0x5];
785 u8 log_min_stride_sz_sq[0x5];
787 u8 reserved_60[0x1b];
788 u8 log_max_wq_sz[0x5];
790 u8 reserved_61[0xa0];
793 u8 log_max_l2_table[0x5];
795 u8 log_uar_page_sz[0x10];
797 u8 reserved_64[0x100];
799 u8 reserved_65[0x1f];
802 u8 cqe_zip_timeout[0x10];
803 u8 cqe_zip_max_num[0x10];
805 u8 reserved_66[0x220];
809 MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_FLOW_TABLE_ = 0x1,
810 MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_TIR = 0x2,
813 struct mlx5_ifc_dest_format_struct_bits {
814 u8 destination_type[0x8];
815 u8 destination_id[0x18];
820 struct mlx5_ifc_fte_match_param_bits {
821 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
823 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
825 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
827 u8 reserved_0[0xa00];
831 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
832 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
833 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
834 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
835 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
838 struct mlx5_ifc_rx_hash_field_select_bits {
839 u8 l3_prot_type[0x1];
840 u8 l4_prot_type[0x1];
841 u8 selected_fields[0x1e];
845 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
846 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
850 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
851 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
854 struct mlx5_ifc_wq_bits {
856 u8 wq_signature[0x1];
857 u8 end_padding_mode[0x2];
861 u8 hds_skip_first_sge[0x1];
862 u8 log2_hds_buf_size[0x3];
880 u8 log_wq_stride[0x4];
882 u8 log_wq_pg_sz[0x5];
886 u8 reserved_7[0x4e0];
888 struct mlx5_ifc_cmd_pas_bits pas[0];
891 struct mlx5_ifc_rq_num_bits {
896 struct mlx5_ifc_mac_address_layout_bits {
898 u8 mac_addr_47_32[0x10];
900 u8 mac_addr_31_0[0x20];
903 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
906 u8 min_time_between_cnps[0x20];
911 u8 cnp_802p_prio[0x3];
913 u8 reserved_3[0x720];
916 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
920 u8 clamp_tgt_rate[0x1];
922 u8 clamp_tgt_rate_after_time_inc[0x1];
927 u8 rpg_time_reset[0x20];
929 u8 rpg_byte_reset[0x20];
931 u8 rpg_threshold[0x20];
933 u8 rpg_max_rate[0x20];
935 u8 rpg_ai_rate[0x20];
937 u8 rpg_hai_rate[0x20];
941 u8 rpg_min_dec_fac[0x20];
943 u8 rpg_min_rate[0x20];
947 u8 rate_to_set_on_first_cnp[0x20];
951 u8 dce_tcp_rtt[0x20];
953 u8 rate_reduce_monitor_period[0x20];
957 u8 initial_alpha_value[0x20];
959 u8 reserved_7[0x4a0];
962 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
965 u8 rppp_max_rps[0x20];
967 u8 rpg_time_reset[0x20];
969 u8 rpg_byte_reset[0x20];
971 u8 rpg_threshold[0x20];
973 u8 rpg_max_rate[0x20];
975 u8 rpg_ai_rate[0x20];
977 u8 rpg_hai_rate[0x20];
981 u8 rpg_min_dec_fac[0x20];
983 u8 rpg_min_rate[0x20];
985 u8 reserved_1[0x640];
989 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
990 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
991 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
994 struct mlx5_ifc_resize_field_select_bits {
995 u8 resize_field_select[0x20];
999 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1000 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1001 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1002 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1005 struct mlx5_ifc_modify_field_select_bits {
1006 u8 modify_field_select[0x20];
1009 struct mlx5_ifc_field_select_r_roce_np_bits {
1010 u8 field_select_r_roce_np[0x20];
1013 struct mlx5_ifc_field_select_r_roce_rp_bits {
1014 u8 field_select_r_roce_rp[0x20];
1018 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1019 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1020 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1021 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1022 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1023 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1024 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1025 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1026 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1027 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1030 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1031 u8 field_select_8021qaurp[0x20];
1034 struct mlx5_ifc_phys_layer_cntrs_bits {
1035 u8 time_since_last_clear_high[0x20];
1037 u8 time_since_last_clear_low[0x20];
1039 u8 symbol_errors_high[0x20];
1041 u8 symbol_errors_low[0x20];
1043 u8 sync_headers_errors_high[0x20];
1045 u8 sync_headers_errors_low[0x20];
1047 u8 edpl_bip_errors_lane0_high[0x20];
1049 u8 edpl_bip_errors_lane0_low[0x20];
1051 u8 edpl_bip_errors_lane1_high[0x20];
1053 u8 edpl_bip_errors_lane1_low[0x20];
1055 u8 edpl_bip_errors_lane2_high[0x20];
1057 u8 edpl_bip_errors_lane2_low[0x20];
1059 u8 edpl_bip_errors_lane3_high[0x20];
1061 u8 edpl_bip_errors_lane3_low[0x20];
1063 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1065 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1067 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1069 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1071 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1073 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1075 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1077 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1079 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1081 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1083 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1085 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1087 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1089 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1091 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1093 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1095 u8 rs_fec_corrected_blocks_high[0x20];
1097 u8 rs_fec_corrected_blocks_low[0x20];
1099 u8 rs_fec_uncorrectable_blocks_high[0x20];
1101 u8 rs_fec_uncorrectable_blocks_low[0x20];
1103 u8 rs_fec_no_errors_blocks_high[0x20];
1105 u8 rs_fec_no_errors_blocks_low[0x20];
1107 u8 rs_fec_single_error_blocks_high[0x20];
1109 u8 rs_fec_single_error_blocks_low[0x20];
1111 u8 rs_fec_corrected_symbols_total_high[0x20];
1113 u8 rs_fec_corrected_symbols_total_low[0x20];
1115 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1117 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1119 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1121 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1123 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1125 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1127 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1129 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1131 u8 link_down_events[0x20];
1133 u8 successful_recovery_events[0x20];
1135 u8 reserved_0[0x180];
1138 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1139 u8 transmit_queue_high[0x20];
1141 u8 transmit_queue_low[0x20];
1143 u8 reserved_0[0x780];
1146 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1147 u8 rx_octets_high[0x20];
1149 u8 rx_octets_low[0x20];
1151 u8 reserved_0[0xc0];
1153 u8 rx_frames_high[0x20];
1155 u8 rx_frames_low[0x20];
1157 u8 tx_octets_high[0x20];
1159 u8 tx_octets_low[0x20];
1161 u8 reserved_1[0xc0];
1163 u8 tx_frames_high[0x20];
1165 u8 tx_frames_low[0x20];
1167 u8 rx_pause_high[0x20];
1169 u8 rx_pause_low[0x20];
1171 u8 rx_pause_duration_high[0x20];
1173 u8 rx_pause_duration_low[0x20];
1175 u8 tx_pause_high[0x20];
1177 u8 tx_pause_low[0x20];
1179 u8 tx_pause_duration_high[0x20];
1181 u8 tx_pause_duration_low[0x20];
1183 u8 rx_pause_transition_high[0x20];
1185 u8 rx_pause_transition_low[0x20];
1187 u8 reserved_2[0x400];
1190 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1191 u8 port_transmit_wait_high[0x20];
1193 u8 port_transmit_wait_low[0x20];
1195 u8 reserved_0[0x780];
1198 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1199 u8 dot3stats_alignment_errors_high[0x20];
1201 u8 dot3stats_alignment_errors_low[0x20];
1203 u8 dot3stats_fcs_errors_high[0x20];
1205 u8 dot3stats_fcs_errors_low[0x20];
1207 u8 dot3stats_single_collision_frames_high[0x20];
1209 u8 dot3stats_single_collision_frames_low[0x20];
1211 u8 dot3stats_multiple_collision_frames_high[0x20];
1213 u8 dot3stats_multiple_collision_frames_low[0x20];
1215 u8 dot3stats_sqe_test_errors_high[0x20];
1217 u8 dot3stats_sqe_test_errors_low[0x20];
1219 u8 dot3stats_deferred_transmissions_high[0x20];
1221 u8 dot3stats_deferred_transmissions_low[0x20];
1223 u8 dot3stats_late_collisions_high[0x20];
1225 u8 dot3stats_late_collisions_low[0x20];
1227 u8 dot3stats_excessive_collisions_high[0x20];
1229 u8 dot3stats_excessive_collisions_low[0x20];
1231 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1233 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1235 u8 dot3stats_carrier_sense_errors_high[0x20];
1237 u8 dot3stats_carrier_sense_errors_low[0x20];
1239 u8 dot3stats_frame_too_longs_high[0x20];
1241 u8 dot3stats_frame_too_longs_low[0x20];
1243 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1245 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1247 u8 dot3stats_symbol_errors_high[0x20];
1249 u8 dot3stats_symbol_errors_low[0x20];
1251 u8 dot3control_in_unknown_opcodes_high[0x20];
1253 u8 dot3control_in_unknown_opcodes_low[0x20];
1255 u8 dot3in_pause_frames_high[0x20];
1257 u8 dot3in_pause_frames_low[0x20];
1259 u8 dot3out_pause_frames_high[0x20];
1261 u8 dot3out_pause_frames_low[0x20];
1263 u8 reserved_0[0x3c0];
1266 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1267 u8 ether_stats_drop_events_high[0x20];
1269 u8 ether_stats_drop_events_low[0x20];
1271 u8 ether_stats_octets_high[0x20];
1273 u8 ether_stats_octets_low[0x20];
1275 u8 ether_stats_pkts_high[0x20];
1277 u8 ether_stats_pkts_low[0x20];
1279 u8 ether_stats_broadcast_pkts_high[0x20];
1281 u8 ether_stats_broadcast_pkts_low[0x20];
1283 u8 ether_stats_multicast_pkts_high[0x20];
1285 u8 ether_stats_multicast_pkts_low[0x20];
1287 u8 ether_stats_crc_align_errors_high[0x20];
1289 u8 ether_stats_crc_align_errors_low[0x20];
1291 u8 ether_stats_undersize_pkts_high[0x20];
1293 u8 ether_stats_undersize_pkts_low[0x20];
1295 u8 ether_stats_oversize_pkts_high[0x20];
1297 u8 ether_stats_oversize_pkts_low[0x20];
1299 u8 ether_stats_fragments_high[0x20];
1301 u8 ether_stats_fragments_low[0x20];
1303 u8 ether_stats_jabbers_high[0x20];
1305 u8 ether_stats_jabbers_low[0x20];
1307 u8 ether_stats_collisions_high[0x20];
1309 u8 ether_stats_collisions_low[0x20];
1311 u8 ether_stats_pkts64octets_high[0x20];
1313 u8 ether_stats_pkts64octets_low[0x20];
1315 u8 ether_stats_pkts65to127octets_high[0x20];
1317 u8 ether_stats_pkts65to127octets_low[0x20];
1319 u8 ether_stats_pkts128to255octets_high[0x20];
1321 u8 ether_stats_pkts128to255octets_low[0x20];
1323 u8 ether_stats_pkts256to511octets_high[0x20];
1325 u8 ether_stats_pkts256to511octets_low[0x20];
1327 u8 ether_stats_pkts512to1023octets_high[0x20];
1329 u8 ether_stats_pkts512to1023octets_low[0x20];
1331 u8 ether_stats_pkts1024to1518octets_high[0x20];
1333 u8 ether_stats_pkts1024to1518octets_low[0x20];
1335 u8 ether_stats_pkts1519to2047octets_high[0x20];
1337 u8 ether_stats_pkts1519to2047octets_low[0x20];
1339 u8 ether_stats_pkts2048to4095octets_high[0x20];
1341 u8 ether_stats_pkts2048to4095octets_low[0x20];
1343 u8 ether_stats_pkts4096to8191octets_high[0x20];
1345 u8 ether_stats_pkts4096to8191octets_low[0x20];
1347 u8 ether_stats_pkts8192to10239octets_high[0x20];
1349 u8 ether_stats_pkts8192to10239octets_low[0x20];
1351 u8 reserved_0[0x280];
1354 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1355 u8 if_in_octets_high[0x20];
1357 u8 if_in_octets_low[0x20];
1359 u8 if_in_ucast_pkts_high[0x20];
1361 u8 if_in_ucast_pkts_low[0x20];
1363 u8 if_in_discards_high[0x20];
1365 u8 if_in_discards_low[0x20];
1367 u8 if_in_errors_high[0x20];
1369 u8 if_in_errors_low[0x20];
1371 u8 if_in_unknown_protos_high[0x20];
1373 u8 if_in_unknown_protos_low[0x20];
1375 u8 if_out_octets_high[0x20];
1377 u8 if_out_octets_low[0x20];
1379 u8 if_out_ucast_pkts_high[0x20];
1381 u8 if_out_ucast_pkts_low[0x20];
1383 u8 if_out_discards_high[0x20];
1385 u8 if_out_discards_low[0x20];
1387 u8 if_out_errors_high[0x20];
1389 u8 if_out_errors_low[0x20];
1391 u8 if_in_multicast_pkts_high[0x20];
1393 u8 if_in_multicast_pkts_low[0x20];
1395 u8 if_in_broadcast_pkts_high[0x20];
1397 u8 if_in_broadcast_pkts_low[0x20];
1399 u8 if_out_multicast_pkts_high[0x20];
1401 u8 if_out_multicast_pkts_low[0x20];
1403 u8 if_out_broadcast_pkts_high[0x20];
1405 u8 if_out_broadcast_pkts_low[0x20];
1407 u8 reserved_0[0x480];
1410 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1411 u8 a_frames_transmitted_ok_high[0x20];
1413 u8 a_frames_transmitted_ok_low[0x20];
1415 u8 a_frames_received_ok_high[0x20];
1417 u8 a_frames_received_ok_low[0x20];
1419 u8 a_frame_check_sequence_errors_high[0x20];
1421 u8 a_frame_check_sequence_errors_low[0x20];
1423 u8 a_alignment_errors_high[0x20];
1425 u8 a_alignment_errors_low[0x20];
1427 u8 a_octets_transmitted_ok_high[0x20];
1429 u8 a_octets_transmitted_ok_low[0x20];
1431 u8 a_octets_received_ok_high[0x20];
1433 u8 a_octets_received_ok_low[0x20];
1435 u8 a_multicast_frames_xmitted_ok_high[0x20];
1437 u8 a_multicast_frames_xmitted_ok_low[0x20];
1439 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1441 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1443 u8 a_multicast_frames_received_ok_high[0x20];
1445 u8 a_multicast_frames_received_ok_low[0x20];
1447 u8 a_broadcast_frames_received_ok_high[0x20];
1449 u8 a_broadcast_frames_received_ok_low[0x20];
1451 u8 a_in_range_length_errors_high[0x20];
1453 u8 a_in_range_length_errors_low[0x20];
1455 u8 a_out_of_range_length_field_high[0x20];
1457 u8 a_out_of_range_length_field_low[0x20];
1459 u8 a_frame_too_long_errors_high[0x20];
1461 u8 a_frame_too_long_errors_low[0x20];
1463 u8 a_symbol_error_during_carrier_high[0x20];
1465 u8 a_symbol_error_during_carrier_low[0x20];
1467 u8 a_mac_control_frames_transmitted_high[0x20];
1469 u8 a_mac_control_frames_transmitted_low[0x20];
1471 u8 a_mac_control_frames_received_high[0x20];
1473 u8 a_mac_control_frames_received_low[0x20];
1475 u8 a_unsupported_opcodes_received_high[0x20];
1477 u8 a_unsupported_opcodes_received_low[0x20];
1479 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1481 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1483 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1485 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1487 u8 reserved_0[0x300];
1490 struct mlx5_ifc_cmd_inter_comp_event_bits {
1491 u8 command_completion_vector[0x20];
1493 u8 reserved_0[0xc0];
1496 struct mlx5_ifc_stall_vl_event_bits {
1497 u8 reserved_0[0x18];
1502 u8 reserved_2[0xa0];
1505 struct mlx5_ifc_db_bf_congestion_event_bits {
1506 u8 event_subtype[0x8];
1508 u8 congestion_level[0x8];
1511 u8 reserved_2[0xa0];
1514 struct mlx5_ifc_gpio_event_bits {
1515 u8 reserved_0[0x60];
1517 u8 gpio_event_hi[0x20];
1519 u8 gpio_event_lo[0x20];
1521 u8 reserved_1[0x40];
1524 struct mlx5_ifc_port_state_change_event_bits {
1525 u8 reserved_0[0x40];
1528 u8 reserved_1[0x1c];
1530 u8 reserved_2[0x80];
1533 struct mlx5_ifc_dropped_packet_logged_bits {
1534 u8 reserved_0[0xe0];
1538 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1539 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1542 struct mlx5_ifc_cq_error_bits {
1546 u8 reserved_1[0x20];
1548 u8 reserved_2[0x18];
1551 u8 reserved_3[0x80];
1554 struct mlx5_ifc_rdma_page_fault_event_bits {
1555 u8 bytes_committed[0x20];
1559 u8 reserved_0[0x10];
1560 u8 packet_len[0x10];
1562 u8 rdma_op_len[0x20];
1573 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1574 u8 bytes_committed[0x20];
1576 u8 reserved_0[0x10];
1579 u8 reserved_1[0x10];
1582 u8 reserved_2[0x60];
1591 struct mlx5_ifc_qp_events_bits {
1592 u8 reserved_0[0xa0];
1595 u8 reserved_1[0x18];
1598 u8 qpn_rqn_sqn[0x18];
1601 struct mlx5_ifc_dct_events_bits {
1602 u8 reserved_0[0xc0];
1605 u8 dct_number[0x18];
1608 struct mlx5_ifc_comp_event_bits {
1609 u8 reserved_0[0xc0];
1616 MLX5_QPC_STATE_RST = 0x0,
1617 MLX5_QPC_STATE_INIT = 0x1,
1618 MLX5_QPC_STATE_RTR = 0x2,
1619 MLX5_QPC_STATE_RTS = 0x3,
1620 MLX5_QPC_STATE_SQER = 0x4,
1621 MLX5_QPC_STATE_ERR = 0x6,
1622 MLX5_QPC_STATE_SQD = 0x7,
1623 MLX5_QPC_STATE_SUSPENDED = 0x9,
1627 MLX5_QPC_ST_RC = 0x0,
1628 MLX5_QPC_ST_UC = 0x1,
1629 MLX5_QPC_ST_UD = 0x2,
1630 MLX5_QPC_ST_XRC = 0x3,
1631 MLX5_QPC_ST_DCI = 0x5,
1632 MLX5_QPC_ST_QP0 = 0x7,
1633 MLX5_QPC_ST_QP1 = 0x8,
1634 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1635 MLX5_QPC_ST_REG_UMR = 0xc,
1639 MLX5_QPC_PM_STATE_ARMED = 0x0,
1640 MLX5_QPC_PM_STATE_REARM = 0x1,
1641 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1642 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1646 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1647 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1651 MLX5_QPC_MTU_256_BYTES = 0x1,
1652 MLX5_QPC_MTU_512_BYTES = 0x2,
1653 MLX5_QPC_MTU_1K_BYTES = 0x3,
1654 MLX5_QPC_MTU_2K_BYTES = 0x4,
1655 MLX5_QPC_MTU_4K_BYTES = 0x5,
1656 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1660 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1661 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1662 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1663 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1664 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1665 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1666 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1667 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1671 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1672 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1673 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1677 MLX5_QPC_CS_RES_DISABLE = 0x0,
1678 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1679 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1682 struct mlx5_ifc_qpc_bits {
1689 u8 end_padding_mode[0x2];
1692 u8 wq_signature[0x1];
1693 u8 block_lb_mc[0x1];
1694 u8 atomic_like_write_en[0x1];
1695 u8 latency_sensitive[0x1];
1697 u8 drain_sigerr[0x1];
1702 u8 log_msg_max[0x5];
1704 u8 log_rq_size[0x4];
1705 u8 log_rq_stride[0x3];
1707 u8 log_sq_size[0x4];
1712 u8 counter_set_id[0x8];
1716 u8 user_index[0x18];
1718 u8 reserved_10[0x3];
1719 u8 log_page_size[0x5];
1720 u8 remote_qpn[0x18];
1722 struct mlx5_ifc_ads_bits primary_address_path;
1724 struct mlx5_ifc_ads_bits secondary_address_path;
1726 u8 log_ack_req_freq[0x4];
1727 u8 reserved_11[0x4];
1728 u8 log_sra_max[0x3];
1729 u8 reserved_12[0x2];
1730 u8 retry_count[0x3];
1732 u8 reserved_13[0x1];
1734 u8 cur_rnr_retry[0x3];
1735 u8 cur_retry_count[0x3];
1736 u8 reserved_14[0x5];
1738 u8 reserved_15[0x20];
1740 u8 reserved_16[0x8];
1741 u8 next_send_psn[0x18];
1743 u8 reserved_17[0x8];
1746 u8 reserved_18[0x40];
1748 u8 reserved_19[0x8];
1749 u8 last_acked_psn[0x18];
1751 u8 reserved_20[0x8];
1754 u8 reserved_21[0x8];
1755 u8 log_rra_max[0x3];
1756 u8 reserved_22[0x1];
1757 u8 atomic_mode[0x4];
1761 u8 reserved_23[0x1];
1762 u8 page_offset[0x6];
1763 u8 reserved_24[0x3];
1764 u8 cd_slave_receive[0x1];
1765 u8 cd_slave_send[0x1];
1768 u8 reserved_25[0x3];
1769 u8 min_rnr_nak[0x5];
1770 u8 next_rcv_psn[0x18];
1772 u8 reserved_26[0x8];
1775 u8 reserved_27[0x8];
1782 u8 reserved_28[0x5];
1786 u8 reserved_29[0x8];
1789 u8 hw_sq_wqebb_counter[0x10];
1790 u8 sw_sq_wqebb_counter[0x10];
1792 u8 hw_rq_counter[0x20];
1794 u8 sw_rq_counter[0x20];
1796 u8 reserved_30[0x20];
1798 u8 reserved_31[0xf];
1803 u8 dc_access_key[0x40];
1805 u8 reserved_32[0xc0];
1808 struct mlx5_ifc_roce_addr_layout_bits {
1809 u8 source_l3_address[16][0x8];
1814 u8 source_mac_47_32[0x10];
1816 u8 source_mac_31_0[0x20];
1818 u8 reserved_1[0x14];
1819 u8 roce_l3_type[0x4];
1820 u8 roce_version[0x8];
1822 u8 reserved_2[0x20];
1825 union mlx5_ifc_hca_cap_union_bits {
1826 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1827 struct mlx5_ifc_odp_cap_bits odp_cap;
1828 struct mlx5_ifc_atomic_caps_bits atomic_caps;
1829 struct mlx5_ifc_roce_cap_bits roce_cap;
1830 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1831 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1832 u8 reserved_0[0x8000];
1836 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
1837 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
1838 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
1841 struct mlx5_ifc_flow_context_bits {
1842 u8 reserved_0[0x20];
1849 u8 reserved_2[0x10];
1853 u8 destination_list_size[0x18];
1855 u8 reserved_4[0x160];
1857 struct mlx5_ifc_fte_match_param_bits match_value;
1859 u8 reserved_5[0x600];
1861 struct mlx5_ifc_dest_format_struct_bits destination[0];
1865 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
1866 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
1869 struct mlx5_ifc_xrc_srqc_bits {
1871 u8 log_xrc_srq_size[0x4];
1872 u8 reserved_0[0x18];
1874 u8 wq_signature[0x1];
1878 u8 basic_cyclic_rcv_wqe[0x1];
1879 u8 log_rq_stride[0x3];
1882 u8 page_offset[0x6];
1886 u8 reserved_3[0x20];
1888 u8 user_index_equal_xrc_srqn[0x1];
1890 u8 log_page_size[0x6];
1891 u8 user_index[0x18];
1893 u8 reserved_5[0x20];
1901 u8 reserved_7[0x40];
1903 u8 db_record_addr_h[0x20];
1905 u8 db_record_addr_l[0x1e];
1908 u8 reserved_9[0x80];
1911 struct mlx5_ifc_traffic_counter_bits {
1917 struct mlx5_ifc_tisc_bits {
1920 u8 reserved_1[0x10];
1922 u8 reserved_2[0x100];
1925 u8 transport_domain[0x18];
1927 u8 reserved_4[0x3c0];
1931 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
1932 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
1936 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
1937 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
1941 MLX5_RX_HASH_FN_NONE = 0x0,
1942 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
1943 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
1947 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
1948 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
1951 struct mlx5_ifc_tirc_bits {
1952 u8 reserved_0[0x20];
1955 u8 reserved_1[0x1c];
1957 u8 reserved_2[0x40];
1960 u8 lro_timeout_period_usecs[0x10];
1961 u8 lro_enable_mask[0x4];
1962 u8 lro_max_ip_payload_size[0x8];
1964 u8 reserved_4[0x40];
1967 u8 inline_rqn[0x18];
1969 u8 rx_hash_symmetric[0x1];
1971 u8 tunneled_offload_en[0x1];
1973 u8 indirect_table[0x18];
1977 u8 self_lb_block[0x2];
1978 u8 transport_domain[0x18];
1980 u8 rx_hash_toeplitz_key[10][0x20];
1982 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
1984 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
1986 u8 reserved_9[0x4c0];
1990 MLX5_SRQC_STATE_GOOD = 0x0,
1991 MLX5_SRQC_STATE_ERROR = 0x1,
1994 struct mlx5_ifc_srqc_bits {
1996 u8 log_srq_size[0x4];
1997 u8 reserved_0[0x18];
1999 u8 wq_signature[0x1];
2004 u8 log_rq_stride[0x3];
2007 u8 page_offset[0x6];
2011 u8 reserved_4[0x20];
2014 u8 log_page_size[0x6];
2015 u8 reserved_6[0x18];
2017 u8 reserved_7[0x20];
2025 u8 reserved_9[0x40];
2029 u8 reserved_10[0x80];
2033 MLX5_SQC_STATE_RST = 0x0,
2034 MLX5_SQC_STATE_RDY = 0x1,
2035 MLX5_SQC_STATE_ERR = 0x3,
2038 struct mlx5_ifc_sqc_bits {
2042 u8 flush_in_error_en[0x1];
2045 u8 reserved_1[0x14];
2048 u8 user_index[0x18];
2053 u8 reserved_4[0xa0];
2055 u8 tis_lst_sz[0x10];
2056 u8 reserved_5[0x10];
2058 u8 reserved_6[0x40];
2063 struct mlx5_ifc_wq_bits wq;
2066 struct mlx5_ifc_rqtc_bits {
2067 u8 reserved_0[0xa0];
2069 u8 reserved_1[0x10];
2070 u8 rqt_max_size[0x10];
2072 u8 reserved_2[0x10];
2073 u8 rqt_actual_size[0x10];
2075 u8 reserved_3[0x6a0];
2077 struct mlx5_ifc_rq_num_bits rq_num[0];
2081 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2082 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2086 MLX5_RQC_STATE_RST = 0x0,
2087 MLX5_RQC_STATE_RDY = 0x1,
2088 MLX5_RQC_STATE_ERR = 0x3,
2091 struct mlx5_ifc_rqc_bits {
2095 u8 mem_rq_type[0x4];
2098 u8 flush_in_error_en[0x1];
2099 u8 reserved_2[0x12];
2102 u8 user_index[0x18];
2107 u8 counter_set_id[0x8];
2108 u8 reserved_5[0x18];
2113 u8 reserved_7[0xe0];
2115 struct mlx5_ifc_wq_bits wq;
2119 MLX5_RMPC_STATE_RDY = 0x1,
2120 MLX5_RMPC_STATE_ERR = 0x3,
2123 struct mlx5_ifc_rmpc_bits {
2126 u8 reserved_1[0x14];
2128 u8 basic_cyclic_rcv_wqe[0x1];
2129 u8 reserved_2[0x1f];
2131 u8 reserved_3[0x140];
2133 struct mlx5_ifc_wq_bits wq;
2137 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0,
2140 struct mlx5_ifc_nic_vport_context_bits {
2141 u8 reserved_0[0x1f];
2144 u8 reserved_1[0x760];
2147 u8 allowed_list_type[0x3];
2149 u8 allowed_list_size[0xc];
2151 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2153 u8 reserved_4[0x20];
2155 u8 current_uc_mac_address[0][0x40];
2159 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2160 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2161 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2164 struct mlx5_ifc_mkc_bits {
2168 u8 small_fence_on_rdma_read_response[0x1];
2175 u8 access_mode[0x2];
2181 u8 reserved_3[0x20];
2187 u8 expected_sigerr_count[0x1];
2192 u8 start_addr[0x40];
2196 u8 bsf_octword_size[0x20];
2198 u8 reserved_6[0x80];
2200 u8 translations_octword_size[0x20];
2202 u8 reserved_7[0x1b];
2203 u8 log_page_size[0x5];
2205 u8 reserved_8[0x20];
2208 struct mlx5_ifc_pkey_bits {
2209 u8 reserved_0[0x10];
2213 struct mlx5_ifc_array128_auto_bits {
2214 u8 array128_auto[16][0x8];
2217 struct mlx5_ifc_hca_vport_context_bits {
2218 u8 field_select[0x20];
2220 u8 reserved_0[0xe0];
2222 u8 sm_virt_aware[0x1];
2225 u8 grh_required[0x1];
2227 u8 port_physical_state[0x4];
2228 u8 vport_state_policy[0x4];
2230 u8 vport_state[0x4];
2232 u8 reserved_2[0x20];
2234 u8 system_image_guid[0x40];
2242 u8 cap_mask1_field_select[0x20];
2246 u8 cap_mask2_field_select[0x20];
2248 u8 reserved_3[0x80];
2252 u8 init_type_reply[0x4];
2254 u8 subnet_timeout[0x5];
2260 u8 qkey_violation_counter[0x10];
2261 u8 pkey_violation_counter[0x10];
2263 u8 reserved_6[0xca0];
2267 MLX5_EQC_STATUS_OK = 0x0,
2268 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2272 MLX5_EQC_ST_ARMED = 0x9,
2273 MLX5_EQC_ST_FIRED = 0xa,
2276 struct mlx5_ifc_eqc_bits {
2285 u8 reserved_3[0x20];
2287 u8 reserved_4[0x14];
2288 u8 page_offset[0x6];
2292 u8 log_eq_size[0x5];
2295 u8 reserved_7[0x20];
2297 u8 reserved_8[0x18];
2301 u8 log_page_size[0x5];
2302 u8 reserved_10[0x18];
2304 u8 reserved_11[0x60];
2306 u8 reserved_12[0x8];
2307 u8 consumer_counter[0x18];
2309 u8 reserved_13[0x8];
2310 u8 producer_counter[0x18];
2312 u8 reserved_14[0x80];
2316 MLX5_DCTC_STATE_ACTIVE = 0x0,
2317 MLX5_DCTC_STATE_DRAINING = 0x1,
2318 MLX5_DCTC_STATE_DRAINED = 0x2,
2322 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2323 MLX5_DCTC_CS_RES_NA = 0x1,
2324 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2328 MLX5_DCTC_MTU_256_BYTES = 0x1,
2329 MLX5_DCTC_MTU_512_BYTES = 0x2,
2330 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2331 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2332 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2335 struct mlx5_ifc_dctc_bits {
2338 u8 reserved_1[0x18];
2341 u8 user_index[0x18];
2346 u8 counter_set_id[0x8];
2347 u8 atomic_mode[0x4];
2351 u8 atomic_like_write_en[0x1];
2352 u8 latency_sensitive[0x1];
2360 u8 min_rnr_nak[0x5];
2370 u8 reserved_10[0x4];
2371 u8 flow_label[0x14];
2373 u8 dc_access_key[0x40];
2375 u8 reserved_11[0x5];
2378 u8 pkey_index[0x10];
2380 u8 reserved_12[0x8];
2381 u8 my_addr_index[0x8];
2382 u8 reserved_13[0x8];
2385 u8 dc_access_key_violation_count[0x20];
2387 u8 reserved_14[0x14];
2393 u8 reserved_15[0x40];
2397 MLX5_CQC_STATUS_OK = 0x0,
2398 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2399 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2403 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2404 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2408 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2409 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2410 MLX5_CQC_ST_FIRED = 0xa,
2413 struct mlx5_ifc_cqc_bits {
2419 u8 scqe_break_moderation_en[0x1];
2423 u8 mini_cqe_res_format[0x2];
2427 u8 reserved_4[0x20];
2429 u8 reserved_5[0x14];
2430 u8 page_offset[0x6];
2434 u8 log_cq_size[0x5];
2439 u8 cq_max_count[0x10];
2441 u8 reserved_9[0x18];
2444 u8 reserved_10[0x3];
2445 u8 log_page_size[0x5];
2446 u8 reserved_11[0x18];
2448 u8 reserved_12[0x20];
2450 u8 reserved_13[0x8];
2451 u8 last_notified_index[0x18];
2453 u8 reserved_14[0x8];
2454 u8 last_solicit_index[0x18];
2456 u8 reserved_15[0x8];
2457 u8 consumer_counter[0x18];
2459 u8 reserved_16[0x8];
2460 u8 producer_counter[0x18];
2462 u8 reserved_17[0x40];
2467 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2468 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2469 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2470 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2471 u8 reserved_0[0x800];
2474 struct mlx5_ifc_query_adapter_param_block_bits {
2475 u8 reserved_0[0xc0];
2478 u8 ieee_vendor_id[0x18];
2480 u8 reserved_2[0x10];
2481 u8 vsd_vendor_id[0x10];
2485 u8 vsd_contd_psid[16][0x8];
2488 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2489 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2490 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2491 u8 reserved_0[0x20];
2494 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2495 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2496 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2497 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2498 u8 reserved_0[0x20];
2501 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2502 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2503 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2504 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2505 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2506 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2507 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2508 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2509 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2510 u8 reserved_0[0x7c0];
2513 union mlx5_ifc_event_auto_bits {
2514 struct mlx5_ifc_comp_event_bits comp_event;
2515 struct mlx5_ifc_dct_events_bits dct_events;
2516 struct mlx5_ifc_qp_events_bits qp_events;
2517 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2518 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2519 struct mlx5_ifc_cq_error_bits cq_error;
2520 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2521 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2522 struct mlx5_ifc_gpio_event_bits gpio_event;
2523 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2524 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2525 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2526 u8 reserved_0[0xe0];
2529 struct mlx5_ifc_health_buffer_bits {
2530 u8 reserved_0[0x100];
2532 u8 assert_existptr[0x20];
2534 u8 assert_callra[0x20];
2536 u8 reserved_1[0x40];
2538 u8 fw_version[0x20];
2542 u8 reserved_2[0x20];
2544 u8 irisc_index[0x8];
2549 struct mlx5_ifc_register_loopback_control_bits {
2553 u8 reserved_1[0x10];
2555 u8 reserved_2[0x60];
2558 struct mlx5_ifc_teardown_hca_out_bits {
2560 u8 reserved_0[0x18];
2564 u8 reserved_1[0x40];
2568 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2569 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2572 struct mlx5_ifc_teardown_hca_in_bits {
2574 u8 reserved_0[0x10];
2576 u8 reserved_1[0x10];
2579 u8 reserved_2[0x10];
2582 u8 reserved_3[0x20];
2585 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2587 u8 reserved_0[0x18];
2591 u8 reserved_1[0x40];
2594 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2596 u8 reserved_0[0x10];
2598 u8 reserved_1[0x10];
2604 u8 reserved_3[0x20];
2606 u8 opt_param_mask[0x20];
2608 u8 reserved_4[0x20];
2610 struct mlx5_ifc_qpc_bits qpc;
2612 u8 reserved_5[0x80];
2615 struct mlx5_ifc_sqd2rts_qp_out_bits {
2617 u8 reserved_0[0x18];
2621 u8 reserved_1[0x40];
2624 struct mlx5_ifc_sqd2rts_qp_in_bits {
2626 u8 reserved_0[0x10];
2628 u8 reserved_1[0x10];
2634 u8 reserved_3[0x20];
2636 u8 opt_param_mask[0x20];
2638 u8 reserved_4[0x20];
2640 struct mlx5_ifc_qpc_bits qpc;
2642 u8 reserved_5[0x80];
2645 struct mlx5_ifc_set_roce_address_out_bits {
2647 u8 reserved_0[0x18];
2651 u8 reserved_1[0x40];
2654 struct mlx5_ifc_set_roce_address_in_bits {
2656 u8 reserved_0[0x10];
2658 u8 reserved_1[0x10];
2661 u8 roce_address_index[0x10];
2662 u8 reserved_2[0x10];
2664 u8 reserved_3[0x20];
2666 struct mlx5_ifc_roce_addr_layout_bits roce_address;
2669 struct mlx5_ifc_set_mad_demux_out_bits {
2671 u8 reserved_0[0x18];
2675 u8 reserved_1[0x40];
2679 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
2680 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
2683 struct mlx5_ifc_set_mad_demux_in_bits {
2685 u8 reserved_0[0x10];
2687 u8 reserved_1[0x10];
2690 u8 reserved_2[0x20];
2694 u8 reserved_4[0x18];
2697 struct mlx5_ifc_set_l2_table_entry_out_bits {
2699 u8 reserved_0[0x18];
2703 u8 reserved_1[0x40];
2706 struct mlx5_ifc_set_l2_table_entry_in_bits {
2708 u8 reserved_0[0x10];
2710 u8 reserved_1[0x10];
2713 u8 reserved_2[0x60];
2716 u8 table_index[0x18];
2718 u8 reserved_4[0x20];
2720 u8 reserved_5[0x13];
2724 struct mlx5_ifc_mac_address_layout_bits mac_address;
2726 u8 reserved_6[0xc0];
2729 struct mlx5_ifc_set_issi_out_bits {
2731 u8 reserved_0[0x18];
2735 u8 reserved_1[0x40];
2738 struct mlx5_ifc_set_issi_in_bits {
2740 u8 reserved_0[0x10];
2742 u8 reserved_1[0x10];
2745 u8 reserved_2[0x10];
2746 u8 current_issi[0x10];
2748 u8 reserved_3[0x20];
2751 struct mlx5_ifc_set_hca_cap_out_bits {
2753 u8 reserved_0[0x18];
2757 u8 reserved_1[0x40];
2760 struct mlx5_ifc_set_hca_cap_in_bits {
2762 u8 reserved_0[0x10];
2764 u8 reserved_1[0x10];
2767 u8 reserved_2[0x40];
2769 union mlx5_ifc_hca_cap_union_bits capability;
2772 struct mlx5_ifc_set_fte_out_bits {
2774 u8 reserved_0[0x18];
2778 u8 reserved_1[0x40];
2781 struct mlx5_ifc_set_fte_in_bits {
2783 u8 reserved_0[0x10];
2785 u8 reserved_1[0x10];
2788 u8 reserved_2[0x40];
2791 u8 reserved_3[0x18];
2796 u8 reserved_5[0x40];
2798 u8 flow_index[0x20];
2800 u8 reserved_6[0xe0];
2802 struct mlx5_ifc_flow_context_bits flow_context;
2805 struct mlx5_ifc_rts2rts_qp_out_bits {
2807 u8 reserved_0[0x18];
2811 u8 reserved_1[0x40];
2814 struct mlx5_ifc_rts2rts_qp_in_bits {
2816 u8 reserved_0[0x10];
2818 u8 reserved_1[0x10];
2824 u8 reserved_3[0x20];
2826 u8 opt_param_mask[0x20];
2828 u8 reserved_4[0x20];
2830 struct mlx5_ifc_qpc_bits qpc;
2832 u8 reserved_5[0x80];
2835 struct mlx5_ifc_rtr2rts_qp_out_bits {
2837 u8 reserved_0[0x18];
2841 u8 reserved_1[0x40];
2844 struct mlx5_ifc_rtr2rts_qp_in_bits {
2846 u8 reserved_0[0x10];
2848 u8 reserved_1[0x10];
2854 u8 reserved_3[0x20];
2856 u8 opt_param_mask[0x20];
2858 u8 reserved_4[0x20];
2860 struct mlx5_ifc_qpc_bits qpc;
2862 u8 reserved_5[0x80];
2865 struct mlx5_ifc_rst2init_qp_out_bits {
2867 u8 reserved_0[0x18];
2871 u8 reserved_1[0x40];
2874 struct mlx5_ifc_rst2init_qp_in_bits {
2876 u8 reserved_0[0x10];
2878 u8 reserved_1[0x10];
2884 u8 reserved_3[0x20];
2886 u8 opt_param_mask[0x20];
2888 u8 reserved_4[0x20];
2890 struct mlx5_ifc_qpc_bits qpc;
2892 u8 reserved_5[0x80];
2895 struct mlx5_ifc_query_xrc_srq_out_bits {
2897 u8 reserved_0[0x18];
2901 u8 reserved_1[0x40];
2903 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
2905 u8 reserved_2[0x600];
2910 struct mlx5_ifc_query_xrc_srq_in_bits {
2912 u8 reserved_0[0x10];
2914 u8 reserved_1[0x10];
2920 u8 reserved_3[0x20];
2924 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
2925 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
2928 struct mlx5_ifc_query_vport_state_out_bits {
2930 u8 reserved_0[0x18];
2934 u8 reserved_1[0x20];
2936 u8 reserved_2[0x18];
2937 u8 admin_state[0x4];
2942 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
2945 struct mlx5_ifc_query_vport_state_in_bits {
2947 u8 reserved_0[0x10];
2949 u8 reserved_1[0x10];
2952 u8 other_vport[0x1];
2954 u8 vport_number[0x10];
2956 u8 reserved_3[0x20];
2959 struct mlx5_ifc_query_vport_counter_out_bits {
2961 u8 reserved_0[0x18];
2965 u8 reserved_1[0x40];
2967 struct mlx5_ifc_traffic_counter_bits received_errors;
2969 struct mlx5_ifc_traffic_counter_bits transmit_errors;
2971 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
2973 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
2975 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
2977 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
2979 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
2981 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
2983 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
2985 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
2987 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
2989 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
2991 u8 reserved_2[0xa00];
2995 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
2998 struct mlx5_ifc_query_vport_counter_in_bits {
3000 u8 reserved_0[0x10];
3002 u8 reserved_1[0x10];
3005 u8 other_vport[0x1];
3007 u8 vport_number[0x10];
3009 u8 reserved_3[0x60];
3012 u8 reserved_4[0x1f];
3014 u8 reserved_5[0x20];
3017 struct mlx5_ifc_query_tis_out_bits {
3019 u8 reserved_0[0x18];
3023 u8 reserved_1[0x40];
3025 struct mlx5_ifc_tisc_bits tis_context;
3028 struct mlx5_ifc_query_tis_in_bits {
3030 u8 reserved_0[0x10];
3032 u8 reserved_1[0x10];
3038 u8 reserved_3[0x20];
3041 struct mlx5_ifc_query_tir_out_bits {
3043 u8 reserved_0[0x18];
3047 u8 reserved_1[0xc0];
3049 struct mlx5_ifc_tirc_bits tir_context;
3052 struct mlx5_ifc_query_tir_in_bits {
3054 u8 reserved_0[0x10];
3056 u8 reserved_1[0x10];
3062 u8 reserved_3[0x20];
3065 struct mlx5_ifc_query_srq_out_bits {
3067 u8 reserved_0[0x18];
3071 u8 reserved_1[0x40];
3073 struct mlx5_ifc_srqc_bits srq_context_entry;
3075 u8 reserved_2[0x600];
3080 struct mlx5_ifc_query_srq_in_bits {
3082 u8 reserved_0[0x10];
3084 u8 reserved_1[0x10];
3090 u8 reserved_3[0x20];
3093 struct mlx5_ifc_query_sq_out_bits {
3095 u8 reserved_0[0x18];
3099 u8 reserved_1[0xc0];
3101 struct mlx5_ifc_sqc_bits sq_context;
3104 struct mlx5_ifc_query_sq_in_bits {
3106 u8 reserved_0[0x10];
3108 u8 reserved_1[0x10];
3114 u8 reserved_3[0x20];
3117 struct mlx5_ifc_query_special_contexts_out_bits {
3119 u8 reserved_0[0x18];
3123 u8 reserved_1[0x20];
3128 struct mlx5_ifc_query_special_contexts_in_bits {
3130 u8 reserved_0[0x10];
3132 u8 reserved_1[0x10];
3135 u8 reserved_2[0x40];
3138 struct mlx5_ifc_query_rqt_out_bits {
3140 u8 reserved_0[0x18];
3144 u8 reserved_1[0xc0];
3146 struct mlx5_ifc_rqtc_bits rqt_context;
3149 struct mlx5_ifc_query_rqt_in_bits {
3151 u8 reserved_0[0x10];
3153 u8 reserved_1[0x10];
3159 u8 reserved_3[0x20];
3162 struct mlx5_ifc_query_rq_out_bits {
3164 u8 reserved_0[0x18];
3168 u8 reserved_1[0xc0];
3170 struct mlx5_ifc_rqc_bits rq_context;
3173 struct mlx5_ifc_query_rq_in_bits {
3175 u8 reserved_0[0x10];
3177 u8 reserved_1[0x10];
3183 u8 reserved_3[0x20];
3186 struct mlx5_ifc_query_roce_address_out_bits {
3188 u8 reserved_0[0x18];
3192 u8 reserved_1[0x40];
3194 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3197 struct mlx5_ifc_query_roce_address_in_bits {
3199 u8 reserved_0[0x10];
3201 u8 reserved_1[0x10];
3204 u8 roce_address_index[0x10];
3205 u8 reserved_2[0x10];
3207 u8 reserved_3[0x20];
3210 struct mlx5_ifc_query_rmp_out_bits {
3212 u8 reserved_0[0x18];
3216 u8 reserved_1[0xc0];
3218 struct mlx5_ifc_rmpc_bits rmp_context;
3221 struct mlx5_ifc_query_rmp_in_bits {
3223 u8 reserved_0[0x10];
3225 u8 reserved_1[0x10];
3231 u8 reserved_3[0x20];
3234 struct mlx5_ifc_query_qp_out_bits {
3236 u8 reserved_0[0x18];
3240 u8 reserved_1[0x40];
3242 u8 opt_param_mask[0x20];
3244 u8 reserved_2[0x20];
3246 struct mlx5_ifc_qpc_bits qpc;
3248 u8 reserved_3[0x80];
3253 struct mlx5_ifc_query_qp_in_bits {
3255 u8 reserved_0[0x10];
3257 u8 reserved_1[0x10];
3263 u8 reserved_3[0x20];
3266 struct mlx5_ifc_query_q_counter_out_bits {
3268 u8 reserved_0[0x18];
3272 u8 reserved_1[0x40];
3274 u8 rx_write_requests[0x20];
3276 u8 reserved_2[0x20];
3278 u8 rx_read_requests[0x20];
3280 u8 reserved_3[0x20];
3282 u8 rx_atomic_requests[0x20];
3284 u8 reserved_4[0x20];
3286 u8 rx_dct_connect[0x20];
3288 u8 reserved_5[0x20];
3290 u8 out_of_buffer[0x20];
3292 u8 reserved_6[0x20];
3294 u8 out_of_sequence[0x20];
3296 u8 reserved_7[0x620];
3299 struct mlx5_ifc_query_q_counter_in_bits {
3301 u8 reserved_0[0x10];
3303 u8 reserved_1[0x10];
3306 u8 reserved_2[0x80];
3309 u8 reserved_3[0x1f];
3311 u8 reserved_4[0x18];
3312 u8 counter_set_id[0x8];
3315 struct mlx5_ifc_query_pages_out_bits {
3317 u8 reserved_0[0x18];
3321 u8 reserved_1[0x10];
3322 u8 function_id[0x10];
3328 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3329 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3330 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3333 struct mlx5_ifc_query_pages_in_bits {
3335 u8 reserved_0[0x10];
3337 u8 reserved_1[0x10];
3340 u8 reserved_2[0x10];
3341 u8 function_id[0x10];
3343 u8 reserved_3[0x20];
3346 struct mlx5_ifc_query_nic_vport_context_out_bits {
3348 u8 reserved_0[0x18];
3352 u8 reserved_1[0x40];
3354 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3357 struct mlx5_ifc_query_nic_vport_context_in_bits {
3359 u8 reserved_0[0x10];
3361 u8 reserved_1[0x10];
3364 u8 other_vport[0x1];
3366 u8 vport_number[0x10];
3369 u8 allowed_list_type[0x3];
3370 u8 reserved_4[0x18];
3373 struct mlx5_ifc_query_mkey_out_bits {
3375 u8 reserved_0[0x18];
3379 u8 reserved_1[0x40];
3381 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3383 u8 reserved_2[0x600];
3385 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3387 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3390 struct mlx5_ifc_query_mkey_in_bits {
3392 u8 reserved_0[0x10];
3394 u8 reserved_1[0x10];
3398 u8 mkey_index[0x18];
3401 u8 reserved_3[0x1f];
3404 struct mlx5_ifc_query_mad_demux_out_bits {
3406 u8 reserved_0[0x18];
3410 u8 reserved_1[0x40];
3412 u8 mad_dumux_parameters_block[0x20];
3415 struct mlx5_ifc_query_mad_demux_in_bits {
3417 u8 reserved_0[0x10];
3419 u8 reserved_1[0x10];
3422 u8 reserved_2[0x40];
3425 struct mlx5_ifc_query_l2_table_entry_out_bits {
3427 u8 reserved_0[0x18];
3431 u8 reserved_1[0xa0];
3433 u8 reserved_2[0x13];
3437 struct mlx5_ifc_mac_address_layout_bits mac_address;
3439 u8 reserved_3[0xc0];
3442 struct mlx5_ifc_query_l2_table_entry_in_bits {
3444 u8 reserved_0[0x10];
3446 u8 reserved_1[0x10];
3449 u8 reserved_2[0x60];
3452 u8 table_index[0x18];
3454 u8 reserved_4[0x140];
3457 struct mlx5_ifc_query_issi_out_bits {
3459 u8 reserved_0[0x18];
3463 u8 reserved_1[0x10];
3464 u8 current_issi[0x10];
3466 u8 reserved_2[0xa0];
3468 u8 supported_issi_reserved[76][0x8];
3469 u8 supported_issi_dw0[0x20];
3472 struct mlx5_ifc_query_issi_in_bits {
3474 u8 reserved_0[0x10];
3476 u8 reserved_1[0x10];
3479 u8 reserved_2[0x40];
3482 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3484 u8 reserved_0[0x18];
3488 u8 reserved_1[0x40];
3490 struct mlx5_ifc_pkey_bits pkey[0];
3493 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3495 u8 reserved_0[0x10];
3497 u8 reserved_1[0x10];
3500 u8 other_vport[0x1];
3503 u8 vport_number[0x10];
3505 u8 reserved_3[0x10];
3506 u8 pkey_index[0x10];
3509 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3511 u8 reserved_0[0x18];
3515 u8 reserved_1[0x20];
3518 u8 reserved_2[0x10];
3520 struct mlx5_ifc_array128_auto_bits gid[0];
3523 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3525 u8 reserved_0[0x10];
3527 u8 reserved_1[0x10];
3530 u8 other_vport[0x1];
3533 u8 vport_number[0x10];
3535 u8 reserved_3[0x10];
3539 struct mlx5_ifc_query_hca_vport_context_out_bits {
3541 u8 reserved_0[0x18];
3545 u8 reserved_1[0x40];
3547 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3550 struct mlx5_ifc_query_hca_vport_context_in_bits {
3552 u8 reserved_0[0x10];
3554 u8 reserved_1[0x10];
3557 u8 other_vport[0x1];
3560 u8 vport_number[0x10];
3562 u8 reserved_3[0x20];
3565 struct mlx5_ifc_query_hca_cap_out_bits {
3567 u8 reserved_0[0x18];
3571 u8 reserved_1[0x40];
3573 union mlx5_ifc_hca_cap_union_bits capability;
3576 struct mlx5_ifc_query_hca_cap_in_bits {
3578 u8 reserved_0[0x10];
3580 u8 reserved_1[0x10];
3583 u8 reserved_2[0x40];
3586 struct mlx5_ifc_query_flow_table_out_bits {
3588 u8 reserved_0[0x18];
3592 u8 reserved_1[0x80];
3599 u8 reserved_4[0x120];
3602 struct mlx5_ifc_query_flow_table_in_bits {
3604 u8 reserved_0[0x10];
3606 u8 reserved_1[0x10];
3609 u8 reserved_2[0x40];
3612 u8 reserved_3[0x18];
3617 u8 reserved_5[0x140];
3620 struct mlx5_ifc_query_fte_out_bits {
3622 u8 reserved_0[0x18];
3626 u8 reserved_1[0x1c0];
3628 struct mlx5_ifc_flow_context_bits flow_context;
3631 struct mlx5_ifc_query_fte_in_bits {
3633 u8 reserved_0[0x10];
3635 u8 reserved_1[0x10];
3638 u8 reserved_2[0x40];
3641 u8 reserved_3[0x18];
3646 u8 reserved_5[0x40];
3648 u8 flow_index[0x20];
3650 u8 reserved_6[0xe0];
3654 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
3655 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
3656 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
3659 struct mlx5_ifc_query_flow_group_out_bits {
3661 u8 reserved_0[0x18];
3665 u8 reserved_1[0xa0];
3667 u8 start_flow_index[0x20];
3669 u8 reserved_2[0x20];
3671 u8 end_flow_index[0x20];
3673 u8 reserved_3[0xa0];
3675 u8 reserved_4[0x18];
3676 u8 match_criteria_enable[0x8];
3678 struct mlx5_ifc_fte_match_param_bits match_criteria;
3680 u8 reserved_5[0xe00];
3683 struct mlx5_ifc_query_flow_group_in_bits {
3685 u8 reserved_0[0x10];
3687 u8 reserved_1[0x10];
3690 u8 reserved_2[0x40];
3693 u8 reserved_3[0x18];
3700 u8 reserved_5[0x120];
3703 struct mlx5_ifc_query_eq_out_bits {
3705 u8 reserved_0[0x18];
3709 u8 reserved_1[0x40];
3711 struct mlx5_ifc_eqc_bits eq_context_entry;
3713 u8 reserved_2[0x40];
3715 u8 event_bitmask[0x40];
3717 u8 reserved_3[0x580];
3722 struct mlx5_ifc_query_eq_in_bits {
3724 u8 reserved_0[0x10];
3726 u8 reserved_1[0x10];
3729 u8 reserved_2[0x18];
3732 u8 reserved_3[0x20];
3735 struct mlx5_ifc_query_dct_out_bits {
3737 u8 reserved_0[0x18];
3741 u8 reserved_1[0x40];
3743 struct mlx5_ifc_dctc_bits dct_context_entry;
3745 u8 reserved_2[0x180];
3748 struct mlx5_ifc_query_dct_in_bits {
3750 u8 reserved_0[0x10];
3752 u8 reserved_1[0x10];
3758 u8 reserved_3[0x20];
3761 struct mlx5_ifc_query_cq_out_bits {
3763 u8 reserved_0[0x18];
3767 u8 reserved_1[0x40];
3769 struct mlx5_ifc_cqc_bits cq_context;
3771 u8 reserved_2[0x600];
3776 struct mlx5_ifc_query_cq_in_bits {
3778 u8 reserved_0[0x10];
3780 u8 reserved_1[0x10];
3786 u8 reserved_3[0x20];
3789 struct mlx5_ifc_query_cong_status_out_bits {
3791 u8 reserved_0[0x18];
3795 u8 reserved_1[0x20];
3799 u8 reserved_2[0x1e];
3802 struct mlx5_ifc_query_cong_status_in_bits {
3804 u8 reserved_0[0x10];
3806 u8 reserved_1[0x10];
3809 u8 reserved_2[0x18];
3811 u8 cong_protocol[0x4];
3813 u8 reserved_3[0x20];
3816 struct mlx5_ifc_query_cong_statistics_out_bits {
3818 u8 reserved_0[0x18];
3822 u8 reserved_1[0x40];
3828 u8 cnp_ignored_high[0x20];
3830 u8 cnp_ignored_low[0x20];
3832 u8 cnp_handled_high[0x20];
3834 u8 cnp_handled_low[0x20];
3836 u8 reserved_2[0x100];
3838 u8 time_stamp_high[0x20];
3840 u8 time_stamp_low[0x20];
3842 u8 accumulators_period[0x20];
3844 u8 ecn_marked_roce_packets_high[0x20];
3846 u8 ecn_marked_roce_packets_low[0x20];
3848 u8 cnps_sent_high[0x20];
3850 u8 cnps_sent_low[0x20];
3852 u8 reserved_3[0x560];
3855 struct mlx5_ifc_query_cong_statistics_in_bits {
3857 u8 reserved_0[0x10];
3859 u8 reserved_1[0x10];
3863 u8 reserved_2[0x1f];
3865 u8 reserved_3[0x20];
3868 struct mlx5_ifc_query_cong_params_out_bits {
3870 u8 reserved_0[0x18];
3874 u8 reserved_1[0x40];
3876 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
3879 struct mlx5_ifc_query_cong_params_in_bits {
3881 u8 reserved_0[0x10];
3883 u8 reserved_1[0x10];
3886 u8 reserved_2[0x1c];
3887 u8 cong_protocol[0x4];
3889 u8 reserved_3[0x20];
3892 struct mlx5_ifc_query_adapter_out_bits {
3894 u8 reserved_0[0x18];
3898 u8 reserved_1[0x40];
3900 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
3903 struct mlx5_ifc_query_adapter_in_bits {
3905 u8 reserved_0[0x10];
3907 u8 reserved_1[0x10];
3910 u8 reserved_2[0x40];
3913 struct mlx5_ifc_qp_2rst_out_bits {
3915 u8 reserved_0[0x18];
3919 u8 reserved_1[0x40];
3922 struct mlx5_ifc_qp_2rst_in_bits {
3924 u8 reserved_0[0x10];
3926 u8 reserved_1[0x10];
3932 u8 reserved_3[0x20];
3935 struct mlx5_ifc_qp_2err_out_bits {
3937 u8 reserved_0[0x18];
3941 u8 reserved_1[0x40];
3944 struct mlx5_ifc_qp_2err_in_bits {
3946 u8 reserved_0[0x10];
3948 u8 reserved_1[0x10];
3954 u8 reserved_3[0x20];
3957 struct mlx5_ifc_page_fault_resume_out_bits {
3959 u8 reserved_0[0x18];
3963 u8 reserved_1[0x40];
3966 struct mlx5_ifc_page_fault_resume_in_bits {
3968 u8 reserved_0[0x10];
3970 u8 reserved_1[0x10];
3980 u8 reserved_3[0x20];
3983 struct mlx5_ifc_nop_out_bits {
3985 u8 reserved_0[0x18];
3989 u8 reserved_1[0x40];
3992 struct mlx5_ifc_nop_in_bits {
3994 u8 reserved_0[0x10];
3996 u8 reserved_1[0x10];
3999 u8 reserved_2[0x40];
4002 struct mlx5_ifc_modify_vport_state_out_bits {
4004 u8 reserved_0[0x18];
4008 u8 reserved_1[0x40];
4011 struct mlx5_ifc_modify_vport_state_in_bits {
4013 u8 reserved_0[0x10];
4015 u8 reserved_1[0x10];
4018 u8 other_vport[0x1];
4020 u8 vport_number[0x10];
4022 u8 reserved_3[0x18];
4023 u8 admin_state[0x4];
4027 struct mlx5_ifc_modify_tis_out_bits {
4029 u8 reserved_0[0x18];
4033 u8 reserved_1[0x40];
4036 struct mlx5_ifc_modify_tis_in_bits {
4038 u8 reserved_0[0x10];
4040 u8 reserved_1[0x10];
4046 u8 reserved_3[0x20];
4048 u8 modify_bitmask[0x40];
4050 u8 reserved_4[0x40];
4052 struct mlx5_ifc_tisc_bits ctx;
4055 struct mlx5_ifc_modify_tir_bitmask_bits {
4056 u8 reserved_0[0x20];
4058 u8 reserved_1[0x1b];
4064 struct mlx5_ifc_modify_tir_out_bits {
4066 u8 reserved_0[0x18];
4070 u8 reserved_1[0x40];
4073 struct mlx5_ifc_modify_tir_in_bits {
4075 u8 reserved_0[0x10];
4077 u8 reserved_1[0x10];
4083 u8 reserved_3[0x20];
4085 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4087 u8 reserved_4[0x40];
4089 struct mlx5_ifc_tirc_bits ctx;
4092 struct mlx5_ifc_modify_sq_out_bits {
4094 u8 reserved_0[0x18];
4098 u8 reserved_1[0x40];
4101 struct mlx5_ifc_modify_sq_in_bits {
4103 u8 reserved_0[0x10];
4105 u8 reserved_1[0x10];
4112 u8 reserved_3[0x20];
4114 u8 modify_bitmask[0x40];
4116 u8 reserved_4[0x40];
4118 struct mlx5_ifc_sqc_bits ctx;
4121 struct mlx5_ifc_modify_rqt_out_bits {
4123 u8 reserved_0[0x18];
4127 u8 reserved_1[0x40];
4130 struct mlx5_ifc_rqt_bitmask_bits {
4137 struct mlx5_ifc_modify_rqt_in_bits {
4139 u8 reserved_0[0x10];
4141 u8 reserved_1[0x10];
4147 u8 reserved_3[0x20];
4149 struct mlx5_ifc_rqt_bitmask_bits bitmask;
4151 u8 reserved_4[0x40];
4153 struct mlx5_ifc_rqtc_bits ctx;
4156 struct mlx5_ifc_modify_rq_out_bits {
4158 u8 reserved_0[0x18];
4162 u8 reserved_1[0x40];
4165 struct mlx5_ifc_modify_rq_in_bits {
4167 u8 reserved_0[0x10];
4169 u8 reserved_1[0x10];
4176 u8 reserved_3[0x20];
4178 u8 modify_bitmask[0x40];
4180 u8 reserved_4[0x40];
4182 struct mlx5_ifc_rqc_bits ctx;
4185 struct mlx5_ifc_modify_rmp_out_bits {
4187 u8 reserved_0[0x18];
4191 u8 reserved_1[0x40];
4194 struct mlx5_ifc_rmp_bitmask_bits {
4201 struct mlx5_ifc_modify_rmp_in_bits {
4203 u8 reserved_0[0x10];
4205 u8 reserved_1[0x10];
4212 u8 reserved_3[0x20];
4214 struct mlx5_ifc_rmp_bitmask_bits bitmask;
4216 u8 reserved_4[0x40];
4218 struct mlx5_ifc_rmpc_bits ctx;
4221 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4223 u8 reserved_0[0x18];
4227 u8 reserved_1[0x40];
4230 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4231 u8 reserved_0[0x1c];
4232 u8 permanent_address[0x1];
4233 u8 addresses_list[0x1];
4238 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4240 u8 reserved_0[0x10];
4242 u8 reserved_1[0x10];
4245 u8 other_vport[0x1];
4247 u8 vport_number[0x10];
4249 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4251 u8 reserved_3[0x780];
4253 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4256 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4258 u8 reserved_0[0x18];
4262 u8 reserved_1[0x40];
4265 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4267 u8 reserved_0[0x10];
4269 u8 reserved_1[0x10];
4272 u8 other_vport[0x1];
4275 u8 vport_number[0x10];
4277 u8 reserved_3[0x20];
4279 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4282 struct mlx5_ifc_modify_cq_out_bits {
4284 u8 reserved_0[0x18];
4288 u8 reserved_1[0x40];
4292 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4293 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4296 struct mlx5_ifc_modify_cq_in_bits {
4298 u8 reserved_0[0x10];
4300 u8 reserved_1[0x10];
4306 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4308 struct mlx5_ifc_cqc_bits cq_context;
4310 u8 reserved_3[0x600];
4315 struct mlx5_ifc_modify_cong_status_out_bits {
4317 u8 reserved_0[0x18];
4321 u8 reserved_1[0x40];
4324 struct mlx5_ifc_modify_cong_status_in_bits {
4326 u8 reserved_0[0x10];
4328 u8 reserved_1[0x10];
4331 u8 reserved_2[0x18];
4333 u8 cong_protocol[0x4];
4337 u8 reserved_3[0x1e];
4340 struct mlx5_ifc_modify_cong_params_out_bits {
4342 u8 reserved_0[0x18];
4346 u8 reserved_1[0x40];
4349 struct mlx5_ifc_modify_cong_params_in_bits {
4351 u8 reserved_0[0x10];
4353 u8 reserved_1[0x10];
4356 u8 reserved_2[0x1c];
4357 u8 cong_protocol[0x4];
4359 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4361 u8 reserved_3[0x80];
4363 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4366 struct mlx5_ifc_manage_pages_out_bits {
4368 u8 reserved_0[0x18];
4372 u8 output_num_entries[0x20];
4374 u8 reserved_1[0x20];
4380 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4381 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4382 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4385 struct mlx5_ifc_manage_pages_in_bits {
4387 u8 reserved_0[0x10];
4389 u8 reserved_1[0x10];
4392 u8 reserved_2[0x10];
4393 u8 function_id[0x10];
4395 u8 input_num_entries[0x20];
4400 struct mlx5_ifc_mad_ifc_out_bits {
4402 u8 reserved_0[0x18];
4406 u8 reserved_1[0x40];
4408 u8 response_mad_packet[256][0x8];
4411 struct mlx5_ifc_mad_ifc_in_bits {
4413 u8 reserved_0[0x10];
4415 u8 reserved_1[0x10];
4418 u8 remote_lid[0x10];
4422 u8 reserved_3[0x20];
4427 struct mlx5_ifc_init_hca_out_bits {
4429 u8 reserved_0[0x18];
4433 u8 reserved_1[0x40];
4436 struct mlx5_ifc_init_hca_in_bits {
4438 u8 reserved_0[0x10];
4440 u8 reserved_1[0x10];
4443 u8 reserved_2[0x40];
4446 struct mlx5_ifc_init2rtr_qp_out_bits {
4448 u8 reserved_0[0x18];
4452 u8 reserved_1[0x40];
4455 struct mlx5_ifc_init2rtr_qp_in_bits {
4457 u8 reserved_0[0x10];
4459 u8 reserved_1[0x10];
4465 u8 reserved_3[0x20];
4467 u8 opt_param_mask[0x20];
4469 u8 reserved_4[0x20];
4471 struct mlx5_ifc_qpc_bits qpc;
4473 u8 reserved_5[0x80];
4476 struct mlx5_ifc_init2init_qp_out_bits {
4478 u8 reserved_0[0x18];
4482 u8 reserved_1[0x40];
4485 struct mlx5_ifc_init2init_qp_in_bits {
4487 u8 reserved_0[0x10];
4489 u8 reserved_1[0x10];
4495 u8 reserved_3[0x20];
4497 u8 opt_param_mask[0x20];
4499 u8 reserved_4[0x20];
4501 struct mlx5_ifc_qpc_bits qpc;
4503 u8 reserved_5[0x80];
4506 struct mlx5_ifc_get_dropped_packet_log_out_bits {
4508 u8 reserved_0[0x18];
4512 u8 reserved_1[0x40];
4514 u8 packet_headers_log[128][0x8];
4516 u8 packet_syndrome[64][0x8];
4519 struct mlx5_ifc_get_dropped_packet_log_in_bits {
4521 u8 reserved_0[0x10];
4523 u8 reserved_1[0x10];
4526 u8 reserved_2[0x40];
4529 struct mlx5_ifc_gen_eqe_in_bits {
4531 u8 reserved_0[0x10];
4533 u8 reserved_1[0x10];
4536 u8 reserved_2[0x18];
4539 u8 reserved_3[0x20];
4544 struct mlx5_ifc_gen_eq_out_bits {
4546 u8 reserved_0[0x18];
4550 u8 reserved_1[0x40];
4553 struct mlx5_ifc_enable_hca_out_bits {
4555 u8 reserved_0[0x18];
4559 u8 reserved_1[0x20];
4562 struct mlx5_ifc_enable_hca_in_bits {
4564 u8 reserved_0[0x10];
4566 u8 reserved_1[0x10];
4569 u8 reserved_2[0x10];
4570 u8 function_id[0x10];
4572 u8 reserved_3[0x20];
4575 struct mlx5_ifc_drain_dct_out_bits {
4577 u8 reserved_0[0x18];
4581 u8 reserved_1[0x40];
4584 struct mlx5_ifc_drain_dct_in_bits {
4586 u8 reserved_0[0x10];
4588 u8 reserved_1[0x10];
4594 u8 reserved_3[0x20];
4597 struct mlx5_ifc_disable_hca_out_bits {
4599 u8 reserved_0[0x18];
4603 u8 reserved_1[0x20];
4606 struct mlx5_ifc_disable_hca_in_bits {
4608 u8 reserved_0[0x10];
4610 u8 reserved_1[0x10];
4613 u8 reserved_2[0x10];
4614 u8 function_id[0x10];
4616 u8 reserved_3[0x20];
4619 struct mlx5_ifc_detach_from_mcg_out_bits {
4621 u8 reserved_0[0x18];
4625 u8 reserved_1[0x40];
4628 struct mlx5_ifc_detach_from_mcg_in_bits {
4630 u8 reserved_0[0x10];
4632 u8 reserved_1[0x10];
4638 u8 reserved_3[0x20];
4640 u8 multicast_gid[16][0x8];
4643 struct mlx5_ifc_destroy_xrc_srq_out_bits {
4645 u8 reserved_0[0x18];
4649 u8 reserved_1[0x40];
4652 struct mlx5_ifc_destroy_xrc_srq_in_bits {
4654 u8 reserved_0[0x10];
4656 u8 reserved_1[0x10];
4662 u8 reserved_3[0x20];
4665 struct mlx5_ifc_destroy_tis_out_bits {
4667 u8 reserved_0[0x18];
4671 u8 reserved_1[0x40];
4674 struct mlx5_ifc_destroy_tis_in_bits {
4676 u8 reserved_0[0x10];
4678 u8 reserved_1[0x10];
4684 u8 reserved_3[0x20];
4687 struct mlx5_ifc_destroy_tir_out_bits {
4689 u8 reserved_0[0x18];
4693 u8 reserved_1[0x40];
4696 struct mlx5_ifc_destroy_tir_in_bits {
4698 u8 reserved_0[0x10];
4700 u8 reserved_1[0x10];
4706 u8 reserved_3[0x20];
4709 struct mlx5_ifc_destroy_srq_out_bits {
4711 u8 reserved_0[0x18];
4715 u8 reserved_1[0x40];
4718 struct mlx5_ifc_destroy_srq_in_bits {
4720 u8 reserved_0[0x10];
4722 u8 reserved_1[0x10];
4728 u8 reserved_3[0x20];
4731 struct mlx5_ifc_destroy_sq_out_bits {
4733 u8 reserved_0[0x18];
4737 u8 reserved_1[0x40];
4740 struct mlx5_ifc_destroy_sq_in_bits {
4742 u8 reserved_0[0x10];
4744 u8 reserved_1[0x10];
4750 u8 reserved_3[0x20];
4753 struct mlx5_ifc_destroy_rqt_out_bits {
4755 u8 reserved_0[0x18];
4759 u8 reserved_1[0x40];
4762 struct mlx5_ifc_destroy_rqt_in_bits {
4764 u8 reserved_0[0x10];
4766 u8 reserved_1[0x10];
4772 u8 reserved_3[0x20];
4775 struct mlx5_ifc_destroy_rq_out_bits {
4777 u8 reserved_0[0x18];
4781 u8 reserved_1[0x40];
4784 struct mlx5_ifc_destroy_rq_in_bits {
4786 u8 reserved_0[0x10];
4788 u8 reserved_1[0x10];
4794 u8 reserved_3[0x20];
4797 struct mlx5_ifc_destroy_rmp_out_bits {
4799 u8 reserved_0[0x18];
4803 u8 reserved_1[0x40];
4806 struct mlx5_ifc_destroy_rmp_in_bits {
4808 u8 reserved_0[0x10];
4810 u8 reserved_1[0x10];
4816 u8 reserved_3[0x20];
4819 struct mlx5_ifc_destroy_qp_out_bits {
4821 u8 reserved_0[0x18];
4825 u8 reserved_1[0x40];
4828 struct mlx5_ifc_destroy_qp_in_bits {
4830 u8 reserved_0[0x10];
4832 u8 reserved_1[0x10];
4838 u8 reserved_3[0x20];
4841 struct mlx5_ifc_destroy_psv_out_bits {
4843 u8 reserved_0[0x18];
4847 u8 reserved_1[0x40];
4850 struct mlx5_ifc_destroy_psv_in_bits {
4852 u8 reserved_0[0x10];
4854 u8 reserved_1[0x10];
4860 u8 reserved_3[0x20];
4863 struct mlx5_ifc_destroy_mkey_out_bits {
4865 u8 reserved_0[0x18];
4869 u8 reserved_1[0x40];
4872 struct mlx5_ifc_destroy_mkey_in_bits {
4874 u8 reserved_0[0x10];
4876 u8 reserved_1[0x10];
4880 u8 mkey_index[0x18];
4882 u8 reserved_3[0x20];
4885 struct mlx5_ifc_destroy_flow_table_out_bits {
4887 u8 reserved_0[0x18];
4891 u8 reserved_1[0x40];
4894 struct mlx5_ifc_destroy_flow_table_in_bits {
4896 u8 reserved_0[0x10];
4898 u8 reserved_1[0x10];
4901 u8 reserved_2[0x40];
4904 u8 reserved_3[0x18];
4909 u8 reserved_5[0x140];
4912 struct mlx5_ifc_destroy_flow_group_out_bits {
4914 u8 reserved_0[0x18];
4918 u8 reserved_1[0x40];
4921 struct mlx5_ifc_destroy_flow_group_in_bits {
4923 u8 reserved_0[0x10];
4925 u8 reserved_1[0x10];
4928 u8 reserved_2[0x40];
4931 u8 reserved_3[0x18];
4938 u8 reserved_5[0x120];
4941 struct mlx5_ifc_destroy_eq_out_bits {
4943 u8 reserved_0[0x18];
4947 u8 reserved_1[0x40];
4950 struct mlx5_ifc_destroy_eq_in_bits {
4952 u8 reserved_0[0x10];
4954 u8 reserved_1[0x10];
4957 u8 reserved_2[0x18];
4960 u8 reserved_3[0x20];
4963 struct mlx5_ifc_destroy_dct_out_bits {
4965 u8 reserved_0[0x18];
4969 u8 reserved_1[0x40];
4972 struct mlx5_ifc_destroy_dct_in_bits {
4974 u8 reserved_0[0x10];
4976 u8 reserved_1[0x10];
4982 u8 reserved_3[0x20];
4985 struct mlx5_ifc_destroy_cq_out_bits {
4987 u8 reserved_0[0x18];
4991 u8 reserved_1[0x40];
4994 struct mlx5_ifc_destroy_cq_in_bits {
4996 u8 reserved_0[0x10];
4998 u8 reserved_1[0x10];
5004 u8 reserved_3[0x20];
5007 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5009 u8 reserved_0[0x18];
5013 u8 reserved_1[0x40];
5016 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5018 u8 reserved_0[0x10];
5020 u8 reserved_1[0x10];
5023 u8 reserved_2[0x20];
5025 u8 reserved_3[0x10];
5026 u8 vxlan_udp_port[0x10];
5029 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5031 u8 reserved_0[0x18];
5035 u8 reserved_1[0x40];
5038 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5040 u8 reserved_0[0x10];
5042 u8 reserved_1[0x10];
5045 u8 reserved_2[0x60];
5048 u8 table_index[0x18];
5050 u8 reserved_4[0x140];
5053 struct mlx5_ifc_delete_fte_out_bits {
5055 u8 reserved_0[0x18];
5059 u8 reserved_1[0x40];
5062 struct mlx5_ifc_delete_fte_in_bits {
5064 u8 reserved_0[0x10];
5066 u8 reserved_1[0x10];
5069 u8 reserved_2[0x40];
5072 u8 reserved_3[0x18];
5077 u8 reserved_5[0x40];
5079 u8 flow_index[0x20];
5081 u8 reserved_6[0xe0];
5084 struct mlx5_ifc_dealloc_xrcd_out_bits {
5086 u8 reserved_0[0x18];
5090 u8 reserved_1[0x40];
5093 struct mlx5_ifc_dealloc_xrcd_in_bits {
5095 u8 reserved_0[0x10];
5097 u8 reserved_1[0x10];
5103 u8 reserved_3[0x20];
5106 struct mlx5_ifc_dealloc_uar_out_bits {
5108 u8 reserved_0[0x18];
5112 u8 reserved_1[0x40];
5115 struct mlx5_ifc_dealloc_uar_in_bits {
5117 u8 reserved_0[0x10];
5119 u8 reserved_1[0x10];
5125 u8 reserved_3[0x20];
5128 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5130 u8 reserved_0[0x18];
5134 u8 reserved_1[0x40];
5137 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5139 u8 reserved_0[0x10];
5141 u8 reserved_1[0x10];
5145 u8 transport_domain[0x18];
5147 u8 reserved_3[0x20];
5150 struct mlx5_ifc_dealloc_q_counter_out_bits {
5152 u8 reserved_0[0x18];
5156 u8 reserved_1[0x40];
5159 struct mlx5_ifc_dealloc_q_counter_in_bits {
5161 u8 reserved_0[0x10];
5163 u8 reserved_1[0x10];
5166 u8 reserved_2[0x18];
5167 u8 counter_set_id[0x8];
5169 u8 reserved_3[0x20];
5172 struct mlx5_ifc_dealloc_pd_out_bits {
5174 u8 reserved_0[0x18];
5178 u8 reserved_1[0x40];
5181 struct mlx5_ifc_dealloc_pd_in_bits {
5183 u8 reserved_0[0x10];
5185 u8 reserved_1[0x10];
5191 u8 reserved_3[0x20];
5194 struct mlx5_ifc_create_xrc_srq_out_bits {
5196 u8 reserved_0[0x18];
5203 u8 reserved_2[0x20];
5206 struct mlx5_ifc_create_xrc_srq_in_bits {
5208 u8 reserved_0[0x10];
5210 u8 reserved_1[0x10];
5213 u8 reserved_2[0x40];
5215 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5217 u8 reserved_3[0x600];
5222 struct mlx5_ifc_create_tis_out_bits {
5224 u8 reserved_0[0x18];
5231 u8 reserved_2[0x20];
5234 struct mlx5_ifc_create_tis_in_bits {
5236 u8 reserved_0[0x10];
5238 u8 reserved_1[0x10];
5241 u8 reserved_2[0xc0];
5243 struct mlx5_ifc_tisc_bits ctx;
5246 struct mlx5_ifc_create_tir_out_bits {
5248 u8 reserved_0[0x18];
5255 u8 reserved_2[0x20];
5258 struct mlx5_ifc_create_tir_in_bits {
5260 u8 reserved_0[0x10];
5262 u8 reserved_1[0x10];
5265 u8 reserved_2[0xc0];
5267 struct mlx5_ifc_tirc_bits ctx;
5270 struct mlx5_ifc_create_srq_out_bits {
5272 u8 reserved_0[0x18];
5279 u8 reserved_2[0x20];
5282 struct mlx5_ifc_create_srq_in_bits {
5284 u8 reserved_0[0x10];
5286 u8 reserved_1[0x10];
5289 u8 reserved_2[0x40];
5291 struct mlx5_ifc_srqc_bits srq_context_entry;
5293 u8 reserved_3[0x600];
5298 struct mlx5_ifc_create_sq_out_bits {
5300 u8 reserved_0[0x18];
5307 u8 reserved_2[0x20];
5310 struct mlx5_ifc_create_sq_in_bits {
5312 u8 reserved_0[0x10];
5314 u8 reserved_1[0x10];
5317 u8 reserved_2[0xc0];
5319 struct mlx5_ifc_sqc_bits ctx;
5322 struct mlx5_ifc_create_rqt_out_bits {
5324 u8 reserved_0[0x18];
5331 u8 reserved_2[0x20];
5334 struct mlx5_ifc_create_rqt_in_bits {
5336 u8 reserved_0[0x10];
5338 u8 reserved_1[0x10];
5341 u8 reserved_2[0xc0];
5343 struct mlx5_ifc_rqtc_bits rqt_context;
5346 struct mlx5_ifc_create_rq_out_bits {
5348 u8 reserved_0[0x18];
5355 u8 reserved_2[0x20];
5358 struct mlx5_ifc_create_rq_in_bits {
5360 u8 reserved_0[0x10];
5362 u8 reserved_1[0x10];
5365 u8 reserved_2[0xc0];
5367 struct mlx5_ifc_rqc_bits ctx;
5370 struct mlx5_ifc_create_rmp_out_bits {
5372 u8 reserved_0[0x18];
5379 u8 reserved_2[0x20];
5382 struct mlx5_ifc_create_rmp_in_bits {
5384 u8 reserved_0[0x10];
5386 u8 reserved_1[0x10];
5389 u8 reserved_2[0xc0];
5391 struct mlx5_ifc_rmpc_bits ctx;
5394 struct mlx5_ifc_create_qp_out_bits {
5396 u8 reserved_0[0x18];
5403 u8 reserved_2[0x20];
5406 struct mlx5_ifc_create_qp_in_bits {
5408 u8 reserved_0[0x10];
5410 u8 reserved_1[0x10];
5413 u8 reserved_2[0x40];
5415 u8 opt_param_mask[0x20];
5417 u8 reserved_3[0x20];
5419 struct mlx5_ifc_qpc_bits qpc;
5421 u8 reserved_4[0x80];
5426 struct mlx5_ifc_create_psv_out_bits {
5428 u8 reserved_0[0x18];
5432 u8 reserved_1[0x40];
5435 u8 psv0_index[0x18];
5438 u8 psv1_index[0x18];
5441 u8 psv2_index[0x18];
5444 u8 psv3_index[0x18];
5447 struct mlx5_ifc_create_psv_in_bits {
5449 u8 reserved_0[0x10];
5451 u8 reserved_1[0x10];
5458 u8 reserved_3[0x20];
5461 struct mlx5_ifc_create_mkey_out_bits {
5463 u8 reserved_0[0x18];
5468 u8 mkey_index[0x18];
5470 u8 reserved_2[0x20];
5473 struct mlx5_ifc_create_mkey_in_bits {
5475 u8 reserved_0[0x10];
5477 u8 reserved_1[0x10];
5480 u8 reserved_2[0x20];
5483 u8 reserved_3[0x1f];
5485 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5487 u8 reserved_4[0x80];
5489 u8 translations_octword_actual_size[0x20];
5491 u8 reserved_5[0x560];
5493 u8 klm_pas_mtt[0][0x20];
5496 struct mlx5_ifc_create_flow_table_out_bits {
5498 u8 reserved_0[0x18];
5505 u8 reserved_2[0x20];
5508 struct mlx5_ifc_create_flow_table_in_bits {
5510 u8 reserved_0[0x10];
5512 u8 reserved_1[0x10];
5515 u8 reserved_2[0x40];
5518 u8 reserved_3[0x18];
5520 u8 reserved_4[0x20];
5527 u8 reserved_7[0x120];
5530 struct mlx5_ifc_create_flow_group_out_bits {
5532 u8 reserved_0[0x18];
5539 u8 reserved_2[0x20];
5543 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5544 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5545 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5548 struct mlx5_ifc_create_flow_group_in_bits {
5550 u8 reserved_0[0x10];
5552 u8 reserved_1[0x10];
5555 u8 reserved_2[0x40];
5558 u8 reserved_3[0x18];
5563 u8 reserved_5[0x20];
5565 u8 start_flow_index[0x20];
5567 u8 reserved_6[0x20];
5569 u8 end_flow_index[0x20];
5571 u8 reserved_7[0xa0];
5573 u8 reserved_8[0x18];
5574 u8 match_criteria_enable[0x8];
5576 struct mlx5_ifc_fte_match_param_bits match_criteria;
5578 u8 reserved_9[0xe00];
5581 struct mlx5_ifc_create_eq_out_bits {
5583 u8 reserved_0[0x18];
5587 u8 reserved_1[0x18];
5590 u8 reserved_2[0x20];
5593 struct mlx5_ifc_create_eq_in_bits {
5595 u8 reserved_0[0x10];
5597 u8 reserved_1[0x10];
5600 u8 reserved_2[0x40];
5602 struct mlx5_ifc_eqc_bits eq_context_entry;
5604 u8 reserved_3[0x40];
5606 u8 event_bitmask[0x40];
5608 u8 reserved_4[0x580];
5613 struct mlx5_ifc_create_dct_out_bits {
5615 u8 reserved_0[0x18];
5622 u8 reserved_2[0x20];
5625 struct mlx5_ifc_create_dct_in_bits {
5627 u8 reserved_0[0x10];
5629 u8 reserved_1[0x10];
5632 u8 reserved_2[0x40];
5634 struct mlx5_ifc_dctc_bits dct_context_entry;
5636 u8 reserved_3[0x180];
5639 struct mlx5_ifc_create_cq_out_bits {
5641 u8 reserved_0[0x18];
5648 u8 reserved_2[0x20];
5651 struct mlx5_ifc_create_cq_in_bits {
5653 u8 reserved_0[0x10];
5655 u8 reserved_1[0x10];
5658 u8 reserved_2[0x40];
5660 struct mlx5_ifc_cqc_bits cq_context;
5662 u8 reserved_3[0x600];
5667 struct mlx5_ifc_config_int_moderation_out_bits {
5669 u8 reserved_0[0x18];
5675 u8 int_vector[0x10];
5677 u8 reserved_2[0x20];
5681 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
5682 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
5685 struct mlx5_ifc_config_int_moderation_in_bits {
5687 u8 reserved_0[0x10];
5689 u8 reserved_1[0x10];
5694 u8 int_vector[0x10];
5696 u8 reserved_3[0x20];
5699 struct mlx5_ifc_attach_to_mcg_out_bits {
5701 u8 reserved_0[0x18];
5705 u8 reserved_1[0x40];
5708 struct mlx5_ifc_attach_to_mcg_in_bits {
5710 u8 reserved_0[0x10];
5712 u8 reserved_1[0x10];
5718 u8 reserved_3[0x20];
5720 u8 multicast_gid[16][0x8];
5723 struct mlx5_ifc_arm_xrc_srq_out_bits {
5725 u8 reserved_0[0x18];
5729 u8 reserved_1[0x40];
5733 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
5736 struct mlx5_ifc_arm_xrc_srq_in_bits {
5738 u8 reserved_0[0x10];
5740 u8 reserved_1[0x10];
5746 u8 reserved_3[0x10];
5750 struct mlx5_ifc_arm_rq_out_bits {
5752 u8 reserved_0[0x18];
5756 u8 reserved_1[0x40];
5760 MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1,
5763 struct mlx5_ifc_arm_rq_in_bits {
5765 u8 reserved_0[0x10];
5767 u8 reserved_1[0x10];
5771 u8 srq_number[0x18];
5773 u8 reserved_3[0x10];
5777 struct mlx5_ifc_arm_dct_out_bits {
5779 u8 reserved_0[0x18];
5783 u8 reserved_1[0x40];
5786 struct mlx5_ifc_arm_dct_in_bits {
5788 u8 reserved_0[0x10];
5790 u8 reserved_1[0x10];
5794 u8 dct_number[0x18];
5796 u8 reserved_3[0x20];
5799 struct mlx5_ifc_alloc_xrcd_out_bits {
5801 u8 reserved_0[0x18];
5808 u8 reserved_2[0x20];
5811 struct mlx5_ifc_alloc_xrcd_in_bits {
5813 u8 reserved_0[0x10];
5815 u8 reserved_1[0x10];
5818 u8 reserved_2[0x40];
5821 struct mlx5_ifc_alloc_uar_out_bits {
5823 u8 reserved_0[0x18];
5830 u8 reserved_2[0x20];
5833 struct mlx5_ifc_alloc_uar_in_bits {
5835 u8 reserved_0[0x10];
5837 u8 reserved_1[0x10];
5840 u8 reserved_2[0x40];
5843 struct mlx5_ifc_alloc_transport_domain_out_bits {
5845 u8 reserved_0[0x18];
5850 u8 transport_domain[0x18];
5852 u8 reserved_2[0x20];
5855 struct mlx5_ifc_alloc_transport_domain_in_bits {
5857 u8 reserved_0[0x10];
5859 u8 reserved_1[0x10];
5862 u8 reserved_2[0x40];
5865 struct mlx5_ifc_alloc_q_counter_out_bits {
5867 u8 reserved_0[0x18];
5871 u8 reserved_1[0x18];
5872 u8 counter_set_id[0x8];
5874 u8 reserved_2[0x20];
5877 struct mlx5_ifc_alloc_q_counter_in_bits {
5879 u8 reserved_0[0x10];
5881 u8 reserved_1[0x10];
5884 u8 reserved_2[0x40];
5887 struct mlx5_ifc_alloc_pd_out_bits {
5889 u8 reserved_0[0x18];
5896 u8 reserved_2[0x20];
5899 struct mlx5_ifc_alloc_pd_in_bits {
5901 u8 reserved_0[0x10];
5903 u8 reserved_1[0x10];
5906 u8 reserved_2[0x40];
5909 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
5911 u8 reserved_0[0x18];
5915 u8 reserved_1[0x40];
5918 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
5920 u8 reserved_0[0x10];
5922 u8 reserved_1[0x10];
5925 u8 reserved_2[0x20];
5927 u8 reserved_3[0x10];
5928 u8 vxlan_udp_port[0x10];
5931 struct mlx5_ifc_access_register_out_bits {
5933 u8 reserved_0[0x18];
5937 u8 reserved_1[0x40];
5939 u8 register_data[0][0x20];
5943 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
5944 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
5947 struct mlx5_ifc_access_register_in_bits {
5949 u8 reserved_0[0x10];
5951 u8 reserved_1[0x10];
5954 u8 reserved_2[0x10];
5955 u8 register_id[0x10];
5959 u8 register_data[0][0x20];
5962 struct mlx5_ifc_sltp_reg_bits {
5971 u8 reserved_2[0x20];
5980 u8 ob_preemp_mode[0x4];
5984 u8 reserved_5[0x20];
5987 struct mlx5_ifc_slrg_reg_bits {
5996 u8 time_to_link_up[0x10];
5998 u8 grade_lane_speed[0x4];
6000 u8 grade_version[0x8];
6004 u8 height_grade_type[0x4];
6005 u8 height_grade[0x18];
6010 u8 reserved_4[0x10];
6011 u8 height_sigma[0x10];
6013 u8 reserved_5[0x20];
6016 u8 phase_grade_type[0x4];
6017 u8 phase_grade[0x18];
6020 u8 phase_eo_pos[0x8];
6022 u8 phase_eo_neg[0x8];
6024 u8 ffe_set_tested[0x10];
6025 u8 test_errors_per_lane[0x10];
6028 struct mlx5_ifc_pvlc_reg_bits {
6031 u8 reserved_1[0x10];
6033 u8 reserved_2[0x1c];
6036 u8 reserved_3[0x1c];
6039 u8 reserved_4[0x1c];
6040 u8 vl_operational[0x4];
6043 struct mlx5_ifc_pude_reg_bits {
6047 u8 admin_status[0x4];
6049 u8 oper_status[0x4];
6051 u8 reserved_2[0x60];
6054 struct mlx5_ifc_ptys_reg_bits {
6060 u8 reserved_2[0x40];
6062 u8 eth_proto_capability[0x20];
6064 u8 ib_link_width_capability[0x10];
6065 u8 ib_proto_capability[0x10];
6067 u8 reserved_3[0x20];
6069 u8 eth_proto_admin[0x20];
6071 u8 ib_link_width_admin[0x10];
6072 u8 ib_proto_admin[0x10];
6074 u8 reserved_4[0x20];
6076 u8 eth_proto_oper[0x20];
6078 u8 ib_link_width_oper[0x10];
6079 u8 ib_proto_oper[0x10];
6081 u8 reserved_5[0x20];
6083 u8 eth_proto_lp_advertise[0x20];
6085 u8 reserved_6[0x60];
6088 struct mlx5_ifc_ptas_reg_bits {
6089 u8 reserved_0[0x20];
6091 u8 algorithm_options[0x10];
6093 u8 repetitions_mode[0x4];
6094 u8 num_of_repetitions[0x8];
6096 u8 grade_version[0x8];
6097 u8 height_grade_type[0x4];
6098 u8 phase_grade_type[0x4];
6099 u8 height_grade_weight[0x8];
6100 u8 phase_grade_weight[0x8];
6102 u8 gisim_measure_bits[0x10];
6103 u8 adaptive_tap_measure_bits[0x10];
6105 u8 ber_bath_high_error_threshold[0x10];
6106 u8 ber_bath_mid_error_threshold[0x10];
6108 u8 ber_bath_low_error_threshold[0x10];
6109 u8 one_ratio_high_threshold[0x10];
6111 u8 one_ratio_high_mid_threshold[0x10];
6112 u8 one_ratio_low_mid_threshold[0x10];
6114 u8 one_ratio_low_threshold[0x10];
6115 u8 ndeo_error_threshold[0x10];
6117 u8 mixer_offset_step_size[0x10];
6119 u8 mix90_phase_for_voltage_bath[0x8];
6121 u8 mixer_offset_start[0x10];
6122 u8 mixer_offset_end[0x10];
6124 u8 reserved_3[0x15];
6125 u8 ber_test_time[0xb];
6128 struct mlx5_ifc_pspa_reg_bits {
6134 u8 reserved_1[0x20];
6137 struct mlx5_ifc_pqdr_reg_bits {
6145 u8 reserved_3[0x20];
6147 u8 reserved_4[0x10];
6148 u8 min_threshold[0x10];
6150 u8 reserved_5[0x10];
6151 u8 max_threshold[0x10];
6153 u8 reserved_6[0x10];
6154 u8 mark_probability_denominator[0x10];
6156 u8 reserved_7[0x60];
6159 struct mlx5_ifc_ppsc_reg_bits {
6162 u8 reserved_1[0x10];
6164 u8 reserved_2[0x60];
6166 u8 reserved_3[0x1c];
6169 u8 reserved_4[0x1c];
6170 u8 wrps_status[0x4];
6173 u8 up_threshold[0x8];
6175 u8 down_threshold[0x8];
6177 u8 reserved_7[0x20];
6179 u8 reserved_8[0x1c];
6182 u8 reserved_9[0x1c];
6183 u8 srps_status[0x4];
6185 u8 reserved_10[0x40];
6188 struct mlx5_ifc_pplr_reg_bits {
6191 u8 reserved_1[0x10];
6199 struct mlx5_ifc_pplm_reg_bits {
6202 u8 reserved_1[0x10];
6204 u8 reserved_2[0x20];
6206 u8 port_profile_mode[0x8];
6207 u8 static_port_profile[0x8];
6208 u8 active_port_profile[0x8];
6211 u8 retransmission_active[0x8];
6212 u8 fec_mode_active[0x18];
6214 u8 reserved_4[0x20];
6217 struct mlx5_ifc_ppcnt_reg_bits {
6225 u8 reserved_1[0x1c];
6228 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6231 struct mlx5_ifc_ppad_reg_bits {
6240 u8 reserved_2[0x40];
6243 struct mlx5_ifc_pmtu_reg_bits {
6246 u8 reserved_1[0x10];
6249 u8 reserved_2[0x10];
6252 u8 reserved_3[0x10];
6255 u8 reserved_4[0x10];
6258 struct mlx5_ifc_pmpr_reg_bits {
6261 u8 reserved_1[0x10];
6263 u8 reserved_2[0x18];
6264 u8 attenuation_5g[0x8];
6266 u8 reserved_3[0x18];
6267 u8 attenuation_7g[0x8];
6269 u8 reserved_4[0x18];
6270 u8 attenuation_12g[0x8];
6273 struct mlx5_ifc_pmpe_reg_bits {
6277 u8 module_status[0x4];
6279 u8 reserved_2[0x60];
6282 struct mlx5_ifc_pmpc_reg_bits {
6283 u8 module_state_updated[32][0x8];
6286 struct mlx5_ifc_pmlpn_reg_bits {
6288 u8 mlpn_status[0x4];
6290 u8 reserved_1[0x10];
6293 u8 reserved_2[0x1f];
6296 struct mlx5_ifc_pmlp_reg_bits {
6303 u8 lane0_module_mapping[0x20];
6305 u8 lane1_module_mapping[0x20];
6307 u8 lane2_module_mapping[0x20];
6309 u8 lane3_module_mapping[0x20];
6311 u8 reserved_2[0x160];
6314 struct mlx5_ifc_pmaos_reg_bits {
6318 u8 admin_status[0x4];
6320 u8 oper_status[0x4];
6324 u8 reserved_3[0x1c];
6327 u8 reserved_4[0x40];
6330 struct mlx5_ifc_plpc_reg_bits {
6337 u8 reserved_3[0x10];
6338 u8 lane_speed[0x10];
6340 u8 reserved_4[0x17];
6342 u8 fec_mode_policy[0x8];
6344 u8 retransmission_capability[0x8];
6345 u8 fec_mode_capability[0x18];
6347 u8 retransmission_support_admin[0x8];
6348 u8 fec_mode_support_admin[0x18];
6350 u8 retransmission_request_admin[0x8];
6351 u8 fec_mode_request_admin[0x18];
6353 u8 reserved_5[0x80];
6356 struct mlx5_ifc_plib_reg_bits {
6362 u8 reserved_2[0x60];
6365 struct mlx5_ifc_plbf_reg_bits {
6371 u8 reserved_2[0x20];
6374 struct mlx5_ifc_pipg_reg_bits {
6377 u8 reserved_1[0x10];
6380 u8 reserved_2[0x19];
6385 struct mlx5_ifc_pifr_reg_bits {
6388 u8 reserved_1[0x10];
6390 u8 reserved_2[0xe0];
6392 u8 port_filter[8][0x20];
6394 u8 port_filter_update_en[8][0x20];
6397 struct mlx5_ifc_pfcc_reg_bits {
6400 u8 reserved_1[0x10];
6404 u8 prio_mask_tx[0x8];
6406 u8 prio_mask_rx[0x8];
6412 u8 reserved_5[0x10];
6418 u8 reserved_7[0x10];
6420 u8 reserved_8[0x80];
6423 struct mlx5_ifc_pelc_reg_bits {
6427 u8 reserved_1[0x10];
6430 u8 op_capability[0x8];
6436 u8 capability[0x40];
6442 u8 reserved_2[0x80];
6445 struct mlx5_ifc_peir_reg_bits {
6448 u8 reserved_1[0x10];
6451 u8 error_count[0x4];
6452 u8 reserved_3[0x10];
6460 struct mlx5_ifc_pcap_reg_bits {
6463 u8 reserved_1[0x10];
6465 u8 port_capability_mask[4][0x20];
6468 struct mlx5_ifc_paos_reg_bits {
6472 u8 admin_status[0x4];
6474 u8 oper_status[0x4];
6478 u8 reserved_2[0x1c];
6481 u8 reserved_3[0x40];
6484 struct mlx5_ifc_pamp_reg_bits {
6486 u8 opamp_group[0x8];
6488 u8 opamp_group_type[0x4];
6490 u8 start_index[0x10];
6492 u8 num_of_indices[0xc];
6494 u8 index_data[18][0x10];
6497 struct mlx5_ifc_lane_2_module_mapping_bits {
6506 struct mlx5_ifc_bufferx_reg_bits {
6513 u8 xoff_threshold[0x10];
6514 u8 xon_threshold[0x10];
6517 struct mlx5_ifc_set_node_in_bits {
6518 u8 node_description[64][0x8];
6521 struct mlx5_ifc_register_power_settings_bits {
6522 u8 reserved_0[0x18];
6523 u8 power_settings_level[0x8];
6525 u8 reserved_1[0x60];
6528 struct mlx5_ifc_register_host_endianness_bits {
6530 u8 reserved_0[0x1f];
6532 u8 reserved_1[0x60];
6535 struct mlx5_ifc_umr_pointer_desc_argument_bits {
6536 u8 reserved_0[0x20];
6540 u8 addressh_63_32[0x20];
6542 u8 addressl_31_0[0x20];
6545 struct mlx5_ifc_ud_adrs_vector_bits {
6550 u8 destination_qp_dct[0x18];
6552 u8 static_rate[0x4];
6553 u8 sl_eth_prio[0x4];
6556 u8 rlid_udp_sport[0x10];
6558 u8 reserved_1[0x20];
6560 u8 rmac_47_16[0x20];
6569 u8 src_addr_index[0x8];
6570 u8 flow_label[0x14];
6572 u8 rgid_rip[16][0x8];
6575 struct mlx5_ifc_pages_req_event_bits {
6576 u8 reserved_0[0x10];
6577 u8 function_id[0x10];
6581 u8 reserved_1[0xa0];
6584 struct mlx5_ifc_eqe_bits {
6588 u8 event_sub_type[0x8];
6590 u8 reserved_2[0xe0];
6592 union mlx5_ifc_event_auto_bits event_data;
6594 u8 reserved_3[0x10];
6601 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
6604 struct mlx5_ifc_cmd_queue_entry_bits {
6606 u8 reserved_0[0x18];
6608 u8 input_length[0x20];
6610 u8 input_mailbox_pointer_63_32[0x20];
6612 u8 input_mailbox_pointer_31_9[0x17];
6615 u8 command_input_inline_data[16][0x8];
6617 u8 command_output_inline_data[16][0x8];
6619 u8 output_mailbox_pointer_63_32[0x20];
6621 u8 output_mailbox_pointer_31_9[0x17];
6624 u8 output_length[0x20];
6633 struct mlx5_ifc_cmd_out_bits {
6635 u8 reserved_0[0x18];
6639 u8 command_output[0x20];
6642 struct mlx5_ifc_cmd_in_bits {
6644 u8 reserved_0[0x10];
6646 u8 reserved_1[0x10];
6649 u8 command[0][0x20];
6652 struct mlx5_ifc_cmd_if_box_bits {
6653 u8 mailbox_data[512][0x8];
6655 u8 reserved_0[0x180];
6657 u8 next_pointer_63_32[0x20];
6659 u8 next_pointer_31_10[0x16];
6662 u8 block_number[0x20];
6666 u8 ctrl_signature[0x8];
6670 struct mlx5_ifc_mtt_bits {
6671 u8 ptag_63_32[0x20];
6680 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
6681 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
6682 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
6686 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
6687 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
6688 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
6692 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
6693 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
6694 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
6695 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
6696 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
6697 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
6698 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
6699 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
6700 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
6701 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
6702 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
6705 struct mlx5_ifc_initial_seg_bits {
6706 u8 fw_rev_minor[0x10];
6707 u8 fw_rev_major[0x10];
6709 u8 cmd_interface_rev[0x10];
6710 u8 fw_rev_subminor[0x10];
6712 u8 reserved_0[0x40];
6714 u8 cmdq_phy_addr_63_32[0x20];
6716 u8 cmdq_phy_addr_31_12[0x14];
6718 u8 nic_interface[0x2];
6719 u8 log_cmdq_size[0x4];
6720 u8 log_cmdq_stride[0x4];
6722 u8 command_doorbell_vector[0x20];
6724 u8 reserved_2[0xf00];
6726 u8 initializing[0x1];
6728 u8 nic_interface_supported[0x3];
6729 u8 reserved_4[0x18];
6731 struct mlx5_ifc_health_buffer_bits health_buffer;
6733 u8 no_dram_nic_offset[0x20];
6735 u8 reserved_5[0x6e40];
6737 u8 reserved_6[0x1f];
6740 u8 health_syndrome[0x8];
6741 u8 health_counter[0x18];
6743 u8 reserved_7[0x17fc0];
6746 union mlx5_ifc_ports_control_registers_document_bits {
6747 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
6748 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
6749 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
6750 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
6751 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
6752 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
6753 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
6754 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
6755 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
6756 struct mlx5_ifc_pamp_reg_bits pamp_reg;
6757 struct mlx5_ifc_paos_reg_bits paos_reg;
6758 struct mlx5_ifc_pcap_reg_bits pcap_reg;
6759 struct mlx5_ifc_peir_reg_bits peir_reg;
6760 struct mlx5_ifc_pelc_reg_bits pelc_reg;
6761 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
6762 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
6763 struct mlx5_ifc_pifr_reg_bits pifr_reg;
6764 struct mlx5_ifc_pipg_reg_bits pipg_reg;
6765 struct mlx5_ifc_plbf_reg_bits plbf_reg;
6766 struct mlx5_ifc_plib_reg_bits plib_reg;
6767 struct mlx5_ifc_plpc_reg_bits plpc_reg;
6768 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
6769 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
6770 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
6771 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
6772 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
6773 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
6774 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
6775 struct mlx5_ifc_ppad_reg_bits ppad_reg;
6776 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
6777 struct mlx5_ifc_pplm_reg_bits pplm_reg;
6778 struct mlx5_ifc_pplr_reg_bits pplr_reg;
6779 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
6780 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
6781 struct mlx5_ifc_pspa_reg_bits pspa_reg;
6782 struct mlx5_ifc_ptas_reg_bits ptas_reg;
6783 struct mlx5_ifc_ptys_reg_bits ptys_reg;
6784 struct mlx5_ifc_pude_reg_bits pude_reg;
6785 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
6786 struct mlx5_ifc_slrg_reg_bits slrg_reg;
6787 struct mlx5_ifc_sltp_reg_bits sltp_reg;
6788 u8 reserved_0[0x60e0];
6791 union mlx5_ifc_debug_enhancements_document_bits {
6792 struct mlx5_ifc_health_buffer_bits health_buffer;
6793 u8 reserved_0[0x200];
6796 union mlx5_ifc_uplink_pci_interface_document_bits {
6797 struct mlx5_ifc_initial_seg_bits initial_seg;
6798 u8 reserved_0[0x20060];
6801 #endif /* MLX5_IFC_H */