include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  71 };
  72
  73 enum {
  74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  75         MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
  76         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  77 };
  78
  79 enum {
  80         MLX5_SHARED_RESOURCE_UID = 0xffff,
  81 };
  82
  83 enum {
  84         MLX5_OBJ_TYPE_SW_ICM = 0x0008,
  85 };
  86
  87 enum {
  88         MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
  89         MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
  90 };
  91
  92 enum {
  93         MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
  94         MLX5_OBJ_TYPE_MKEY = 0xff01,
  95         MLX5_OBJ_TYPE_QP = 0xff02,
  96         MLX5_OBJ_TYPE_PSV = 0xff03,
  97         MLX5_OBJ_TYPE_RMP = 0xff04,
  98         MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
  99         MLX5_OBJ_TYPE_RQ = 0xff06,
 100         MLX5_OBJ_TYPE_SQ = 0xff07,
 101         MLX5_OBJ_TYPE_TIR = 0xff08,
 102         MLX5_OBJ_TYPE_TIS = 0xff09,
 103         MLX5_OBJ_TYPE_DCT = 0xff0a,
 104         MLX5_OBJ_TYPE_XRQ = 0xff0b,
 105         MLX5_OBJ_TYPE_RQT = 0xff0e,
 106         MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
 107         MLX5_OBJ_TYPE_CQ = 0xff10,
 108 };
 109
 110 enum {
 111         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
 112         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
 113         MLX5_CMD_OP_INIT_HCA                      = 0x102,
 114         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
 115         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
 116         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
 117         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
 118         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
 119         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
 120         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
 121         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 122         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 123         MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
 124         MLX5_CMD_OP_ALLOC_SF                      = 0x113,
 125         MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
 126         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 127         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 128         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 129         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 130         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 131         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 132         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 133         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 134         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 135         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 136         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 137         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 138         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 139         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 140         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 141         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 142         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 143         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 144         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 145         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 146         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 147         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 148         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 149         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 150         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 151         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 152         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 153         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 154         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 155         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 156         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 157         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 158         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 159         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 160         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 161         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 162         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 163         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 164         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 165         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 166         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 167         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 168         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 169         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 170         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 171         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 172         MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
 173         MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
 174         MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
 175         MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
 176         MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
 177         MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
 178         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 179         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 180         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 181         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 182         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 183         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 184         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 185         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 186         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 187         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 188         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 189         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 190         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 191         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 192         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 193         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 194         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 195         MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
 196         MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
 197         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 198         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 199         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 200         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 201         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 202         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 203         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 204         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 205         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 206         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 207         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 208         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 209         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 210         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 211         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 212         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 213         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 214         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 215         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 216         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 217         MLX5_CMD_OP_NOP                           = 0x80d,
 218         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 219         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 220         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 221         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 222         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 223         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 224         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 225         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 226         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 227         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 228         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 229         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 230         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 231         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 232         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 233         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 234         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 235         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 236         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 237         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 238         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 239         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 240         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 241         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 242         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 243         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 244         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 245         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 246         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 247         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 248         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 249         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 250         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 251         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 252         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 253         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 254         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 255         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 256         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 257         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 258         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 259         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 260         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 261         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 262         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 263         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 264         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 265         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 266         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 267         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 268         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 269         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 270         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 271         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 272         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 273         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 274         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 275         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 276         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 277         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 278         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 279         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 280         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 281         MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
 282         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 283         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 284         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 285         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 286         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 287         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 288         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 289         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 290         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 291         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 292         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 293         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 294         MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
 295         MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
 296         MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
 297         MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
 298         MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
 299         MLX5_CMD_OP_MAX
 300 };
 301
 302 /* Valid range for general commands that don't work over an object */
 303 enum {
 304         MLX5_CMD_OP_GENERAL_START = 0xb00,
 305         MLX5_CMD_OP_GENERAL_END = 0xd00,
 306 };
 307
 308 struct mlx5_ifc_flow_table_fields_supported_bits {
 309         u8         outer_dmac[0x1];
 310         u8         outer_smac[0x1];
 311         u8         outer_ether_type[0x1];
 312         u8         outer_ip_version[0x1];
 313         u8         outer_first_prio[0x1];
 314         u8         outer_first_cfi[0x1];
 315         u8         outer_first_vid[0x1];
 316         u8         outer_ipv4_ttl[0x1];
 317         u8         outer_second_prio[0x1];
 318         u8         outer_second_cfi[0x1];
 319         u8         outer_second_vid[0x1];
 320         u8         reserved_at_b[0x1];
 321         u8         outer_sip[0x1];
 322         u8         outer_dip[0x1];
 323         u8         outer_frag[0x1];
 324         u8         outer_ip_protocol[0x1];
 325         u8         outer_ip_ecn[0x1];
 326         u8         outer_ip_dscp[0x1];
 327         u8         outer_udp_sport[0x1];
 328         u8         outer_udp_dport[0x1];
 329         u8         outer_tcp_sport[0x1];
 330         u8         outer_tcp_dport[0x1];
 331         u8         outer_tcp_flags[0x1];
 332         u8         outer_gre_protocol[0x1];
 333         u8         outer_gre_key[0x1];
 334         u8         outer_vxlan_vni[0x1];
 335         u8         outer_geneve_vni[0x1];
 336         u8         outer_geneve_oam[0x1];
 337         u8         outer_geneve_protocol_type[0x1];
 338         u8         outer_geneve_opt_len[0x1];
 339         u8         reserved_at_1e[0x1];
 340         u8         source_eswitch_port[0x1];
 341
 342         u8         inner_dmac[0x1];
 343         u8         inner_smac[0x1];
 344         u8         inner_ether_type[0x1];
 345         u8         inner_ip_version[0x1];
 346         u8         inner_first_prio[0x1];
 347         u8         inner_first_cfi[0x1];
 348         u8         inner_first_vid[0x1];
 349         u8         reserved_at_27[0x1];
 350         u8         inner_second_prio[0x1];
 351         u8         inner_second_cfi[0x1];
 352         u8         inner_second_vid[0x1];
 353         u8         reserved_at_2b[0x1];
 354         u8         inner_sip[0x1];
 355         u8         inner_dip[0x1];
 356         u8         inner_frag[0x1];
 357         u8         inner_ip_protocol[0x1];
 358         u8         inner_ip_ecn[0x1];
 359         u8         inner_ip_dscp[0x1];
 360         u8         inner_udp_sport[0x1];
 361         u8         inner_udp_dport[0x1];
 362         u8         inner_tcp_sport[0x1];
 363         u8         inner_tcp_dport[0x1];
 364         u8         inner_tcp_flags[0x1];
 365         u8         reserved_at_37[0x9];
 366
 367         u8         geneve_tlv_option_0_data[0x1];
 368         u8         reserved_at_41[0x4];
 369         u8         outer_first_mpls_over_udp[0x4];
 370         u8         outer_first_mpls_over_gre[0x4];
 371         u8         inner_first_mpls[0x4];
 372         u8         outer_first_mpls[0x4];
 373         u8         reserved_at_55[0x2];
 374         u8         outer_esp_spi[0x1];
 375         u8         reserved_at_58[0x2];
 376         u8         bth_dst_qp[0x1];
 377
 378         u8         reserved_at_5b[0x25];
 379 };
 380
 381 struct mlx5_ifc_flow_table_prop_layout_bits {
 382         u8         ft_support[0x1];
 383         u8         reserved_at_1[0x1];
 384         u8         flow_counter[0x1];
 385         u8         flow_modify_en[0x1];
 386         u8         modify_root[0x1];
 387         u8         identified_miss_table_mode[0x1];
 388         u8         flow_table_modify[0x1];
 389         u8         reformat[0x1];
 390         u8         decap[0x1];
 391         u8         reserved_at_9[0x1];
 392         u8         pop_vlan[0x1];
 393         u8         push_vlan[0x1];
 394         u8         reserved_at_c[0x1];
 395         u8         pop_vlan_2[0x1];
 396         u8         push_vlan_2[0x1];
 397         u8         reformat_and_vlan_action[0x1];
 398         u8         reserved_at_10[0x1];
 399         u8         sw_owner[0x1];
 400         u8         reformat_l3_tunnel_to_l2[0x1];
 401         u8         reformat_l2_to_l3_tunnel[0x1];
 402         u8         reformat_and_modify_action[0x1];
 403         u8         reserved_at_15[0x2];
 404         u8         table_miss_action_domain[0x1];
 405         u8         termination_table[0x1];
 406         u8         reserved_at_19[0x7];
 407         u8         reserved_at_20[0x2];
 408         u8         log_max_ft_size[0x6];
 409         u8         log_max_modify_header_context[0x8];
 410         u8         max_modify_header_actions[0x8];
 411         u8         max_ft_level[0x8];
 412
 413         u8         reserved_at_40[0x20];
 414
 415         u8         reserved_at_60[0x18];
 416         u8         log_max_ft_num[0x8];
 417
 418         u8         reserved_at_80[0x10];
 419         u8         log_max_flow_counter[0x8];
 420         u8         log_max_destination[0x8];
 421
 422         u8         reserved_at_a0[0x18];
 423         u8         log_max_flow[0x8];
 424
 425         u8         reserved_at_c0[0x40];
 426
 427         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 428
 429         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 430 };
 431
 432 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 433         u8         send[0x1];
 434         u8         receive[0x1];
 435         u8         write[0x1];
 436         u8         read[0x1];
 437         u8         atomic[0x1];
 438         u8         srq_receive[0x1];
 439         u8         reserved_at_6[0x1a];
 440 };
 441
 442 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 443         u8         smac_47_16[0x20];
 444
 445         u8         smac_15_0[0x10];
 446         u8         ethertype[0x10];
 447
 448         u8         dmac_47_16[0x20];
 449
 450         u8         dmac_15_0[0x10];
 451         u8         first_prio[0x3];
 452         u8         first_cfi[0x1];
 453         u8         first_vid[0xc];
 454
 455         u8         ip_protocol[0x8];
 456         u8         ip_dscp[0x6];
 457         u8         ip_ecn[0x2];
 458         u8         cvlan_tag[0x1];
 459         u8         svlan_tag[0x1];
 460         u8         frag[0x1];
 461         u8         ip_version[0x4];
 462         u8         tcp_flags[0x9];
 463
 464         u8         tcp_sport[0x10];
 465         u8         tcp_dport[0x10];
 466
 467         u8         reserved_at_c0[0x18];
 468         u8         ttl_hoplimit[0x8];
 469
 470         u8         udp_sport[0x10];
 471         u8         udp_dport[0x10];
 472
 473         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 474
 475         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 476 };
 477
 478 struct mlx5_ifc_nvgre_key_bits {
 479         u8 hi[0x18];
 480         u8 lo[0x8];
 481 };
 482
 483 union mlx5_ifc_gre_key_bits {
 484         struct mlx5_ifc_nvgre_key_bits nvgre;
 485         u8 key[0x20];
 486 };
 487
 488 struct mlx5_ifc_fte_match_set_misc_bits {
 489         u8         gre_c_present[0x1];
 490         u8         reserved_at_1[0x1];
 491         u8         gre_k_present[0x1];
 492         u8         gre_s_present[0x1];
 493         u8         source_vhca_port[0x4];
 494         u8         source_sqn[0x18];
 495
 496         u8         source_eswitch_owner_vhca_id[0x10];
 497         u8         source_port[0x10];
 498
 499         u8         outer_second_prio[0x3];
 500         u8         outer_second_cfi[0x1];
 501         u8         outer_second_vid[0xc];
 502         u8         inner_second_prio[0x3];
 503         u8         inner_second_cfi[0x1];
 504         u8         inner_second_vid[0xc];
 505
 506         u8         outer_second_cvlan_tag[0x1];
 507         u8         inner_second_cvlan_tag[0x1];
 508         u8         outer_second_svlan_tag[0x1];
 509         u8         inner_second_svlan_tag[0x1];
 510         u8         reserved_at_64[0xc];
 511         u8         gre_protocol[0x10];
 512
 513         union mlx5_ifc_gre_key_bits gre_key;
 514
 515         u8         vxlan_vni[0x18];
 516         u8         reserved_at_b8[0x8];
 517
 518         u8         geneve_vni[0x18];
 519         u8         reserved_at_d8[0x7];
 520         u8         geneve_oam[0x1];
 521
 522         u8         reserved_at_e0[0xc];
 523         u8         outer_ipv6_flow_label[0x14];
 524
 525         u8         reserved_at_100[0xc];
 526         u8         inner_ipv6_flow_label[0x14];
 527
 528         u8         reserved_at_120[0xa];
 529         u8         geneve_opt_len[0x6];
 530         u8         geneve_protocol_type[0x10];
 531
 532         u8         reserved_at_140[0x8];
 533         u8         bth_dst_qp[0x18];
 534         u8         reserved_at_160[0x20];
 535         u8         outer_esp_spi[0x20];
 536         u8         reserved_at_1a0[0x60];
 537 };
 538
 539 struct mlx5_ifc_fte_match_mpls_bits {
 540         u8         mpls_label[0x14];
 541         u8         mpls_exp[0x3];
 542         u8         mpls_s_bos[0x1];
 543         u8         mpls_ttl[0x8];
 544 };
 545
 546 struct mlx5_ifc_fte_match_set_misc2_bits {
 547         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 548
 549         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 550
 551         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 552
 553         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 554
 555         u8         metadata_reg_c_7[0x20];
 556
 557         u8         metadata_reg_c_6[0x20];
 558
 559         u8         metadata_reg_c_5[0x20];
 560
 561         u8         metadata_reg_c_4[0x20];
 562
 563         u8         metadata_reg_c_3[0x20];
 564
 565         u8         metadata_reg_c_2[0x20];
 566
 567         u8         metadata_reg_c_1[0x20];
 568
 569         u8         metadata_reg_c_0[0x20];
 570
 571         u8         metadata_reg_a[0x20];
 572
 573         u8         metadata_reg_b[0x20];
 574
 575         u8         reserved_at_1c0[0x40];
 576 };
 577
 578 struct mlx5_ifc_fte_match_set_misc3_bits {
 579         u8         inner_tcp_seq_num[0x20];
 580
 581         u8         outer_tcp_seq_num[0x20];
 582
 583         u8         inner_tcp_ack_num[0x20];
 584
 585         u8         outer_tcp_ack_num[0x20];
 586
 587         u8         reserved_at_80[0x8];
 588         u8         outer_vxlan_gpe_vni[0x18];
 589
 590         u8         outer_vxlan_gpe_next_protocol[0x8];
 591         u8         outer_vxlan_gpe_flags[0x8];
 592         u8         reserved_at_b0[0x10];
 593
 594         u8         icmp_header_data[0x20];
 595
 596         u8         icmpv6_header_data[0x20];
 597
 598         u8         icmp_type[0x8];
 599         u8         icmp_code[0x8];
 600         u8         icmpv6_type[0x8];
 601         u8         icmpv6_code[0x8];
 602
 603         u8         geneve_tlv_option_0_data[0x20];
 604
 605         u8         reserved_at_140[0xc0];
 606 };
 607
 608 struct mlx5_ifc_cmd_pas_bits {
 609         u8         pa_h[0x20];
 610
 611         u8         pa_l[0x14];
 612         u8         reserved_at_34[0xc];
 613 };
 614
 615 struct mlx5_ifc_uint64_bits {
 616         u8         hi[0x20];
 617
 618         u8         lo[0x20];
 619 };
 620
 621 enum {
 622         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 623         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 624         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 625         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 626         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 627         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 628         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 629         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 630         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 631         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 632 };
 633
 634 struct mlx5_ifc_ads_bits {
 635         u8         fl[0x1];
 636         u8         free_ar[0x1];
 637         u8         reserved_at_2[0xe];
 638         u8         pkey_index[0x10];
 639
 640         u8         reserved_at_20[0x8];
 641         u8         grh[0x1];
 642         u8         mlid[0x7];
 643         u8         rlid[0x10];
 644
 645         u8         ack_timeout[0x5];
 646         u8         reserved_at_45[0x3];
 647         u8         src_addr_index[0x8];
 648         u8         reserved_at_50[0x4];
 649         u8         stat_rate[0x4];
 650         u8         hop_limit[0x8];
 651
 652         u8         reserved_at_60[0x4];
 653         u8         tclass[0x8];
 654         u8         flow_label[0x14];
 655
 656         u8         rgid_rip[16][0x8];
 657
 658         u8         reserved_at_100[0x4];
 659         u8         f_dscp[0x1];
 660         u8         f_ecn[0x1];
 661         u8         reserved_at_106[0x1];
 662         u8         f_eth_prio[0x1];
 663         u8         ecn[0x2];
 664         u8         dscp[0x6];
 665         u8         udp_sport[0x10];
 666
 667         u8         dei_cfi[0x1];
 668         u8         eth_prio[0x3];
 669         u8         sl[0x4];
 670         u8         vhca_port_num[0x8];
 671         u8         rmac_47_32[0x10];
 672
 673         u8         rmac_31_0[0x20];
 674 };
 675
 676 struct mlx5_ifc_flow_table_nic_cap_bits {
 677         u8         nic_rx_multi_path_tirs[0x1];
 678         u8         nic_rx_multi_path_tirs_fts[0x1];
 679         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 680         u8         reserved_at_3[0x1d];
 681         u8         encap_general_header[0x1];
 682         u8         reserved_at_21[0xa];
 683         u8         log_max_packet_reformat_context[0x5];
 684         u8         reserved_at_30[0x6];
 685         u8         max_encap_header_size[0xa];
 686         u8         reserved_at_40[0x1c0];
 687
 688         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 689
 690         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 691
 692         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 693
 694         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 695
 696         u8         reserved_at_a00[0x200];
 697
 698         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 699
 700         u8         reserved_at_e00[0x1200];
 701
 702         u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
 703
 704         u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
 705
 706         u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
 707
 708         u8         reserved_at_20c0[0x5f40];
 709 };
 710
 711 enum {
 712         MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
 713         MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
 714         MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
 715         MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
 716         MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
 717         MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
 718         MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
 719         MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
 720 };
 721
 722 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 723         u8      fdb_to_vport_reg_c_id[0x8];
 724         u8      reserved_at_8[0xf];
 725         u8      flow_source[0x1];
 726         u8      reserved_at_18[0x2];
 727         u8      multi_fdb_encap[0x1];
 728         u8      reserved_at_1b[0x1];
 729         u8      fdb_multi_path_to_table[0x1];
 730         u8      reserved_at_1d[0x3];
 731
 732         u8      reserved_at_20[0x1e0];
 733
 734         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 735
 736         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 737
 738         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 739
 740         u8      reserved_at_800[0x1000];
 741
 742         u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
 743
 744         u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
 745
 746         u8      sw_steering_uplink_icm_address_rx[0x40];
 747
 748         u8      sw_steering_uplink_icm_address_tx[0x40];
 749
 750         u8      reserved_at_1900[0x6700];
 751 };
 752
 753 enum {
 754         MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
 755         MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
 756 };
 757
 758 struct mlx5_ifc_e_switch_cap_bits {
 759         u8         vport_svlan_strip[0x1];
 760         u8         vport_cvlan_strip[0x1];
 761         u8         vport_svlan_insert[0x1];
 762         u8         vport_cvlan_insert_if_not_exist[0x1];
 763         u8         vport_cvlan_insert_overwrite[0x1];
 764         u8         reserved_at_5[0x3];
 765         u8         esw_uplink_ingress_acl[0x1];
 766         u8         reserved_at_9[0x10];
 767         u8         esw_functions_changed[0x1];
 768         u8         reserved_at_1a[0x1];
 769         u8         ecpf_vport_exists[0x1];
 770         u8         counter_eswitch_affinity[0x1];
 771         u8         merged_eswitch[0x1];
 772         u8         nic_vport_node_guid_modify[0x1];
 773         u8         nic_vport_port_guid_modify[0x1];
 774
 775         u8         vxlan_encap_decap[0x1];
 776         u8         nvgre_encap_decap[0x1];
 777         u8         reserved_at_22[0x1];
 778         u8         log_max_fdb_encap_uplink[0x5];
 779         u8         reserved_at_21[0x3];
 780         u8         log_max_packet_reformat_context[0x5];
 781         u8         reserved_2b[0x6];
 782         u8         max_encap_header_size[0xa];
 783
 784         u8         reserved_at_40[0xb];
 785         u8         log_max_esw_sf[0x5];
 786         u8         esw_sf_base_id[0x10];
 787
 788         u8         reserved_at_60[0x7a0];
 789
 790 };
 791
 792 struct mlx5_ifc_qos_cap_bits {
 793         u8         packet_pacing[0x1];
 794         u8         esw_scheduling[0x1];
 795         u8         esw_bw_share[0x1];
 796         u8         esw_rate_limit[0x1];
 797         u8         reserved_at_4[0x1];
 798         u8         packet_pacing_burst_bound[0x1];
 799         u8         packet_pacing_typical_size[0x1];
 800         u8         reserved_at_7[0x19];
 801
 802         u8         reserved_at_20[0x20];
 803
 804         u8         packet_pacing_max_rate[0x20];
 805
 806         u8         packet_pacing_min_rate[0x20];
 807
 808         u8         reserved_at_80[0x10];
 809         u8         packet_pacing_rate_table_size[0x10];
 810
 811         u8         esw_element_type[0x10];
 812         u8         esw_tsar_type[0x10];
 813
 814         u8         reserved_at_c0[0x10];
 815         u8         max_qos_para_vport[0x10];
 816
 817         u8         max_tsar_bw_share[0x20];
 818
 819         u8         reserved_at_100[0x700];
 820 };
 821
 822 struct mlx5_ifc_debug_cap_bits {
 823         u8         core_dump_general[0x1];
 824         u8         core_dump_qp[0x1];
 825         u8         reserved_at_2[0x1e];
 826
 827         u8         reserved_at_20[0x2];
 828         u8         stall_detect[0x1];
 829         u8         reserved_at_23[0x1d];
 830
 831         u8         reserved_at_40[0x7c0];
 832 };
 833
 834 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 835         u8         csum_cap[0x1];
 836         u8         vlan_cap[0x1];
 837         u8         lro_cap[0x1];
 838         u8         lro_psh_flag[0x1];
 839         u8         lro_time_stamp[0x1];
 840         u8         reserved_at_5[0x2];
 841         u8         wqe_vlan_insert[0x1];
 842         u8         self_lb_en_modifiable[0x1];
 843         u8         reserved_at_9[0x2];
 844         u8         max_lso_cap[0x5];
 845         u8         multi_pkt_send_wqe[0x2];
 846         u8         wqe_inline_mode[0x2];
 847         u8         rss_ind_tbl_cap[0x4];
 848         u8         reg_umr_sq[0x1];
 849         u8         scatter_fcs[0x1];
 850         u8         enhanced_multi_pkt_send_wqe[0x1];
 851         u8         tunnel_lso_const_out_ip_id[0x1];
 852         u8         reserved_at_1c[0x2];
 853         u8         tunnel_stateless_gre[0x1];
 854         u8         tunnel_stateless_vxlan[0x1];
 855
 856         u8         swp[0x1];
 857         u8         swp_csum[0x1];
 858         u8         swp_lso[0x1];
 859         u8         cqe_checksum_full[0x1];
 860         u8         tunnel_stateless_geneve_tx[0x1];
 861         u8         tunnel_stateless_mpls_over_udp[0x1];
 862         u8         tunnel_stateless_mpls_over_gre[0x1];
 863         u8         tunnel_stateless_vxlan_gpe[0x1];
 864         u8         tunnel_stateless_ipv4_over_vxlan[0x1];
 865         u8         tunnel_stateless_ip_over_ip[0x1];
 866         u8         reserved_at_2a[0x6];
 867         u8         max_vxlan_udp_ports[0x8];
 868         u8         reserved_at_38[0x6];
 869         u8         max_geneve_opt_len[0x1];
 870         u8         tunnel_stateless_geneve_rx[0x1];
 871
 872         u8         reserved_at_40[0x10];
 873         u8         lro_min_mss_size[0x10];
 874
 875         u8         reserved_at_60[0x120];
 876
 877         u8         lro_timer_supported_periods[4][0x20];
 878
 879         u8         reserved_at_200[0x600];
 880 };
 881
 882 struct mlx5_ifc_roce_cap_bits {
 883         u8         roce_apm[0x1];
 884         u8         reserved_at_1[0x1f];
 885
 886         u8         reserved_at_20[0x60];
 887
 888         u8         reserved_at_80[0xc];
 889         u8         l3_type[0x4];
 890         u8         reserved_at_90[0x8];
 891         u8         roce_version[0x8];
 892
 893         u8         reserved_at_a0[0x10];
 894         u8         r_roce_dest_udp_port[0x10];
 895
 896         u8         r_roce_max_src_udp_port[0x10];
 897         u8         r_roce_min_src_udp_port[0x10];
 898
 899         u8         reserved_at_e0[0x10];
 900         u8         roce_address_table_size[0x10];
 901
 902         u8         reserved_at_100[0x700];
 903 };
 904
 905 struct mlx5_ifc_sync_steering_in_bits {
 906         u8         opcode[0x10];
 907         u8         uid[0x10];
 908
 909         u8         reserved_at_20[0x10];
 910         u8         op_mod[0x10];
 911
 912         u8         reserved_at_40[0xc0];
 913 };
 914
 915 struct mlx5_ifc_sync_steering_out_bits {
 916         u8         status[0x8];
 917         u8         reserved_at_8[0x18];
 918
 919         u8         syndrome[0x20];
 920
 921         u8         reserved_at_40[0x40];
 922 };
 923
 924 struct mlx5_ifc_device_mem_cap_bits {
 925         u8         memic[0x1];
 926         u8         reserved_at_1[0x1f];
 927
 928         u8         reserved_at_20[0xb];
 929         u8         log_min_memic_alloc_size[0x5];
 930         u8         reserved_at_30[0x8];
 931         u8         log_max_memic_addr_alignment[0x8];
 932
 933         u8         memic_bar_start_addr[0x40];
 934
 935         u8         memic_bar_size[0x20];
 936
 937         u8         max_memic_size[0x20];
 938
 939         u8         steering_sw_icm_start_address[0x40];
 940
 941         u8         reserved_at_100[0x8];
 942         u8         log_header_modify_sw_icm_size[0x8];
 943         u8         reserved_at_110[0x2];
 944         u8         log_sw_icm_alloc_granularity[0x6];
 945         u8         log_steering_sw_icm_size[0x8];
 946
 947         u8         reserved_at_120[0x20];
 948
 949         u8         header_modify_sw_icm_start_address[0x40];
 950
 951         u8         reserved_at_180[0x680];
 952 };
 953
 954 struct mlx5_ifc_device_event_cap_bits {
 955         u8         user_affiliated_events[4][0x40];
 956
 957         u8         user_unaffiliated_events[4][0x40];
 958 };
 959
 960 enum {
 961         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 962         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 963         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 964         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 965         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 966         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 967         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 968         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 969         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 970 };
 971
 972 enum {
 973         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 974         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 975         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 976         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 977         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 978         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 979         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 980         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 981         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 982 };
 983
 984 struct mlx5_ifc_atomic_caps_bits {
 985         u8         reserved_at_0[0x40];
 986
 987         u8         atomic_req_8B_endianness_mode[0x2];
 988         u8         reserved_at_42[0x4];
 989         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 990
 991         u8         reserved_at_47[0x19];
 992
 993         u8         reserved_at_60[0x20];
 994
 995         u8         reserved_at_80[0x10];
 996         u8         atomic_operations[0x10];
 997
 998         u8         reserved_at_a0[0x10];
 999         u8         atomic_size_qp[0x10];
1000
1001         u8         reserved_at_c0[0x10];
1002         u8         atomic_size_dc[0x10];
1003
1004         u8         reserved_at_e0[0x720];
1005 };
1006
1007 struct mlx5_ifc_odp_cap_bits {
1008         u8         reserved_at_0[0x40];
1009
1010         u8         sig[0x1];
1011         u8         reserved_at_41[0x1f];
1012
1013         u8         reserved_at_60[0x20];
1014
1015         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1016
1017         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1018
1019         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1020
1021         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1022
1023         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1024
1025         u8         reserved_at_120[0x6E0];
1026 };
1027
1028 struct mlx5_ifc_calc_op {
1029         u8        reserved_at_0[0x10];
1030         u8        reserved_at_10[0x9];
1031         u8        op_swap_endianness[0x1];
1032         u8        op_min[0x1];
1033         u8        op_xor[0x1];
1034         u8        op_or[0x1];
1035         u8        op_and[0x1];
1036         u8        op_max[0x1];
1037         u8        op_add[0x1];
1038 };
1039
1040 struct mlx5_ifc_vector_calc_cap_bits {
1041         u8         calc_matrix[0x1];
1042         u8         reserved_at_1[0x1f];
1043         u8         reserved_at_20[0x8];
1044         u8         max_vec_count[0x8];
1045         u8         reserved_at_30[0xd];
1046         u8         max_chunk_size[0x3];
1047         struct mlx5_ifc_calc_op calc0;
1048         struct mlx5_ifc_calc_op calc1;
1049         struct mlx5_ifc_calc_op calc2;
1050         struct mlx5_ifc_calc_op calc3;
1051
1052         u8         reserved_at_c0[0x720];
1053 };
1054
1055 struct mlx5_ifc_tls_cap_bits {
1056         u8         tls_1_2_aes_gcm_128[0x1];
1057         u8         tls_1_3_aes_gcm_128[0x1];
1058         u8         tls_1_2_aes_gcm_256[0x1];
1059         u8         tls_1_3_aes_gcm_256[0x1];
1060         u8         reserved_at_4[0x1c];
1061
1062         u8         reserved_at_20[0x7e0];
1063 };
1064
1065 enum {
1066         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1067         MLX5_WQ_TYPE_CYCLIC       = 0x1,
1068         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1069         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1070 };
1071
1072 enum {
1073         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1074         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1075 };
1076
1077 enum {
1078         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1079         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1080         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1081         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1082         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1083 };
1084
1085 enum {
1086         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1087         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1088         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1089         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1090         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1091         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1092 };
1093
1094 enum {
1095         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1096         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1097 };
1098
1099 enum {
1100         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1101         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1102         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1103 };
1104
1105 enum {
1106         MLX5_CAP_PORT_TYPE_IB  = 0x0,
1107         MLX5_CAP_PORT_TYPE_ETH = 0x1,
1108 };
1109
1110 enum {
1111         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
1112         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
1113         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
1114 };
1115
1116 enum {
1117         MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED      = 1 << 7,
1118         MLX5_FLEX_PARSER_ICMP_V4_ENABLED        = 1 << 8,
1119         MLX5_FLEX_PARSER_ICMP_V6_ENABLED        = 1 << 9,
1120 };
1121
1122 enum {
1123         MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1124         MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1125 };
1126
1127 #define MLX5_FC_BULK_SIZE_FACTOR 128
1128
1129 enum mlx5_fc_bulk_alloc_bitmask {
1130         MLX5_FC_BULK_128   = (1 << 0),
1131         MLX5_FC_BULK_256   = (1 << 1),
1132         MLX5_FC_BULK_512   = (1 << 2),
1133         MLX5_FC_BULK_1024  = (1 << 3),
1134         MLX5_FC_BULK_2048  = (1 << 4),
1135         MLX5_FC_BULK_4096  = (1 << 5),
1136         MLX5_FC_BULK_8192  = (1 << 6),
1137         MLX5_FC_BULK_16384 = (1 << 7),
1138 };
1139
1140 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1141
1142 enum {
1143         MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1144         MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1145 };
1146
1147 struct mlx5_ifc_cmd_hca_cap_bits {
1148         u8         reserved_at_0[0x30];
1149         u8         vhca_id[0x10];
1150
1151         u8         reserved_at_40[0x40];
1152
1153         u8         log_max_srq_sz[0x8];
1154         u8         log_max_qp_sz[0x8];
1155         u8         event_cap[0x1];
1156         u8         reserved_at_91[0x7];
1157         u8         prio_tag_required[0x1];
1158         u8         reserved_at_99[0x2];
1159         u8         log_max_qp[0x5];
1160
1161         u8         reserved_at_a0[0xb];
1162         u8         log_max_srq[0x5];
1163         u8         reserved_at_b0[0x10];
1164
1165         u8         reserved_at_c0[0x8];
1166         u8         log_max_cq_sz[0x8];
1167         u8         reserved_at_d0[0xb];
1168         u8         log_max_cq[0x5];
1169
1170         u8         log_max_eq_sz[0x8];
1171         u8         reserved_at_e8[0x2];
1172         u8         log_max_mkey[0x6];
1173         u8         reserved_at_f0[0x8];
1174         u8         dump_fill_mkey[0x1];
1175         u8         reserved_at_f9[0x2];
1176         u8         fast_teardown[0x1];
1177         u8         log_max_eq[0x4];
1178
1179         u8         max_indirection[0x8];
1180         u8         fixed_buffer_size[0x1];
1181         u8         log_max_mrw_sz[0x7];
1182         u8         force_teardown[0x1];
1183         u8         reserved_at_111[0x1];
1184         u8         log_max_bsf_list_size[0x6];
1185         u8         umr_extended_translation_offset[0x1];
1186         u8         null_mkey[0x1];
1187         u8         log_max_klm_list_size[0x6];
1188
1189         u8         reserved_at_120[0xa];
1190         u8         log_max_ra_req_dc[0x6];
1191         u8         reserved_at_130[0xa];
1192         u8         log_max_ra_res_dc[0x6];
1193
1194         u8         reserved_at_140[0xa];
1195         u8         log_max_ra_req_qp[0x6];
1196         u8         reserved_at_150[0xa];
1197         u8         log_max_ra_res_qp[0x6];
1198
1199         u8         end_pad[0x1];
1200         u8         cc_query_allowed[0x1];
1201         u8         cc_modify_allowed[0x1];
1202         u8         start_pad[0x1];
1203         u8         cache_line_128byte[0x1];
1204         u8         reserved_at_165[0x4];
1205         u8         rts2rts_qp_counters_set_id[0x1];
1206         u8         reserved_at_16a[0x2];
1207         u8         vnic_env_int_rq_oob[0x1];
1208         u8         sbcam_reg[0x1];
1209         u8         reserved_at_16e[0x1];
1210         u8         qcam_reg[0x1];
1211         u8         gid_table_size[0x10];
1212
1213         u8         out_of_seq_cnt[0x1];
1214         u8         vport_counters[0x1];
1215         u8         retransmission_q_counters[0x1];
1216         u8         debug[0x1];
1217         u8         modify_rq_counter_set_id[0x1];
1218         u8         rq_delay_drop[0x1];
1219         u8         max_qp_cnt[0xa];
1220         u8         pkey_table_size[0x10];
1221
1222         u8         vport_group_manager[0x1];
1223         u8         vhca_group_manager[0x1];
1224         u8         ib_virt[0x1];
1225         u8         eth_virt[0x1];
1226         u8         vnic_env_queue_counters[0x1];
1227         u8         ets[0x1];
1228         u8         nic_flow_table[0x1];
1229         u8         eswitch_manager[0x1];
1230         u8         device_memory[0x1];
1231         u8         mcam_reg[0x1];
1232         u8         pcam_reg[0x1];
1233         u8         local_ca_ack_delay[0x5];
1234         u8         port_module_event[0x1];
1235         u8         enhanced_error_q_counters[0x1];
1236         u8         ports_check[0x1];
1237         u8         reserved_at_1b3[0x1];
1238         u8         disable_link_up[0x1];
1239         u8         beacon_led[0x1];
1240         u8         port_type[0x2];
1241         u8         num_ports[0x8];
1242
1243         u8         reserved_at_1c0[0x1];
1244         u8         pps[0x1];
1245         u8         pps_modify[0x1];
1246         u8         log_max_msg[0x5];
1247         u8         reserved_at_1c8[0x4];
1248         u8         max_tc[0x4];
1249         u8         temp_warn_event[0x1];
1250         u8         dcbx[0x1];
1251         u8         general_notification_event[0x1];
1252         u8         reserved_at_1d3[0x2];
1253         u8         fpga[0x1];
1254         u8         rol_s[0x1];
1255         u8         rol_g[0x1];
1256         u8         reserved_at_1d8[0x1];
1257         u8         wol_s[0x1];
1258         u8         wol_g[0x1];
1259         u8         wol_a[0x1];
1260         u8         wol_b[0x1];
1261         u8         wol_m[0x1];
1262         u8         wol_u[0x1];
1263         u8         wol_p[0x1];
1264
1265         u8         stat_rate_support[0x10];
1266         u8         reserved_at_1f0[0xc];
1267         u8         cqe_version[0x4];
1268
1269         u8         compact_address_vector[0x1];
1270         u8         striding_rq[0x1];
1271         u8         reserved_at_202[0x1];
1272         u8         ipoib_enhanced_offloads[0x1];
1273         u8         ipoib_basic_offloads[0x1];
1274         u8         reserved_at_205[0x1];
1275         u8         repeated_block_disabled[0x1];
1276         u8         umr_modify_entity_size_disabled[0x1];
1277         u8         umr_modify_atomic_disabled[0x1];
1278         u8         umr_indirect_mkey_disabled[0x1];
1279         u8         umr_fence[0x2];
1280         u8         dc_req_scat_data_cqe[0x1];
1281         u8         reserved_at_20d[0x2];
1282         u8         drain_sigerr[0x1];
1283         u8         cmdif_checksum[0x2];
1284         u8         sigerr_cqe[0x1];
1285         u8         reserved_at_213[0x1];
1286         u8         wq_signature[0x1];
1287         u8         sctr_data_cqe[0x1];
1288         u8         reserved_at_216[0x1];
1289         u8         sho[0x1];
1290         u8         tph[0x1];
1291         u8         rf[0x1];
1292         u8         dct[0x1];
1293         u8         qos[0x1];
1294         u8         eth_net_offloads[0x1];
1295         u8         roce[0x1];
1296         u8         atomic[0x1];
1297         u8         reserved_at_21f[0x1];
1298
1299         u8         cq_oi[0x1];
1300         u8         cq_resize[0x1];
1301         u8         cq_moderation[0x1];
1302         u8         reserved_at_223[0x3];
1303         u8         cq_eq_remap[0x1];
1304         u8         pg[0x1];
1305         u8         block_lb_mc[0x1];
1306         u8         reserved_at_229[0x1];
1307         u8         scqe_break_moderation[0x1];
1308         u8         cq_period_start_from_cqe[0x1];
1309         u8         cd[0x1];
1310         u8         reserved_at_22d[0x1];
1311         u8         apm[0x1];
1312         u8         vector_calc[0x1];
1313         u8         umr_ptr_rlky[0x1];
1314         u8         imaicl[0x1];
1315         u8         qp_packet_based[0x1];
1316         u8         reserved_at_233[0x3];
1317         u8         qkv[0x1];
1318         u8         pkv[0x1];
1319         u8         set_deth_sqpn[0x1];
1320         u8         reserved_at_239[0x3];
1321         u8         xrc[0x1];
1322         u8         ud[0x1];
1323         u8         uc[0x1];
1324         u8         rc[0x1];
1325
1326         u8         uar_4k[0x1];
1327         u8         reserved_at_241[0x9];
1328         u8         uar_sz[0x6];
1329         u8         reserved_at_250[0x8];
1330         u8         log_pg_sz[0x8];
1331
1332         u8         bf[0x1];
1333         u8         driver_version[0x1];
1334         u8         pad_tx_eth_packet[0x1];
1335         u8         reserved_at_263[0x8];
1336         u8         log_bf_reg_size[0x5];
1337
1338         u8         reserved_at_270[0x8];
1339         u8         lag_tx_port_affinity[0x1];
1340         u8         reserved_at_279[0x2];
1341         u8         lag_master[0x1];
1342         u8         num_lag_ports[0x4];
1343
1344         u8         reserved_at_280[0x10];
1345         u8         max_wqe_sz_sq[0x10];
1346
1347         u8         reserved_at_2a0[0x10];
1348         u8         max_wqe_sz_rq[0x10];
1349
1350         u8         max_flow_counter_31_16[0x10];
1351         u8         max_wqe_sz_sq_dc[0x10];
1352
1353         u8         reserved_at_2e0[0x7];
1354         u8         max_qp_mcg[0x19];
1355
1356         u8         reserved_at_300[0x10];
1357         u8         flow_counter_bulk_alloc[0x8];
1358         u8         log_max_mcg[0x8];
1359
1360         u8         reserved_at_320[0x3];
1361         u8         log_max_transport_domain[0x5];
1362         u8         reserved_at_328[0x3];
1363         u8         log_max_pd[0x5];
1364         u8         reserved_at_330[0xb];
1365         u8         log_max_xrcd[0x5];
1366
1367         u8         nic_receive_steering_discard[0x1];
1368         u8         receive_discard_vport_down[0x1];
1369         u8         transmit_discard_vport_down[0x1];
1370         u8         reserved_at_343[0x5];
1371         u8         log_max_flow_counter_bulk[0x8];
1372         u8         max_flow_counter_15_0[0x10];
1373
1374
1375         u8         reserved_at_360[0x3];
1376         u8         log_max_rq[0x5];
1377         u8         reserved_at_368[0x3];
1378         u8         log_max_sq[0x5];
1379         u8         reserved_at_370[0x3];
1380         u8         log_max_tir[0x5];
1381         u8         reserved_at_378[0x3];
1382         u8         log_max_tis[0x5];
1383
1384         u8         basic_cyclic_rcv_wqe[0x1];
1385         u8         reserved_at_381[0x2];
1386         u8         log_max_rmp[0x5];
1387         u8         reserved_at_388[0x3];
1388         u8         log_max_rqt[0x5];
1389         u8         reserved_at_390[0x3];
1390         u8         log_max_rqt_size[0x5];
1391         u8         reserved_at_398[0x3];
1392         u8         log_max_tis_per_sq[0x5];
1393
1394         u8         ext_stride_num_range[0x1];
1395         u8         reserved_at_3a1[0x2];
1396         u8         log_max_stride_sz_rq[0x5];
1397         u8         reserved_at_3a8[0x3];
1398         u8         log_min_stride_sz_rq[0x5];
1399         u8         reserved_at_3b0[0x3];
1400         u8         log_max_stride_sz_sq[0x5];
1401         u8         reserved_at_3b8[0x3];
1402         u8         log_min_stride_sz_sq[0x5];
1403
1404         u8         hairpin[0x1];
1405         u8         reserved_at_3c1[0x2];
1406         u8         log_max_hairpin_queues[0x5];
1407         u8         reserved_at_3c8[0x3];
1408         u8         log_max_hairpin_wq_data_sz[0x5];
1409         u8         reserved_at_3d0[0x3];
1410         u8         log_max_hairpin_num_packets[0x5];
1411         u8         reserved_at_3d8[0x3];
1412         u8         log_max_wq_sz[0x5];
1413
1414         u8         nic_vport_change_event[0x1];
1415         u8         disable_local_lb_uc[0x1];
1416         u8         disable_local_lb_mc[0x1];
1417         u8         log_min_hairpin_wq_data_sz[0x5];
1418         u8         reserved_at_3e8[0x3];
1419         u8         log_max_vlan_list[0x5];
1420         u8         reserved_at_3f0[0x3];
1421         u8         log_max_current_mc_list[0x5];
1422         u8         reserved_at_3f8[0x3];
1423         u8         log_max_current_uc_list[0x5];
1424
1425         u8         general_obj_types[0x40];
1426
1427         u8         reserved_at_440[0x4];
1428         u8         steering_format_version[0x4];
1429         u8         create_qp_start_hint[0x18];
1430
1431         u8         reserved_at_460[0x3];
1432         u8         log_max_uctx[0x5];
1433         u8         reserved_at_468[0x3];
1434         u8         log_max_umem[0x5];
1435         u8         max_num_eqs[0x10];
1436
1437         u8         reserved_at_480[0x1];
1438         u8         tls_tx[0x1];
1439         u8         reserved_at_482[0x1];
1440         u8         log_max_l2_table[0x5];
1441         u8         reserved_at_488[0x8];
1442         u8         log_uar_page_sz[0x10];
1443
1444         u8         reserved_at_4a0[0x20];
1445         u8         device_frequency_mhz[0x20];
1446         u8         device_frequency_khz[0x20];
1447
1448         u8         reserved_at_500[0x20];
1449         u8         num_of_uars_per_page[0x20];
1450
1451         u8         flex_parser_protocols[0x20];
1452
1453         u8         max_geneve_tlv_options[0x8];
1454         u8         reserved_at_568[0x3];
1455         u8         max_geneve_tlv_option_data_len[0x5];
1456         u8         reserved_at_570[0x10];
1457
1458         u8         reserved_at_580[0x33];
1459         u8         log_max_dek[0x5];
1460         u8         reserved_at_5b8[0x4];
1461         u8         mini_cqe_resp_stride_index[0x1];
1462         u8         cqe_128_always[0x1];
1463         u8         cqe_compression_128[0x1];
1464         u8         cqe_compression[0x1];
1465
1466         u8         cqe_compression_timeout[0x10];
1467         u8         cqe_compression_max_num[0x10];
1468
1469         u8         reserved_at_5e0[0x10];
1470         u8         tag_matching[0x1];
1471         u8         rndv_offload_rc[0x1];
1472         u8         rndv_offload_dc[0x1];
1473         u8         log_tag_matching_list_sz[0x5];
1474         u8         reserved_at_5f8[0x3];
1475         u8         log_max_xrq[0x5];
1476
1477         u8         affiliate_nic_vport_criteria[0x8];
1478         u8         native_port_num[0x8];
1479         u8         num_vhca_ports[0x8];
1480         u8         reserved_at_618[0x6];
1481         u8         sw_owner_id[0x1];
1482         u8         reserved_at_61f[0x1];
1483
1484         u8         max_num_of_monitor_counters[0x10];
1485         u8         num_ppcnt_monitor_counters[0x10];
1486
1487         u8         reserved_at_640[0x10];
1488         u8         num_q_monitor_counters[0x10];
1489
1490         u8         reserved_at_660[0x20];
1491
1492         u8         sf[0x1];
1493         u8         sf_set_partition[0x1];
1494         u8         reserved_at_682[0x1];
1495         u8         log_max_sf[0x5];
1496         u8         reserved_at_688[0x8];
1497         u8         log_min_sf_size[0x8];
1498         u8         max_num_sf_partitions[0x8];
1499
1500         u8         uctx_cap[0x20];
1501
1502         u8         reserved_at_6c0[0x4];
1503         u8         flex_parser_id_geneve_tlv_option_0[0x4];
1504         u8         flex_parser_id_icmp_dw1[0x4];
1505         u8         flex_parser_id_icmp_dw0[0x4];
1506         u8         flex_parser_id_icmpv6_dw1[0x4];
1507         u8         flex_parser_id_icmpv6_dw0[0x4];
1508         u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
1509         u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1510
1511         u8         reserved_at_6e0[0x10];
1512         u8         sf_base_id[0x10];
1513
1514         u8         reserved_at_700[0x80];
1515         u8         vhca_tunnel_commands[0x40];
1516         u8         reserved_at_7c0[0x40];
1517 };
1518
1519 enum mlx5_flow_destination_type {
1520         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1521         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1522         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1523
1524         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1525         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1526         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1527 };
1528
1529 enum mlx5_flow_table_miss_action {
1530         MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1531         MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1532         MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1533 };
1534
1535 struct mlx5_ifc_dest_format_struct_bits {
1536         u8         destination_type[0x8];
1537         u8         destination_id[0x18];
1538
1539         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1540         u8         packet_reformat[0x1];
1541         u8         reserved_at_22[0xe];
1542         u8         destination_eswitch_owner_vhca_id[0x10];
1543 };
1544
1545 struct mlx5_ifc_flow_counter_list_bits {
1546         u8         flow_counter_id[0x20];
1547
1548         u8         reserved_at_20[0x20];
1549 };
1550
1551 struct mlx5_ifc_extended_dest_format_bits {
1552         struct mlx5_ifc_dest_format_struct_bits destination_entry;
1553
1554         u8         packet_reformat_id[0x20];
1555
1556         u8         reserved_at_60[0x20];
1557 };
1558
1559 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1560         struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1561         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1562 };
1563
1564 struct mlx5_ifc_fte_match_param_bits {
1565         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1566
1567         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1568
1569         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1570
1571         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1572
1573         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1574
1575         u8         reserved_at_a00[0x600];
1576 };
1577
1578 enum {
1579         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1580         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1581         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1582         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1583         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1584 };
1585
1586 struct mlx5_ifc_rx_hash_field_select_bits {
1587         u8         l3_prot_type[0x1];
1588         u8         l4_prot_type[0x1];
1589         u8         selected_fields[0x1e];
1590 };
1591
1592 enum {
1593         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1594         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1595 };
1596
1597 enum {
1598         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1599         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1600 };
1601
1602 struct mlx5_ifc_wq_bits {
1603         u8         wq_type[0x4];
1604         u8         wq_signature[0x1];
1605         u8         end_padding_mode[0x2];
1606         u8         cd_slave[0x1];
1607         u8         reserved_at_8[0x18];
1608
1609         u8         hds_skip_first_sge[0x1];
1610         u8         log2_hds_buf_size[0x3];
1611         u8         reserved_at_24[0x7];
1612         u8         page_offset[0x5];
1613         u8         lwm[0x10];
1614
1615         u8         reserved_at_40[0x8];
1616         u8         pd[0x18];
1617
1618         u8         reserved_at_60[0x8];
1619         u8         uar_page[0x18];
1620
1621         u8         dbr_addr[0x40];
1622
1623         u8         hw_counter[0x20];
1624
1625         u8         sw_counter[0x20];
1626
1627         u8         reserved_at_100[0xc];
1628         u8         log_wq_stride[0x4];
1629         u8         reserved_at_110[0x3];
1630         u8         log_wq_pg_sz[0x5];
1631         u8         reserved_at_118[0x3];
1632         u8         log_wq_sz[0x5];
1633
1634         u8         dbr_umem_valid[0x1];
1635         u8         wq_umem_valid[0x1];
1636         u8         reserved_at_122[0x1];
1637         u8         log_hairpin_num_packets[0x5];
1638         u8         reserved_at_128[0x3];
1639         u8         log_hairpin_data_sz[0x5];
1640
1641         u8         reserved_at_130[0x4];
1642         u8         log_wqe_num_of_strides[0x4];
1643         u8         two_byte_shift_en[0x1];
1644         u8         reserved_at_139[0x4];
1645         u8         log_wqe_stride_size[0x3];
1646
1647         u8         reserved_at_140[0x4c0];
1648
1649         struct mlx5_ifc_cmd_pas_bits pas[0];
1650 };
1651
1652 struct mlx5_ifc_rq_num_bits {
1653         u8         reserved_at_0[0x8];
1654         u8         rq_num[0x18];
1655 };
1656
1657 struct mlx5_ifc_mac_address_layout_bits {
1658         u8         reserved_at_0[0x10];
1659         u8         mac_addr_47_32[0x10];
1660
1661         u8         mac_addr_31_0[0x20];
1662 };
1663
1664 struct mlx5_ifc_vlan_layout_bits {
1665         u8         reserved_at_0[0x14];
1666         u8         vlan[0x0c];
1667
1668         u8         reserved_at_20[0x20];
1669 };
1670
1671 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1672         u8         reserved_at_0[0xa0];
1673
1674         u8         min_time_between_cnps[0x20];
1675
1676         u8         reserved_at_c0[0x12];
1677         u8         cnp_dscp[0x6];
1678         u8         reserved_at_d8[0x4];
1679         u8         cnp_prio_mode[0x1];
1680         u8         cnp_802p_prio[0x3];
1681
1682         u8         reserved_at_e0[0x720];
1683 };
1684
1685 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1686         u8         reserved_at_0[0x60];
1687
1688         u8         reserved_at_60[0x4];
1689         u8         clamp_tgt_rate[0x1];
1690         u8         reserved_at_65[0x3];
1691         u8         clamp_tgt_rate_after_time_inc[0x1];
1692         u8         reserved_at_69[0x17];
1693
1694         u8         reserved_at_80[0x20];
1695
1696         u8         rpg_time_reset[0x20];
1697
1698         u8         rpg_byte_reset[0x20];
1699
1700         u8         rpg_threshold[0x20];
1701
1702         u8         rpg_max_rate[0x20];
1703
1704         u8         rpg_ai_rate[0x20];
1705
1706         u8         rpg_hai_rate[0x20];
1707
1708         u8         rpg_gd[0x20];
1709
1710         u8         rpg_min_dec_fac[0x20];
1711
1712         u8         rpg_min_rate[0x20];
1713
1714         u8         reserved_at_1c0[0xe0];
1715
1716         u8         rate_to_set_on_first_cnp[0x20];
1717
1718         u8         dce_tcp_g[0x20];
1719
1720         u8         dce_tcp_rtt[0x20];
1721
1722         u8         rate_reduce_monitor_period[0x20];
1723
1724         u8         reserved_at_320[0x20];
1725
1726         u8         initial_alpha_value[0x20];
1727
1728         u8         reserved_at_360[0x4a0];
1729 };
1730
1731 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1732         u8         reserved_at_0[0x80];
1733
1734         u8         rppp_max_rps[0x20];
1735
1736         u8         rpg_time_reset[0x20];
1737
1738         u8         rpg_byte_reset[0x20];
1739
1740         u8         rpg_threshold[0x20];
1741
1742         u8         rpg_max_rate[0x20];
1743
1744         u8         rpg_ai_rate[0x20];
1745
1746         u8         rpg_hai_rate[0x20];
1747
1748         u8         rpg_gd[0x20];
1749
1750         u8         rpg_min_dec_fac[0x20];
1751
1752         u8         rpg_min_rate[0x20];
1753
1754         u8         reserved_at_1c0[0x640];
1755 };
1756
1757 enum {
1758         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1759         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1760         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1761 };
1762
1763 struct mlx5_ifc_resize_field_select_bits {
1764         u8         resize_field_select[0x20];
1765 };
1766
1767 enum {
1768         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1769         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1770         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1771         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1772 };
1773
1774 struct mlx5_ifc_modify_field_select_bits {
1775         u8         modify_field_select[0x20];
1776 };
1777
1778 struct mlx5_ifc_field_select_r_roce_np_bits {
1779         u8         field_select_r_roce_np[0x20];
1780 };
1781
1782 struct mlx5_ifc_field_select_r_roce_rp_bits {
1783         u8         field_select_r_roce_rp[0x20];
1784 };
1785
1786 enum {
1787         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1788         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1789         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1790         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1791         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1792         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1793         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1794         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1795         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1796         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1797 };
1798
1799 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1800         u8         field_select_8021qaurp[0x20];
1801 };
1802
1803 struct mlx5_ifc_phys_layer_cntrs_bits {
1804         u8         time_since_last_clear_high[0x20];
1805
1806         u8         time_since_last_clear_low[0x20];
1807
1808         u8         symbol_errors_high[0x20];
1809
1810         u8         symbol_errors_low[0x20];
1811
1812         u8         sync_headers_errors_high[0x20];
1813
1814         u8         sync_headers_errors_low[0x20];
1815
1816         u8         edpl_bip_errors_lane0_high[0x20];
1817
1818         u8         edpl_bip_errors_lane0_low[0x20];
1819
1820         u8         edpl_bip_errors_lane1_high[0x20];
1821
1822         u8         edpl_bip_errors_lane1_low[0x20];
1823
1824         u8         edpl_bip_errors_lane2_high[0x20];
1825
1826         u8         edpl_bip_errors_lane2_low[0x20];
1827
1828         u8         edpl_bip_errors_lane3_high[0x20];
1829
1830         u8         edpl_bip_errors_lane3_low[0x20];
1831
1832         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1833
1834         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1835
1836         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1837
1838         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1839
1840         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1841
1842         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1843
1844         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1845
1846         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1847
1848         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1849
1850         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1851
1852         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1853
1854         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1855
1856         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1857
1858         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1859
1860         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1861
1862         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1863
1864         u8         rs_fec_corrected_blocks_high[0x20];
1865
1866         u8         rs_fec_corrected_blocks_low[0x20];
1867
1868         u8         rs_fec_uncorrectable_blocks_high[0x20];
1869
1870         u8         rs_fec_uncorrectable_blocks_low[0x20];
1871
1872         u8         rs_fec_no_errors_blocks_high[0x20];
1873
1874         u8         rs_fec_no_errors_blocks_low[0x20];
1875
1876         u8         rs_fec_single_error_blocks_high[0x20];
1877
1878         u8         rs_fec_single_error_blocks_low[0x20];
1879
1880         u8         rs_fec_corrected_symbols_total_high[0x20];
1881
1882         u8         rs_fec_corrected_symbols_total_low[0x20];
1883
1884         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1885
1886         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1887
1888         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1889
1890         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1891
1892         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1893
1894         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1895
1896         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1897
1898         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1899
1900         u8         link_down_events[0x20];
1901
1902         u8         successful_recovery_events[0x20];
1903
1904         u8         reserved_at_640[0x180];
1905 };
1906
1907 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1908         u8         time_since_last_clear_high[0x20];
1909
1910         u8         time_since_last_clear_low[0x20];
1911
1912         u8         phy_received_bits_high[0x20];
1913
1914         u8         phy_received_bits_low[0x20];
1915
1916         u8         phy_symbol_errors_high[0x20];
1917
1918         u8         phy_symbol_errors_low[0x20];
1919
1920         u8         phy_corrected_bits_high[0x20];
1921
1922         u8         phy_corrected_bits_low[0x20];
1923
1924         u8         phy_corrected_bits_lane0_high[0x20];
1925
1926         u8         phy_corrected_bits_lane0_low[0x20];
1927
1928         u8         phy_corrected_bits_lane1_high[0x20];
1929
1930         u8         phy_corrected_bits_lane1_low[0x20];
1931
1932         u8         phy_corrected_bits_lane2_high[0x20];
1933
1934         u8         phy_corrected_bits_lane2_low[0x20];
1935
1936         u8         phy_corrected_bits_lane3_high[0x20];
1937
1938         u8         phy_corrected_bits_lane3_low[0x20];
1939
1940         u8         reserved_at_200[0x5c0];
1941 };
1942
1943 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1944         u8         symbol_error_counter[0x10];
1945
1946         u8         link_error_recovery_counter[0x8];
1947
1948         u8         link_downed_counter[0x8];
1949
1950         u8         port_rcv_errors[0x10];
1951
1952         u8         port_rcv_remote_physical_errors[0x10];
1953
1954         u8         port_rcv_switch_relay_errors[0x10];
1955
1956         u8         port_xmit_discards[0x10];
1957
1958         u8         port_xmit_constraint_errors[0x8];
1959
1960         u8         port_rcv_constraint_errors[0x8];
1961
1962         u8         reserved_at_70[0x8];
1963
1964         u8         link_overrun_errors[0x8];
1965
1966         u8         reserved_at_80[0x10];
1967
1968         u8         vl_15_dropped[0x10];
1969
1970         u8         reserved_at_a0[0x80];
1971
1972         u8         port_xmit_wait[0x20];
1973 };
1974
1975 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
1976         u8         transmit_queue_high[0x20];
1977
1978         u8         transmit_queue_low[0x20];
1979
1980         u8         no_buffer_discard_uc_high[0x20];
1981
1982         u8         no_buffer_discard_uc_low[0x20];
1983
1984         u8         reserved_at_80[0x740];
1985 };
1986
1987 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
1988         u8         wred_discard_high[0x20];
1989
1990         u8         wred_discard_low[0x20];
1991
1992         u8         ecn_marked_tc_high[0x20];
1993
1994         u8         ecn_marked_tc_low[0x20];
1995
1996         u8         reserved_at_80[0x740];
1997 };
1998
1999 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2000         u8         rx_octets_high[0x20];
2001
2002         u8         rx_octets_low[0x20];
2003
2004         u8         reserved_at_40[0xc0];
2005
2006         u8         rx_frames_high[0x20];
2007
2008         u8         rx_frames_low[0x20];
2009
2010         u8         tx_octets_high[0x20];
2011
2012         u8         tx_octets_low[0x20];
2013
2014         u8         reserved_at_180[0xc0];
2015
2016         u8         tx_frames_high[0x20];
2017
2018         u8         tx_frames_low[0x20];
2019
2020         u8         rx_pause_high[0x20];
2021
2022         u8         rx_pause_low[0x20];
2023
2024         u8         rx_pause_duration_high[0x20];
2025
2026         u8         rx_pause_duration_low[0x20];
2027
2028         u8         tx_pause_high[0x20];
2029
2030         u8         tx_pause_low[0x20];
2031
2032         u8         tx_pause_duration_high[0x20];
2033
2034         u8         tx_pause_duration_low[0x20];
2035
2036         u8         rx_pause_transition_high[0x20];
2037
2038         u8         rx_pause_transition_low[0x20];
2039
2040         u8         reserved_at_3c0[0x40];
2041
2042         u8         device_stall_minor_watermark_cnt_high[0x20];
2043
2044         u8         device_stall_minor_watermark_cnt_low[0x20];
2045
2046         u8         device_stall_critical_watermark_cnt_high[0x20];
2047
2048         u8         device_stall_critical_watermark_cnt_low[0x20];
2049
2050         u8         reserved_at_480[0x340];
2051 };
2052
2053 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2054         u8         port_transmit_wait_high[0x20];
2055
2056         u8         port_transmit_wait_low[0x20];
2057
2058         u8         reserved_at_40[0x100];
2059
2060         u8         rx_buffer_almost_full_high[0x20];
2061
2062         u8         rx_buffer_almost_full_low[0x20];
2063
2064         u8         rx_buffer_full_high[0x20];
2065
2066         u8         rx_buffer_full_low[0x20];
2067
2068         u8         rx_icrc_encapsulated_high[0x20];
2069
2070         u8         rx_icrc_encapsulated_low[0x20];
2071
2072         u8         reserved_at_200[0x5c0];
2073 };
2074
2075 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2076         u8         dot3stats_alignment_errors_high[0x20];
2077
2078         u8         dot3stats_alignment_errors_low[0x20];
2079
2080         u8         dot3stats_fcs_errors_high[0x20];
2081
2082         u8         dot3stats_fcs_errors_low[0x20];
2083
2084         u8         dot3stats_single_collision_frames_high[0x20];
2085
2086         u8         dot3stats_single_collision_frames_low[0x20];
2087
2088         u8         dot3stats_multiple_collision_frames_high[0x20];
2089
2090         u8         dot3stats_multiple_collision_frames_low[0x20];
2091
2092         u8         dot3stats_sqe_test_errors_high[0x20];
2093
2094         u8         dot3stats_sqe_test_errors_low[0x20];
2095
2096         u8         dot3stats_deferred_transmissions_high[0x20];
2097
2098         u8         dot3stats_deferred_transmissions_low[0x20];
2099
2100         u8         dot3stats_late_collisions_high[0x20];
2101
2102         u8         dot3stats_late_collisions_low[0x20];
2103
2104         u8         dot3stats_excessive_collisions_high[0x20];
2105
2106         u8         dot3stats_excessive_collisions_low[0x20];
2107
2108         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2109
2110         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2111
2112         u8         dot3stats_carrier_sense_errors_high[0x20];
2113
2114         u8         dot3stats_carrier_sense_errors_low[0x20];
2115
2116         u8         dot3stats_frame_too_longs_high[0x20];
2117
2118         u8         dot3stats_frame_too_longs_low[0x20];
2119
2120         u8         dot3stats_internal_mac_receive_errors_high[0x20];
2121
2122         u8         dot3stats_internal_mac_receive_errors_low[0x20];
2123
2124         u8         dot3stats_symbol_errors_high[0x20];
2125
2126         u8         dot3stats_symbol_errors_low[0x20];
2127
2128         u8         dot3control_in_unknown_opcodes_high[0x20];
2129
2130         u8         dot3control_in_unknown_opcodes_low[0x20];
2131
2132         u8         dot3in_pause_frames_high[0x20];
2133
2134         u8         dot3in_pause_frames_low[0x20];
2135
2136         u8         dot3out_pause_frames_high[0x20];
2137
2138         u8         dot3out_pause_frames_low[0x20];
2139
2140         u8         reserved_at_400[0x3c0];
2141 };
2142
2143 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2144         u8         ether_stats_drop_events_high[0x20];
2145
2146         u8         ether_stats_drop_events_low[0x20];
2147
2148         u8         ether_stats_octets_high[0x20];
2149
2150         u8         ether_stats_octets_low[0x20];
2151
2152         u8         ether_stats_pkts_high[0x20];
2153
2154         u8         ether_stats_pkts_low[0x20];
2155
2156         u8         ether_stats_broadcast_pkts_high[0x20];
2157
2158         u8         ether_stats_broadcast_pkts_low[0x20];
2159
2160         u8         ether_stats_multicast_pkts_high[0x20];
2161
2162         u8         ether_stats_multicast_pkts_low[0x20];
2163
2164         u8         ether_stats_crc_align_errors_high[0x20];
2165
2166         u8         ether_stats_crc_align_errors_low[0x20];
2167
2168         u8         ether_stats_undersize_pkts_high[0x20];
2169
2170         u8         ether_stats_undersize_pkts_low[0x20];
2171
2172         u8         ether_stats_oversize_pkts_high[0x20];
2173
2174         u8         ether_stats_oversize_pkts_low[0x20];
2175
2176         u8         ether_stats_fragments_high[0x20];
2177
2178         u8         ether_stats_fragments_low[0x20];
2179
2180         u8         ether_stats_jabbers_high[0x20];
2181
2182         u8         ether_stats_jabbers_low[0x20];
2183
2184         u8         ether_stats_collisions_high[0x20];
2185
2186         u8         ether_stats_collisions_low[0x20];
2187
2188         u8         ether_stats_pkts64octets_high[0x20];
2189
2190         u8         ether_stats_pkts64octets_low[0x20];
2191
2192         u8         ether_stats_pkts65to127octets_high[0x20];
2193
2194         u8         ether_stats_pkts65to127octets_low[0x20];
2195
2196         u8         ether_stats_pkts128to255octets_high[0x20];
2197
2198         u8         ether_stats_pkts128to255octets_low[0x20];
2199
2200         u8         ether_stats_pkts256to511octets_high[0x20];
2201
2202         u8         ether_stats_pkts256to511octets_low[0x20];
2203
2204         u8         ether_stats_pkts512to1023octets_high[0x20];
2205
2206         u8         ether_stats_pkts512to1023octets_low[0x20];
2207
2208         u8         ether_stats_pkts1024to1518octets_high[0x20];
2209
2210         u8         ether_stats_pkts1024to1518octets_low[0x20];
2211
2212         u8         ether_stats_pkts1519to2047octets_high[0x20];
2213
2214         u8         ether_stats_pkts1519to2047octets_low[0x20];
2215
2216         u8         ether_stats_pkts2048to4095octets_high[0x20];
2217
2218         u8         ether_stats_pkts2048to4095octets_low[0x20];
2219
2220         u8         ether_stats_pkts4096to8191octets_high[0x20];
2221
2222         u8         ether_stats_pkts4096to8191octets_low[0x20];
2223
2224         u8         ether_stats_pkts8192to10239octets_high[0x20];
2225
2226         u8         ether_stats_pkts8192to10239octets_low[0x20];
2227
2228         u8         reserved_at_540[0x280];
2229 };
2230
2231 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2232         u8         if_in_octets_high[0x20];
2233
2234         u8         if_in_octets_low[0x20];
2235
2236         u8         if_in_ucast_pkts_high[0x20];
2237
2238         u8         if_in_ucast_pkts_low[0x20];
2239
2240         u8         if_in_discards_high[0x20];
2241
2242         u8         if_in_discards_low[0x20];
2243
2244         u8         if_in_errors_high[0x20];
2245
2246         u8         if_in_errors_low[0x20];
2247
2248         u8         if_in_unknown_protos_high[0x20];
2249
2250         u8         if_in_unknown_protos_low[0x20];
2251
2252         u8         if_out_octets_high[0x20];
2253
2254         u8         if_out_octets_low[0x20];
2255
2256         u8         if_out_ucast_pkts_high[0x20];
2257
2258         u8         if_out_ucast_pkts_low[0x20];
2259
2260         u8         if_out_discards_high[0x20];
2261
2262         u8         if_out_discards_low[0x20];
2263
2264         u8         if_out_errors_high[0x20];
2265
2266         u8         if_out_errors_low[0x20];
2267
2268         u8         if_in_multicast_pkts_high[0x20];
2269
2270         u8         if_in_multicast_pkts_low[0x20];
2271
2272         u8         if_in_broadcast_pkts_high[0x20];
2273
2274         u8         if_in_broadcast_pkts_low[0x20];
2275
2276         u8         if_out_multicast_pkts_high[0x20];
2277
2278         u8         if_out_multicast_pkts_low[0x20];
2279
2280         u8         if_out_broadcast_pkts_high[0x20];
2281
2282         u8         if_out_broadcast_pkts_low[0x20];
2283
2284         u8         reserved_at_340[0x480];
2285 };
2286
2287 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2288         u8         a_frames_transmitted_ok_high[0x20];
2289
2290         u8         a_frames_transmitted_ok_low[0x20];
2291
2292         u8         a_frames_received_ok_high[0x20];
2293
2294         u8         a_frames_received_ok_low[0x20];
2295
2296         u8         a_frame_check_sequence_errors_high[0x20];
2297
2298         u8         a_frame_check_sequence_errors_low[0x20];
2299
2300         u8         a_alignment_errors_high[0x20];
2301
2302         u8         a_alignment_errors_low[0x20];
2303
2304         u8         a_octets_transmitted_ok_high[0x20];
2305
2306         u8         a_octets_transmitted_ok_low[0x20];
2307
2308         u8         a_octets_received_ok_high[0x20];
2309
2310         u8         a_octets_received_ok_low[0x20];
2311
2312         u8         a_multicast_frames_xmitted_ok_high[0x20];
2313
2314         u8         a_multicast_frames_xmitted_ok_low[0x20];
2315
2316         u8         a_broadcast_frames_xmitted_ok_high[0x20];
2317
2318         u8         a_broadcast_frames_xmitted_ok_low[0x20];
2319
2320         u8         a_multicast_frames_received_ok_high[0x20];
2321
2322         u8         a_multicast_frames_received_ok_low[0x20];
2323
2324         u8         a_broadcast_frames_received_ok_high[0x20];
2325
2326         u8         a_broadcast_frames_received_ok_low[0x20];
2327
2328         u8         a_in_range_length_errors_high[0x20];
2329
2330         u8         a_in_range_length_errors_low[0x20];
2331
2332         u8         a_out_of_range_length_field_high[0x20];
2333
2334         u8         a_out_of_range_length_field_low[0x20];
2335
2336         u8         a_frame_too_long_errors_high[0x20];
2337
2338         u8         a_frame_too_long_errors_low[0x20];
2339
2340         u8         a_symbol_error_during_carrier_high[0x20];
2341
2342         u8         a_symbol_error_during_carrier_low[0x20];
2343
2344         u8         a_mac_control_frames_transmitted_high[0x20];
2345
2346         u8         a_mac_control_frames_transmitted_low[0x20];
2347
2348         u8         a_mac_control_frames_received_high[0x20];
2349
2350         u8         a_mac_control_frames_received_low[0x20];
2351
2352         u8         a_unsupported_opcodes_received_high[0x20];
2353
2354         u8         a_unsupported_opcodes_received_low[0x20];
2355
2356         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2357
2358         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2359
2360         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2361
2362         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2363
2364         u8         reserved_at_4c0[0x300];
2365 };
2366
2367 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2368         u8         life_time_counter_high[0x20];
2369
2370         u8         life_time_counter_low[0x20];
2371
2372         u8         rx_errors[0x20];
2373
2374         u8         tx_errors[0x20];
2375
2376         u8         l0_to_recovery_eieos[0x20];
2377
2378         u8         l0_to_recovery_ts[0x20];
2379
2380         u8         l0_to_recovery_framing[0x20];
2381
2382         u8         l0_to_recovery_retrain[0x20];
2383
2384         u8         crc_error_dllp[0x20];
2385
2386         u8         crc_error_tlp[0x20];
2387
2388         u8         tx_overflow_buffer_pkt_high[0x20];
2389
2390         u8         tx_overflow_buffer_pkt_low[0x20];
2391
2392         u8         outbound_stalled_reads[0x20];
2393
2394         u8         outbound_stalled_writes[0x20];
2395
2396         u8         outbound_stalled_reads_events[0x20];
2397
2398         u8         outbound_stalled_writes_events[0x20];
2399
2400         u8         reserved_at_200[0x5c0];
2401 };
2402
2403 struct mlx5_ifc_cmd_inter_comp_event_bits {
2404         u8         command_completion_vector[0x20];
2405
2406         u8         reserved_at_20[0xc0];
2407 };
2408
2409 struct mlx5_ifc_stall_vl_event_bits {
2410         u8         reserved_at_0[0x18];
2411         u8         port_num[0x1];
2412         u8         reserved_at_19[0x3];
2413         u8         vl[0x4];
2414
2415         u8         reserved_at_20[0xa0];
2416 };
2417
2418 struct mlx5_ifc_db_bf_congestion_event_bits {
2419         u8         event_subtype[0x8];
2420         u8         reserved_at_8[0x8];
2421         u8         congestion_level[0x8];
2422         u8         reserved_at_18[0x8];
2423
2424         u8         reserved_at_20[0xa0];
2425 };
2426
2427 struct mlx5_ifc_gpio_event_bits {
2428         u8         reserved_at_0[0x60];
2429
2430         u8         gpio_event_hi[0x20];
2431
2432         u8         gpio_event_lo[0x20];
2433
2434         u8         reserved_at_a0[0x40];
2435 };
2436
2437 struct mlx5_ifc_port_state_change_event_bits {
2438         u8         reserved_at_0[0x40];
2439
2440         u8         port_num[0x4];
2441         u8         reserved_at_44[0x1c];
2442
2443         u8         reserved_at_60[0x80];
2444 };
2445
2446 struct mlx5_ifc_dropped_packet_logged_bits {
2447         u8         reserved_at_0[0xe0];
2448 };
2449
2450 enum {
2451         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2452         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2453 };
2454
2455 struct mlx5_ifc_cq_error_bits {
2456         u8         reserved_at_0[0x8];
2457         u8         cqn[0x18];
2458
2459         u8         reserved_at_20[0x20];
2460
2461         u8         reserved_at_40[0x18];
2462         u8         syndrome[0x8];
2463
2464         u8         reserved_at_60[0x80];
2465 };
2466
2467 struct mlx5_ifc_rdma_page_fault_event_bits {
2468         u8         bytes_committed[0x20];
2469
2470         u8         r_key[0x20];
2471
2472         u8         reserved_at_40[0x10];
2473         u8         packet_len[0x10];
2474
2475         u8         rdma_op_len[0x20];
2476
2477         u8         rdma_va[0x40];
2478
2479         u8         reserved_at_c0[0x5];
2480         u8         rdma[0x1];
2481         u8         write[0x1];
2482         u8         requestor[0x1];
2483         u8         qp_number[0x18];
2484 };
2485
2486 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2487         u8         bytes_committed[0x20];
2488
2489         u8         reserved_at_20[0x10];
2490         u8         wqe_index[0x10];
2491
2492         u8         reserved_at_40[0x10];
2493         u8         len[0x10];
2494
2495         u8         reserved_at_60[0x60];
2496
2497         u8         reserved_at_c0[0x5];
2498         u8         rdma[0x1];
2499         u8         write_read[0x1];
2500         u8         requestor[0x1];
2501         u8         qpn[0x18];
2502 };
2503
2504 struct mlx5_ifc_qp_events_bits {
2505         u8         reserved_at_0[0xa0];
2506
2507         u8         type[0x8];
2508         u8         reserved_at_a8[0x18];
2509
2510         u8         reserved_at_c0[0x8];
2511         u8         qpn_rqn_sqn[0x18];
2512 };
2513
2514 struct mlx5_ifc_dct_events_bits {
2515         u8         reserved_at_0[0xc0];
2516
2517         u8         reserved_at_c0[0x8];
2518         u8         dct_number[0x18];
2519 };
2520
2521 struct mlx5_ifc_comp_event_bits {
2522         u8         reserved_at_0[0xc0];
2523
2524         u8         reserved_at_c0[0x8];
2525         u8         cq_number[0x18];
2526 };
2527
2528 enum {
2529         MLX5_QPC_STATE_RST        = 0x0,
2530         MLX5_QPC_STATE_INIT       = 0x1,
2531         MLX5_QPC_STATE_RTR        = 0x2,
2532         MLX5_QPC_STATE_RTS        = 0x3,
2533         MLX5_QPC_STATE_SQER       = 0x4,
2534         MLX5_QPC_STATE_ERR        = 0x6,
2535         MLX5_QPC_STATE_SQD        = 0x7,
2536         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2537 };
2538
2539 enum {
2540         MLX5_QPC_ST_RC            = 0x0,
2541         MLX5_QPC_ST_UC            = 0x1,
2542         MLX5_QPC_ST_UD            = 0x2,
2543         MLX5_QPC_ST_XRC           = 0x3,
2544         MLX5_QPC_ST_DCI           = 0x5,
2545         MLX5_QPC_ST_QP0           = 0x7,
2546         MLX5_QPC_ST_QP1           = 0x8,
2547         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2548         MLX5_QPC_ST_REG_UMR       = 0xc,
2549 };
2550
2551 enum {
2552         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2553         MLX5_QPC_PM_STATE_REARM     = 0x1,
2554         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2555         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2556 };
2557
2558 enum {
2559         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2560 };
2561
2562 enum {
2563         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2564         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2565 };
2566
2567 enum {
2568         MLX5_QPC_MTU_256_BYTES        = 0x1,
2569         MLX5_QPC_MTU_512_BYTES        = 0x2,
2570         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2571         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2572         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2573         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2574 };
2575
2576 enum {
2577         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2578         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2579         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2580         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2581         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2582         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2583         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2584         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2585 };
2586
2587 enum {
2588         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2589         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2590         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2591 };
2592
2593 enum {
2594         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2595         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2596         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2597 };
2598
2599 struct mlx5_ifc_qpc_bits {
2600         u8         state[0x4];
2601         u8         lag_tx_port_affinity[0x4];
2602         u8         st[0x8];
2603         u8         reserved_at_10[0x3];
2604         u8         pm_state[0x2];
2605         u8         reserved_at_15[0x1];
2606         u8         req_e2e_credit_mode[0x2];
2607         u8         offload_type[0x4];
2608         u8         end_padding_mode[0x2];
2609         u8         reserved_at_1e[0x2];
2610
2611         u8         wq_signature[0x1];
2612         u8         block_lb_mc[0x1];
2613         u8         atomic_like_write_en[0x1];
2614         u8         latency_sensitive[0x1];
2615         u8         reserved_at_24[0x1];
2616         u8         drain_sigerr[0x1];
2617         u8         reserved_at_26[0x2];
2618         u8         pd[0x18];
2619
2620         u8         mtu[0x3];
2621         u8         log_msg_max[0x5];
2622         u8         reserved_at_48[0x1];
2623         u8         log_rq_size[0x4];
2624         u8         log_rq_stride[0x3];
2625         u8         no_sq[0x1];
2626         u8         log_sq_size[0x4];
2627         u8         reserved_at_55[0x6];
2628         u8         rlky[0x1];
2629         u8         ulp_stateless_offload_mode[0x4];
2630
2631         u8         counter_set_id[0x8];
2632         u8         uar_page[0x18];
2633
2634         u8         reserved_at_80[0x8];
2635         u8         user_index[0x18];
2636
2637         u8         reserved_at_a0[0x3];
2638         u8         log_page_size[0x5];
2639         u8         remote_qpn[0x18];
2640
2641         struct mlx5_ifc_ads_bits primary_address_path;
2642
2643         struct mlx5_ifc_ads_bits secondary_address_path;
2644
2645         u8         log_ack_req_freq[0x4];
2646         u8         reserved_at_384[0x4];
2647         u8         log_sra_max[0x3];
2648         u8         reserved_at_38b[0x2];
2649         u8         retry_count[0x3];
2650         u8         rnr_retry[0x3];
2651         u8         reserved_at_393[0x1];
2652         u8         fre[0x1];
2653         u8         cur_rnr_retry[0x3];
2654         u8         cur_retry_count[0x3];
2655         u8         reserved_at_39b[0x5];
2656
2657         u8         reserved_at_3a0[0x20];
2658
2659         u8         reserved_at_3c0[0x8];
2660         u8         next_send_psn[0x18];
2661
2662         u8         reserved_at_3e0[0x8];
2663         u8         cqn_snd[0x18];
2664
2665         u8         reserved_at_400[0x8];
2666         u8         deth_sqpn[0x18];
2667
2668         u8         reserved_at_420[0x20];
2669
2670         u8         reserved_at_440[0x8];
2671         u8         last_acked_psn[0x18];
2672
2673         u8         reserved_at_460[0x8];
2674         u8         ssn[0x18];
2675
2676         u8         reserved_at_480[0x8];
2677         u8         log_rra_max[0x3];
2678         u8         reserved_at_48b[0x1];
2679         u8         atomic_mode[0x4];
2680         u8         rre[0x1];
2681         u8         rwe[0x1];
2682         u8         rae[0x1];
2683         u8         reserved_at_493[0x1];
2684         u8         page_offset[0x6];
2685         u8         reserved_at_49a[0x3];
2686         u8         cd_slave_receive[0x1];
2687         u8         cd_slave_send[0x1];
2688         u8         cd_master[0x1];
2689
2690         u8         reserved_at_4a0[0x3];
2691         u8         min_rnr_nak[0x5];
2692         u8         next_rcv_psn[0x18];
2693
2694         u8         reserved_at_4c0[0x8];
2695         u8         xrcd[0x18];
2696
2697         u8         reserved_at_4e0[0x8];
2698         u8         cqn_rcv[0x18];
2699
2700         u8         dbr_addr[0x40];
2701
2702         u8         q_key[0x20];
2703
2704         u8         reserved_at_560[0x5];
2705         u8         rq_type[0x3];
2706         u8         srqn_rmpn_xrqn[0x18];
2707
2708         u8         reserved_at_580[0x8];
2709         u8         rmsn[0x18];
2710
2711         u8         hw_sq_wqebb_counter[0x10];
2712         u8         sw_sq_wqebb_counter[0x10];
2713
2714         u8         hw_rq_counter[0x20];
2715
2716         u8         sw_rq_counter[0x20];
2717
2718         u8         reserved_at_600[0x20];
2719
2720         u8         reserved_at_620[0xf];
2721         u8         cgs[0x1];
2722         u8         cs_req[0x8];
2723         u8         cs_res[0x8];
2724
2725         u8         dc_access_key[0x40];
2726
2727         u8         reserved_at_680[0x3];
2728         u8         dbr_umem_valid[0x1];
2729
2730         u8         reserved_at_684[0xbc];
2731 };
2732
2733 struct mlx5_ifc_roce_addr_layout_bits {
2734         u8         source_l3_address[16][0x8];
2735
2736         u8         reserved_at_80[0x3];
2737         u8         vlan_valid[0x1];
2738         u8         vlan_id[0xc];
2739         u8         source_mac_47_32[0x10];
2740
2741         u8         source_mac_31_0[0x20];
2742
2743         u8         reserved_at_c0[0x14];
2744         u8         roce_l3_type[0x4];
2745         u8         roce_version[0x8];
2746
2747         u8         reserved_at_e0[0x20];
2748 };
2749
2750 union mlx5_ifc_hca_cap_union_bits {
2751         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2752         struct mlx5_ifc_odp_cap_bits odp_cap;
2753         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2754         struct mlx5_ifc_roce_cap_bits roce_cap;
2755         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2756         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2757         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2758         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2759         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2760         struct mlx5_ifc_qos_cap_bits qos_cap;
2761         struct mlx5_ifc_debug_cap_bits debug_cap;
2762         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2763         struct mlx5_ifc_tls_cap_bits tls_cap;
2764         struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
2765         u8         reserved_at_0[0x8000];
2766 };
2767
2768 enum {
2769         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2770         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2771         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2772         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2773         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2774         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2775         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2776         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2777         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2778         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
2779         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2780 };
2781
2782 enum {
2783         MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
2784         MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
2785         MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
2786 };
2787
2788 struct mlx5_ifc_vlan_bits {
2789         u8         ethtype[0x10];
2790         u8         prio[0x3];
2791         u8         cfi[0x1];
2792         u8         vid[0xc];
2793 };
2794
2795 struct mlx5_ifc_flow_context_bits {
2796         struct mlx5_ifc_vlan_bits push_vlan;
2797
2798         u8         group_id[0x20];
2799
2800         u8         reserved_at_40[0x8];
2801         u8         flow_tag[0x18];
2802
2803         u8         reserved_at_60[0x10];
2804         u8         action[0x10];
2805
2806         u8         extended_destination[0x1];
2807         u8         reserved_at_81[0x1];
2808         u8         flow_source[0x2];
2809         u8         reserved_at_84[0x4];
2810         u8         destination_list_size[0x18];
2811
2812         u8         reserved_at_a0[0x8];
2813         u8         flow_counter_list_size[0x18];
2814
2815         u8         packet_reformat_id[0x20];
2816
2817         u8         modify_header_id[0x20];
2818
2819         struct mlx5_ifc_vlan_bits push_vlan_2;
2820
2821         u8         reserved_at_120[0xe0];
2822
2823         struct mlx5_ifc_fte_match_param_bits match_value;
2824
2825         u8         reserved_at_1200[0x600];
2826
2827         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2828 };
2829
2830 enum {
2831         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2832         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2833 };
2834
2835 struct mlx5_ifc_xrc_srqc_bits {
2836         u8         state[0x4];
2837         u8         log_xrc_srq_size[0x4];
2838         u8         reserved_at_8[0x18];
2839
2840         u8         wq_signature[0x1];
2841         u8         cont_srq[0x1];
2842         u8         reserved_at_22[0x1];
2843         u8         rlky[0x1];
2844         u8         basic_cyclic_rcv_wqe[0x1];
2845         u8         log_rq_stride[0x3];
2846         u8         xrcd[0x18];
2847
2848         u8         page_offset[0x6];
2849         u8         reserved_at_46[0x1];
2850         u8         dbr_umem_valid[0x1];
2851         u8         cqn[0x18];
2852
2853         u8         reserved_at_60[0x20];
2854
2855         u8         user_index_equal_xrc_srqn[0x1];
2856         u8         reserved_at_81[0x1];
2857         u8         log_page_size[0x6];
2858         u8         user_index[0x18];
2859
2860         u8         reserved_at_a0[0x20];
2861
2862         u8         reserved_at_c0[0x8];
2863         u8         pd[0x18];
2864
2865         u8         lwm[0x10];
2866         u8         wqe_cnt[0x10];
2867
2868         u8         reserved_at_100[0x40];
2869
2870         u8         db_record_addr_h[0x20];
2871
2872         u8         db_record_addr_l[0x1e];
2873         u8         reserved_at_17e[0x2];
2874
2875         u8         reserved_at_180[0x80];
2876 };
2877
2878 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2879         u8         counter_error_queues[0x20];
2880
2881         u8         total_error_queues[0x20];
2882
2883         u8         send_queue_priority_update_flow[0x20];
2884
2885         u8         reserved_at_60[0x20];
2886
2887         u8         nic_receive_steering_discard[0x40];
2888
2889         u8         receive_discard_vport_down[0x40];
2890
2891         u8         transmit_discard_vport_down[0x40];
2892
2893         u8         reserved_at_140[0xa0];
2894
2895         u8         internal_rq_out_of_buffer[0x20];
2896
2897         u8         reserved_at_200[0xe00];
2898 };
2899
2900 struct mlx5_ifc_traffic_counter_bits {
2901         u8         packets[0x40];
2902
2903         u8         octets[0x40];
2904 };
2905
2906 struct mlx5_ifc_tisc_bits {
2907         u8         strict_lag_tx_port_affinity[0x1];
2908         u8         tls_en[0x1];
2909         u8         reserved_at_2[0x2];
2910         u8         lag_tx_port_affinity[0x04];
2911
2912         u8         reserved_at_8[0x4];
2913         u8         prio[0x4];
2914         u8         reserved_at_10[0x10];
2915
2916         u8         reserved_at_20[0x100];
2917
2918         u8         reserved_at_120[0x8];
2919         u8         transport_domain[0x18];
2920
2921         u8         reserved_at_140[0x8];
2922         u8         underlay_qpn[0x18];
2923
2924         u8         reserved_at_160[0x8];
2925         u8         pd[0x18];
2926
2927         u8         reserved_at_180[0x380];
2928 };
2929
2930 enum {
2931         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2932         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2933 };
2934
2935 enum {
2936         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2937         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2938 };
2939
2940 enum {
2941         MLX5_RX_HASH_FN_NONE           = 0x0,
2942         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2943         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2944 };
2945
2946 enum {
2947         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
2948         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
2949 };
2950
2951 struct mlx5_ifc_tirc_bits {
2952         u8         reserved_at_0[0x20];
2953
2954         u8         disp_type[0x4];
2955         u8         reserved_at_24[0x1c];
2956
2957         u8         reserved_at_40[0x40];
2958
2959         u8         reserved_at_80[0x4];
2960         u8         lro_timeout_period_usecs[0x10];
2961         u8         lro_enable_mask[0x4];
2962         u8         lro_max_ip_payload_size[0x8];
2963
2964         u8         reserved_at_a0[0x40];
2965
2966         u8         reserved_at_e0[0x8];
2967         u8         inline_rqn[0x18];
2968
2969         u8         rx_hash_symmetric[0x1];
2970         u8         reserved_at_101[0x1];
2971         u8         tunneled_offload_en[0x1];
2972         u8         reserved_at_103[0x5];
2973         u8         indirect_table[0x18];
2974
2975         u8         rx_hash_fn[0x4];
2976         u8         reserved_at_124[0x2];
2977         u8         self_lb_block[0x2];
2978         u8         transport_domain[0x18];
2979
2980         u8         rx_hash_toeplitz_key[10][0x20];
2981
2982         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2983
2984         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2985
2986         u8         reserved_at_2c0[0x4c0];
2987 };
2988
2989 enum {
2990         MLX5_SRQC_STATE_GOOD   = 0x0,
2991         MLX5_SRQC_STATE_ERROR  = 0x1,
2992 };
2993
2994 struct mlx5_ifc_srqc_bits {
2995         u8         state[0x4];
2996         u8         log_srq_size[0x4];
2997         u8         reserved_at_8[0x18];
2998
2999         u8         wq_signature[0x1];
3000         u8         cont_srq[0x1];
3001         u8         reserved_at_22[0x1];
3002         u8         rlky[0x1];
3003         u8         reserved_at_24[0x1];
3004         u8         log_rq_stride[0x3];
3005         u8         xrcd[0x18];
3006
3007         u8         page_offset[0x6];
3008         u8         reserved_at_46[0x2];
3009         u8         cqn[0x18];
3010
3011         u8         reserved_at_60[0x20];
3012
3013         u8         reserved_at_80[0x2];
3014         u8         log_page_size[0x6];
3015         u8         reserved_at_88[0x18];
3016
3017         u8         reserved_at_a0[0x20];
3018
3019         u8         reserved_at_c0[0x8];
3020         u8         pd[0x18];
3021
3022         u8         lwm[0x10];
3023         u8         wqe_cnt[0x10];
3024
3025         u8         reserved_at_100[0x40];
3026
3027         u8         dbr_addr[0x40];
3028
3029         u8         reserved_at_180[0x80];
3030 };
3031
3032 enum {
3033         MLX5_SQC_STATE_RST  = 0x0,
3034         MLX5_SQC_STATE_RDY  = 0x1,
3035         MLX5_SQC_STATE_ERR  = 0x3,
3036 };
3037
3038 struct mlx5_ifc_sqc_bits {
3039         u8         rlky[0x1];
3040         u8         cd_master[0x1];
3041         u8         fre[0x1];
3042         u8         flush_in_error_en[0x1];
3043         u8         allow_multi_pkt_send_wqe[0x1];
3044         u8         min_wqe_inline_mode[0x3];
3045         u8         state[0x4];
3046         u8         reg_umr[0x1];
3047         u8         allow_swp[0x1];
3048         u8         hairpin[0x1];
3049         u8         reserved_at_f[0x11];
3050
3051         u8         reserved_at_20[0x8];
3052         u8         user_index[0x18];
3053
3054         u8         reserved_at_40[0x8];
3055         u8         cqn[0x18];
3056
3057         u8         reserved_at_60[0x8];
3058         u8         hairpin_peer_rq[0x18];
3059
3060         u8         reserved_at_80[0x10];
3061         u8         hairpin_peer_vhca[0x10];
3062
3063         u8         reserved_at_a0[0x50];
3064
3065         u8         packet_pacing_rate_limit_index[0x10];
3066         u8         tis_lst_sz[0x10];
3067         u8         reserved_at_110[0x10];
3068
3069         u8         reserved_at_120[0x40];
3070
3071         u8         reserved_at_160[0x8];
3072         u8         tis_num_0[0x18];
3073
3074         struct mlx5_ifc_wq_bits wq;
3075 };
3076
3077 enum {
3078         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3079         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3080         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3081         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3082 };
3083
3084 enum {
3085         ELEMENT_TYPE_CAP_MASK_TASR              = 1 << 0,
3086         ELEMENT_TYPE_CAP_MASK_VPORT             = 1 << 1,
3087         ELEMENT_TYPE_CAP_MASK_VPORT_TC          = 1 << 2,
3088         ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC     = 1 << 3,
3089 };
3090
3091 struct mlx5_ifc_scheduling_context_bits {
3092         u8         element_type[0x8];
3093         u8         reserved_at_8[0x18];
3094
3095         u8         element_attributes[0x20];
3096
3097         u8         parent_element_id[0x20];
3098
3099         u8         reserved_at_60[0x40];
3100
3101         u8         bw_share[0x20];
3102
3103         u8         max_average_bw[0x20];
3104
3105         u8         reserved_at_e0[0x120];
3106 };
3107
3108 struct mlx5_ifc_rqtc_bits {
3109         u8         reserved_at_0[0xa0];
3110
3111         u8         reserved_at_a0[0x10];
3112         u8         rqt_max_size[0x10];
3113
3114         u8         reserved_at_c0[0x10];
3115         u8         rqt_actual_size[0x10];
3116
3117         u8         reserved_at_e0[0x6a0];
3118
3119         struct mlx5_ifc_rq_num_bits rq_num[0];
3120 };
3121
3122 enum {
3123         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3124         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3125 };
3126
3127 enum {
3128         MLX5_RQC_STATE_RST  = 0x0,
3129         MLX5_RQC_STATE_RDY  = 0x1,
3130         MLX5_RQC_STATE_ERR  = 0x3,
3131 };
3132
3133 struct mlx5_ifc_rqc_bits {
3134         u8         rlky[0x1];
3135         u8         delay_drop_en[0x1];
3136         u8         scatter_fcs[0x1];
3137         u8         vsd[0x1];
3138         u8         mem_rq_type[0x4];
3139         u8         state[0x4];
3140         u8         reserved_at_c[0x1];
3141         u8         flush_in_error_en[0x1];
3142         u8         hairpin[0x1];
3143         u8         reserved_at_f[0x11];
3144
3145         u8         reserved_at_20[0x8];
3146         u8         user_index[0x18];
3147
3148         u8         reserved_at_40[0x8];
3149         u8         cqn[0x18];
3150
3151         u8         counter_set_id[0x8];
3152         u8         reserved_at_68[0x18];
3153
3154         u8         reserved_at_80[0x8];
3155         u8         rmpn[0x18];
3156
3157         u8         reserved_at_a0[0x8];
3158         u8         hairpin_peer_sq[0x18];
3159
3160         u8         reserved_at_c0[0x10];
3161         u8         hairpin_peer_vhca[0x10];
3162
3163         u8         reserved_at_e0[0xa0];
3164
3165         struct mlx5_ifc_wq_bits wq;
3166 };
3167
3168 enum {
3169         MLX5_RMPC_STATE_RDY  = 0x1,
3170         MLX5_RMPC_STATE_ERR  = 0x3,
3171 };
3172
3173 struct mlx5_ifc_rmpc_bits {
3174         u8         reserved_at_0[0x8];
3175         u8         state[0x4];
3176         u8         reserved_at_c[0x14];
3177
3178         u8         basic_cyclic_rcv_wqe[0x1];
3179         u8         reserved_at_21[0x1f];
3180
3181         u8         reserved_at_40[0x140];
3182
3183         struct mlx5_ifc_wq_bits wq;
3184 };
3185
3186 struct mlx5_ifc_nic_vport_context_bits {
3187         u8         reserved_at_0[0x5];
3188         u8         min_wqe_inline_mode[0x3];
3189         u8         reserved_at_8[0x15];
3190         u8         disable_mc_local_lb[0x1];
3191         u8         disable_uc_local_lb[0x1];
3192         u8         roce_en[0x1];
3193
3194         u8         arm_change_event[0x1];
3195         u8         reserved_at_21[0x1a];
3196         u8         event_on_mtu[0x1];
3197         u8         event_on_promisc_change[0x1];
3198         u8         event_on_vlan_change[0x1];
3199         u8         event_on_mc_address_change[0x1];
3200         u8         event_on_uc_address_change[0x1];
3201
3202         u8         reserved_at_40[0xc];
3203
3204         u8         affiliation_criteria[0x4];
3205         u8         affiliated_vhca_id[0x10];
3206
3207         u8         reserved_at_60[0xd0];
3208
3209         u8         mtu[0x10];
3210
3211         u8         system_image_guid[0x40];
3212         u8         port_guid[0x40];
3213         u8         node_guid[0x40];
3214
3215         u8         reserved_at_200[0x140];
3216         u8         qkey_violation_counter[0x10];
3217         u8         reserved_at_350[0x430];
3218
3219         u8         promisc_uc[0x1];
3220         u8         promisc_mc[0x1];
3221         u8         promisc_all[0x1];
3222         u8         reserved_at_783[0x2];
3223         u8         allowed_list_type[0x3];
3224         u8         reserved_at_788[0xc];
3225         u8         allowed_list_size[0xc];
3226
3227         struct mlx5_ifc_mac_address_layout_bits permanent_address;
3228
3229         u8         reserved_at_7e0[0x20];
3230
3231         u8         current_uc_mac_address[0][0x40];
3232 };
3233
3234 enum {
3235         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
3236         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
3237         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
3238         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
3239         MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3240         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3241 };
3242
3243 struct mlx5_ifc_mkc_bits {
3244         u8         reserved_at_0[0x1];
3245         u8         free[0x1];
3246         u8         reserved_at_2[0x1];
3247         u8         access_mode_4_2[0x3];
3248         u8         reserved_at_6[0x7];
3249         u8         relaxed_ordering_write[0x1];
3250         u8         reserved_at_e[0x1];
3251         u8         small_fence_on_rdma_read_response[0x1];
3252         u8         umr_en[0x1];
3253         u8         a[0x1];
3254         u8         rw[0x1];
3255         u8         rr[0x1];
3256         u8         lw[0x1];
3257         u8         lr[0x1];
3258         u8         access_mode_1_0[0x2];
3259         u8         reserved_at_18[0x8];
3260
3261         u8         qpn[0x18];
3262         u8         mkey_7_0[0x8];
3263
3264         u8         reserved_at_40[0x20];
3265
3266         u8         length64[0x1];
3267         u8         bsf_en[0x1];
3268         u8         sync_umr[0x1];
3269         u8         reserved_at_63[0x2];
3270         u8         expected_sigerr_count[0x1];
3271         u8         reserved_at_66[0x1];
3272         u8         en_rinval[0x1];
3273         u8         pd[0x18];
3274
3275         u8         start_addr[0x40];
3276
3277         u8         len[0x40];
3278
3279         u8         bsf_octword_size[0x20];
3280
3281         u8         reserved_at_120[0x80];
3282
3283         u8         translations_octword_size[0x20];
3284
3285         u8         reserved_at_1c0[0x1b];
3286         u8         log_page_size[0x5];
3287
3288         u8         reserved_at_1e0[0x20];
3289 };
3290
3291 struct mlx5_ifc_pkey_bits {
3292         u8         reserved_at_0[0x10];
3293         u8         pkey[0x10];
3294 };
3295
3296 struct mlx5_ifc_array128_auto_bits {
3297         u8         array128_auto[16][0x8];
3298 };
3299
3300 struct mlx5_ifc_hca_vport_context_bits {
3301         u8         field_select[0x20];
3302
3303         u8         reserved_at_20[0xe0];
3304
3305         u8         sm_virt_aware[0x1];
3306         u8         has_smi[0x1];
3307         u8         has_raw[0x1];
3308         u8         grh_required[0x1];
3309         u8         reserved_at_104[0xc];
3310         u8         port_physical_state[0x4];
3311         u8         vport_state_policy[0x4];
3312         u8         port_state[0x4];
3313         u8         vport_state[0x4];
3314
3315         u8         reserved_at_120[0x20];
3316
3317         u8         system_image_guid[0x40];
3318
3319         u8         port_guid[0x40];
3320
3321         u8         node_guid[0x40];
3322
3323         u8         cap_mask1[0x20];
3324
3325         u8         cap_mask1_field_select[0x20];
3326
3327         u8         cap_mask2[0x20];
3328
3329         u8         cap_mask2_field_select[0x20];
3330
3331         u8         reserved_at_280[0x80];
3332
3333         u8         lid[0x10];
3334         u8         reserved_at_310[0x4];
3335         u8         init_type_reply[0x4];
3336         u8         lmc[0x3];
3337         u8         subnet_timeout[0x5];
3338
3339         u8         sm_lid[0x10];
3340         u8         sm_sl[0x4];
3341         u8         reserved_at_334[0xc];
3342
3343         u8         qkey_violation_counter[0x10];
3344         u8         pkey_violation_counter[0x10];
3345
3346         u8         reserved_at_360[0xca0];
3347 };
3348
3349 struct mlx5_ifc_esw_vport_context_bits {
3350         u8         fdb_to_vport_reg_c[0x1];
3351         u8         reserved_at_1[0x2];
3352         u8         vport_svlan_strip[0x1];
3353         u8         vport_cvlan_strip[0x1];
3354         u8         vport_svlan_insert[0x1];
3355         u8         vport_cvlan_insert[0x2];
3356         u8         fdb_to_vport_reg_c_id[0x8];
3357         u8         reserved_at_10[0x10];
3358
3359         u8         reserved_at_20[0x20];
3360
3361         u8         svlan_cfi[0x1];
3362         u8         svlan_pcp[0x3];
3363         u8         svlan_id[0xc];
3364         u8         cvlan_cfi[0x1];
3365         u8         cvlan_pcp[0x3];
3366         u8         cvlan_id[0xc];
3367
3368         u8         reserved_at_60[0x720];
3369
3370         u8         sw_steering_vport_icm_address_rx[0x40];
3371
3372         u8         sw_steering_vport_icm_address_tx[0x40];
3373 };
3374
3375 enum {
3376         MLX5_EQC_STATUS_OK                = 0x0,
3377         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
3378 };
3379
3380 enum {
3381         MLX5_EQC_ST_ARMED  = 0x9,
3382         MLX5_EQC_ST_FIRED  = 0xa,
3383 };
3384
3385 struct mlx5_ifc_eqc_bits {
3386         u8         status[0x4];
3387         u8         reserved_at_4[0x9];
3388         u8         ec[0x1];
3389         u8         oi[0x1];
3390         u8         reserved_at_f[0x5];
3391         u8         st[0x4];
3392         u8         reserved_at_18[0x8];
3393
3394         u8         reserved_at_20[0x20];
3395
3396         u8         reserved_at_40[0x14];
3397         u8         page_offset[0x6];
3398         u8         reserved_at_5a[0x6];
3399
3400         u8         reserved_at_60[0x3];
3401         u8         log_eq_size[0x5];
3402         u8         uar_page[0x18];
3403
3404         u8         reserved_at_80[0x20];
3405
3406         u8         reserved_at_a0[0x18];
3407         u8         intr[0x8];
3408
3409         u8         reserved_at_c0[0x3];
3410         u8         log_page_size[0x5];
3411         u8         reserved_at_c8[0x18];
3412
3413         u8         reserved_at_e0[0x60];
3414
3415         u8         reserved_at_140[0x8];
3416         u8         consumer_counter[0x18];
3417
3418         u8         reserved_at_160[0x8];
3419         u8         producer_counter[0x18];
3420
3421         u8         reserved_at_180[0x80];
3422 };
3423
3424 enum {
3425         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3426         MLX5_DCTC_STATE_DRAINING  = 0x1,
3427         MLX5_DCTC_STATE_DRAINED   = 0x2,
3428 };
3429
3430 enum {
3431         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3432         MLX5_DCTC_CS_RES_NA         = 0x1,
3433         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3434 };
3435
3436 enum {
3437         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3438         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3439         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3440         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3441         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3442 };
3443
3444 struct mlx5_ifc_dctc_bits {
3445         u8         reserved_at_0[0x4];
3446         u8         state[0x4];
3447         u8         reserved_at_8[0x18];
3448
3449         u8         reserved_at_20[0x8];
3450         u8         user_index[0x18];
3451
3452         u8         reserved_at_40[0x8];
3453         u8         cqn[0x18];
3454
3455         u8         counter_set_id[0x8];
3456         u8         atomic_mode[0x4];
3457         u8         rre[0x1];
3458         u8         rwe[0x1];
3459         u8         rae[0x1];
3460         u8         atomic_like_write_en[0x1];
3461         u8         latency_sensitive[0x1];
3462         u8         rlky[0x1];
3463         u8         free_ar[0x1];
3464         u8         reserved_at_73[0xd];
3465
3466         u8         reserved_at_80[0x8];
3467         u8         cs_res[0x8];
3468         u8         reserved_at_90[0x3];
3469         u8         min_rnr_nak[0x5];
3470         u8         reserved_at_98[0x8];
3471
3472         u8         reserved_at_a0[0x8];
3473         u8         srqn_xrqn[0x18];
3474
3475         u8         reserved_at_c0[0x8];
3476         u8         pd[0x18];
3477
3478         u8         tclass[0x8];
3479         u8         reserved_at_e8[0x4];
3480         u8         flow_label[0x14];
3481
3482         u8         dc_access_key[0x40];
3483
3484         u8         reserved_at_140[0x5];
3485         u8         mtu[0x3];
3486         u8         port[0x8];
3487         u8         pkey_index[0x10];
3488
3489         u8         reserved_at_160[0x8];
3490         u8         my_addr_index[0x8];
3491         u8         reserved_at_170[0x8];
3492         u8         hop_limit[0x8];
3493
3494         u8         dc_access_key_violation_count[0x20];
3495
3496         u8         reserved_at_1a0[0x14];
3497         u8         dei_cfi[0x1];
3498         u8         eth_prio[0x3];
3499         u8         ecn[0x2];
3500         u8         dscp[0x6];
3501
3502         u8         reserved_at_1c0[0x40];
3503 };
3504
3505 enum {
3506         MLX5_CQC_STATUS_OK             = 0x0,
3507         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3508         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3509 };
3510
3511 enum {
3512         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3513         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3514 };
3515
3516 enum {
3517         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3518         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3519         MLX5_CQC_ST_FIRED                                 = 0xa,
3520 };
3521
3522 enum {
3523         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3524         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3525         MLX5_CQ_PERIOD_NUM_MODES
3526 };
3527
3528 struct mlx5_ifc_cqc_bits {
3529         u8         status[0x4];
3530         u8         reserved_at_4[0x2];
3531         u8         dbr_umem_valid[0x1];
3532         u8         reserved_at_7[0x1];
3533         u8         cqe_sz[0x3];
3534         u8         cc[0x1];
3535         u8         reserved_at_c[0x1];
3536         u8         scqe_break_moderation_en[0x1];
3537         u8         oi[0x1];
3538         u8         cq_period_mode[0x2];
3539         u8         cqe_comp_en[0x1];
3540         u8         mini_cqe_res_format[0x2];
3541         u8         st[0x4];
3542         u8         reserved_at_18[0x8];
3543
3544         u8         reserved_at_20[0x20];
3545
3546         u8         reserved_at_40[0x14];
3547         u8         page_offset[0x6];
3548         u8         reserved_at_5a[0x6];
3549
3550         u8         reserved_at_60[0x3];
3551         u8         log_cq_size[0x5];
3552         u8         uar_page[0x18];
3553
3554         u8         reserved_at_80[0x4];
3555         u8         cq_period[0xc];
3556         u8         cq_max_count[0x10];
3557
3558         u8         reserved_at_a0[0x18];
3559         u8         c_eqn[0x8];
3560
3561         u8         reserved_at_c0[0x3];
3562         u8         log_page_size[0x5];
3563         u8         reserved_at_c8[0x18];
3564
3565         u8         reserved_at_e0[0x20];
3566
3567         u8         reserved_at_100[0x8];
3568         u8         last_notified_index[0x18];
3569
3570         u8         reserved_at_120[0x8];
3571         u8         last_solicit_index[0x18];
3572
3573         u8         reserved_at_140[0x8];
3574         u8         consumer_counter[0x18];
3575
3576         u8         reserved_at_160[0x8];
3577         u8         producer_counter[0x18];
3578
3579         u8         reserved_at_180[0x40];
3580
3581         u8         dbr_addr[0x40];
3582 };
3583
3584 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3585         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3586         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3587         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3588         u8         reserved_at_0[0x800];
3589 };
3590
3591 struct mlx5_ifc_query_adapter_param_block_bits {
3592         u8         reserved_at_0[0xc0];
3593
3594         u8         reserved_at_c0[0x8];
3595         u8         ieee_vendor_id[0x18];
3596
3597         u8         reserved_at_e0[0x10];
3598         u8         vsd_vendor_id[0x10];
3599
3600         u8         vsd[208][0x8];
3601
3602         u8         vsd_contd_psid[16][0x8];
3603 };
3604
3605 enum {
3606         MLX5_XRQC_STATE_GOOD   = 0x0,
3607         MLX5_XRQC_STATE_ERROR  = 0x1,
3608 };
3609
3610 enum {
3611         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3612         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3613 };
3614
3615 enum {
3616         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3617 };
3618
3619 struct mlx5_ifc_tag_matching_topology_context_bits {
3620         u8         log_matching_list_sz[0x4];
3621         u8         reserved_at_4[0xc];
3622         u8         append_next_index[0x10];
3623
3624         u8         sw_phase_cnt[0x10];
3625         u8         hw_phase_cnt[0x10];
3626
3627         u8         reserved_at_40[0x40];
3628 };
3629
3630 struct mlx5_ifc_xrqc_bits {
3631         u8         state[0x4];
3632         u8         rlkey[0x1];
3633         u8         reserved_at_5[0xf];
3634         u8         topology[0x4];
3635         u8         reserved_at_18[0x4];
3636         u8         offload[0x4];
3637
3638         u8         reserved_at_20[0x8];
3639         u8         user_index[0x18];
3640
3641         u8         reserved_at_40[0x8];
3642         u8         cqn[0x18];
3643
3644         u8         reserved_at_60[0xa0];
3645
3646         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3647
3648         u8         reserved_at_180[0x280];
3649
3650         struct mlx5_ifc_wq_bits wq;
3651 };
3652
3653 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3654         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3655         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3656         u8         reserved_at_0[0x20];
3657 };
3658
3659 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3660         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3661         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3662         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3663         u8         reserved_at_0[0x20];
3664 };
3665
3666 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3667         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3668         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3669         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3670         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3671         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3672         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3673         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
3674         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
3675         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3676         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3677         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3678         u8         reserved_at_0[0x7c0];
3679 };
3680
3681 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3682         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3683         u8         reserved_at_0[0x7c0];
3684 };
3685
3686 union mlx5_ifc_event_auto_bits {
3687         struct mlx5_ifc_comp_event_bits comp_event;
3688         struct mlx5_ifc_dct_events_bits dct_events;
3689         struct mlx5_ifc_qp_events_bits qp_events;
3690         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3691         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3692         struct mlx5_ifc_cq_error_bits cq_error;
3693         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3694         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3695         struct mlx5_ifc_gpio_event_bits gpio_event;
3696         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3697         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3698         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3699         u8         reserved_at_0[0xe0];
3700 };
3701
3702 struct mlx5_ifc_health_buffer_bits {
3703         u8         reserved_at_0[0x100];
3704
3705         u8         assert_existptr[0x20];
3706
3707         u8         assert_callra[0x20];
3708
3709         u8         reserved_at_140[0x40];
3710
3711         u8         fw_version[0x20];
3712
3713         u8         hw_id[0x20];
3714
3715         u8         reserved_at_1c0[0x20];
3716
3717         u8         irisc_index[0x8];
3718         u8         synd[0x8];
3719         u8         ext_synd[0x10];
3720 };
3721
3722 struct mlx5_ifc_register_loopback_control_bits {
3723         u8         no_lb[0x1];
3724         u8         reserved_at_1[0x7];
3725         u8         port[0x8];
3726         u8         reserved_at_10[0x10];
3727
3728         u8         reserved_at_20[0x60];
3729 };
3730
3731 struct mlx5_ifc_vport_tc_element_bits {
3732         u8         traffic_class[0x4];
3733         u8         reserved_at_4[0xc];
3734         u8         vport_number[0x10];
3735 };
3736
3737 struct mlx5_ifc_vport_element_bits {
3738         u8         reserved_at_0[0x10];
3739         u8         vport_number[0x10];
3740 };
3741
3742 enum {
3743         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3744         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3745         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3746 };
3747
3748 struct mlx5_ifc_tsar_element_bits {
3749         u8         reserved_at_0[0x8];
3750         u8         tsar_type[0x8];
3751         u8         reserved_at_10[0x10];
3752 };
3753
3754 enum {
3755         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3756         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3757 };
3758
3759 struct mlx5_ifc_teardown_hca_out_bits {
3760         u8         status[0x8];
3761         u8         reserved_at_8[0x18];
3762
3763         u8         syndrome[0x20];
3764
3765         u8         reserved_at_40[0x3f];
3766
3767         u8         state[0x1];
3768 };
3769
3770 enum {
3771         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3772         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3773         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3774 };
3775
3776 struct mlx5_ifc_teardown_hca_in_bits {
3777         u8         opcode[0x10];
3778         u8         reserved_at_10[0x10];
3779
3780         u8         reserved_at_20[0x10];
3781         u8         op_mod[0x10];
3782
3783         u8         reserved_at_40[0x10];
3784         u8         profile[0x10];
3785
3786         u8         reserved_at_60[0x20];
3787 };
3788
3789 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3790         u8         status[0x8];
3791         u8         reserved_at_8[0x18];
3792
3793         u8         syndrome[0x20];
3794
3795         u8         reserved_at_40[0x40];
3796 };
3797
3798 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3799         u8         opcode[0x10];
3800         u8         uid[0x10];
3801
3802         u8         reserved_at_20[0x10];
3803         u8         op_mod[0x10];
3804
3805         u8         reserved_at_40[0x8];
3806         u8         qpn[0x18];
3807
3808         u8         reserved_at_60[0x20];
3809
3810         u8         opt_param_mask[0x20];
3811
3812         u8         reserved_at_a0[0x20];
3813
3814         struct mlx5_ifc_qpc_bits qpc;
3815
3816         u8         reserved_at_800[0x80];
3817 };
3818
3819 struct mlx5_ifc_sqd2rts_qp_out_bits {
3820         u8         status[0x8];
3821         u8         reserved_at_8[0x18];
3822
3823         u8         syndrome[0x20];
3824
3825         u8         reserved_at_40[0x40];
3826 };
3827
3828 struct mlx5_ifc_sqd2rts_qp_in_bits {
3829         u8         opcode[0x10];
3830         u8         uid[0x10];
3831
3832         u8         reserved_at_20[0x10];
3833         u8         op_mod[0x10];
3834
3835         u8         reserved_at_40[0x8];
3836         u8         qpn[0x18];
3837
3838         u8         reserved_at_60[0x20];
3839
3840         u8         opt_param_mask[0x20];
3841
3842         u8         reserved_at_a0[0x20];
3843
3844         struct mlx5_ifc_qpc_bits qpc;
3845
3846         u8         reserved_at_800[0x80];
3847 };
3848
3849 struct mlx5_ifc_set_roce_address_out_bits {
3850         u8         status[0x8];
3851         u8         reserved_at_8[0x18];
3852
3853         u8         syndrome[0x20];
3854
3855         u8         reserved_at_40[0x40];
3856 };
3857
3858 struct mlx5_ifc_set_roce_address_in_bits {
3859         u8         opcode[0x10];
3860         u8         reserved_at_10[0x10];
3861
3862         u8         reserved_at_20[0x10];
3863         u8         op_mod[0x10];
3864
3865         u8         roce_address_index[0x10];
3866         u8         reserved_at_50[0xc];
3867         u8         vhca_port_num[0x4];
3868
3869         u8         reserved_at_60[0x20];
3870
3871         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3872 };
3873
3874 struct mlx5_ifc_set_mad_demux_out_bits {
3875         u8         status[0x8];
3876         u8         reserved_at_8[0x18];
3877
3878         u8         syndrome[0x20];
3879
3880         u8         reserved_at_40[0x40];
3881 };
3882
3883 enum {
3884         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3885         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3886 };
3887
3888 struct mlx5_ifc_set_mad_demux_in_bits {
3889         u8         opcode[0x10];
3890         u8         reserved_at_10[0x10];
3891
3892         u8         reserved_at_20[0x10];
3893         u8         op_mod[0x10];
3894
3895         u8         reserved_at_40[0x20];
3896
3897         u8         reserved_at_60[0x6];
3898         u8         demux_mode[0x2];
3899         u8         reserved_at_68[0x18];
3900 };
3901
3902 struct mlx5_ifc_set_l2_table_entry_out_bits {
3903         u8         status[0x8];
3904         u8         reserved_at_8[0x18];
3905
3906         u8         syndrome[0x20];
3907
3908         u8         reserved_at_40[0x40];
3909 };
3910
3911 struct mlx5_ifc_set_l2_table_entry_in_bits {
3912         u8         opcode[0x10];
3913         u8         reserved_at_10[0x10];
3914
3915         u8         reserved_at_20[0x10];
3916         u8         op_mod[0x10];
3917
3918         u8         reserved_at_40[0x60];
3919
3920         u8         reserved_at_a0[0x8];
3921         u8         table_index[0x18];
3922
3923         u8         reserved_at_c0[0x20];
3924
3925         u8         reserved_at_e0[0x13];
3926         u8         vlan_valid[0x1];
3927         u8         vlan[0xc];
3928
3929         struct mlx5_ifc_mac_address_layout_bits mac_address;
3930
3931         u8         reserved_at_140[0xc0];
3932 };
3933
3934 struct mlx5_ifc_set_issi_out_bits {
3935         u8         status[0x8];
3936         u8         reserved_at_8[0x18];
3937
3938         u8         syndrome[0x20];
3939
3940         u8         reserved_at_40[0x40];
3941 };
3942
3943 struct mlx5_ifc_set_issi_in_bits {
3944         u8         opcode[0x10];
3945         u8         reserved_at_10[0x10];
3946
3947         u8         reserved_at_20[0x10];
3948         u8         op_mod[0x10];
3949
3950         u8         reserved_at_40[0x10];
3951         u8         current_issi[0x10];
3952
3953         u8         reserved_at_60[0x20];
3954 };
3955
3956 struct mlx5_ifc_set_hca_cap_out_bits {
3957         u8         status[0x8];
3958         u8         reserved_at_8[0x18];
3959
3960         u8         syndrome[0x20];
3961
3962         u8         reserved_at_40[0x40];
3963 };
3964
3965 struct mlx5_ifc_set_hca_cap_in_bits {
3966         u8         opcode[0x10];
3967         u8         reserved_at_10[0x10];
3968
3969         u8         reserved_at_20[0x10];
3970         u8         op_mod[0x10];
3971
3972         u8         reserved_at_40[0x40];
3973
3974         union mlx5_ifc_hca_cap_union_bits capability;
3975 };
3976
3977 enum {
3978         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3979         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3980         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3981         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3982 };
3983
3984 struct mlx5_ifc_set_fte_out_bits {
3985         u8         status[0x8];
3986         u8         reserved_at_8[0x18];
3987
3988         u8         syndrome[0x20];
3989
3990         u8         reserved_at_40[0x40];
3991 };
3992
3993 struct mlx5_ifc_set_fte_in_bits {
3994         u8         opcode[0x10];
3995         u8         reserved_at_10[0x10];
3996
3997         u8         reserved_at_20[0x10];
3998         u8         op_mod[0x10];
3999
4000         u8         other_vport[0x1];
4001         u8         reserved_at_41[0xf];
4002         u8         vport_number[0x10];
4003
4004         u8         reserved_at_60[0x20];
4005
4006         u8         table_type[0x8];
4007         u8         reserved_at_88[0x18];
4008
4009         u8         reserved_at_a0[0x8];
4010         u8         table_id[0x18];
4011
4012         u8         reserved_at_c0[0x18];
4013         u8         modify_enable_mask[0x8];
4014
4015         u8         reserved_at_e0[0x20];
4016
4017         u8         flow_index[0x20];
4018
4019         u8         reserved_at_120[0xe0];
4020
4021         struct mlx5_ifc_flow_context_bits flow_context;
4022 };
4023
4024 struct mlx5_ifc_rts2rts_qp_out_bits {
4025         u8         status[0x8];
4026         u8         reserved_at_8[0x18];
4027
4028         u8         syndrome[0x20];
4029
4030         u8         reserved_at_40[0x40];
4031 };
4032
4033 struct mlx5_ifc_rts2rts_qp_in_bits {
4034         u8         opcode[0x10];
4035         u8         uid[0x10];
4036
4037         u8         reserved_at_20[0x10];
4038         u8         op_mod[0x10];
4039
4040         u8         reserved_at_40[0x8];
4041         u8         qpn[0x18];
4042
4043         u8         reserved_at_60[0x20];
4044
4045         u8         opt_param_mask[0x20];
4046
4047         u8         reserved_at_a0[0x20];
4048
4049         struct mlx5_ifc_qpc_bits qpc;
4050
4051         u8         reserved_at_800[0x80];
4052 };
4053
4054 struct mlx5_ifc_rtr2rts_qp_out_bits {
4055         u8         status[0x8];
4056         u8         reserved_at_8[0x18];
4057
4058         u8         syndrome[0x20];
4059
4060         u8         reserved_at_40[0x40];
4061 };
4062
4063 struct mlx5_ifc_rtr2rts_qp_in_bits {
4064         u8         opcode[0x10];
4065         u8         uid[0x10];
4066
4067         u8         reserved_at_20[0x10];
4068         u8         op_mod[0x10];
4069
4070         u8         reserved_at_40[0x8];
4071         u8         qpn[0x18];
4072
4073         u8         reserved_at_60[0x20];
4074
4075         u8         opt_param_mask[0x20];
4076
4077         u8         reserved_at_a0[0x20];
4078
4079         struct mlx5_ifc_qpc_bits qpc;
4080
4081         u8         reserved_at_800[0x80];
4082 };
4083
4084 struct mlx5_ifc_rst2init_qp_out_bits {
4085         u8         status[0x8];
4086         u8         reserved_at_8[0x18];
4087
4088         u8         syndrome[0x20];
4089
4090         u8         reserved_at_40[0x40];
4091 };
4092
4093 struct mlx5_ifc_rst2init_qp_in_bits {
4094         u8         opcode[0x10];
4095         u8         uid[0x10];
4096
4097         u8         reserved_at_20[0x10];
4098         u8         op_mod[0x10];
4099
4100         u8         reserved_at_40[0x8];
4101         u8         qpn[0x18];
4102
4103         u8         reserved_at_60[0x20];
4104
4105         u8         opt_param_mask[0x20];
4106
4107         u8         reserved_at_a0[0x20];
4108
4109         struct mlx5_ifc_qpc_bits qpc;
4110
4111         u8         reserved_at_800[0x80];
4112 };
4113
4114 struct mlx5_ifc_query_xrq_out_bits {
4115         u8         status[0x8];
4116         u8         reserved_at_8[0x18];
4117
4118         u8         syndrome[0x20];
4119
4120         u8         reserved_at_40[0x40];
4121
4122         struct mlx5_ifc_xrqc_bits xrq_context;
4123 };
4124
4125 struct mlx5_ifc_query_xrq_in_bits {
4126         u8         opcode[0x10];
4127         u8         reserved_at_10[0x10];
4128
4129         u8         reserved_at_20[0x10];
4130         u8         op_mod[0x10];
4131
4132         u8         reserved_at_40[0x8];
4133         u8         xrqn[0x18];
4134
4135         u8         reserved_at_60[0x20];
4136 };
4137
4138 struct mlx5_ifc_query_xrc_srq_out_bits {
4139         u8         status[0x8];
4140         u8         reserved_at_8[0x18];
4141
4142         u8         syndrome[0x20];
4143
4144         u8         reserved_at_40[0x40];
4145
4146         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4147
4148         u8         reserved_at_280[0x600];
4149
4150         u8         pas[0][0x40];
4151 };
4152
4153 struct mlx5_ifc_query_xrc_srq_in_bits {
4154         u8         opcode[0x10];
4155         u8         reserved_at_10[0x10];
4156
4157         u8         reserved_at_20[0x10];
4158         u8         op_mod[0x10];
4159
4160         u8         reserved_at_40[0x8];
4161         u8         xrc_srqn[0x18];
4162
4163         u8         reserved_at_60[0x20];
4164 };
4165
4166 enum {
4167         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4168         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4169 };
4170
4171 struct mlx5_ifc_query_vport_state_out_bits {
4172         u8         status[0x8];
4173         u8         reserved_at_8[0x18];
4174
4175         u8         syndrome[0x20];
4176
4177         u8         reserved_at_40[0x20];
4178
4179         u8         reserved_at_60[0x18];
4180         u8         admin_state[0x4];
4181         u8         state[0x4];
4182 };
4183
4184 enum {
4185         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
4186         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
4187         MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
4188 };
4189
4190 struct mlx5_ifc_arm_monitor_counter_in_bits {
4191         u8         opcode[0x10];
4192         u8         uid[0x10];
4193
4194         u8         reserved_at_20[0x10];
4195         u8         op_mod[0x10];
4196
4197         u8         reserved_at_40[0x20];
4198
4199         u8         reserved_at_60[0x20];
4200 };
4201
4202 struct mlx5_ifc_arm_monitor_counter_out_bits {
4203         u8         status[0x8];
4204         u8         reserved_at_8[0x18];
4205
4206         u8         syndrome[0x20];
4207
4208         u8         reserved_at_40[0x40];
4209 };
4210
4211 enum {
4212         MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
4213         MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4214 };
4215
4216 enum mlx5_monitor_counter_ppcnt {
4217         MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
4218         MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
4219         MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
4220         MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4221         MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
4222         MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
4223 };
4224
4225 enum {
4226         MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
4227 };
4228
4229 struct mlx5_ifc_monitor_counter_output_bits {
4230         u8         reserved_at_0[0x4];
4231         u8         type[0x4];
4232         u8         reserved_at_8[0x8];
4233         u8         counter[0x10];
4234
4235         u8         counter_group_id[0x20];
4236 };
4237
4238 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4239 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
4240 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4241                                           MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4242
4243 struct mlx5_ifc_set_monitor_counter_in_bits {
4244         u8         opcode[0x10];
4245         u8         uid[0x10];
4246
4247         u8         reserved_at_20[0x10];
4248         u8         op_mod[0x10];
4249
4250         u8         reserved_at_40[0x10];
4251         u8         num_of_counters[0x10];
4252
4253         u8         reserved_at_60[0x20];
4254
4255         struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4256 };
4257
4258 struct mlx5_ifc_set_monitor_counter_out_bits {
4259         u8         status[0x8];
4260         u8         reserved_at_8[0x18];
4261
4262         u8         syndrome[0x20];
4263
4264         u8         reserved_at_40[0x40];
4265 };
4266
4267 struct mlx5_ifc_query_vport_state_in_bits {
4268         u8         opcode[0x10];
4269         u8         reserved_at_10[0x10];
4270
4271         u8         reserved_at_20[0x10];
4272         u8         op_mod[0x10];
4273
4274         u8         other_vport[0x1];
4275         u8         reserved_at_41[0xf];
4276         u8         vport_number[0x10];
4277
4278         u8         reserved_at_60[0x20];
4279 };
4280
4281 struct mlx5_ifc_query_vnic_env_out_bits {
4282         u8         status[0x8];
4283         u8         reserved_at_8[0x18];
4284
4285         u8         syndrome[0x20];
4286
4287         u8         reserved_at_40[0x40];
4288
4289         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4290 };
4291
4292 enum {
4293         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4294 };
4295
4296 struct mlx5_ifc_query_vnic_env_in_bits {
4297         u8         opcode[0x10];
4298         u8         reserved_at_10[0x10];
4299
4300         u8         reserved_at_20[0x10];
4301         u8         op_mod[0x10];
4302
4303         u8         other_vport[0x1];
4304         u8         reserved_at_41[0xf];
4305         u8         vport_number[0x10];
4306
4307         u8         reserved_at_60[0x20];
4308 };
4309
4310 struct mlx5_ifc_query_vport_counter_out_bits {
4311         u8         status[0x8];
4312         u8         reserved_at_8[0x18];
4313
4314         u8         syndrome[0x20];
4315
4316         u8         reserved_at_40[0x40];
4317
4318         struct mlx5_ifc_traffic_counter_bits received_errors;
4319
4320         struct mlx5_ifc_traffic_counter_bits transmit_errors;
4321
4322         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4323
4324         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4325
4326         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4327
4328         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4329
4330         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4331
4332         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4333
4334         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4335
4336         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4337
4338         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4339
4340         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4341
4342         u8         reserved_at_680[0xa00];
4343 };
4344
4345 enum {
4346         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4347 };
4348
4349 struct mlx5_ifc_query_vport_counter_in_bits {
4350         u8         opcode[0x10];
4351         u8         reserved_at_10[0x10];
4352
4353         u8         reserved_at_20[0x10];
4354         u8         op_mod[0x10];
4355
4356         u8         other_vport[0x1];
4357         u8         reserved_at_41[0xb];
4358         u8         port_num[0x4];
4359         u8         vport_number[0x10];
4360
4361         u8         reserved_at_60[0x60];
4362
4363         u8         clear[0x1];
4364         u8         reserved_at_c1[0x1f];
4365
4366         u8         reserved_at_e0[0x20];
4367 };
4368
4369 struct mlx5_ifc_query_tis_out_bits {
4370         u8         status[0x8];
4371         u8         reserved_at_8[0x18];
4372
4373         u8         syndrome[0x20];
4374
4375         u8         reserved_at_40[0x40];
4376
4377         struct mlx5_ifc_tisc_bits tis_context;
4378 };
4379
4380 struct mlx5_ifc_query_tis_in_bits {
4381         u8         opcode[0x10];
4382         u8         reserved_at_10[0x10];
4383
4384         u8         reserved_at_20[0x10];
4385         u8         op_mod[0x10];
4386
4387         u8         reserved_at_40[0x8];
4388         u8         tisn[0x18];
4389
4390         u8         reserved_at_60[0x20];
4391 };
4392
4393 struct mlx5_ifc_query_tir_out_bits {
4394         u8         status[0x8];
4395         u8         reserved_at_8[0x18];
4396
4397         u8         syndrome[0x20];
4398
4399         u8         reserved_at_40[0xc0];
4400
4401         struct mlx5_ifc_tirc_bits tir_context;
4402 };
4403
4404 struct mlx5_ifc_query_tir_in_bits {
4405         u8         opcode[0x10];
4406         u8         reserved_at_10[0x10];
4407
4408         u8         reserved_at_20[0x10];
4409         u8         op_mod[0x10];
4410
4411         u8         reserved_at_40[0x8];
4412         u8         tirn[0x18];
4413
4414         u8         reserved_at_60[0x20];
4415 };
4416
4417 struct mlx5_ifc_query_srq_out_bits {
4418         u8         status[0x8];
4419         u8         reserved_at_8[0x18];
4420
4421         u8         syndrome[0x20];
4422
4423         u8         reserved_at_40[0x40];
4424
4425         struct mlx5_ifc_srqc_bits srq_context_entry;
4426
4427         u8         reserved_at_280[0x600];
4428
4429         u8         pas[0][0x40];
4430 };
4431
4432 struct mlx5_ifc_query_srq_in_bits {
4433         u8         opcode[0x10];
4434         u8         reserved_at_10[0x10];
4435
4436         u8         reserved_at_20[0x10];
4437         u8         op_mod[0x10];
4438
4439         u8         reserved_at_40[0x8];
4440         u8         srqn[0x18];
4441
4442         u8         reserved_at_60[0x20];
4443 };
4444
4445 struct mlx5_ifc_query_sq_out_bits {
4446         u8         status[0x8];
4447         u8         reserved_at_8[0x18];
4448
4449         u8         syndrome[0x20];
4450
4451         u8         reserved_at_40[0xc0];
4452
4453         struct mlx5_ifc_sqc_bits sq_context;
4454 };
4455
4456 struct mlx5_ifc_query_sq_in_bits {
4457         u8         opcode[0x10];
4458         u8         reserved_at_10[0x10];
4459
4460         u8         reserved_at_20[0x10];
4461         u8         op_mod[0x10];
4462
4463         u8         reserved_at_40[0x8];
4464         u8         sqn[0x18];
4465
4466         u8         reserved_at_60[0x20];
4467 };
4468
4469 struct mlx5_ifc_query_special_contexts_out_bits {
4470         u8         status[0x8];
4471         u8         reserved_at_8[0x18];
4472
4473         u8         syndrome[0x20];
4474
4475         u8         dump_fill_mkey[0x20];
4476
4477         u8         resd_lkey[0x20];
4478
4479         u8         null_mkey[0x20];
4480
4481         u8         reserved_at_a0[0x60];
4482 };
4483
4484 struct mlx5_ifc_query_special_contexts_in_bits {
4485         u8         opcode[0x10];
4486         u8         reserved_at_10[0x10];
4487
4488         u8         reserved_at_20[0x10];
4489         u8         op_mod[0x10];
4490
4491         u8         reserved_at_40[0x40];
4492 };
4493
4494 struct mlx5_ifc_query_scheduling_element_out_bits {
4495         u8         opcode[0x10];
4496         u8         reserved_at_10[0x10];
4497
4498         u8         reserved_at_20[0x10];
4499         u8         op_mod[0x10];
4500
4501         u8         reserved_at_40[0xc0];
4502
4503         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4504
4505         u8         reserved_at_300[0x100];
4506 };
4507
4508 enum {
4509         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4510 };
4511
4512 struct mlx5_ifc_query_scheduling_element_in_bits {
4513         u8         opcode[0x10];
4514         u8         reserved_at_10[0x10];
4515
4516         u8         reserved_at_20[0x10];
4517         u8         op_mod[0x10];
4518
4519         u8         scheduling_hierarchy[0x8];
4520         u8         reserved_at_48[0x18];
4521
4522         u8         scheduling_element_id[0x20];
4523
4524         u8         reserved_at_80[0x180];
4525 };
4526
4527 struct mlx5_ifc_query_rqt_out_bits {
4528         u8         status[0x8];
4529         u8         reserved_at_8[0x18];
4530
4531         u8         syndrome[0x20];
4532
4533         u8         reserved_at_40[0xc0];
4534
4535         struct mlx5_ifc_rqtc_bits rqt_context;
4536 };
4537
4538 struct mlx5_ifc_query_rqt_in_bits {
4539         u8         opcode[0x10];
4540         u8         reserved_at_10[0x10];
4541
4542         u8         reserved_at_20[0x10];
4543         u8         op_mod[0x10];
4544
4545         u8         reserved_at_40[0x8];
4546         u8         rqtn[0x18];
4547
4548         u8         reserved_at_60[0x20];
4549 };
4550
4551 struct mlx5_ifc_query_rq_out_bits {
4552         u8         status[0x8];
4553         u8         reserved_at_8[0x18];
4554
4555         u8         syndrome[0x20];
4556
4557         u8         reserved_at_40[0xc0];
4558
4559         struct mlx5_ifc_rqc_bits rq_context;
4560 };
4561
4562 struct mlx5_ifc_query_rq_in_bits {
4563         u8         opcode[0x10];
4564         u8         reserved_at_10[0x10];
4565
4566         u8         reserved_at_20[0x10];
4567         u8         op_mod[0x10];
4568
4569         u8         reserved_at_40[0x8];
4570         u8         rqn[0x18];
4571
4572         u8         reserved_at_60[0x20];
4573 };
4574
4575 struct mlx5_ifc_query_roce_address_out_bits {
4576         u8         status[0x8];
4577         u8         reserved_at_8[0x18];
4578
4579         u8         syndrome[0x20];
4580
4581         u8         reserved_at_40[0x40];
4582
4583         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4584 };
4585
4586 struct mlx5_ifc_query_roce_address_in_bits {
4587         u8         opcode[0x10];
4588         u8         reserved_at_10[0x10];
4589
4590         u8         reserved_at_20[0x10];
4591         u8         op_mod[0x10];
4592
4593         u8         roce_address_index[0x10];
4594         u8         reserved_at_50[0xc];
4595         u8         vhca_port_num[0x4];
4596
4597         u8         reserved_at_60[0x20];
4598 };
4599
4600 struct mlx5_ifc_query_rmp_out_bits {
4601         u8         status[0x8];
4602         u8         reserved_at_8[0x18];
4603
4604         u8         syndrome[0x20];
4605
4606         u8         reserved_at_40[0xc0];
4607
4608         struct mlx5_ifc_rmpc_bits rmp_context;
4609 };
4610
4611 struct mlx5_ifc_query_rmp_in_bits {
4612         u8         opcode[0x10];
4613         u8         reserved_at_10[0x10];
4614
4615         u8         reserved_at_20[0x10];
4616         u8         op_mod[0x10];
4617
4618         u8         reserved_at_40[0x8];
4619         u8         rmpn[0x18];
4620
4621         u8         reserved_at_60[0x20];
4622 };
4623
4624 struct mlx5_ifc_query_qp_out_bits {
4625         u8         status[0x8];
4626         u8         reserved_at_8[0x18];
4627
4628         u8         syndrome[0x20];
4629
4630         u8         reserved_at_40[0x40];
4631
4632         u8         opt_param_mask[0x20];
4633
4634         u8         reserved_at_a0[0x20];
4635
4636         struct mlx5_ifc_qpc_bits qpc;
4637
4638         u8         reserved_at_800[0x80];
4639
4640         u8         pas[0][0x40];
4641 };
4642
4643 struct mlx5_ifc_query_qp_in_bits {
4644         u8         opcode[0x10];
4645         u8         reserved_at_10[0x10];
4646
4647         u8         reserved_at_20[0x10];
4648         u8         op_mod[0x10];
4649
4650         u8         reserved_at_40[0x8];
4651         u8         qpn[0x18];
4652
4653         u8         reserved_at_60[0x20];
4654 };
4655
4656 struct mlx5_ifc_query_q_counter_out_bits {
4657         u8         status[0x8];
4658         u8         reserved_at_8[0x18];
4659
4660         u8         syndrome[0x20];
4661
4662         u8         reserved_at_40[0x40];
4663
4664         u8         rx_write_requests[0x20];
4665
4666         u8         reserved_at_a0[0x20];
4667
4668         u8         rx_read_requests[0x20];
4669
4670         u8         reserved_at_e0[0x20];
4671
4672         u8         rx_atomic_requests[0x20];
4673
4674         u8         reserved_at_120[0x20];
4675
4676         u8         rx_dct_connect[0x20];
4677
4678         u8         reserved_at_160[0x20];
4679
4680         u8         out_of_buffer[0x20];
4681
4682         u8         reserved_at_1a0[0x20];
4683
4684         u8         out_of_sequence[0x20];
4685
4686         u8         reserved_at_1e0[0x20];
4687
4688         u8         duplicate_request[0x20];
4689
4690         u8         reserved_at_220[0x20];
4691
4692         u8         rnr_nak_retry_err[0x20];
4693
4694         u8         reserved_at_260[0x20];
4695
4696         u8         packet_seq_err[0x20];
4697
4698         u8         reserved_at_2a0[0x20];
4699
4700         u8         implied_nak_seq_err[0x20];
4701
4702         u8         reserved_at_2e0[0x20];
4703
4704         u8         local_ack_timeout_err[0x20];
4705
4706         u8         reserved_at_320[0xa0];
4707
4708         u8         resp_local_length_error[0x20];
4709
4710         u8         req_local_length_error[0x20];
4711
4712         u8         resp_local_qp_error[0x20];
4713
4714         u8         local_operation_error[0x20];
4715
4716         u8         resp_local_protection[0x20];
4717
4718         u8         req_local_protection[0x20];
4719
4720         u8         resp_cqe_error[0x20];
4721
4722         u8         req_cqe_error[0x20];
4723
4724         u8         req_mw_binding[0x20];
4725
4726         u8         req_bad_response[0x20];
4727
4728         u8         req_remote_invalid_request[0x20];
4729
4730         u8         resp_remote_invalid_request[0x20];
4731
4732         u8         req_remote_access_errors[0x20];
4733
4734         u8         resp_remote_access_errors[0x20];
4735
4736         u8         req_remote_operation_errors[0x20];
4737
4738         u8         req_transport_retries_exceeded[0x20];
4739
4740         u8         cq_overflow[0x20];
4741
4742         u8         resp_cqe_flush_error[0x20];
4743
4744         u8         req_cqe_flush_error[0x20];
4745
4746         u8         reserved_at_620[0x1e0];
4747 };
4748
4749 struct mlx5_ifc_query_q_counter_in_bits {
4750         u8         opcode[0x10];
4751         u8         reserved_at_10[0x10];
4752
4753         u8         reserved_at_20[0x10];
4754         u8         op_mod[0x10];
4755
4756         u8         reserved_at_40[0x80];
4757
4758         u8         clear[0x1];
4759         u8         reserved_at_c1[0x1f];
4760
4761         u8         reserved_at_e0[0x18];
4762         u8         counter_set_id[0x8];
4763 };
4764
4765 struct mlx5_ifc_query_pages_out_bits {
4766         u8         status[0x8];
4767         u8         reserved_at_8[0x18];
4768
4769         u8         syndrome[0x20];
4770
4771         u8         embedded_cpu_function[0x1];
4772         u8         reserved_at_41[0xf];
4773         u8         function_id[0x10];
4774
4775         u8         num_pages[0x20];
4776 };
4777
4778 enum {
4779         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4780         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4781         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4782 };
4783
4784 struct mlx5_ifc_query_pages_in_bits {
4785         u8         opcode[0x10];
4786         u8         reserved_at_10[0x10];
4787
4788         u8         reserved_at_20[0x10];
4789         u8         op_mod[0x10];
4790
4791         u8         embedded_cpu_function[0x1];
4792         u8         reserved_at_41[0xf];
4793         u8         function_id[0x10];
4794
4795         u8         reserved_at_60[0x20];
4796 };
4797
4798 struct mlx5_ifc_query_nic_vport_context_out_bits {
4799         u8         status[0x8];
4800         u8         reserved_at_8[0x18];
4801
4802         u8         syndrome[0x20];
4803
4804         u8         reserved_at_40[0x40];
4805
4806         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4807 };
4808
4809 struct mlx5_ifc_query_nic_vport_context_in_bits {
4810         u8         opcode[0x10];
4811         u8         reserved_at_10[0x10];
4812
4813         u8         reserved_at_20[0x10];
4814         u8         op_mod[0x10];
4815
4816         u8         other_vport[0x1];
4817         u8         reserved_at_41[0xf];
4818         u8         vport_number[0x10];
4819
4820         u8         reserved_at_60[0x5];
4821         u8         allowed_list_type[0x3];
4822         u8         reserved_at_68[0x18];
4823 };
4824
4825 struct mlx5_ifc_query_mkey_out_bits {
4826         u8         status[0x8];
4827         u8         reserved_at_8[0x18];
4828
4829         u8         syndrome[0x20];
4830
4831         u8         reserved_at_40[0x40];
4832
4833         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4834
4835         u8         reserved_at_280[0x600];
4836
4837         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4838
4839         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4840 };
4841
4842 struct mlx5_ifc_query_mkey_in_bits {
4843         u8         opcode[0x10];
4844         u8         reserved_at_10[0x10];
4845
4846         u8         reserved_at_20[0x10];
4847         u8         op_mod[0x10];
4848
4849         u8         reserved_at_40[0x8];
4850         u8         mkey_index[0x18];
4851
4852         u8         pg_access[0x1];
4853         u8         reserved_at_61[0x1f];
4854 };
4855
4856 struct mlx5_ifc_query_mad_demux_out_bits {
4857         u8         status[0x8];
4858         u8         reserved_at_8[0x18];
4859
4860         u8         syndrome[0x20];
4861
4862         u8         reserved_at_40[0x40];
4863
4864         u8         mad_dumux_parameters_block[0x20];
4865 };
4866
4867 struct mlx5_ifc_query_mad_demux_in_bits {
4868         u8         opcode[0x10];
4869         u8         reserved_at_10[0x10];
4870
4871         u8         reserved_at_20[0x10];
4872         u8         op_mod[0x10];
4873
4874         u8         reserved_at_40[0x40];
4875 };
4876
4877 struct mlx5_ifc_query_l2_table_entry_out_bits {
4878         u8         status[0x8];
4879         u8         reserved_at_8[0x18];
4880
4881         u8         syndrome[0x20];
4882
4883         u8         reserved_at_40[0xa0];
4884
4885         u8         reserved_at_e0[0x13];
4886         u8         vlan_valid[0x1];
4887         u8         vlan[0xc];
4888
4889         struct mlx5_ifc_mac_address_layout_bits mac_address;
4890
4891         u8         reserved_at_140[0xc0];
4892 };
4893
4894 struct mlx5_ifc_query_l2_table_entry_in_bits {
4895         u8         opcode[0x10];
4896         u8         reserved_at_10[0x10];
4897
4898         u8         reserved_at_20[0x10];
4899         u8         op_mod[0x10];
4900
4901         u8         reserved_at_40[0x60];
4902
4903         u8         reserved_at_a0[0x8];
4904         u8         table_index[0x18];
4905
4906         u8         reserved_at_c0[0x140];
4907 };
4908
4909 struct mlx5_ifc_query_issi_out_bits {
4910         u8         status[0x8];
4911         u8         reserved_at_8[0x18];
4912
4913         u8         syndrome[0x20];
4914
4915         u8         reserved_at_40[0x10];
4916         u8         current_issi[0x10];
4917
4918         u8         reserved_at_60[0xa0];
4919
4920         u8         reserved_at_100[76][0x8];
4921         u8         supported_issi_dw0[0x20];
4922 };
4923
4924 struct mlx5_ifc_query_issi_in_bits {
4925         u8         opcode[0x10];
4926         u8         reserved_at_10[0x10];
4927
4928         u8         reserved_at_20[0x10];
4929         u8         op_mod[0x10];
4930
4931         u8         reserved_at_40[0x40];
4932 };
4933
4934 struct mlx5_ifc_set_driver_version_out_bits {
4935         u8         status[0x8];
4936         u8         reserved_0[0x18];
4937
4938         u8         syndrome[0x20];
4939         u8         reserved_1[0x40];
4940 };
4941
4942 struct mlx5_ifc_set_driver_version_in_bits {
4943         u8         opcode[0x10];
4944         u8         reserved_0[0x10];
4945
4946         u8         reserved_1[0x10];
4947         u8         op_mod[0x10];
4948
4949         u8         reserved_2[0x40];
4950         u8         driver_version[64][0x8];
4951 };
4952
4953 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4954         u8         status[0x8];
4955         u8         reserved_at_8[0x18];
4956
4957         u8         syndrome[0x20];
4958
4959         u8         reserved_at_40[0x40];
4960
4961         struct mlx5_ifc_pkey_bits pkey[0];
4962 };
4963
4964 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4965         u8         opcode[0x10];
4966         u8         reserved_at_10[0x10];
4967
4968         u8         reserved_at_20[0x10];
4969         u8         op_mod[0x10];
4970
4971         u8         other_vport[0x1];
4972         u8         reserved_at_41[0xb];
4973         u8         port_num[0x4];
4974         u8         vport_number[0x10];
4975
4976         u8         reserved_at_60[0x10];
4977         u8         pkey_index[0x10];
4978 };
4979
4980 enum {
4981         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4982         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4983         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4984 };
4985
4986 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4987         u8         status[0x8];
4988         u8         reserved_at_8[0x18];
4989
4990         u8         syndrome[0x20];
4991
4992         u8         reserved_at_40[0x20];
4993
4994         u8         gids_num[0x10];
4995         u8         reserved_at_70[0x10];
4996
4997         struct mlx5_ifc_array128_auto_bits gid[0];
4998 };
4999
5000 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5001         u8         opcode[0x10];
5002         u8         reserved_at_10[0x10];
5003
5004         u8         reserved_at_20[0x10];
5005         u8         op_mod[0x10];
5006
5007         u8         other_vport[0x1];
5008         u8         reserved_at_41[0xb];
5009         u8         port_num[0x4];
5010         u8         vport_number[0x10];
5011
5012         u8         reserved_at_60[0x10];
5013         u8         gid_index[0x10];
5014 };
5015
5016 struct mlx5_ifc_query_hca_vport_context_out_bits {
5017         u8         status[0x8];
5018         u8         reserved_at_8[0x18];
5019
5020         u8         syndrome[0x20];
5021
5022         u8         reserved_at_40[0x40];
5023
5024         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5025 };
5026
5027 struct mlx5_ifc_query_hca_vport_context_in_bits {
5028         u8         opcode[0x10];
5029         u8         reserved_at_10[0x10];
5030
5031         u8         reserved_at_20[0x10];
5032         u8         op_mod[0x10];
5033
5034         u8         other_vport[0x1];
5035         u8         reserved_at_41[0xb];
5036         u8         port_num[0x4];
5037         u8         vport_number[0x10];
5038
5039         u8         reserved_at_60[0x20];
5040 };
5041
5042 struct mlx5_ifc_query_hca_cap_out_bits {
5043         u8         status[0x8];
5044         u8         reserved_at_8[0x18];
5045
5046         u8         syndrome[0x20];
5047
5048         u8         reserved_at_40[0x40];
5049
5050         union mlx5_ifc_hca_cap_union_bits capability;
5051 };
5052
5053 struct mlx5_ifc_query_hca_cap_in_bits {
5054         u8         opcode[0x10];
5055         u8         reserved_at_10[0x10];
5056
5057         u8         reserved_at_20[0x10];
5058         u8         op_mod[0x10];
5059
5060         u8         other_function[0x1];
5061         u8         reserved_at_41[0xf];
5062         u8         function_id[0x10];
5063
5064         u8         reserved_at_60[0x20];
5065 };
5066
5067 struct mlx5_ifc_other_hca_cap_bits {
5068         u8         roce[0x1];
5069         u8         reserved_at_1[0x27f];
5070 };
5071
5072 struct mlx5_ifc_query_other_hca_cap_out_bits {
5073         u8         status[0x8];
5074         u8         reserved_at_8[0x18];
5075
5076         u8         syndrome[0x20];
5077
5078         u8         reserved_at_40[0x40];
5079
5080         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5081 };
5082
5083 struct mlx5_ifc_query_other_hca_cap_in_bits {
5084         u8         opcode[0x10];
5085         u8         reserved_at_10[0x10];
5086
5087         u8         reserved_at_20[0x10];
5088         u8         op_mod[0x10];
5089
5090         u8         reserved_at_40[0x10];
5091         u8         function_id[0x10];
5092
5093         u8         reserved_at_60[0x20];
5094 };
5095
5096 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5097         u8         status[0x8];
5098         u8         reserved_at_8[0x18];
5099
5100         u8         syndrome[0x20];
5101
5102         u8         reserved_at_40[0x40];
5103 };
5104
5105 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5106         u8         opcode[0x10];
5107         u8         reserved_at_10[0x10];
5108
5109         u8         reserved_at_20[0x10];
5110         u8         op_mod[0x10];
5111
5112         u8         reserved_at_40[0x10];
5113         u8         function_id[0x10];
5114         u8         field_select[0x20];
5115
5116         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5117 };
5118
5119 struct mlx5_ifc_flow_table_context_bits {
5120         u8         reformat_en[0x1];
5121         u8         decap_en[0x1];
5122         u8         sw_owner[0x1];
5123         u8         termination_table[0x1];
5124         u8         table_miss_action[0x4];
5125         u8         level[0x8];
5126         u8         reserved_at_10[0x8];
5127         u8         log_size[0x8];
5128
5129         u8         reserved_at_20[0x8];
5130         u8         table_miss_id[0x18];
5131
5132         u8         reserved_at_40[0x8];
5133         u8         lag_master_next_table_id[0x18];
5134
5135         u8         reserved_at_60[0x60];
5136
5137         u8         sw_owner_icm_root_1[0x40];
5138
5139         u8         sw_owner_icm_root_0[0x40];
5140
5141 };
5142
5143 struct mlx5_ifc_query_flow_table_out_bits {
5144         u8         status[0x8];
5145         u8         reserved_at_8[0x18];
5146
5147         u8         syndrome[0x20];
5148
5149         u8         reserved_at_40[0x80];
5150
5151         struct mlx5_ifc_flow_table_context_bits flow_table_context;
5152 };
5153
5154 struct mlx5_ifc_query_flow_table_in_bits {
5155         u8         opcode[0x10];
5156         u8         reserved_at_10[0x10];
5157
5158         u8         reserved_at_20[0x10];
5159         u8         op_mod[0x10];
5160
5161         u8         reserved_at_40[0x40];
5162
5163         u8         table_type[0x8];
5164         u8         reserved_at_88[0x18];
5165
5166         u8         reserved_at_a0[0x8];
5167         u8         table_id[0x18];
5168
5169         u8         reserved_at_c0[0x140];
5170 };
5171
5172 struct mlx5_ifc_query_fte_out_bits {
5173         u8         status[0x8];
5174         u8         reserved_at_8[0x18];
5175
5176         u8         syndrome[0x20];
5177
5178         u8         reserved_at_40[0x1c0];
5179
5180         struct mlx5_ifc_flow_context_bits flow_context;
5181 };
5182
5183 struct mlx5_ifc_query_fte_in_bits {
5184         u8         opcode[0x10];
5185         u8         reserved_at_10[0x10];
5186
5187         u8         reserved_at_20[0x10];
5188         u8         op_mod[0x10];
5189
5190         u8         reserved_at_40[0x40];
5191
5192         u8         table_type[0x8];
5193         u8         reserved_at_88[0x18];
5194
5195         u8         reserved_at_a0[0x8];
5196         u8         table_id[0x18];
5197
5198         u8         reserved_at_c0[0x40];
5199
5200         u8         flow_index[0x20];
5201
5202         u8         reserved_at_120[0xe0];
5203 };
5204
5205 enum {
5206         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5207         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5208         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5209         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5210         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5211 };
5212
5213 struct mlx5_ifc_query_flow_group_out_bits {
5214         u8         status[0x8];
5215         u8         reserved_at_8[0x18];
5216
5217         u8         syndrome[0x20];
5218
5219         u8         reserved_at_40[0xa0];
5220
5221         u8         start_flow_index[0x20];
5222
5223         u8         reserved_at_100[0x20];
5224
5225         u8         end_flow_index[0x20];
5226
5227         u8         reserved_at_140[0xa0];
5228
5229         u8         reserved_at_1e0[0x18];
5230         u8         match_criteria_enable[0x8];
5231
5232         struct mlx5_ifc_fte_match_param_bits match_criteria;
5233
5234         u8         reserved_at_1200[0xe00];
5235 };
5236
5237 struct mlx5_ifc_query_flow_group_in_bits {
5238         u8         opcode[0x10];
5239         u8         reserved_at_10[0x10];
5240
5241         u8         reserved_at_20[0x10];
5242         u8         op_mod[0x10];
5243
5244         u8         reserved_at_40[0x40];
5245
5246         u8         table_type[0x8];
5247         u8         reserved_at_88[0x18];
5248
5249         u8         reserved_at_a0[0x8];
5250         u8         table_id[0x18];
5251
5252         u8         group_id[0x20];
5253
5254         u8         reserved_at_e0[0x120];
5255 };
5256
5257 struct mlx5_ifc_query_flow_counter_out_bits {
5258         u8         status[0x8];
5259         u8         reserved_at_8[0x18];
5260
5261         u8         syndrome[0x20];
5262
5263         u8         reserved_at_40[0x40];
5264
5265         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
5266 };
5267
5268 struct mlx5_ifc_query_flow_counter_in_bits {
5269         u8         opcode[0x10];
5270         u8         reserved_at_10[0x10];
5271
5272         u8         reserved_at_20[0x10];
5273         u8         op_mod[0x10];
5274
5275         u8         reserved_at_40[0x80];
5276
5277         u8         clear[0x1];
5278         u8         reserved_at_c1[0xf];
5279         u8         num_of_counters[0x10];
5280
5281         u8         flow_counter_id[0x20];
5282 };
5283
5284 struct mlx5_ifc_query_esw_vport_context_out_bits {
5285         u8         status[0x8];
5286         u8         reserved_at_8[0x18];
5287
5288         u8         syndrome[0x20];
5289
5290         u8         reserved_at_40[0x40];
5291
5292         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5293 };
5294
5295 struct mlx5_ifc_query_esw_vport_context_in_bits {
5296         u8         opcode[0x10];
5297         u8         reserved_at_10[0x10];
5298
5299         u8         reserved_at_20[0x10];
5300         u8         op_mod[0x10];
5301
5302         u8         other_vport[0x1];
5303         u8         reserved_at_41[0xf];
5304         u8         vport_number[0x10];
5305
5306         u8         reserved_at_60[0x20];
5307 };
5308
5309 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5310         u8         status[0x8];
5311         u8         reserved_at_8[0x18];
5312
5313         u8         syndrome[0x20];
5314
5315         u8         reserved_at_40[0x40];
5316 };
5317
5318 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5319         u8         reserved_at_0[0x1b];
5320         u8         fdb_to_vport_reg_c_id[0x1];
5321         u8         vport_cvlan_insert[0x1];
5322         u8         vport_svlan_insert[0x1];
5323         u8         vport_cvlan_strip[0x1];
5324         u8         vport_svlan_strip[0x1];
5325 };
5326
5327 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5328         u8         opcode[0x10];
5329         u8         reserved_at_10[0x10];
5330
5331         u8         reserved_at_20[0x10];
5332         u8         op_mod[0x10];
5333
5334         u8         other_vport[0x1];
5335         u8         reserved_at_41[0xf];
5336         u8         vport_number[0x10];
5337
5338         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5339
5340         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5341 };
5342
5343 struct mlx5_ifc_query_eq_out_bits {
5344         u8         status[0x8];
5345         u8         reserved_at_8[0x18];
5346
5347         u8         syndrome[0x20];
5348
5349         u8         reserved_at_40[0x40];
5350
5351         struct mlx5_ifc_eqc_bits eq_context_entry;
5352
5353         u8         reserved_at_280[0x40];
5354
5355         u8         event_bitmask[0x40];
5356
5357         u8         reserved_at_300[0x580];
5358
5359         u8         pas[0][0x40];
5360 };
5361
5362 struct mlx5_ifc_query_eq_in_bits {
5363         u8         opcode[0x10];
5364         u8         reserved_at_10[0x10];
5365
5366         u8         reserved_at_20[0x10];
5367         u8         op_mod[0x10];
5368
5369         u8         reserved_at_40[0x18];
5370         u8         eq_number[0x8];
5371
5372         u8         reserved_at_60[0x20];
5373 };
5374
5375 struct mlx5_ifc_packet_reformat_context_in_bits {
5376         u8         reserved_at_0[0x5];
5377         u8         reformat_type[0x3];
5378         u8         reserved_at_8[0xe];
5379         u8         reformat_data_size[0xa];
5380
5381         u8         reserved_at_20[0x10];
5382         u8         reformat_data[2][0x8];
5383
5384         u8         more_reformat_data[0][0x8];
5385 };
5386
5387 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5388         u8         status[0x8];
5389         u8         reserved_at_8[0x18];
5390
5391         u8         syndrome[0x20];
5392
5393         u8         reserved_at_40[0xa0];
5394
5395         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
5396 };
5397
5398 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5399         u8         opcode[0x10];
5400         u8         reserved_at_10[0x10];
5401
5402         u8         reserved_at_20[0x10];
5403         u8         op_mod[0x10];
5404
5405         u8         packet_reformat_id[0x20];
5406
5407         u8         reserved_at_60[0xa0];
5408 };
5409
5410 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5411         u8         status[0x8];
5412         u8         reserved_at_8[0x18];
5413
5414         u8         syndrome[0x20];
5415
5416         u8         packet_reformat_id[0x20];
5417
5418         u8         reserved_at_60[0x20];
5419 };
5420
5421 enum mlx5_reformat_ctx_type {
5422         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5423         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5424         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5425         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5426         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5427 };
5428
5429 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5430         u8         opcode[0x10];
5431         u8         reserved_at_10[0x10];
5432
5433         u8         reserved_at_20[0x10];
5434         u8         op_mod[0x10];
5435
5436         u8         reserved_at_40[0xa0];
5437
5438         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5439 };
5440
5441 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5442         u8         status[0x8];
5443         u8         reserved_at_8[0x18];
5444
5445         u8         syndrome[0x20];
5446
5447         u8         reserved_at_40[0x40];
5448 };
5449
5450 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5451         u8         opcode[0x10];
5452         u8         reserved_at_10[0x10];
5453
5454         u8         reserved_20[0x10];
5455         u8         op_mod[0x10];
5456
5457         u8         packet_reformat_id[0x20];
5458
5459         u8         reserved_60[0x20];
5460 };
5461
5462 struct mlx5_ifc_set_action_in_bits {
5463         u8         action_type[0x4];
5464         u8         field[0xc];
5465         u8         reserved_at_10[0x3];
5466         u8         offset[0x5];
5467         u8         reserved_at_18[0x3];
5468         u8         length[0x5];
5469
5470         u8         data[0x20];
5471 };
5472
5473 struct mlx5_ifc_add_action_in_bits {
5474         u8         action_type[0x4];
5475         u8         field[0xc];
5476         u8         reserved_at_10[0x10];
5477
5478         u8         data[0x20];
5479 };
5480
5481 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
5482         struct mlx5_ifc_set_action_in_bits set_action_in;
5483         struct mlx5_ifc_add_action_in_bits add_action_in;
5484         u8         reserved_at_0[0x40];
5485 };
5486
5487 enum {
5488         MLX5_ACTION_TYPE_SET   = 0x1,
5489         MLX5_ACTION_TYPE_ADD   = 0x2,
5490 };
5491
5492 enum {
5493         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
5494         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
5495         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
5496         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
5497         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
5498         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
5499         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
5500         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
5501         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
5502         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
5503         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
5504         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
5505         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
5506         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
5507         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
5508         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
5509         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
5510         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
5511         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
5512         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
5513         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
5514         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
5515         MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
5516         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5517         MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
5518         MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
5519         MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
5520         MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
5521         MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
5522         MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
5523         MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
5524         MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
5525         MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
5526         MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
5527 };
5528
5529 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5530         u8         status[0x8];
5531         u8         reserved_at_8[0x18];
5532
5533         u8         syndrome[0x20];
5534
5535         u8         modify_header_id[0x20];
5536
5537         u8         reserved_at_60[0x20];
5538 };
5539
5540 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5541         u8         opcode[0x10];
5542         u8         reserved_at_10[0x10];
5543
5544         u8         reserved_at_20[0x10];
5545         u8         op_mod[0x10];
5546
5547         u8         reserved_at_40[0x20];
5548
5549         u8         table_type[0x8];
5550         u8         reserved_at_68[0x10];
5551         u8         num_of_actions[0x8];
5552
5553         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
5554 };
5555
5556 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5557         u8         status[0x8];
5558         u8         reserved_at_8[0x18];
5559
5560         u8         syndrome[0x20];
5561
5562         u8         reserved_at_40[0x40];
5563 };
5564
5565 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5566         u8         opcode[0x10];
5567         u8         reserved_at_10[0x10];
5568
5569         u8         reserved_at_20[0x10];
5570         u8         op_mod[0x10];
5571
5572         u8         modify_header_id[0x20];
5573
5574         u8         reserved_at_60[0x20];
5575 };
5576
5577 struct mlx5_ifc_query_dct_out_bits {
5578         u8         status[0x8];
5579         u8         reserved_at_8[0x18];
5580
5581         u8         syndrome[0x20];
5582
5583         u8         reserved_at_40[0x40];
5584
5585         struct mlx5_ifc_dctc_bits dct_context_entry;
5586
5587         u8         reserved_at_280[0x180];
5588 };
5589
5590 struct mlx5_ifc_query_dct_in_bits {
5591         u8         opcode[0x10];
5592         u8         reserved_at_10[0x10];
5593
5594         u8         reserved_at_20[0x10];
5595         u8         op_mod[0x10];
5596
5597         u8         reserved_at_40[0x8];
5598         u8         dctn[0x18];
5599
5600         u8         reserved_at_60[0x20];
5601 };
5602
5603 struct mlx5_ifc_query_cq_out_bits {
5604         u8         status[0x8];
5605         u8         reserved_at_8[0x18];
5606
5607         u8         syndrome[0x20];
5608
5609         u8         reserved_at_40[0x40];
5610
5611         struct mlx5_ifc_cqc_bits cq_context;
5612
5613         u8         reserved_at_280[0x600];
5614
5615         u8         pas[0][0x40];
5616 };
5617
5618 struct mlx5_ifc_query_cq_in_bits {
5619         u8         opcode[0x10];
5620         u8         reserved_at_10[0x10];
5621
5622         u8         reserved_at_20[0x10];
5623         u8         op_mod[0x10];
5624
5625         u8         reserved_at_40[0x8];
5626         u8         cqn[0x18];
5627
5628         u8         reserved_at_60[0x20];
5629 };
5630
5631 struct mlx5_ifc_query_cong_status_out_bits {
5632         u8         status[0x8];
5633         u8         reserved_at_8[0x18];
5634
5635         u8         syndrome[0x20];
5636
5637         u8         reserved_at_40[0x20];
5638
5639         u8         enable[0x1];
5640         u8         tag_enable[0x1];
5641         u8         reserved_at_62[0x1e];
5642 };
5643
5644 struct mlx5_ifc_query_cong_status_in_bits {
5645         u8         opcode[0x10];
5646         u8         reserved_at_10[0x10];
5647
5648         u8         reserved_at_20[0x10];
5649         u8         op_mod[0x10];
5650
5651         u8         reserved_at_40[0x18];
5652         u8         priority[0x4];
5653         u8         cong_protocol[0x4];
5654
5655         u8         reserved_at_60[0x20];
5656 };
5657
5658 struct mlx5_ifc_query_cong_statistics_out_bits {
5659         u8         status[0x8];
5660         u8         reserved_at_8[0x18];
5661
5662         u8         syndrome[0x20];
5663
5664         u8         reserved_at_40[0x40];
5665
5666         u8         rp_cur_flows[0x20];
5667
5668         u8         sum_flows[0x20];
5669
5670         u8         rp_cnp_ignored_high[0x20];
5671
5672         u8         rp_cnp_ignored_low[0x20];
5673
5674         u8         rp_cnp_handled_high[0x20];
5675
5676         u8         rp_cnp_handled_low[0x20];
5677
5678         u8         reserved_at_140[0x100];
5679
5680         u8         time_stamp_high[0x20];
5681
5682         u8         time_stamp_low[0x20];
5683
5684         u8         accumulators_period[0x20];
5685
5686         u8         np_ecn_marked_roce_packets_high[0x20];
5687
5688         u8         np_ecn_marked_roce_packets_low[0x20];
5689
5690         u8         np_cnp_sent_high[0x20];
5691
5692         u8         np_cnp_sent_low[0x20];
5693
5694         u8         reserved_at_320[0x560];
5695 };
5696
5697 struct mlx5_ifc_query_cong_statistics_in_bits {
5698         u8         opcode[0x10];
5699         u8         reserved_at_10[0x10];
5700
5701         u8         reserved_at_20[0x10];
5702         u8         op_mod[0x10];
5703
5704         u8         clear[0x1];
5705         u8         reserved_at_41[0x1f];
5706
5707         u8         reserved_at_60[0x20];
5708 };
5709
5710 struct mlx5_ifc_query_cong_params_out_bits {
5711         u8         status[0x8];
5712         u8         reserved_at_8[0x18];
5713
5714         u8         syndrome[0x20];
5715
5716         u8         reserved_at_40[0x40];
5717
5718         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5719 };
5720
5721 struct mlx5_ifc_query_cong_params_in_bits {
5722         u8         opcode[0x10];
5723         u8         reserved_at_10[0x10];
5724
5725         u8         reserved_at_20[0x10];
5726         u8         op_mod[0x10];
5727
5728         u8         reserved_at_40[0x1c];
5729         u8         cong_protocol[0x4];
5730
5731         u8         reserved_at_60[0x20];
5732 };
5733
5734 struct mlx5_ifc_query_adapter_out_bits {
5735         u8         status[0x8];
5736         u8         reserved_at_8[0x18];
5737
5738         u8         syndrome[0x20];
5739
5740         u8         reserved_at_40[0x40];
5741
5742         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5743 };
5744
5745 struct mlx5_ifc_query_adapter_in_bits {
5746         u8         opcode[0x10];
5747         u8         reserved_at_10[0x10];
5748
5749         u8         reserved_at_20[0x10];
5750         u8         op_mod[0x10];
5751
5752         u8         reserved_at_40[0x40];
5753 };
5754
5755 struct mlx5_ifc_qp_2rst_out_bits {
5756         u8         status[0x8];
5757         u8         reserved_at_8[0x18];
5758
5759         u8         syndrome[0x20];
5760
5761         u8         reserved_at_40[0x40];
5762 };
5763
5764 struct mlx5_ifc_qp_2rst_in_bits {
5765         u8         opcode[0x10];
5766         u8         uid[0x10];
5767
5768         u8         reserved_at_20[0x10];
5769         u8         op_mod[0x10];
5770
5771         u8         reserved_at_40[0x8];
5772         u8         qpn[0x18];
5773
5774         u8         reserved_at_60[0x20];
5775 };
5776
5777 struct mlx5_ifc_qp_2err_out_bits {
5778         u8         status[0x8];
5779         u8         reserved_at_8[0x18];
5780
5781         u8         syndrome[0x20];
5782
5783         u8         reserved_at_40[0x40];
5784 };
5785
5786 struct mlx5_ifc_qp_2err_in_bits {
5787         u8         opcode[0x10];
5788         u8         uid[0x10];
5789
5790         u8         reserved_at_20[0x10];
5791         u8         op_mod[0x10];
5792
5793         u8         reserved_at_40[0x8];
5794         u8         qpn[0x18];
5795
5796         u8         reserved_at_60[0x20];
5797 };
5798
5799 struct mlx5_ifc_page_fault_resume_out_bits {
5800         u8         status[0x8];
5801         u8         reserved_at_8[0x18];
5802
5803         u8         syndrome[0x20];
5804
5805         u8         reserved_at_40[0x40];
5806 };
5807
5808 struct mlx5_ifc_page_fault_resume_in_bits {
5809         u8         opcode[0x10];
5810         u8         reserved_at_10[0x10];
5811
5812         u8         reserved_at_20[0x10];
5813         u8         op_mod[0x10];
5814
5815         u8         error[0x1];
5816         u8         reserved_at_41[0x4];
5817         u8         page_fault_type[0x3];
5818         u8         wq_number[0x18];
5819
5820         u8         reserved_at_60[0x8];
5821         u8         token[0x18];
5822 };
5823
5824 struct mlx5_ifc_nop_out_bits {
5825         u8         status[0x8];
5826         u8         reserved_at_8[0x18];
5827
5828         u8         syndrome[0x20];
5829
5830         u8         reserved_at_40[0x40];
5831 };
5832
5833 struct mlx5_ifc_nop_in_bits {
5834         u8         opcode[0x10];
5835         u8         reserved_at_10[0x10];
5836
5837         u8         reserved_at_20[0x10];
5838         u8         op_mod[0x10];
5839
5840         u8         reserved_at_40[0x40];
5841 };
5842
5843 struct mlx5_ifc_modify_vport_state_out_bits {
5844         u8         status[0x8];
5845         u8         reserved_at_8[0x18];
5846
5847         u8         syndrome[0x20];
5848
5849         u8         reserved_at_40[0x40];
5850 };
5851
5852 struct mlx5_ifc_modify_vport_state_in_bits {
5853         u8         opcode[0x10];
5854         u8         reserved_at_10[0x10];
5855
5856         u8         reserved_at_20[0x10];
5857         u8         op_mod[0x10];
5858
5859         u8         other_vport[0x1];
5860         u8         reserved_at_41[0xf];
5861         u8         vport_number[0x10];
5862
5863         u8         reserved_at_60[0x18];
5864         u8         admin_state[0x4];
5865         u8         reserved_at_7c[0x4];
5866 };
5867
5868 struct mlx5_ifc_modify_tis_out_bits {
5869         u8         status[0x8];
5870         u8         reserved_at_8[0x18];
5871
5872         u8         syndrome[0x20];
5873
5874         u8         reserved_at_40[0x40];
5875 };
5876
5877 struct mlx5_ifc_modify_tis_bitmask_bits {
5878         u8         reserved_at_0[0x20];
5879
5880         u8         reserved_at_20[0x1d];
5881         u8         lag_tx_port_affinity[0x1];
5882         u8         strict_lag_tx_port_affinity[0x1];
5883         u8         prio[0x1];
5884 };
5885
5886 struct mlx5_ifc_modify_tis_in_bits {
5887         u8         opcode[0x10];
5888         u8         uid[0x10];
5889
5890         u8         reserved_at_20[0x10];
5891         u8         op_mod[0x10];
5892
5893         u8         reserved_at_40[0x8];
5894         u8         tisn[0x18];
5895
5896         u8         reserved_at_60[0x20];
5897
5898         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5899
5900         u8         reserved_at_c0[0x40];
5901
5902         struct mlx5_ifc_tisc_bits ctx;
5903 };
5904
5905 struct mlx5_ifc_modify_tir_bitmask_bits {
5906         u8         reserved_at_0[0x20];
5907
5908         u8         reserved_at_20[0x1b];
5909         u8         self_lb_en[0x1];
5910         u8         reserved_at_3c[0x1];
5911         u8         hash[0x1];
5912         u8         reserved_at_3e[0x1];
5913         u8         lro[0x1];
5914 };
5915
5916 struct mlx5_ifc_modify_tir_out_bits {
5917         u8         status[0x8];
5918         u8         reserved_at_8[0x18];
5919
5920         u8         syndrome[0x20];
5921
5922         u8         reserved_at_40[0x40];
5923 };
5924
5925 struct mlx5_ifc_modify_tir_in_bits {
5926         u8         opcode[0x10];
5927         u8         uid[0x10];
5928
5929         u8         reserved_at_20[0x10];
5930         u8         op_mod[0x10];
5931
5932         u8         reserved_at_40[0x8];
5933         u8         tirn[0x18];
5934
5935         u8         reserved_at_60[0x20];
5936
5937         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5938
5939         u8         reserved_at_c0[0x40];
5940
5941         struct mlx5_ifc_tirc_bits ctx;
5942 };
5943
5944 struct mlx5_ifc_modify_sq_out_bits {
5945         u8         status[0x8];
5946         u8         reserved_at_8[0x18];
5947
5948         u8         syndrome[0x20];
5949
5950         u8         reserved_at_40[0x40];
5951 };
5952
5953 struct mlx5_ifc_modify_sq_in_bits {
5954         u8         opcode[0x10];
5955         u8         uid[0x10];
5956
5957         u8         reserved_at_20[0x10];
5958         u8         op_mod[0x10];
5959
5960         u8         sq_state[0x4];
5961         u8         reserved_at_44[0x4];
5962         u8         sqn[0x18];
5963
5964         u8         reserved_at_60[0x20];
5965
5966         u8         modify_bitmask[0x40];
5967
5968         u8         reserved_at_c0[0x40];
5969
5970         struct mlx5_ifc_sqc_bits ctx;
5971 };
5972
5973 struct mlx5_ifc_modify_scheduling_element_out_bits {
5974         u8         status[0x8];
5975         u8         reserved_at_8[0x18];
5976
5977         u8         syndrome[0x20];
5978
5979         u8         reserved_at_40[0x1c0];
5980 };
5981
5982 enum {
5983         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5984         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5985 };
5986
5987 struct mlx5_ifc_modify_scheduling_element_in_bits {
5988         u8         opcode[0x10];
5989         u8         reserved_at_10[0x10];
5990
5991         u8         reserved_at_20[0x10];
5992         u8         op_mod[0x10];
5993
5994         u8         scheduling_hierarchy[0x8];
5995         u8         reserved_at_48[0x18];
5996
5997         u8         scheduling_element_id[0x20];
5998
5999         u8         reserved_at_80[0x20];
6000
6001         u8         modify_bitmask[0x20];
6002
6003         u8         reserved_at_c0[0x40];
6004
6005         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6006
6007         u8         reserved_at_300[0x100];
6008 };
6009
6010 struct mlx5_ifc_modify_rqt_out_bits {
6011         u8         status[0x8];
6012         u8         reserved_at_8[0x18];
6013
6014         u8         syndrome[0x20];
6015
6016         u8         reserved_at_40[0x40];
6017 };
6018
6019 struct mlx5_ifc_rqt_bitmask_bits {
6020         u8         reserved_at_0[0x20];
6021
6022         u8         reserved_at_20[0x1f];
6023         u8         rqn_list[0x1];
6024 };
6025
6026 struct mlx5_ifc_modify_rqt_in_bits {
6027         u8         opcode[0x10];
6028         u8         uid[0x10];
6029
6030         u8         reserved_at_20[0x10];
6031         u8         op_mod[0x10];
6032
6033         u8         reserved_at_40[0x8];
6034         u8         rqtn[0x18];
6035
6036         u8         reserved_at_60[0x20];
6037
6038         struct mlx5_ifc_rqt_bitmask_bits bitmask;
6039
6040         u8         reserved_at_c0[0x40];
6041
6042         struct mlx5_ifc_rqtc_bits ctx;
6043 };
6044
6045 struct mlx5_ifc_modify_rq_out_bits {
6046         u8         status[0x8];
6047         u8         reserved_at_8[0x18];
6048
6049         u8         syndrome[0x20];
6050
6051         u8         reserved_at_40[0x40];
6052 };
6053
6054 enum {
6055         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6056         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
6057         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
6058 };
6059
6060 struct mlx5_ifc_modify_rq_in_bits {
6061         u8         opcode[0x10];
6062         u8         uid[0x10];
6063
6064         u8         reserved_at_20[0x10];
6065         u8         op_mod[0x10];
6066
6067         u8         rq_state[0x4];
6068         u8         reserved_at_44[0x4];
6069         u8         rqn[0x18];
6070
6071         u8         reserved_at_60[0x20];
6072
6073         u8         modify_bitmask[0x40];
6074
6075         u8         reserved_at_c0[0x40];
6076
6077         struct mlx5_ifc_rqc_bits ctx;
6078 };
6079
6080 struct mlx5_ifc_modify_rmp_out_bits {
6081         u8         status[0x8];
6082         u8         reserved_at_8[0x18];
6083
6084         u8         syndrome[0x20];
6085
6086         u8         reserved_at_40[0x40];
6087 };
6088
6089 struct mlx5_ifc_rmp_bitmask_bits {
6090         u8         reserved_at_0[0x20];
6091
6092         u8         reserved_at_20[0x1f];
6093         u8         lwm[0x1];
6094 };
6095
6096 struct mlx5_ifc_modify_rmp_in_bits {
6097         u8         opcode[0x10];
6098         u8         uid[0x10];
6099
6100         u8         reserved_at_20[0x10];
6101         u8         op_mod[0x10];
6102
6103         u8         rmp_state[0x4];
6104         u8         reserved_at_44[0x4];
6105         u8         rmpn[0x18];
6106
6107         u8         reserved_at_60[0x20];
6108
6109         struct mlx5_ifc_rmp_bitmask_bits bitmask;
6110
6111         u8         reserved_at_c0[0x40];
6112
6113         struct mlx5_ifc_rmpc_bits ctx;
6114 };
6115
6116 struct mlx5_ifc_modify_nic_vport_context_out_bits {
6117         u8         status[0x8];
6118         u8         reserved_at_8[0x18];
6119
6120         u8         syndrome[0x20];
6121
6122         u8         reserved_at_40[0x40];
6123 };
6124
6125 struct mlx5_ifc_modify_nic_vport_field_select_bits {
6126         u8         reserved_at_0[0x12];
6127         u8         affiliation[0x1];
6128         u8         reserved_at_13[0x1];
6129         u8         disable_uc_local_lb[0x1];
6130         u8         disable_mc_local_lb[0x1];
6131         u8         node_guid[0x1];
6132         u8         port_guid[0x1];
6133         u8         min_inline[0x1];
6134         u8         mtu[0x1];
6135         u8         change_event[0x1];
6136         u8         promisc[0x1];
6137         u8         permanent_address[0x1];
6138         u8         addresses_list[0x1];
6139         u8         roce_en[0x1];
6140         u8         reserved_at_1f[0x1];
6141 };
6142
6143 struct mlx5_ifc_modify_nic_vport_context_in_bits {
6144         u8         opcode[0x10];
6145         u8         reserved_at_10[0x10];
6146
6147         u8         reserved_at_20[0x10];
6148         u8         op_mod[0x10];
6149
6150         u8         other_vport[0x1];
6151         u8         reserved_at_41[0xf];
6152         u8         vport_number[0x10];
6153
6154         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6155
6156         u8         reserved_at_80[0x780];
6157
6158         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6159 };
6160
6161 struct mlx5_ifc_modify_hca_vport_context_out_bits {
6162         u8         status[0x8];
6163         u8         reserved_at_8[0x18];
6164
6165         u8         syndrome[0x20];
6166
6167         u8         reserved_at_40[0x40];
6168 };
6169
6170 struct mlx5_ifc_modify_hca_vport_context_in_bits {
6171         u8         opcode[0x10];
6172         u8         reserved_at_10[0x10];
6173
6174         u8         reserved_at_20[0x10];
6175         u8         op_mod[0x10];
6176
6177         u8         other_vport[0x1];
6178         u8         reserved_at_41[0xb];
6179         u8         port_num[0x4];
6180         u8         vport_number[0x10];
6181
6182         u8         reserved_at_60[0x20];
6183
6184         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6185 };
6186
6187 struct mlx5_ifc_modify_cq_out_bits {
6188         u8         status[0x8];
6189         u8         reserved_at_8[0x18];
6190
6191         u8         syndrome[0x20];
6192
6193         u8         reserved_at_40[0x40];
6194 };
6195
6196 enum {
6197         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
6198         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
6199 };
6200
6201 struct mlx5_ifc_modify_cq_in_bits {
6202         u8         opcode[0x10];
6203         u8         uid[0x10];
6204
6205         u8         reserved_at_20[0x10];
6206         u8         op_mod[0x10];
6207
6208         u8         reserved_at_40[0x8];
6209         u8         cqn[0x18];
6210
6211         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6212
6213         struct mlx5_ifc_cqc_bits cq_context;
6214
6215         u8         reserved_at_280[0x60];
6216
6217         u8         cq_umem_valid[0x1];
6218         u8         reserved_at_2e1[0x1f];
6219
6220         u8         reserved_at_300[0x580];
6221
6222         u8         pas[0][0x40];
6223 };
6224
6225 struct mlx5_ifc_modify_cong_status_out_bits {
6226         u8         status[0x8];
6227         u8         reserved_at_8[0x18];
6228
6229         u8         syndrome[0x20];
6230
6231         u8         reserved_at_40[0x40];
6232 };
6233
6234 struct mlx5_ifc_modify_cong_status_in_bits {
6235         u8         opcode[0x10];
6236         u8         reserved_at_10[0x10];
6237
6238         u8         reserved_at_20[0x10];
6239         u8         op_mod[0x10];
6240
6241         u8         reserved_at_40[0x18];
6242         u8         priority[0x4];
6243         u8         cong_protocol[0x4];
6244
6245         u8         enable[0x1];
6246         u8         tag_enable[0x1];
6247         u8         reserved_at_62[0x1e];
6248 };
6249
6250 struct mlx5_ifc_modify_cong_params_out_bits {
6251         u8         status[0x8];
6252         u8         reserved_at_8[0x18];
6253
6254         u8         syndrome[0x20];
6255
6256         u8         reserved_at_40[0x40];
6257 };
6258
6259 struct mlx5_ifc_modify_cong_params_in_bits {
6260         u8         opcode[0x10];
6261         u8         reserved_at_10[0x10];
6262
6263         u8         reserved_at_20[0x10];
6264         u8         op_mod[0x10];
6265
6266         u8         reserved_at_40[0x1c];
6267         u8         cong_protocol[0x4];
6268
6269         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6270
6271         u8         reserved_at_80[0x80];
6272
6273         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6274 };
6275
6276 struct mlx5_ifc_manage_pages_out_bits {
6277         u8         status[0x8];
6278         u8         reserved_at_8[0x18];
6279
6280         u8         syndrome[0x20];
6281
6282         u8         output_num_entries[0x20];
6283
6284         u8         reserved_at_60[0x20];
6285
6286         u8         pas[0][0x40];
6287 };
6288
6289 enum {
6290         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
6291         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
6292         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
6293 };
6294
6295 struct mlx5_ifc_manage_pages_in_bits {
6296         u8         opcode[0x10];
6297         u8         reserved_at_10[0x10];
6298
6299         u8         reserved_at_20[0x10];
6300         u8         op_mod[0x10];
6301
6302         u8         embedded_cpu_function[0x1];
6303         u8         reserved_at_41[0xf];
6304         u8         function_id[0x10];
6305
6306         u8         input_num_entries[0x20];
6307
6308         u8         pas[0][0x40];
6309 };
6310
6311 struct mlx5_ifc_mad_ifc_out_bits {
6312         u8         status[0x8];
6313         u8         reserved_at_8[0x18];
6314
6315         u8         syndrome[0x20];
6316
6317         u8         reserved_at_40[0x40];
6318
6319         u8         response_mad_packet[256][0x8];
6320 };
6321
6322 struct mlx5_ifc_mad_ifc_in_bits {
6323         u8         opcode[0x10];
6324         u8         reserved_at_10[0x10];
6325
6326         u8         reserved_at_20[0x10];
6327         u8         op_mod[0x10];
6328
6329         u8         remote_lid[0x10];
6330         u8         reserved_at_50[0x8];
6331         u8         port[0x8];
6332
6333         u8         reserved_at_60[0x20];
6334
6335         u8         mad[256][0x8];
6336 };
6337
6338 struct mlx5_ifc_init_hca_out_bits {
6339         u8         status[0x8];
6340         u8         reserved_at_8[0x18];
6341
6342         u8         syndrome[0x20];
6343
6344         u8         reserved_at_40[0x40];
6345 };
6346
6347 struct mlx5_ifc_init_hca_in_bits {
6348         u8         opcode[0x10];
6349         u8         reserved_at_10[0x10];
6350
6351         u8         reserved_at_20[0x10];
6352         u8         op_mod[0x10];
6353
6354         u8         reserved_at_40[0x40];
6355         u8         sw_owner_id[4][0x20];
6356 };
6357
6358 struct mlx5_ifc_init2rtr_qp_out_bits {
6359         u8         status[0x8];
6360         u8         reserved_at_8[0x18];
6361
6362         u8         syndrome[0x20];
6363
6364         u8         reserved_at_40[0x40];
6365 };
6366
6367 struct mlx5_ifc_init2rtr_qp_in_bits {
6368         u8         opcode[0x10];
6369         u8         uid[0x10];
6370
6371         u8         reserved_at_20[0x10];
6372         u8         op_mod[0x10];
6373
6374         u8         reserved_at_40[0x8];
6375         u8         qpn[0x18];
6376
6377         u8         reserved_at_60[0x20];
6378
6379         u8         opt_param_mask[0x20];
6380
6381         u8         reserved_at_a0[0x20];
6382
6383         struct mlx5_ifc_qpc_bits qpc;
6384
6385         u8         reserved_at_800[0x80];
6386 };
6387
6388 struct mlx5_ifc_init2init_qp_out_bits {
6389         u8         status[0x8];
6390         u8         reserved_at_8[0x18];
6391
6392         u8         syndrome[0x20];
6393
6394         u8         reserved_at_40[0x40];
6395 };
6396
6397 struct mlx5_ifc_init2init_qp_in_bits {
6398         u8         opcode[0x10];
6399         u8         uid[0x10];
6400
6401         u8         reserved_at_20[0x10];
6402         u8         op_mod[0x10];
6403
6404         u8         reserved_at_40[0x8];
6405         u8         qpn[0x18];
6406
6407         u8         reserved_at_60[0x20];
6408
6409         u8         opt_param_mask[0x20];
6410
6411         u8         reserved_at_a0[0x20];
6412
6413         struct mlx5_ifc_qpc_bits qpc;
6414
6415         u8         reserved_at_800[0x80];
6416 };
6417
6418 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6419         u8         status[0x8];
6420         u8         reserved_at_8[0x18];
6421
6422         u8         syndrome[0x20];
6423
6424         u8         reserved_at_40[0x40];
6425
6426         u8         packet_headers_log[128][0x8];
6427
6428         u8         packet_syndrome[64][0x8];
6429 };
6430
6431 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6432         u8         opcode[0x10];
6433         u8         reserved_at_10[0x10];
6434
6435         u8         reserved_at_20[0x10];
6436         u8         op_mod[0x10];
6437
6438         u8         reserved_at_40[0x40];
6439 };
6440
6441 struct mlx5_ifc_gen_eqe_in_bits {
6442         u8         opcode[0x10];
6443         u8         reserved_at_10[0x10];
6444
6445         u8         reserved_at_20[0x10];
6446         u8         op_mod[0x10];
6447
6448         u8         reserved_at_40[0x18];
6449         u8         eq_number[0x8];
6450
6451         u8         reserved_at_60[0x20];
6452
6453         u8         eqe[64][0x8];
6454 };
6455
6456 struct mlx5_ifc_gen_eq_out_bits {
6457         u8         status[0x8];
6458         u8         reserved_at_8[0x18];
6459
6460         u8         syndrome[0x20];
6461
6462         u8         reserved_at_40[0x40];
6463 };
6464
6465 struct mlx5_ifc_enable_hca_out_bits {
6466         u8         status[0x8];
6467         u8         reserved_at_8[0x18];
6468
6469         u8         syndrome[0x20];
6470
6471         u8         reserved_at_40[0x20];
6472 };
6473
6474 struct mlx5_ifc_enable_hca_in_bits {
6475         u8         opcode[0x10];
6476         u8         reserved_at_10[0x10];
6477
6478         u8         reserved_at_20[0x10];
6479         u8         op_mod[0x10];
6480
6481         u8         embedded_cpu_function[0x1];
6482         u8         reserved_at_41[0xf];
6483         u8         function_id[0x10];
6484
6485         u8         reserved_at_60[0x20];
6486 };
6487
6488 struct mlx5_ifc_drain_dct_out_bits {
6489         u8         status[0x8];
6490         u8         reserved_at_8[0x18];
6491
6492         u8         syndrome[0x20];
6493
6494         u8         reserved_at_40[0x40];
6495 };
6496
6497 struct mlx5_ifc_drain_dct_in_bits {
6498         u8         opcode[0x10];
6499         u8         uid[0x10];
6500
6501         u8         reserved_at_20[0x10];
6502         u8         op_mod[0x10];
6503
6504         u8         reserved_at_40[0x8];
6505         u8         dctn[0x18];
6506
6507         u8         reserved_at_60[0x20];
6508 };
6509
6510 struct mlx5_ifc_disable_hca_out_bits {
6511         u8         status[0x8];
6512         u8         reserved_at_8[0x18];
6513
6514         u8         syndrome[0x20];
6515
6516         u8         reserved_at_40[0x20];
6517 };
6518
6519 struct mlx5_ifc_disable_hca_in_bits {
6520         u8         opcode[0x10];
6521         u8         reserved_at_10[0x10];
6522
6523         u8         reserved_at_20[0x10];
6524         u8         op_mod[0x10];
6525
6526         u8         embedded_cpu_function[0x1];
6527         u8         reserved_at_41[0xf];
6528         u8         function_id[0x10];
6529
6530         u8         reserved_at_60[0x20];
6531 };
6532
6533 struct mlx5_ifc_detach_from_mcg_out_bits {
6534         u8         status[0x8];
6535         u8         reserved_at_8[0x18];
6536
6537         u8         syndrome[0x20];
6538
6539         u8         reserved_at_40[0x40];
6540 };
6541
6542 struct mlx5_ifc_detach_from_mcg_in_bits {
6543         u8         opcode[0x10];
6544         u8         uid[0x10];
6545
6546         u8         reserved_at_20[0x10];
6547         u8         op_mod[0x10];
6548
6549         u8         reserved_at_40[0x8];
6550         u8         qpn[0x18];
6551
6552         u8         reserved_at_60[0x20];
6553
6554         u8         multicast_gid[16][0x8];
6555 };
6556
6557 struct mlx5_ifc_destroy_xrq_out_bits {
6558         u8         status[0x8];
6559         u8         reserved_at_8[0x18];
6560
6561         u8         syndrome[0x20];
6562
6563         u8         reserved_at_40[0x40];
6564 };
6565
6566 struct mlx5_ifc_destroy_xrq_in_bits {
6567         u8         opcode[0x10];
6568         u8         uid[0x10];
6569
6570         u8         reserved_at_20[0x10];
6571         u8         op_mod[0x10];
6572
6573         u8         reserved_at_40[0x8];
6574         u8         xrqn[0x18];
6575
6576         u8         reserved_at_60[0x20];
6577 };
6578
6579 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6580         u8         status[0x8];
6581         u8         reserved_at_8[0x18];
6582
6583         u8         syndrome[0x20];
6584
6585         u8         reserved_at_40[0x40];
6586 };
6587
6588 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6589         u8         opcode[0x10];
6590         u8         uid[0x10];
6591
6592         u8         reserved_at_20[0x10];
6593         u8         op_mod[0x10];
6594
6595         u8         reserved_at_40[0x8];
6596         u8         xrc_srqn[0x18];
6597
6598         u8         reserved_at_60[0x20];
6599 };
6600
6601 struct mlx5_ifc_destroy_tis_out_bits {
6602         u8         status[0x8];
6603         u8         reserved_at_8[0x18];
6604
6605         u8         syndrome[0x20];
6606
6607         u8         reserved_at_40[0x40];
6608 };
6609
6610 struct mlx5_ifc_destroy_tis_in_bits {
6611         u8         opcode[0x10];
6612         u8         uid[0x10];
6613
6614         u8         reserved_at_20[0x10];
6615         u8         op_mod[0x10];
6616
6617         u8         reserved_at_40[0x8];
6618         u8         tisn[0x18];
6619
6620         u8         reserved_at_60[0x20];
6621 };
6622
6623 struct mlx5_ifc_destroy_tir_out_bits {
6624         u8         status[0x8];
6625         u8         reserved_at_8[0x18];
6626
6627         u8         syndrome[0x20];
6628
6629         u8         reserved_at_40[0x40];
6630 };
6631
6632 struct mlx5_ifc_destroy_tir_in_bits {
6633         u8         opcode[0x10];
6634         u8         uid[0x10];
6635
6636         u8         reserved_at_20[0x10];
6637         u8         op_mod[0x10];
6638
6639         u8         reserved_at_40[0x8];
6640         u8         tirn[0x18];
6641
6642         u8         reserved_at_60[0x20];
6643 };
6644
6645 struct mlx5_ifc_destroy_srq_out_bits {
6646         u8         status[0x8];
6647         u8         reserved_at_8[0x18];
6648
6649         u8         syndrome[0x20];
6650
6651         u8         reserved_at_40[0x40];
6652 };
6653
6654 struct mlx5_ifc_destroy_srq_in_bits {
6655         u8         opcode[0x10];
6656         u8         uid[0x10];
6657
6658         u8         reserved_at_20[0x10];
6659         u8         op_mod[0x10];
6660
6661         u8         reserved_at_40[0x8];
6662         u8         srqn[0x18];
6663
6664         u8         reserved_at_60[0x20];
6665 };
6666
6667 struct mlx5_ifc_destroy_sq_out_bits {
6668         u8         status[0x8];
6669         u8         reserved_at_8[0x18];
6670
6671         u8         syndrome[0x20];
6672
6673         u8         reserved_at_40[0x40];
6674 };
6675
6676 struct mlx5_ifc_destroy_sq_in_bits {
6677         u8         opcode[0x10];
6678         u8         uid[0x10];
6679
6680         u8         reserved_at_20[0x10];
6681         u8         op_mod[0x10];
6682
6683         u8         reserved_at_40[0x8];
6684         u8         sqn[0x18];
6685
6686         u8         reserved_at_60[0x20];
6687 };
6688
6689 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6690         u8         status[0x8];
6691         u8         reserved_at_8[0x18];
6692
6693         u8         syndrome[0x20];
6694
6695         u8         reserved_at_40[0x1c0];
6696 };
6697
6698 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6699         u8         opcode[0x10];
6700         u8         reserved_at_10[0x10];
6701
6702         u8         reserved_at_20[0x10];
6703         u8         op_mod[0x10];
6704
6705         u8         scheduling_hierarchy[0x8];
6706         u8         reserved_at_48[0x18];
6707
6708         u8         scheduling_element_id[0x20];
6709
6710         u8         reserved_at_80[0x180];
6711 };
6712
6713 struct mlx5_ifc_destroy_rqt_out_bits {
6714         u8         status[0x8];
6715         u8         reserved_at_8[0x18];
6716
6717         u8         syndrome[0x20];
6718
6719         u8         reserved_at_40[0x40];
6720 };
6721
6722 struct mlx5_ifc_destroy_rqt_in_bits {
6723         u8         opcode[0x10];
6724         u8         uid[0x10];
6725
6726         u8         reserved_at_20[0x10];
6727         u8         op_mod[0x10];
6728
6729         u8         reserved_at_40[0x8];
6730         u8         rqtn[0x18];
6731
6732         u8         reserved_at_60[0x20];
6733 };
6734
6735 struct mlx5_ifc_destroy_rq_out_bits {
6736         u8         status[0x8];
6737         u8         reserved_at_8[0x18];
6738
6739         u8         syndrome[0x20];
6740
6741         u8         reserved_at_40[0x40];
6742 };
6743
6744 struct mlx5_ifc_destroy_rq_in_bits {
6745         u8         opcode[0x10];
6746         u8         uid[0x10];
6747
6748         u8         reserved_at_20[0x10];
6749         u8         op_mod[0x10];
6750
6751         u8         reserved_at_40[0x8];
6752         u8         rqn[0x18];
6753
6754         u8         reserved_at_60[0x20];
6755 };
6756
6757 struct mlx5_ifc_set_delay_drop_params_in_bits {
6758         u8         opcode[0x10];
6759         u8         reserved_at_10[0x10];
6760
6761         u8         reserved_at_20[0x10];
6762         u8         op_mod[0x10];
6763
6764         u8         reserved_at_40[0x20];
6765
6766         u8         reserved_at_60[0x10];
6767         u8         delay_drop_timeout[0x10];
6768 };
6769
6770 struct mlx5_ifc_set_delay_drop_params_out_bits {
6771         u8         status[0x8];
6772         u8         reserved_at_8[0x18];
6773
6774         u8         syndrome[0x20];
6775
6776         u8         reserved_at_40[0x40];
6777 };
6778
6779 struct mlx5_ifc_destroy_rmp_out_bits {
6780         u8         status[0x8];
6781         u8         reserved_at_8[0x18];
6782
6783         u8         syndrome[0x20];
6784
6785         u8         reserved_at_40[0x40];
6786 };
6787
6788 struct mlx5_ifc_destroy_rmp_in_bits {
6789         u8         opcode[0x10];
6790         u8         uid[0x10];
6791
6792         u8         reserved_at_20[0x10];
6793         u8         op_mod[0x10];
6794
6795         u8         reserved_at_40[0x8];
6796         u8         rmpn[0x18];
6797
6798         u8         reserved_at_60[0x20];
6799 };
6800
6801 struct mlx5_ifc_destroy_qp_out_bits {
6802         u8         status[0x8];
6803         u8         reserved_at_8[0x18];
6804
6805         u8         syndrome[0x20];
6806
6807         u8         reserved_at_40[0x40];
6808 };
6809
6810 struct mlx5_ifc_destroy_qp_in_bits {
6811         u8         opcode[0x10];
6812         u8         uid[0x10];
6813
6814         u8         reserved_at_20[0x10];
6815         u8         op_mod[0x10];
6816
6817         u8         reserved_at_40[0x8];
6818         u8         qpn[0x18];
6819
6820         u8         reserved_at_60[0x20];
6821 };
6822
6823 struct mlx5_ifc_destroy_psv_out_bits {
6824         u8         status[0x8];
6825         u8         reserved_at_8[0x18];
6826
6827         u8         syndrome[0x20];
6828
6829         u8         reserved_at_40[0x40];
6830 };
6831
6832 struct mlx5_ifc_destroy_psv_in_bits {
6833         u8         opcode[0x10];
6834         u8         reserved_at_10[0x10];
6835
6836         u8         reserved_at_20[0x10];
6837         u8         op_mod[0x10];
6838
6839         u8         reserved_at_40[0x8];
6840         u8         psvn[0x18];
6841
6842         u8         reserved_at_60[0x20];
6843 };
6844
6845 struct mlx5_ifc_destroy_mkey_out_bits {
6846         u8         status[0x8];
6847         u8         reserved_at_8[0x18];
6848
6849         u8         syndrome[0x20];
6850
6851         u8         reserved_at_40[0x40];
6852 };
6853
6854 struct mlx5_ifc_destroy_mkey_in_bits {
6855         u8         opcode[0x10];
6856         u8         reserved_at_10[0x10];
6857
6858         u8         reserved_at_20[0x10];
6859         u8         op_mod[0x10];
6860
6861         u8         reserved_at_40[0x8];
6862         u8         mkey_index[0x18];
6863
6864         u8         reserved_at_60[0x20];
6865 };
6866
6867 struct mlx5_ifc_destroy_flow_table_out_bits {
6868         u8         status[0x8];
6869         u8         reserved_at_8[0x18];
6870
6871         u8         syndrome[0x20];
6872
6873         u8         reserved_at_40[0x40];
6874 };
6875
6876 struct mlx5_ifc_destroy_flow_table_in_bits {
6877         u8         opcode[0x10];
6878         u8         reserved_at_10[0x10];
6879
6880         u8         reserved_at_20[0x10];
6881         u8         op_mod[0x10];
6882
6883         u8         other_vport[0x1];
6884         u8         reserved_at_41[0xf];
6885         u8         vport_number[0x10];
6886
6887         u8         reserved_at_60[0x20];
6888
6889         u8         table_type[0x8];
6890         u8         reserved_at_88[0x18];
6891
6892         u8         reserved_at_a0[0x8];
6893         u8         table_id[0x18];
6894
6895         u8         reserved_at_c0[0x140];
6896 };
6897
6898 struct mlx5_ifc_destroy_flow_group_out_bits {
6899         u8         status[0x8];
6900         u8         reserved_at_8[0x18];
6901
6902         u8         syndrome[0x20];
6903
6904         u8         reserved_at_40[0x40];
6905 };
6906
6907 struct mlx5_ifc_destroy_flow_group_in_bits {
6908         u8         opcode[0x10];
6909         u8         reserved_at_10[0x10];
6910
6911         u8         reserved_at_20[0x10];
6912         u8         op_mod[0x10];
6913
6914         u8         other_vport[0x1];
6915         u8         reserved_at_41[0xf];
6916         u8         vport_number[0x10];
6917
6918         u8         reserved_at_60[0x20];
6919
6920         u8         table_type[0x8];
6921         u8         reserved_at_88[0x18];
6922
6923         u8         reserved_at_a0[0x8];
6924         u8         table_id[0x18];
6925
6926         u8         group_id[0x20];
6927
6928         u8         reserved_at_e0[0x120];
6929 };
6930
6931 struct mlx5_ifc_destroy_eq_out_bits {
6932         u8         status[0x8];
6933         u8         reserved_at_8[0x18];
6934
6935         u8         syndrome[0x20];
6936
6937         u8         reserved_at_40[0x40];
6938 };
6939
6940 struct mlx5_ifc_destroy_eq_in_bits {
6941         u8         opcode[0x10];
6942         u8         reserved_at_10[0x10];
6943
6944         u8         reserved_at_20[0x10];
6945         u8         op_mod[0x10];
6946
6947         u8         reserved_at_40[0x18];
6948         u8         eq_number[0x8];
6949
6950         u8         reserved_at_60[0x20];
6951 };
6952
6953 struct mlx5_ifc_destroy_dct_out_bits {
6954         u8         status[0x8];
6955         u8         reserved_at_8[0x18];
6956
6957         u8         syndrome[0x20];
6958
6959         u8         reserved_at_40[0x40];
6960 };
6961
6962 struct mlx5_ifc_destroy_dct_in_bits {
6963         u8         opcode[0x10];
6964         u8         uid[0x10];
6965
6966         u8         reserved_at_20[0x10];
6967         u8         op_mod[0x10];
6968
6969         u8         reserved_at_40[0x8];
6970         u8         dctn[0x18];
6971
6972         u8         reserved_at_60[0x20];
6973 };
6974
6975 struct mlx5_ifc_destroy_cq_out_bits {
6976         u8         status[0x8];
6977         u8         reserved_at_8[0x18];
6978
6979         u8         syndrome[0x20];
6980
6981         u8         reserved_at_40[0x40];
6982 };
6983
6984 struct mlx5_ifc_destroy_cq_in_bits {
6985         u8         opcode[0x10];
6986         u8         uid[0x10];
6987
6988         u8         reserved_at_20[0x10];
6989         u8         op_mod[0x10];
6990
6991         u8         reserved_at_40[0x8];
6992         u8         cqn[0x18];
6993
6994         u8         reserved_at_60[0x20];
6995 };
6996
6997 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6998         u8         status[0x8];
6999         u8         reserved_at_8[0x18];
7000
7001         u8         syndrome[0x20];
7002
7003         u8         reserved_at_40[0x40];
7004 };
7005
7006 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7007         u8         opcode[0x10];
7008         u8         reserved_at_10[0x10];
7009
7010         u8         reserved_at_20[0x10];
7011         u8         op_mod[0x10];
7012
7013         u8         reserved_at_40[0x20];
7014
7015         u8         reserved_at_60[0x10];
7016         u8         vxlan_udp_port[0x10];
7017 };
7018
7019 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7020         u8         status[0x8];
7021         u8         reserved_at_8[0x18];
7022
7023         u8         syndrome[0x20];
7024
7025         u8         reserved_at_40[0x40];
7026 };
7027
7028 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7029         u8         opcode[0x10];
7030         u8         reserved_at_10[0x10];
7031
7032         u8         reserved_at_20[0x10];
7033         u8         op_mod[0x10];
7034
7035         u8         reserved_at_40[0x60];
7036
7037         u8         reserved_at_a0[0x8];
7038         u8         table_index[0x18];
7039
7040         u8         reserved_at_c0[0x140];
7041 };
7042
7043 struct mlx5_ifc_delete_fte_out_bits {
7044         u8         status[0x8];
7045         u8         reserved_at_8[0x18];
7046
7047         u8         syndrome[0x20];
7048
7049         u8         reserved_at_40[0x40];
7050 };
7051
7052 struct mlx5_ifc_delete_fte_in_bits {
7053         u8         opcode[0x10];
7054         u8         reserved_at_10[0x10];
7055
7056         u8         reserved_at_20[0x10];
7057         u8         op_mod[0x10];
7058
7059         u8         other_vport[0x1];
7060         u8         reserved_at_41[0xf];
7061         u8         vport_number[0x10];
7062
7063         u8         reserved_at_60[0x20];
7064
7065         u8         table_type[0x8];
7066         u8         reserved_at_88[0x18];
7067
7068         u8         reserved_at_a0[0x8];
7069         u8         table_id[0x18];
7070
7071         u8         reserved_at_c0[0x40];
7072
7073         u8         flow_index[0x20];
7074
7075         u8         reserved_at_120[0xe0];
7076 };
7077
7078 struct mlx5_ifc_dealloc_xrcd_out_bits {
7079         u8         status[0x8];
7080         u8         reserved_at_8[0x18];
7081
7082         u8         syndrome[0x20];
7083
7084         u8         reserved_at_40[0x40];
7085 };
7086
7087 struct mlx5_ifc_dealloc_xrcd_in_bits {
7088         u8         opcode[0x10];
7089         u8         uid[0x10];
7090
7091         u8         reserved_at_20[0x10];
7092         u8         op_mod[0x10];
7093
7094         u8         reserved_at_40[0x8];
7095         u8         xrcd[0x18];
7096
7097         u8         reserved_at_60[0x20];
7098 };
7099
7100 struct mlx5_ifc_dealloc_uar_out_bits {
7101         u8         status[0x8];
7102         u8         reserved_at_8[0x18];
7103
7104         u8         syndrome[0x20];
7105
7106         u8         reserved_at_40[0x40];
7107 };
7108
7109 struct mlx5_ifc_dealloc_uar_in_bits {
7110         u8         opcode[0x10];
7111         u8         reserved_at_10[0x10];
7112
7113         u8         reserved_at_20[0x10];
7114         u8         op_mod[0x10];
7115
7116         u8         reserved_at_40[0x8];
7117         u8         uar[0x18];
7118
7119         u8         reserved_at_60[0x20];
7120 };
7121
7122 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7123         u8         status[0x8];
7124         u8         reserved_at_8[0x18];
7125
7126         u8         syndrome[0x20];
7127
7128         u8         reserved_at_40[0x40];
7129 };
7130
7131 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7132         u8         opcode[0x10];
7133         u8         uid[0x10];
7134
7135         u8         reserved_at_20[0x10];
7136         u8         op_mod[0x10];
7137
7138         u8         reserved_at_40[0x8];
7139         u8         transport_domain[0x18];
7140
7141         u8         reserved_at_60[0x20];
7142 };
7143
7144 struct mlx5_ifc_dealloc_q_counter_out_bits {
7145         u8         status[0x8];
7146         u8         reserved_at_8[0x18];
7147
7148         u8         syndrome[0x20];
7149
7150         u8         reserved_at_40[0x40];
7151 };
7152
7153 struct mlx5_ifc_dealloc_q_counter_in_bits {
7154         u8         opcode[0x10];
7155         u8         reserved_at_10[0x10];
7156
7157         u8         reserved_at_20[0x10];
7158         u8         op_mod[0x10];
7159
7160         u8         reserved_at_40[0x18];
7161         u8         counter_set_id[0x8];
7162
7163         u8         reserved_at_60[0x20];
7164 };
7165
7166 struct mlx5_ifc_dealloc_pd_out_bits {
7167         u8         status[0x8];
7168         u8         reserved_at_8[0x18];
7169
7170         u8         syndrome[0x20];
7171
7172         u8         reserved_at_40[0x40];
7173 };
7174
7175 struct mlx5_ifc_dealloc_pd_in_bits {
7176         u8         opcode[0x10];
7177         u8         uid[0x10];
7178
7179         u8         reserved_at_20[0x10];
7180         u8         op_mod[0x10];
7181
7182         u8         reserved_at_40[0x8];
7183         u8         pd[0x18];
7184
7185         u8         reserved_at_60[0x20];
7186 };
7187
7188 struct mlx5_ifc_dealloc_flow_counter_out_bits {
7189         u8         status[0x8];
7190         u8         reserved_at_8[0x18];
7191
7192         u8         syndrome[0x20];
7193
7194         u8         reserved_at_40[0x40];
7195 };
7196
7197 struct mlx5_ifc_dealloc_flow_counter_in_bits {
7198         u8         opcode[0x10];
7199         u8         reserved_at_10[0x10];
7200
7201         u8         reserved_at_20[0x10];
7202         u8         op_mod[0x10];
7203
7204         u8         flow_counter_id[0x20];
7205
7206         u8         reserved_at_60[0x20];
7207 };
7208
7209 struct mlx5_ifc_create_xrq_out_bits {
7210         u8         status[0x8];
7211         u8         reserved_at_8[0x18];
7212
7213         u8         syndrome[0x20];
7214
7215         u8         reserved_at_40[0x8];
7216         u8         xrqn[0x18];
7217
7218         u8         reserved_at_60[0x20];
7219 };
7220
7221 struct mlx5_ifc_create_xrq_in_bits {
7222         u8         opcode[0x10];
7223         u8         uid[0x10];
7224
7225         u8         reserved_at_20[0x10];
7226         u8         op_mod[0x10];
7227
7228         u8         reserved_at_40[0x40];
7229
7230         struct mlx5_ifc_xrqc_bits xrq_context;
7231 };
7232
7233 struct mlx5_ifc_create_xrc_srq_out_bits {
7234         u8         status[0x8];
7235         u8         reserved_at_8[0x18];
7236
7237         u8         syndrome[0x20];
7238
7239         u8         reserved_at_40[0x8];
7240         u8         xrc_srqn[0x18];
7241
7242         u8         reserved_at_60[0x20];
7243 };
7244
7245 struct mlx5_ifc_create_xrc_srq_in_bits {
7246         u8         opcode[0x10];
7247         u8         uid[0x10];
7248
7249         u8         reserved_at_20[0x10];
7250         u8         op_mod[0x10];
7251
7252         u8         reserved_at_40[0x40];
7253
7254         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7255
7256         u8         reserved_at_280[0x60];
7257
7258         u8         xrc_srq_umem_valid[0x1];
7259         u8         reserved_at_2e1[0x1f];
7260
7261         u8         reserved_at_300[0x580];
7262
7263         u8         pas[0][0x40];
7264 };
7265
7266 struct mlx5_ifc_create_tis_out_bits {
7267         u8         status[0x8];
7268         u8         reserved_at_8[0x18];
7269
7270         u8         syndrome[0x20];
7271
7272         u8         reserved_at_40[0x8];
7273         u8         tisn[0x18];
7274
7275         u8         reserved_at_60[0x20];
7276 };
7277
7278 struct mlx5_ifc_create_tis_in_bits {
7279         u8         opcode[0x10];
7280         u8         uid[0x10];
7281
7282         u8         reserved_at_20[0x10];
7283         u8         op_mod[0x10];
7284
7285         u8         reserved_at_40[0xc0];
7286
7287         struct mlx5_ifc_tisc_bits ctx;
7288 };
7289
7290 struct mlx5_ifc_create_tir_out_bits {
7291         u8         status[0x8];
7292         u8         icm_address_63_40[0x18];
7293
7294         u8         syndrome[0x20];
7295
7296         u8         icm_address_39_32[0x8];
7297         u8         tirn[0x18];
7298
7299         u8         icm_address_31_0[0x20];
7300 };
7301
7302 struct mlx5_ifc_create_tir_in_bits {
7303         u8         opcode[0x10];
7304         u8         uid[0x10];
7305
7306         u8         reserved_at_20[0x10];
7307         u8         op_mod[0x10];
7308
7309         u8         reserved_at_40[0xc0];
7310
7311         struct mlx5_ifc_tirc_bits ctx;
7312 };
7313
7314 struct mlx5_ifc_create_srq_out_bits {
7315         u8         status[0x8];
7316         u8         reserved_at_8[0x18];
7317
7318         u8         syndrome[0x20];
7319
7320         u8         reserved_at_40[0x8];
7321         u8         srqn[0x18];
7322
7323         u8         reserved_at_60[0x20];
7324 };
7325
7326 struct mlx5_ifc_create_srq_in_bits {
7327         u8         opcode[0x10];
7328         u8         uid[0x10];
7329
7330         u8         reserved_at_20[0x10];
7331         u8         op_mod[0x10];
7332
7333         u8         reserved_at_40[0x40];
7334
7335         struct mlx5_ifc_srqc_bits srq_context_entry;
7336
7337         u8         reserved_at_280[0x600];
7338
7339         u8         pas[0][0x40];
7340 };
7341
7342 struct mlx5_ifc_create_sq_out_bits {
7343         u8         status[0x8];
7344         u8         reserved_at_8[0x18];
7345
7346         u8         syndrome[0x20];
7347
7348         u8         reserved_at_40[0x8];
7349         u8         sqn[0x18];
7350
7351         u8         reserved_at_60[0x20];
7352 };
7353
7354 struct mlx5_ifc_create_sq_in_bits {
7355         u8         opcode[0x10];
7356         u8         uid[0x10];
7357
7358         u8         reserved_at_20[0x10];
7359         u8         op_mod[0x10];
7360
7361         u8         reserved_at_40[0xc0];
7362
7363         struct mlx5_ifc_sqc_bits ctx;
7364 };
7365
7366 struct mlx5_ifc_create_scheduling_element_out_bits {
7367         u8         status[0x8];
7368         u8         reserved_at_8[0x18];
7369
7370         u8         syndrome[0x20];
7371
7372         u8         reserved_at_40[0x40];
7373
7374         u8         scheduling_element_id[0x20];
7375
7376         u8         reserved_at_a0[0x160];
7377 };
7378
7379 struct mlx5_ifc_create_scheduling_element_in_bits {
7380         u8         opcode[0x10];
7381         u8         reserved_at_10[0x10];
7382
7383         u8         reserved_at_20[0x10];
7384         u8         op_mod[0x10];
7385
7386         u8         scheduling_hierarchy[0x8];
7387         u8         reserved_at_48[0x18];
7388
7389         u8         reserved_at_60[0xa0];
7390
7391         struct mlx5_ifc_scheduling_context_bits scheduling_context;
7392
7393         u8         reserved_at_300[0x100];
7394 };
7395
7396 struct mlx5_ifc_create_rqt_out_bits {
7397         u8         status[0x8];
7398         u8         reserved_at_8[0x18];
7399
7400         u8         syndrome[0x20];
7401
7402         u8         reserved_at_40[0x8];
7403         u8         rqtn[0x18];
7404
7405         u8         reserved_at_60[0x20];
7406 };
7407
7408 struct mlx5_ifc_create_rqt_in_bits {
7409         u8         opcode[0x10];
7410         u8         uid[0x10];
7411
7412         u8         reserved_at_20[0x10];
7413         u8         op_mod[0x10];
7414
7415         u8         reserved_at_40[0xc0];
7416
7417         struct mlx5_ifc_rqtc_bits rqt_context;
7418 };
7419
7420 struct mlx5_ifc_create_rq_out_bits {
7421         u8         status[0x8];
7422         u8         reserved_at_8[0x18];
7423
7424         u8         syndrome[0x20];
7425
7426         u8         reserved_at_40[0x8];
7427         u8         rqn[0x18];
7428
7429         u8         reserved_at_60[0x20];
7430 };
7431
7432 struct mlx5_ifc_create_rq_in_bits {
7433         u8         opcode[0x10];
7434         u8         uid[0x10];
7435
7436         u8         reserved_at_20[0x10];
7437         u8         op_mod[0x10];
7438
7439         u8         reserved_at_40[0xc0];
7440
7441         struct mlx5_ifc_rqc_bits ctx;
7442 };
7443
7444 struct mlx5_ifc_create_rmp_out_bits {
7445         u8         status[0x8];
7446         u8         reserved_at_8[0x18];
7447
7448         u8         syndrome[0x20];
7449
7450         u8         reserved_at_40[0x8];
7451         u8         rmpn[0x18];
7452
7453         u8         reserved_at_60[0x20];
7454 };
7455
7456 struct mlx5_ifc_create_rmp_in_bits {
7457         u8         opcode[0x10];
7458         u8         uid[0x10];
7459
7460         u8         reserved_at_20[0x10];
7461         u8         op_mod[0x10];
7462
7463         u8         reserved_at_40[0xc0];
7464
7465         struct mlx5_ifc_rmpc_bits ctx;
7466 };
7467
7468 struct mlx5_ifc_create_qp_out_bits {
7469         u8         status[0x8];
7470         u8         reserved_at_8[0x18];
7471
7472         u8         syndrome[0x20];
7473
7474         u8         reserved_at_40[0x8];
7475         u8         qpn[0x18];
7476
7477         u8         reserved_at_60[0x20];
7478 };
7479
7480 struct mlx5_ifc_create_qp_in_bits {
7481         u8         opcode[0x10];
7482         u8         uid[0x10];
7483
7484         u8         reserved_at_20[0x10];
7485         u8         op_mod[0x10];
7486
7487         u8         reserved_at_40[0x40];
7488
7489         u8         opt_param_mask[0x20];
7490
7491         u8         reserved_at_a0[0x20];
7492
7493         struct mlx5_ifc_qpc_bits qpc;
7494
7495         u8         reserved_at_800[0x60];
7496
7497         u8         wq_umem_valid[0x1];
7498         u8         reserved_at_861[0x1f];
7499
7500         u8         pas[0][0x40];
7501 };
7502
7503 struct mlx5_ifc_create_psv_out_bits {
7504         u8         status[0x8];
7505         u8         reserved_at_8[0x18];
7506
7507         u8         syndrome[0x20];
7508
7509         u8         reserved_at_40[0x40];
7510
7511         u8         reserved_at_80[0x8];
7512         u8         psv0_index[0x18];
7513
7514         u8         reserved_at_a0[0x8];
7515         u8         psv1_index[0x18];
7516
7517         u8         reserved_at_c0[0x8];
7518         u8         psv2_index[0x18];
7519
7520         u8         reserved_at_e0[0x8];
7521         u8         psv3_index[0x18];
7522 };
7523
7524 struct mlx5_ifc_create_psv_in_bits {
7525         u8         opcode[0x10];
7526         u8         reserved_at_10[0x10];
7527
7528         u8         reserved_at_20[0x10];
7529         u8         op_mod[0x10];
7530
7531         u8         num_psv[0x4];
7532         u8         reserved_at_44[0x4];
7533         u8         pd[0x18];
7534
7535         u8         reserved_at_60[0x20];
7536 };
7537
7538 struct mlx5_ifc_create_mkey_out_bits {
7539         u8         status[0x8];
7540         u8         reserved_at_8[0x18];
7541
7542         u8         syndrome[0x20];
7543
7544         u8         reserved_at_40[0x8];
7545         u8         mkey_index[0x18];
7546
7547         u8         reserved_at_60[0x20];
7548 };
7549
7550 struct mlx5_ifc_create_mkey_in_bits {
7551         u8         opcode[0x10];
7552         u8         reserved_at_10[0x10];
7553
7554         u8         reserved_at_20[0x10];
7555         u8         op_mod[0x10];
7556
7557         u8         reserved_at_40[0x20];
7558
7559         u8         pg_access[0x1];
7560         u8         mkey_umem_valid[0x1];
7561         u8         reserved_at_62[0x1e];
7562
7563         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7564
7565         u8         reserved_at_280[0x80];
7566
7567         u8         translations_octword_actual_size[0x20];
7568
7569         u8         reserved_at_320[0x560];
7570
7571         u8         klm_pas_mtt[0][0x20];
7572 };
7573
7574 enum {
7575         MLX5_FLOW_TABLE_TYPE_NIC_RX             = 0x0,
7576         MLX5_FLOW_TABLE_TYPE_NIC_TX             = 0x1,
7577         MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL     = 0x2,
7578         MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL    = 0x3,
7579         MLX5_FLOW_TABLE_TYPE_FDB                = 0X4,
7580         MLX5_FLOW_TABLE_TYPE_SNIFFER_RX         = 0X5,
7581         MLX5_FLOW_TABLE_TYPE_SNIFFER_TX         = 0X6,
7582 };
7583
7584 struct mlx5_ifc_create_flow_table_out_bits {
7585         u8         status[0x8];
7586         u8         icm_address_63_40[0x18];
7587
7588         u8         syndrome[0x20];
7589
7590         u8         icm_address_39_32[0x8];
7591         u8         table_id[0x18];
7592
7593         u8         icm_address_31_0[0x20];
7594 };
7595
7596 struct mlx5_ifc_create_flow_table_in_bits {
7597         u8         opcode[0x10];
7598         u8         reserved_at_10[0x10];
7599
7600         u8         reserved_at_20[0x10];
7601         u8         op_mod[0x10];
7602
7603         u8         other_vport[0x1];
7604         u8         reserved_at_41[0xf];
7605         u8         vport_number[0x10];
7606
7607         u8         reserved_at_60[0x20];
7608
7609         u8         table_type[0x8];
7610         u8         reserved_at_88[0x18];
7611
7612         u8         reserved_at_a0[0x20];
7613
7614         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7615 };
7616
7617 struct mlx5_ifc_create_flow_group_out_bits {
7618         u8         status[0x8];
7619         u8         reserved_at_8[0x18];
7620
7621         u8         syndrome[0x20];
7622
7623         u8         reserved_at_40[0x8];
7624         u8         group_id[0x18];
7625
7626         u8         reserved_at_60[0x20];
7627 };
7628
7629 enum {
7630         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
7631         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
7632         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
7633         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7634 };
7635
7636 struct mlx5_ifc_create_flow_group_in_bits {
7637         u8         opcode[0x10];
7638         u8         reserved_at_10[0x10];
7639
7640         u8         reserved_at_20[0x10];
7641         u8         op_mod[0x10];
7642
7643         u8         other_vport[0x1];
7644         u8         reserved_at_41[0xf];
7645         u8         vport_number[0x10];
7646
7647         u8         reserved_at_60[0x20];
7648
7649         u8         table_type[0x8];
7650         u8         reserved_at_88[0x18];
7651
7652         u8         reserved_at_a0[0x8];
7653         u8         table_id[0x18];
7654
7655         u8         source_eswitch_owner_vhca_id_valid[0x1];
7656
7657         u8         reserved_at_c1[0x1f];
7658
7659         u8         start_flow_index[0x20];
7660
7661         u8         reserved_at_100[0x20];
7662
7663         u8         end_flow_index[0x20];
7664
7665         u8         reserved_at_140[0xa0];
7666
7667         u8         reserved_at_1e0[0x18];
7668         u8         match_criteria_enable[0x8];
7669
7670         struct mlx5_ifc_fte_match_param_bits match_criteria;
7671
7672         u8         reserved_at_1200[0xe00];
7673 };
7674
7675 struct mlx5_ifc_create_eq_out_bits {
7676         u8         status[0x8];
7677         u8         reserved_at_8[0x18];
7678
7679         u8         syndrome[0x20];
7680
7681         u8         reserved_at_40[0x18];
7682         u8         eq_number[0x8];
7683
7684         u8         reserved_at_60[0x20];
7685 };
7686
7687 struct mlx5_ifc_create_eq_in_bits {
7688         u8         opcode[0x10];
7689         u8         uid[0x10];
7690
7691         u8         reserved_at_20[0x10];
7692         u8         op_mod[0x10];
7693
7694         u8         reserved_at_40[0x40];
7695
7696         struct mlx5_ifc_eqc_bits eq_context_entry;
7697
7698         u8         reserved_at_280[0x40];
7699
7700         u8         event_bitmask[4][0x40];
7701
7702         u8         reserved_at_3c0[0x4c0];
7703
7704         u8         pas[0][0x40];
7705 };
7706
7707 struct mlx5_ifc_create_dct_out_bits {
7708         u8         status[0x8];
7709         u8         reserved_at_8[0x18];
7710
7711         u8         syndrome[0x20];
7712
7713         u8         reserved_at_40[0x8];
7714         u8         dctn[0x18];
7715
7716         u8         reserved_at_60[0x20];
7717 };
7718
7719 struct mlx5_ifc_create_dct_in_bits {
7720         u8         opcode[0x10];
7721         u8         uid[0x10];
7722
7723         u8         reserved_at_20[0x10];
7724         u8         op_mod[0x10];
7725
7726         u8         reserved_at_40[0x40];
7727
7728         struct mlx5_ifc_dctc_bits dct_context_entry;
7729
7730         u8         reserved_at_280[0x180];
7731 };
7732
7733 struct mlx5_ifc_create_cq_out_bits {
7734         u8         status[0x8];
7735         u8         reserved_at_8[0x18];
7736
7737         u8         syndrome[0x20];
7738
7739         u8         reserved_at_40[0x8];
7740         u8         cqn[0x18];
7741
7742         u8         reserved_at_60[0x20];
7743 };
7744
7745 struct mlx5_ifc_create_cq_in_bits {
7746         u8         opcode[0x10];
7747         u8         uid[0x10];
7748
7749         u8         reserved_at_20[0x10];
7750         u8         op_mod[0x10];
7751
7752         u8         reserved_at_40[0x40];
7753
7754         struct mlx5_ifc_cqc_bits cq_context;
7755
7756         u8         reserved_at_280[0x60];
7757
7758         u8         cq_umem_valid[0x1];
7759         u8         reserved_at_2e1[0x59f];
7760
7761         u8         pas[0][0x40];
7762 };
7763
7764 struct mlx5_ifc_config_int_moderation_out_bits {
7765         u8         status[0x8];
7766         u8         reserved_at_8[0x18];
7767
7768         u8         syndrome[0x20];
7769
7770         u8         reserved_at_40[0x4];
7771         u8         min_delay[0xc];
7772         u8         int_vector[0x10];
7773
7774         u8         reserved_at_60[0x20];
7775 };
7776
7777 enum {
7778         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7779         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7780 };
7781
7782 struct mlx5_ifc_config_int_moderation_in_bits {
7783         u8         opcode[0x10];
7784         u8         reserved_at_10[0x10];
7785
7786         u8         reserved_at_20[0x10];
7787         u8         op_mod[0x10];
7788
7789         u8         reserved_at_40[0x4];
7790         u8         min_delay[0xc];
7791         u8         int_vector[0x10];
7792
7793         u8         reserved_at_60[0x20];
7794 };
7795
7796 struct mlx5_ifc_attach_to_mcg_out_bits {
7797         u8         status[0x8];
7798         u8         reserved_at_8[0x18];
7799
7800         u8         syndrome[0x20];
7801
7802         u8         reserved_at_40[0x40];
7803 };
7804
7805 struct mlx5_ifc_attach_to_mcg_in_bits {
7806         u8         opcode[0x10];
7807         u8         uid[0x10];
7808
7809         u8         reserved_at_20[0x10];
7810         u8         op_mod[0x10];
7811
7812         u8         reserved_at_40[0x8];
7813         u8         qpn[0x18];
7814
7815         u8         reserved_at_60[0x20];
7816
7817         u8         multicast_gid[16][0x8];
7818 };
7819
7820 struct mlx5_ifc_arm_xrq_out_bits {
7821         u8         status[0x8];
7822         u8         reserved_at_8[0x18];
7823
7824         u8         syndrome[0x20];
7825
7826         u8         reserved_at_40[0x40];
7827 };
7828
7829 struct mlx5_ifc_arm_xrq_in_bits {
7830         u8         opcode[0x10];
7831         u8         reserved_at_10[0x10];
7832
7833         u8         reserved_at_20[0x10];
7834         u8         op_mod[0x10];
7835
7836         u8         reserved_at_40[0x8];
7837         u8         xrqn[0x18];
7838
7839         u8         reserved_at_60[0x10];
7840         u8         lwm[0x10];
7841 };
7842
7843 struct mlx5_ifc_arm_xrc_srq_out_bits {
7844         u8         status[0x8];
7845         u8         reserved_at_8[0x18];
7846
7847         u8         syndrome[0x20];
7848
7849         u8         reserved_at_40[0x40];
7850 };
7851
7852 enum {
7853         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7854 };
7855
7856 struct mlx5_ifc_arm_xrc_srq_in_bits {
7857         u8         opcode[0x10];
7858         u8         uid[0x10];
7859
7860         u8         reserved_at_20[0x10];
7861         u8         op_mod[0x10];
7862
7863         u8         reserved_at_40[0x8];
7864         u8         xrc_srqn[0x18];
7865
7866         u8         reserved_at_60[0x10];
7867         u8         lwm[0x10];
7868 };
7869
7870 struct mlx5_ifc_arm_rq_out_bits {
7871         u8         status[0x8];
7872         u8         reserved_at_8[0x18];
7873
7874         u8         syndrome[0x20];
7875
7876         u8         reserved_at_40[0x40];
7877 };
7878
7879 enum {
7880         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7881         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7882 };
7883
7884 struct mlx5_ifc_arm_rq_in_bits {
7885         u8         opcode[0x10];
7886         u8         uid[0x10];
7887
7888         u8         reserved_at_20[0x10];
7889         u8         op_mod[0x10];
7890
7891         u8         reserved_at_40[0x8];
7892         u8         srq_number[0x18];
7893
7894         u8         reserved_at_60[0x10];
7895         u8         lwm[0x10];
7896 };
7897
7898 struct mlx5_ifc_arm_dct_out_bits {
7899         u8         status[0x8];
7900         u8         reserved_at_8[0x18];
7901
7902         u8         syndrome[0x20];
7903
7904         u8         reserved_at_40[0x40];
7905 };
7906
7907 struct mlx5_ifc_arm_dct_in_bits {
7908         u8         opcode[0x10];
7909         u8         reserved_at_10[0x10];
7910
7911         u8         reserved_at_20[0x10];
7912         u8         op_mod[0x10];
7913
7914         u8         reserved_at_40[0x8];
7915         u8         dct_number[0x18];
7916
7917         u8         reserved_at_60[0x20];
7918 };
7919
7920 struct mlx5_ifc_alloc_xrcd_out_bits {
7921         u8         status[0x8];
7922         u8         reserved_at_8[0x18];
7923
7924         u8         syndrome[0x20];
7925
7926         u8         reserved_at_40[0x8];
7927         u8         xrcd[0x18];
7928
7929         u8         reserved_at_60[0x20];
7930 };
7931
7932 struct mlx5_ifc_alloc_xrcd_in_bits {
7933         u8         opcode[0x10];
7934         u8         uid[0x10];
7935
7936         u8         reserved_at_20[0x10];
7937         u8         op_mod[0x10];
7938
7939         u8         reserved_at_40[0x40];
7940 };
7941
7942 struct mlx5_ifc_alloc_uar_out_bits {
7943         u8         status[0x8];
7944         u8         reserved_at_8[0x18];
7945
7946         u8         syndrome[0x20];
7947
7948         u8         reserved_at_40[0x8];
7949         u8         uar[0x18];
7950
7951         u8         reserved_at_60[0x20];
7952 };
7953
7954 struct mlx5_ifc_alloc_uar_in_bits {
7955         u8         opcode[0x10];
7956         u8         reserved_at_10[0x10];
7957
7958         u8         reserved_at_20[0x10];
7959         u8         op_mod[0x10];
7960
7961         u8         reserved_at_40[0x40];
7962 };
7963
7964 struct mlx5_ifc_alloc_transport_domain_out_bits {
7965         u8         status[0x8];
7966         u8         reserved_at_8[0x18];
7967
7968         u8         syndrome[0x20];
7969
7970         u8         reserved_at_40[0x8];
7971         u8         transport_domain[0x18];
7972
7973         u8         reserved_at_60[0x20];
7974 };
7975
7976 struct mlx5_ifc_alloc_transport_domain_in_bits {
7977         u8         opcode[0x10];
7978         u8         uid[0x10];
7979
7980         u8         reserved_at_20[0x10];
7981         u8         op_mod[0x10];
7982
7983         u8         reserved_at_40[0x40];
7984 };
7985
7986 struct mlx5_ifc_alloc_q_counter_out_bits {
7987         u8         status[0x8];
7988         u8         reserved_at_8[0x18];
7989
7990         u8         syndrome[0x20];
7991
7992         u8         reserved_at_40[0x18];
7993         u8         counter_set_id[0x8];
7994
7995         u8         reserved_at_60[0x20];
7996 };
7997
7998 struct mlx5_ifc_alloc_q_counter_in_bits {
7999         u8         opcode[0x10];
8000         u8         uid[0x10];
8001
8002         u8         reserved_at_20[0x10];
8003         u8         op_mod[0x10];
8004
8005         u8         reserved_at_40[0x40];
8006 };
8007
8008 struct mlx5_ifc_alloc_pd_out_bits {
8009         u8         status[0x8];
8010         u8         reserved_at_8[0x18];
8011
8012         u8         syndrome[0x20];
8013
8014         u8         reserved_at_40[0x8];
8015         u8         pd[0x18];
8016
8017         u8         reserved_at_60[0x20];
8018 };
8019
8020 struct mlx5_ifc_alloc_pd_in_bits {
8021         u8         opcode[0x10];
8022         u8         uid[0x10];
8023
8024         u8         reserved_at_20[0x10];
8025         u8         op_mod[0x10];
8026
8027         u8         reserved_at_40[0x40];
8028 };
8029
8030 struct mlx5_ifc_alloc_flow_counter_out_bits {
8031         u8         status[0x8];
8032         u8         reserved_at_8[0x18];
8033
8034         u8         syndrome[0x20];
8035
8036         u8         flow_counter_id[0x20];
8037
8038         u8         reserved_at_60[0x20];
8039 };
8040
8041 struct mlx5_ifc_alloc_flow_counter_in_bits {
8042         u8         opcode[0x10];
8043         u8         reserved_at_10[0x10];
8044
8045         u8         reserved_at_20[0x10];
8046         u8         op_mod[0x10];
8047
8048         u8         reserved_at_40[0x38];
8049         u8         flow_counter_bulk[0x8];
8050 };
8051
8052 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8053         u8         status[0x8];
8054         u8         reserved_at_8[0x18];
8055
8056         u8         syndrome[0x20];
8057
8058         u8         reserved_at_40[0x40];
8059 };
8060
8061 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8062         u8         opcode[0x10];
8063         u8         reserved_at_10[0x10];
8064
8065         u8         reserved_at_20[0x10];
8066         u8         op_mod[0x10];
8067
8068         u8         reserved_at_40[0x20];
8069
8070         u8         reserved_at_60[0x10];
8071         u8         vxlan_udp_port[0x10];
8072 };
8073
8074 struct mlx5_ifc_set_pp_rate_limit_out_bits {
8075         u8         status[0x8];
8076         u8         reserved_at_8[0x18];
8077
8078         u8         syndrome[0x20];
8079
8080         u8         reserved_at_40[0x40];
8081 };
8082
8083 struct mlx5_ifc_set_pp_rate_limit_in_bits {
8084         u8         opcode[0x10];
8085         u8         reserved_at_10[0x10];
8086
8087         u8         reserved_at_20[0x10];
8088         u8         op_mod[0x10];
8089
8090         u8         reserved_at_40[0x10];
8091         u8         rate_limit_index[0x10];
8092
8093         u8         reserved_at_60[0x20];
8094
8095         u8         rate_limit[0x20];
8096
8097         u8         burst_upper_bound[0x20];
8098
8099         u8         reserved_at_c0[0x10];
8100         u8         typical_packet_size[0x10];
8101
8102         u8         reserved_at_e0[0x120];
8103 };
8104
8105 struct mlx5_ifc_access_register_out_bits {
8106         u8         status[0x8];
8107         u8         reserved_at_8[0x18];
8108
8109         u8         syndrome[0x20];
8110
8111         u8         reserved_at_40[0x40];
8112
8113         u8         register_data[0][0x20];
8114 };
8115
8116 enum {
8117         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
8118         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
8119 };
8120
8121 struct mlx5_ifc_access_register_in_bits {
8122         u8         opcode[0x10];
8123         u8         reserved_at_10[0x10];
8124
8125         u8         reserved_at_20[0x10];
8126         u8         op_mod[0x10];
8127
8128         u8         reserved_at_40[0x10];
8129         u8         register_id[0x10];
8130
8131         u8         argument[0x20];
8132
8133         u8         register_data[0][0x20];
8134 };
8135
8136 struct mlx5_ifc_sltp_reg_bits {
8137         u8         status[0x4];
8138         u8         version[0x4];
8139         u8         local_port[0x8];
8140         u8         pnat[0x2];
8141         u8         reserved_at_12[0x2];
8142         u8         lane[0x4];
8143         u8         reserved_at_18[0x8];
8144
8145         u8         reserved_at_20[0x20];
8146
8147         u8         reserved_at_40[0x7];
8148         u8         polarity[0x1];
8149         u8         ob_tap0[0x8];
8150         u8         ob_tap1[0x8];
8151         u8         ob_tap2[0x8];
8152
8153         u8         reserved_at_60[0xc];
8154         u8         ob_preemp_mode[0x4];
8155         u8         ob_reg[0x8];
8156         u8         ob_bias[0x8];
8157
8158         u8         reserved_at_80[0x20];
8159 };
8160
8161 struct mlx5_ifc_slrg_reg_bits {
8162         u8         status[0x4];
8163         u8         version[0x4];
8164         u8         local_port[0x8];
8165         u8         pnat[0x2];
8166         u8         reserved_at_12[0x2];
8167         u8         lane[0x4];
8168         u8         reserved_at_18[0x8];
8169
8170         u8         time_to_link_up[0x10];
8171         u8         reserved_at_30[0xc];
8172         u8         grade_lane_speed[0x4];
8173
8174         u8         grade_version[0x8];
8175         u8         grade[0x18];
8176
8177         u8         reserved_at_60[0x4];
8178         u8         height_grade_type[0x4];
8179         u8         height_grade[0x18];
8180
8181         u8         height_dz[0x10];
8182         u8         height_dv[0x10];
8183
8184         u8         reserved_at_a0[0x10];
8185         u8         height_sigma[0x10];
8186
8187         u8         reserved_at_c0[0x20];
8188
8189         u8         reserved_at_e0[0x4];
8190         u8         phase_grade_type[0x4];
8191         u8         phase_grade[0x18];
8192
8193         u8         reserved_at_100[0x8];
8194         u8         phase_eo_pos[0x8];
8195         u8         reserved_at_110[0x8];
8196         u8         phase_eo_neg[0x8];
8197
8198         u8         ffe_set_tested[0x10];
8199         u8         test_errors_per_lane[0x10];
8200 };
8201
8202 struct mlx5_ifc_pvlc_reg_bits {
8203         u8         reserved_at_0[0x8];
8204         u8         local_port[0x8];
8205         u8         reserved_at_10[0x10];
8206
8207         u8         reserved_at_20[0x1c];
8208         u8         vl_hw_cap[0x4];
8209
8210         u8         reserved_at_40[0x1c];
8211         u8         vl_admin[0x4];
8212
8213         u8         reserved_at_60[0x1c];
8214         u8         vl_operational[0x4];
8215 };
8216
8217 struct mlx5_ifc_pude_reg_bits {
8218         u8         swid[0x8];
8219         u8         local_port[0x8];
8220         u8         reserved_at_10[0x4];
8221         u8         admin_status[0x4];
8222         u8         reserved_at_18[0x4];
8223         u8         oper_status[0x4];
8224
8225         u8         reserved_at_20[0x60];
8226 };
8227
8228 struct mlx5_ifc_ptys_reg_bits {
8229         u8         reserved_at_0[0x1];
8230         u8         an_disable_admin[0x1];
8231         u8         an_disable_cap[0x1];
8232         u8         reserved_at_3[0x5];
8233         u8         local_port[0x8];
8234         u8         reserved_at_10[0xd];
8235         u8         proto_mask[0x3];
8236
8237         u8         an_status[0x4];
8238         u8         reserved_at_24[0x1c];
8239
8240         u8         ext_eth_proto_capability[0x20];
8241
8242         u8         eth_proto_capability[0x20];
8243
8244         u8         ib_link_width_capability[0x10];
8245         u8         ib_proto_capability[0x10];
8246
8247         u8         ext_eth_proto_admin[0x20];
8248
8249         u8         eth_proto_admin[0x20];
8250
8251         u8         ib_link_width_admin[0x10];
8252         u8         ib_proto_admin[0x10];
8253
8254         u8         ext_eth_proto_oper[0x20];
8255
8256         u8         eth_proto_oper[0x20];
8257
8258         u8         ib_link_width_oper[0x10];
8259         u8         ib_proto_oper[0x10];
8260
8261         u8         reserved_at_160[0x1c];
8262         u8         connector_type[0x4];
8263
8264         u8         eth_proto_lp_advertise[0x20];
8265
8266         u8         reserved_at_1a0[0x60];
8267 };
8268
8269 struct mlx5_ifc_mlcr_reg_bits {
8270         u8         reserved_at_0[0x8];
8271         u8         local_port[0x8];
8272         u8         reserved_at_10[0x20];
8273
8274         u8         beacon_duration[0x10];
8275         u8         reserved_at_40[0x10];
8276
8277         u8         beacon_remain[0x10];
8278 };
8279
8280 struct mlx5_ifc_ptas_reg_bits {
8281         u8         reserved_at_0[0x20];
8282
8283         u8         algorithm_options[0x10];
8284         u8         reserved_at_30[0x4];
8285         u8         repetitions_mode[0x4];
8286         u8         num_of_repetitions[0x8];
8287
8288         u8         grade_version[0x8];
8289         u8         height_grade_type[0x4];
8290         u8         phase_grade_type[0x4];
8291         u8         height_grade_weight[0x8];
8292         u8         phase_grade_weight[0x8];
8293
8294         u8         gisim_measure_bits[0x10];
8295         u8         adaptive_tap_measure_bits[0x10];
8296
8297         u8         ber_bath_high_error_threshold[0x10];
8298         u8         ber_bath_mid_error_threshold[0x10];
8299
8300         u8         ber_bath_low_error_threshold[0x10];
8301         u8         one_ratio_high_threshold[0x10];
8302
8303         u8         one_ratio_high_mid_threshold[0x10];
8304         u8         one_ratio_low_mid_threshold[0x10];
8305
8306         u8         one_ratio_low_threshold[0x10];
8307         u8         ndeo_error_threshold[0x10];
8308
8309         u8         mixer_offset_step_size[0x10];
8310         u8         reserved_at_110[0x8];
8311         u8         mix90_phase_for_voltage_bath[0x8];
8312
8313         u8         mixer_offset_start[0x10];
8314         u8         mixer_offset_end[0x10];
8315
8316         u8         reserved_at_140[0x15];
8317         u8         ber_test_time[0xb];
8318 };
8319
8320 struct mlx5_ifc_pspa_reg_bits {
8321         u8         swid[0x8];
8322         u8         local_port[0x8];
8323         u8         sub_port[0x8];
8324         u8         reserved_at_18[0x8];
8325
8326         u8         reserved_at_20[0x20];
8327 };
8328
8329 struct mlx5_ifc_pqdr_reg_bits {
8330         u8         reserved_at_0[0x8];
8331         u8         local_port[0x8];
8332         u8         reserved_at_10[0x5];
8333         u8         prio[0x3];
8334         u8         reserved_at_18[0x6];
8335         u8         mode[0x2];
8336
8337         u8         reserved_at_20[0x20];
8338
8339         u8         reserved_at_40[0x10];
8340         u8         min_threshold[0x10];
8341
8342         u8         reserved_at_60[0x10];
8343         u8         max_threshold[0x10];
8344
8345         u8         reserved_at_80[0x10];
8346         u8         mark_probability_denominator[0x10];
8347
8348         u8         reserved_at_a0[0x60];
8349 };
8350
8351 struct mlx5_ifc_ppsc_reg_bits {
8352         u8         reserved_at_0[0x8];
8353         u8         local_port[0x8];
8354         u8         reserved_at_10[0x10];
8355
8356         u8         reserved_at_20[0x60];
8357
8358         u8         reserved_at_80[0x1c];
8359         u8         wrps_admin[0x4];
8360
8361         u8         reserved_at_a0[0x1c];
8362         u8         wrps_status[0x4];
8363
8364         u8         reserved_at_c0[0x8];
8365         u8         up_threshold[0x8];
8366         u8         reserved_at_d0[0x8];
8367         u8         down_threshold[0x8];
8368
8369         u8         reserved_at_e0[0x20];
8370
8371         u8         reserved_at_100[0x1c];
8372         u8         srps_admin[0x4];
8373
8374         u8         reserved_at_120[0x1c];
8375         u8         srps_status[0x4];
8376
8377         u8         reserved_at_140[0x40];
8378 };
8379
8380 struct mlx5_ifc_pplr_reg_bits {
8381         u8         reserved_at_0[0x8];
8382         u8         local_port[0x8];
8383         u8         reserved_at_10[0x10];
8384
8385         u8         reserved_at_20[0x8];
8386         u8         lb_cap[0x8];
8387         u8         reserved_at_30[0x8];
8388         u8         lb_en[0x8];
8389 };
8390
8391 struct mlx5_ifc_pplm_reg_bits {
8392         u8         reserved_at_0[0x8];
8393         u8         local_port[0x8];
8394         u8         reserved_at_10[0x10];
8395
8396         u8         reserved_at_20[0x20];
8397
8398         u8         port_profile_mode[0x8];
8399         u8         static_port_profile[0x8];
8400         u8         active_port_profile[0x8];
8401         u8         reserved_at_58[0x8];
8402
8403         u8         retransmission_active[0x8];
8404         u8         fec_mode_active[0x18];
8405
8406         u8         rs_fec_correction_bypass_cap[0x4];
8407         u8         reserved_at_84[0x8];
8408         u8         fec_override_cap_56g[0x4];
8409         u8         fec_override_cap_100g[0x4];
8410         u8         fec_override_cap_50g[0x4];
8411         u8         fec_override_cap_25g[0x4];
8412         u8         fec_override_cap_10g_40g[0x4];
8413
8414         u8         rs_fec_correction_bypass_admin[0x4];
8415         u8         reserved_at_a4[0x8];
8416         u8         fec_override_admin_56g[0x4];
8417         u8         fec_override_admin_100g[0x4];
8418         u8         fec_override_admin_50g[0x4];
8419         u8         fec_override_admin_25g[0x4];
8420         u8         fec_override_admin_10g_40g[0x4];
8421 };
8422
8423 struct mlx5_ifc_ppcnt_reg_bits {
8424         u8         swid[0x8];
8425         u8         local_port[0x8];
8426         u8         pnat[0x2];
8427         u8         reserved_at_12[0x8];
8428         u8         grp[0x6];
8429
8430         u8         clr[0x1];
8431         u8         reserved_at_21[0x1c];
8432         u8         prio_tc[0x3];
8433
8434         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8435 };
8436
8437 struct mlx5_ifc_mpein_reg_bits {
8438         u8         reserved_at_0[0x2];
8439         u8         depth[0x6];
8440         u8         pcie_index[0x8];
8441         u8         node[0x8];
8442         u8         reserved_at_18[0x8];
8443
8444         u8         capability_mask[0x20];
8445
8446         u8         reserved_at_40[0x8];
8447         u8         link_width_enabled[0x8];
8448         u8         link_speed_enabled[0x10];
8449
8450         u8         lane0_physical_position[0x8];
8451         u8         link_width_active[0x8];
8452         u8         link_speed_active[0x10];
8453
8454         u8         num_of_pfs[0x10];
8455         u8         num_of_vfs[0x10];
8456
8457         u8         bdf0[0x10];
8458         u8         reserved_at_b0[0x10];
8459
8460         u8         max_read_request_size[0x4];
8461         u8         max_payload_size[0x4];
8462         u8         reserved_at_c8[0x5];
8463         u8         pwr_status[0x3];
8464         u8         port_type[0x4];
8465         u8         reserved_at_d4[0xb];
8466         u8         lane_reversal[0x1];
8467
8468         u8         reserved_at_e0[0x14];
8469         u8         pci_power[0xc];
8470
8471         u8         reserved_at_100[0x20];
8472
8473         u8         device_status[0x10];
8474         u8         port_state[0x8];
8475         u8         reserved_at_138[0x8];
8476
8477         u8         reserved_at_140[0x10];
8478         u8         receiver_detect_result[0x10];
8479
8480         u8         reserved_at_160[0x20];
8481 };
8482
8483 struct mlx5_ifc_mpcnt_reg_bits {
8484         u8         reserved_at_0[0x8];
8485         u8         pcie_index[0x8];
8486         u8         reserved_at_10[0xa];
8487         u8         grp[0x6];
8488
8489         u8         clr[0x1];
8490         u8         reserved_at_21[0x1f];
8491
8492         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8493 };
8494
8495 struct mlx5_ifc_ppad_reg_bits {
8496         u8         reserved_at_0[0x3];
8497         u8         single_mac[0x1];
8498         u8         reserved_at_4[0x4];
8499         u8         local_port[0x8];
8500         u8         mac_47_32[0x10];
8501
8502         u8         mac_31_0[0x20];
8503
8504         u8         reserved_at_40[0x40];
8505 };
8506
8507 struct mlx5_ifc_pmtu_reg_bits {
8508         u8         reserved_at_0[0x8];
8509         u8         local_port[0x8];
8510         u8         reserved_at_10[0x10];
8511
8512         u8         max_mtu[0x10];
8513         u8         reserved_at_30[0x10];
8514
8515         u8         admin_mtu[0x10];
8516         u8         reserved_at_50[0x10];
8517
8518         u8         oper_mtu[0x10];
8519         u8         reserved_at_70[0x10];
8520 };
8521
8522 struct mlx5_ifc_pmpr_reg_bits {
8523         u8         reserved_at_0[0x8];
8524         u8         module[0x8];
8525         u8         reserved_at_10[0x10];
8526
8527         u8         reserved_at_20[0x18];
8528         u8         attenuation_5g[0x8];
8529
8530         u8         reserved_at_40[0x18];
8531         u8         attenuation_7g[0x8];
8532
8533         u8         reserved_at_60[0x18];
8534         u8         attenuation_12g[0x8];
8535 };
8536
8537 struct mlx5_ifc_pmpe_reg_bits {
8538         u8         reserved_at_0[0x8];
8539         u8         module[0x8];
8540         u8         reserved_at_10[0xc];
8541         u8         module_status[0x4];
8542
8543         u8         reserved_at_20[0x60];
8544 };
8545
8546 struct mlx5_ifc_pmpc_reg_bits {
8547         u8         module_state_updated[32][0x8];
8548 };
8549
8550 struct mlx5_ifc_pmlpn_reg_bits {
8551         u8         reserved_at_0[0x4];
8552         u8         mlpn_status[0x4];
8553         u8         local_port[0x8];
8554         u8         reserved_at_10[0x10];
8555
8556         u8         e[0x1];
8557         u8         reserved_at_21[0x1f];
8558 };
8559
8560 struct mlx5_ifc_pmlp_reg_bits {
8561         u8         rxtx[0x1];
8562         u8         reserved_at_1[0x7];
8563         u8         local_port[0x8];
8564         u8         reserved_at_10[0x8];
8565         u8         width[0x8];
8566
8567         u8         lane0_module_mapping[0x20];
8568
8569         u8         lane1_module_mapping[0x20];
8570
8571         u8         lane2_module_mapping[0x20];
8572
8573         u8         lane3_module_mapping[0x20];
8574
8575         u8         reserved_at_a0[0x160];
8576 };
8577
8578 struct mlx5_ifc_pmaos_reg_bits {
8579         u8         reserved_at_0[0x8];
8580         u8         module[0x8];
8581         u8         reserved_at_10[0x4];
8582         u8         admin_status[0x4];
8583         u8         reserved_at_18[0x4];
8584         u8         oper_status[0x4];
8585
8586         u8         ase[0x1];
8587         u8         ee[0x1];
8588         u8         reserved_at_22[0x1c];
8589         u8         e[0x2];
8590
8591         u8         reserved_at_40[0x40];
8592 };
8593
8594 struct mlx5_ifc_plpc_reg_bits {
8595         u8         reserved_at_0[0x4];
8596         u8         profile_id[0xc];
8597         u8         reserved_at_10[0x4];
8598         u8         proto_mask[0x4];
8599         u8         reserved_at_18[0x8];
8600
8601         u8         reserved_at_20[0x10];
8602         u8         lane_speed[0x10];
8603
8604         u8         reserved_at_40[0x17];
8605         u8         lpbf[0x1];
8606         u8         fec_mode_policy[0x8];
8607
8608         u8         retransmission_capability[0x8];
8609         u8         fec_mode_capability[0x18];
8610
8611         u8         retransmission_support_admin[0x8];
8612         u8         fec_mode_support_admin[0x18];
8613
8614         u8         retransmission_request_admin[0x8];
8615         u8         fec_mode_request_admin[0x18];
8616
8617         u8         reserved_at_c0[0x80];
8618 };
8619
8620 struct mlx5_ifc_plib_reg_bits {
8621         u8         reserved_at_0[0x8];
8622         u8         local_port[0x8];
8623         u8         reserved_at_10[0x8];
8624         u8         ib_port[0x8];
8625
8626         u8         reserved_at_20[0x60];
8627 };
8628
8629 struct mlx5_ifc_plbf_reg_bits {
8630         u8         reserved_at_0[0x8];
8631         u8         local_port[0x8];
8632         u8         reserved_at_10[0xd];
8633         u8         lbf_mode[0x3];
8634
8635         u8         reserved_at_20[0x20];
8636 };
8637
8638 struct mlx5_ifc_pipg_reg_bits {
8639         u8         reserved_at_0[0x8];
8640         u8         local_port[0x8];
8641         u8         reserved_at_10[0x10];
8642
8643         u8         dic[0x1];
8644         u8         reserved_at_21[0x19];
8645         u8         ipg[0x4];
8646         u8         reserved_at_3e[0x2];
8647 };
8648
8649 struct mlx5_ifc_pifr_reg_bits {
8650         u8         reserved_at_0[0x8];
8651         u8         local_port[0x8];
8652         u8         reserved_at_10[0x10];
8653
8654         u8         reserved_at_20[0xe0];
8655
8656         u8         port_filter[8][0x20];
8657
8658         u8         port_filter_update_en[8][0x20];
8659 };
8660
8661 struct mlx5_ifc_pfcc_reg_bits {
8662         u8         reserved_at_0[0x8];
8663         u8         local_port[0x8];
8664         u8         reserved_at_10[0xb];
8665         u8         ppan_mask_n[0x1];
8666         u8         minor_stall_mask[0x1];
8667         u8         critical_stall_mask[0x1];
8668         u8         reserved_at_1e[0x2];
8669
8670         u8         ppan[0x4];
8671         u8         reserved_at_24[0x4];
8672         u8         prio_mask_tx[0x8];
8673         u8         reserved_at_30[0x8];
8674         u8         prio_mask_rx[0x8];
8675
8676         u8         pptx[0x1];
8677         u8         aptx[0x1];
8678         u8         pptx_mask_n[0x1];
8679         u8         reserved_at_43[0x5];
8680         u8         pfctx[0x8];
8681         u8         reserved_at_50[0x10];
8682
8683         u8         pprx[0x1];
8684         u8         aprx[0x1];
8685         u8         pprx_mask_n[0x1];
8686         u8         reserved_at_63[0x5];
8687         u8         pfcrx[0x8];
8688         u8         reserved_at_70[0x10];
8689
8690         u8         device_stall_minor_watermark[0x10];
8691         u8         device_stall_critical_watermark[0x10];
8692
8693         u8         reserved_at_a0[0x60];
8694 };
8695
8696 struct mlx5_ifc_pelc_reg_bits {
8697         u8         op[0x4];
8698         u8         reserved_at_4[0x4];
8699         u8         local_port[0x8];
8700         u8         reserved_at_10[0x10];
8701
8702         u8         op_admin[0x8];
8703         u8         op_capability[0x8];
8704         u8         op_request[0x8];
8705         u8         op_active[0x8];
8706
8707         u8         admin[0x40];
8708
8709         u8         capability[0x40];
8710
8711         u8         request[0x40];
8712
8713         u8         active[0x40];
8714
8715         u8         reserved_at_140[0x80];
8716 };
8717
8718 struct mlx5_ifc_peir_reg_bits {
8719         u8         reserved_at_0[0x8];
8720         u8         local_port[0x8];
8721         u8         reserved_at_10[0x10];
8722
8723         u8         reserved_at_20[0xc];
8724         u8         error_count[0x4];
8725         u8         reserved_at_30[0x10];
8726
8727         u8         reserved_at_40[0xc];
8728         u8         lane[0x4];
8729         u8         reserved_at_50[0x8];
8730         u8         error_type[0x8];
8731 };
8732
8733 struct mlx5_ifc_mpegc_reg_bits {
8734         u8         reserved_at_0[0x30];
8735         u8         field_select[0x10];
8736
8737         u8         tx_overflow_sense[0x1];
8738         u8         mark_cqe[0x1];
8739         u8         mark_cnp[0x1];
8740         u8         reserved_at_43[0x1b];
8741         u8         tx_lossy_overflow_oper[0x2];
8742
8743         u8         reserved_at_60[0x100];
8744 };
8745
8746 struct mlx5_ifc_pcam_enhanced_features_bits {
8747         u8         reserved_at_0[0x6d];
8748         u8         rx_icrc_encapsulated_counter[0x1];
8749         u8         reserved_at_6e[0x4];
8750         u8         ptys_extended_ethernet[0x1];
8751         u8         reserved_at_73[0x3];
8752         u8         pfcc_mask[0x1];
8753         u8         reserved_at_77[0x3];
8754         u8         per_lane_error_counters[0x1];
8755         u8         rx_buffer_fullness_counters[0x1];
8756         u8         ptys_connector_type[0x1];
8757         u8         reserved_at_7d[0x1];
8758         u8         ppcnt_discard_group[0x1];
8759         u8         ppcnt_statistical_group[0x1];
8760 };
8761
8762 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8763         u8         port_access_reg_cap_mask_127_to_96[0x20];
8764         u8         port_access_reg_cap_mask_95_to_64[0x20];
8765
8766         u8         port_access_reg_cap_mask_63_to_36[0x1c];
8767         u8         pplm[0x1];
8768         u8         port_access_reg_cap_mask_34_to_32[0x3];
8769
8770         u8         port_access_reg_cap_mask_31_to_13[0x13];
8771         u8         pbmc[0x1];
8772         u8         pptb[0x1];
8773         u8         port_access_reg_cap_mask_10_to_09[0x2];
8774         u8         ppcnt[0x1];
8775         u8         port_access_reg_cap_mask_07_to_00[0x8];
8776 };
8777
8778 struct mlx5_ifc_pcam_reg_bits {
8779         u8         reserved_at_0[0x8];
8780         u8         feature_group[0x8];
8781         u8         reserved_at_10[0x8];
8782         u8         access_reg_group[0x8];
8783
8784         u8         reserved_at_20[0x20];
8785
8786         union {
8787                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8788                 u8         reserved_at_0[0x80];
8789         } port_access_reg_cap_mask;
8790
8791         u8         reserved_at_c0[0x80];
8792
8793         union {
8794                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8795                 u8         reserved_at_0[0x80];
8796         } feature_cap_mask;
8797
8798         u8         reserved_at_1c0[0xc0];
8799 };
8800
8801 struct mlx5_ifc_mcam_enhanced_features_bits {
8802         u8         reserved_at_0[0x6e];
8803         u8         pci_status_and_power[0x1];
8804         u8         reserved_at_6f[0x5];
8805         u8         mark_tx_action_cnp[0x1];
8806         u8         mark_tx_action_cqe[0x1];
8807         u8         dynamic_tx_overflow[0x1];
8808         u8         reserved_at_77[0x4];
8809         u8         pcie_outbound_stalled[0x1];
8810         u8         tx_overflow_buffer_pkt[0x1];
8811         u8         mtpps_enh_out_per_adj[0x1];
8812         u8         mtpps_fs[0x1];
8813         u8         pcie_performance_group[0x1];
8814 };
8815
8816 struct mlx5_ifc_mcam_access_reg_bits {
8817         u8         reserved_at_0[0x1c];
8818         u8         mcda[0x1];
8819         u8         mcc[0x1];
8820         u8         mcqi[0x1];
8821         u8         mcqs[0x1];
8822
8823         u8         regs_95_to_87[0x9];
8824         u8         mpegc[0x1];
8825         u8         regs_85_to_68[0x12];
8826         u8         tracer_registers[0x4];
8827
8828         u8         regs_63_to_32[0x20];
8829         u8         regs_31_to_0[0x20];
8830 };
8831
8832 struct mlx5_ifc_mcam_reg_bits {
8833         u8         reserved_at_0[0x8];
8834         u8         feature_group[0x8];
8835         u8         reserved_at_10[0x8];
8836         u8         access_reg_group[0x8];
8837
8838         u8         reserved_at_20[0x20];
8839
8840         union {
8841                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8842                 u8         reserved_at_0[0x80];
8843         } mng_access_reg_cap_mask;
8844
8845         u8         reserved_at_c0[0x80];
8846
8847         union {
8848                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8849                 u8         reserved_at_0[0x80];
8850         } mng_feature_cap_mask;
8851
8852         u8         reserved_at_1c0[0x80];
8853 };
8854
8855 struct mlx5_ifc_qcam_access_reg_cap_mask {
8856         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
8857         u8         qpdpm[0x1];
8858         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
8859         u8         qdpm[0x1];
8860         u8         qpts[0x1];
8861         u8         qcap[0x1];
8862         u8         qcam_access_reg_cap_mask_0[0x1];
8863 };
8864
8865 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8866         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
8867         u8         qpts_trust_both[0x1];
8868 };
8869
8870 struct mlx5_ifc_qcam_reg_bits {
8871         u8         reserved_at_0[0x8];
8872         u8         feature_group[0x8];
8873         u8         reserved_at_10[0x8];
8874         u8         access_reg_group[0x8];
8875         u8         reserved_at_20[0x20];
8876
8877         union {
8878                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8879                 u8  reserved_at_0[0x80];
8880         } qos_access_reg_cap_mask;
8881
8882         u8         reserved_at_c0[0x80];
8883
8884         union {
8885                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8886                 u8  reserved_at_0[0x80];
8887         } qos_feature_cap_mask;
8888
8889         u8         reserved_at_1c0[0x80];
8890 };
8891
8892 struct mlx5_ifc_core_dump_reg_bits {
8893         u8         reserved_at_0[0x18];
8894         u8         core_dump_type[0x8];
8895
8896         u8         reserved_at_20[0x30];
8897         u8         vhca_id[0x10];
8898
8899         u8         reserved_at_60[0x8];
8900         u8         qpn[0x18];
8901         u8         reserved_at_80[0x180];
8902 };
8903
8904 struct mlx5_ifc_pcap_reg_bits {
8905         u8         reserved_at_0[0x8];
8906         u8         local_port[0x8];
8907         u8         reserved_at_10[0x10];
8908
8909         u8         port_capability_mask[4][0x20];
8910 };
8911
8912 struct mlx5_ifc_paos_reg_bits {
8913         u8         swid[0x8];
8914         u8         local_port[0x8];
8915         u8         reserved_at_10[0x4];
8916         u8         admin_status[0x4];
8917         u8         reserved_at_18[0x4];
8918         u8         oper_status[0x4];
8919
8920         u8         ase[0x1];
8921         u8         ee[0x1];
8922         u8         reserved_at_22[0x1c];
8923         u8         e[0x2];
8924
8925         u8         reserved_at_40[0x40];
8926 };
8927
8928 struct mlx5_ifc_pamp_reg_bits {
8929         u8         reserved_at_0[0x8];
8930         u8         opamp_group[0x8];
8931         u8         reserved_at_10[0xc];
8932         u8         opamp_group_type[0x4];
8933
8934         u8         start_index[0x10];
8935         u8         reserved_at_30[0x4];
8936         u8         num_of_indices[0xc];
8937
8938         u8         index_data[18][0x10];
8939 };
8940
8941 struct mlx5_ifc_pcmr_reg_bits {
8942         u8         reserved_at_0[0x8];
8943         u8         local_port[0x8];
8944         u8         reserved_at_10[0x10];
8945
8946         u8         entropy_force_cap[0x1];
8947         u8         entropy_calc_cap[0x1];
8948         u8         entropy_gre_calc_cap[0x1];
8949         u8         reserved_at_23[0xf];
8950         u8         rx_ts_over_crc_cap[0x1];
8951         u8         reserved_at_33[0xb];
8952         u8         fcs_cap[0x1];
8953         u8         reserved_at_3f[0x1];
8954
8955         u8         entropy_force[0x1];
8956         u8         entropy_calc[0x1];
8957         u8         entropy_gre_calc[0x1];
8958         u8         reserved_at_43[0xf];
8959         u8         rx_ts_over_crc[0x1];
8960         u8         reserved_at_53[0xb];
8961         u8         fcs_chk[0x1];
8962         u8         reserved_at_5f[0x1];
8963 };
8964
8965 struct mlx5_ifc_lane_2_module_mapping_bits {
8966         u8         reserved_at_0[0x6];
8967         u8         rx_lane[0x2];
8968         u8         reserved_at_8[0x6];
8969         u8         tx_lane[0x2];
8970         u8         reserved_at_10[0x8];
8971         u8         module[0x8];
8972 };
8973
8974 struct mlx5_ifc_bufferx_reg_bits {
8975         u8         reserved_at_0[0x6];
8976         u8         lossy[0x1];
8977         u8         epsb[0x1];
8978         u8         reserved_at_8[0x8];
8979         u8         size[0x10];
8980
8981         u8         xoff_threshold[0x10];
8982         u8         xon_threshold[0x10];
8983 };
8984
8985 struct mlx5_ifc_set_node_in_bits {
8986         u8         node_description[64][0x8];
8987 };
8988
8989 struct mlx5_ifc_register_power_settings_bits {
8990         u8         reserved_at_0[0x18];
8991         u8         power_settings_level[0x8];
8992
8993         u8         reserved_at_20[0x60];
8994 };
8995
8996 struct mlx5_ifc_register_host_endianness_bits {
8997         u8         he[0x1];
8998         u8         reserved_at_1[0x1f];
8999
9000         u8         reserved_at_20[0x60];
9001 };
9002
9003 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9004         u8         reserved_at_0[0x20];
9005
9006         u8         mkey[0x20];
9007
9008         u8         addressh_63_32[0x20];
9009
9010         u8         addressl_31_0[0x20];
9011 };
9012
9013 struct mlx5_ifc_ud_adrs_vector_bits {
9014         u8         dc_key[0x40];
9015
9016         u8         ext[0x1];
9017         u8         reserved_at_41[0x7];
9018         u8         destination_qp_dct[0x18];
9019
9020         u8         static_rate[0x4];
9021         u8         sl_eth_prio[0x4];
9022         u8         fl[0x1];
9023         u8         mlid[0x7];
9024         u8         rlid_udp_sport[0x10];
9025
9026         u8         reserved_at_80[0x20];
9027
9028         u8         rmac_47_16[0x20];
9029
9030         u8         rmac_15_0[0x10];
9031         u8         tclass[0x8];
9032         u8         hop_limit[0x8];
9033
9034         u8         reserved_at_e0[0x1];
9035         u8         grh[0x1];
9036         u8         reserved_at_e2[0x2];
9037         u8         src_addr_index[0x8];
9038         u8         flow_label[0x14];
9039
9040         u8         rgid_rip[16][0x8];
9041 };
9042
9043 struct mlx5_ifc_pages_req_event_bits {
9044         u8         reserved_at_0[0x10];
9045         u8         function_id[0x10];
9046
9047         u8         num_pages[0x20];
9048
9049         u8         reserved_at_40[0xa0];
9050 };
9051
9052 struct mlx5_ifc_eqe_bits {
9053         u8         reserved_at_0[0x8];
9054         u8         event_type[0x8];
9055         u8         reserved_at_10[0x8];
9056         u8         event_sub_type[0x8];
9057
9058         u8         reserved_at_20[0xe0];
9059
9060         union mlx5_ifc_event_auto_bits event_data;
9061
9062         u8         reserved_at_1e0[0x10];
9063         u8         signature[0x8];
9064         u8         reserved_at_1f8[0x7];
9065         u8         owner[0x1];
9066 };
9067
9068 enum {
9069         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9070 };
9071
9072 struct mlx5_ifc_cmd_queue_entry_bits {
9073         u8         type[0x8];
9074         u8         reserved_at_8[0x18];
9075
9076         u8         input_length[0x20];
9077
9078         u8         input_mailbox_pointer_63_32[0x20];
9079
9080         u8         input_mailbox_pointer_31_9[0x17];
9081         u8         reserved_at_77[0x9];
9082
9083         u8         command_input_inline_data[16][0x8];
9084
9085         u8         command_output_inline_data[16][0x8];
9086
9087         u8         output_mailbox_pointer_63_32[0x20];
9088
9089         u8         output_mailbox_pointer_31_9[0x17];
9090         u8         reserved_at_1b7[0x9];
9091
9092         u8         output_length[0x20];
9093
9094         u8         token[0x8];
9095         u8         signature[0x8];
9096         u8         reserved_at_1f0[0x8];
9097         u8         status[0x7];
9098         u8         ownership[0x1];
9099 };
9100
9101 struct mlx5_ifc_cmd_out_bits {
9102         u8         status[0x8];
9103         u8         reserved_at_8[0x18];
9104
9105         u8         syndrome[0x20];
9106
9107         u8         command_output[0x20];
9108 };
9109
9110 struct mlx5_ifc_cmd_in_bits {
9111         u8         opcode[0x10];
9112         u8         reserved_at_10[0x10];
9113
9114         u8         reserved_at_20[0x10];
9115         u8         op_mod[0x10];
9116
9117         u8         command[0][0x20];
9118 };
9119
9120 struct mlx5_ifc_cmd_if_box_bits {
9121         u8         mailbox_data[512][0x8];
9122
9123         u8         reserved_at_1000[0x180];
9124
9125         u8         next_pointer_63_32[0x20];
9126
9127         u8         next_pointer_31_10[0x16];
9128         u8         reserved_at_11b6[0xa];
9129
9130         u8         block_number[0x20];
9131
9132         u8         reserved_at_11e0[0x8];
9133         u8         token[0x8];
9134         u8         ctrl_signature[0x8];
9135         u8         signature[0x8];
9136 };
9137
9138 struct mlx5_ifc_mtt_bits {
9139         u8         ptag_63_32[0x20];
9140
9141         u8         ptag_31_8[0x18];
9142         u8         reserved_at_38[0x6];
9143         u8         wr_en[0x1];
9144         u8         rd_en[0x1];
9145 };
9146
9147 struct mlx5_ifc_query_wol_rol_out_bits {
9148         u8         status[0x8];
9149         u8         reserved_at_8[0x18];
9150
9151         u8         syndrome[0x20];
9152
9153         u8         reserved_at_40[0x10];
9154         u8         rol_mode[0x8];
9155         u8         wol_mode[0x8];
9156
9157         u8         reserved_at_60[0x20];
9158 };
9159
9160 struct mlx5_ifc_query_wol_rol_in_bits {
9161         u8         opcode[0x10];
9162         u8         reserved_at_10[0x10];
9163
9164         u8         reserved_at_20[0x10];
9165         u8         op_mod[0x10];
9166
9167         u8         reserved_at_40[0x40];
9168 };
9169
9170 struct mlx5_ifc_set_wol_rol_out_bits {
9171         u8         status[0x8];
9172         u8         reserved_at_8[0x18];
9173
9174         u8         syndrome[0x20];
9175
9176         u8         reserved_at_40[0x40];
9177 };
9178
9179 struct mlx5_ifc_set_wol_rol_in_bits {
9180         u8         opcode[0x10];
9181         u8         reserved_at_10[0x10];
9182
9183         u8         reserved_at_20[0x10];
9184         u8         op_mod[0x10];
9185
9186         u8         rol_mode_valid[0x1];
9187         u8         wol_mode_valid[0x1];
9188         u8         reserved_at_42[0xe];
9189         u8         rol_mode[0x8];
9190         u8         wol_mode[0x8];
9191
9192         u8         reserved_at_60[0x20];
9193 };
9194
9195 enum {
9196         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
9197         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
9198         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
9199 };
9200
9201 enum {
9202         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
9203         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
9204         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
9205 };
9206
9207 enum {
9208         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
9209         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
9210         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
9211         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
9212         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
9213         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
9214         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
9215         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
9216         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
9217         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
9218         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
9219 };
9220
9221 struct mlx5_ifc_initial_seg_bits {
9222         u8         fw_rev_minor[0x10];
9223         u8         fw_rev_major[0x10];
9224
9225         u8         cmd_interface_rev[0x10];
9226         u8         fw_rev_subminor[0x10];
9227
9228         u8         reserved_at_40[0x40];
9229
9230         u8         cmdq_phy_addr_63_32[0x20];
9231
9232         u8         cmdq_phy_addr_31_12[0x14];
9233         u8         reserved_at_b4[0x2];
9234         u8         nic_interface[0x2];
9235         u8         log_cmdq_size[0x4];
9236         u8         log_cmdq_stride[0x4];
9237
9238         u8         command_doorbell_vector[0x20];
9239
9240         u8         reserved_at_e0[0xf00];
9241
9242         u8         initializing[0x1];
9243         u8         reserved_at_fe1[0x4];
9244         u8         nic_interface_supported[0x3];
9245         u8         embedded_cpu[0x1];
9246         u8         reserved_at_fe9[0x17];
9247
9248         struct mlx5_ifc_health_buffer_bits health_buffer;
9249
9250         u8         no_dram_nic_offset[0x20];
9251
9252         u8         reserved_at_1220[0x6e40];
9253
9254         u8         reserved_at_8060[0x1f];
9255         u8         clear_int[0x1];
9256
9257         u8         health_syndrome[0x8];
9258         u8         health_counter[0x18];
9259
9260         u8         reserved_at_80a0[0x17fc0];
9261 };
9262
9263 struct mlx5_ifc_mtpps_reg_bits {
9264         u8         reserved_at_0[0xc];
9265         u8         cap_number_of_pps_pins[0x4];
9266         u8         reserved_at_10[0x4];
9267         u8         cap_max_num_of_pps_in_pins[0x4];
9268         u8         reserved_at_18[0x4];
9269         u8         cap_max_num_of_pps_out_pins[0x4];
9270
9271         u8         reserved_at_20[0x24];
9272         u8         cap_pin_3_mode[0x4];
9273         u8         reserved_at_48[0x4];
9274         u8         cap_pin_2_mode[0x4];
9275         u8         reserved_at_50[0x4];
9276         u8         cap_pin_1_mode[0x4];
9277         u8         reserved_at_58[0x4];
9278         u8         cap_pin_0_mode[0x4];
9279
9280         u8         reserved_at_60[0x4];
9281         u8         cap_pin_7_mode[0x4];
9282         u8         reserved_at_68[0x4];
9283         u8         cap_pin_6_mode[0x4];
9284         u8         reserved_at_70[0x4];
9285         u8         cap_pin_5_mode[0x4];
9286         u8         reserved_at_78[0x4];
9287         u8         cap_pin_4_mode[0x4];
9288
9289         u8         field_select[0x20];
9290         u8         reserved_at_a0[0x60];
9291
9292         u8         enable[0x1];
9293         u8         reserved_at_101[0xb];
9294         u8         pattern[0x4];
9295         u8         reserved_at_110[0x4];
9296         u8         pin_mode[0x4];
9297         u8         pin[0x8];
9298
9299         u8         reserved_at_120[0x20];
9300
9301         u8         time_stamp[0x40];
9302
9303         u8         out_pulse_duration[0x10];
9304         u8         out_periodic_adjustment[0x10];
9305         u8         enhanced_out_periodic_adjustment[0x20];
9306
9307         u8         reserved_at_1c0[0x20];
9308 };
9309
9310 struct mlx5_ifc_mtppse_reg_bits {
9311         u8         reserved_at_0[0x18];
9312         u8         pin[0x8];
9313         u8         event_arm[0x1];
9314         u8         reserved_at_21[0x1b];
9315         u8         event_generation_mode[0x4];
9316         u8         reserved_at_40[0x40];
9317 };
9318
9319 struct mlx5_ifc_mcqs_reg_bits {
9320         u8         last_index_flag[0x1];
9321         u8         reserved_at_1[0x7];
9322         u8         fw_device[0x8];
9323         u8         component_index[0x10];
9324
9325         u8         reserved_at_20[0x10];
9326         u8         identifier[0x10];
9327
9328         u8         reserved_at_40[0x17];
9329         u8         component_status[0x5];
9330         u8         component_update_state[0x4];
9331
9332         u8         last_update_state_changer_type[0x4];
9333         u8         last_update_state_changer_host_id[0x4];
9334         u8         reserved_at_68[0x18];
9335 };
9336
9337 struct mlx5_ifc_mcqi_cap_bits {
9338         u8         supported_info_bitmask[0x20];
9339
9340         u8         component_size[0x20];
9341
9342         u8         max_component_size[0x20];
9343
9344         u8         log_mcda_word_size[0x4];
9345         u8         reserved_at_64[0xc];
9346         u8         mcda_max_write_size[0x10];
9347
9348         u8         rd_en[0x1];
9349         u8         reserved_at_81[0x1];
9350         u8         match_chip_id[0x1];
9351         u8         match_psid[0x1];
9352         u8         check_user_timestamp[0x1];
9353         u8         match_base_guid_mac[0x1];
9354         u8         reserved_at_86[0x1a];
9355 };
9356
9357 struct mlx5_ifc_mcqi_version_bits {
9358         u8         reserved_at_0[0x2];
9359         u8         build_time_valid[0x1];
9360         u8         user_defined_time_valid[0x1];
9361         u8         reserved_at_4[0x14];
9362         u8         version_string_length[0x8];
9363
9364         u8         version[0x20];
9365
9366         u8         build_time[0x40];
9367
9368         u8         user_defined_time[0x40];
9369
9370         u8         build_tool_version[0x20];
9371
9372         u8         reserved_at_e0[0x20];
9373
9374         u8         version_string[92][0x8];
9375 };
9376
9377 struct mlx5_ifc_mcqi_activation_method_bits {
9378         u8         pending_server_ac_power_cycle[0x1];
9379         u8         pending_server_dc_power_cycle[0x1];
9380         u8         pending_server_reboot[0x1];
9381         u8         pending_fw_reset[0x1];
9382         u8         auto_activate[0x1];
9383         u8         all_hosts_sync[0x1];
9384         u8         device_hw_reset[0x1];
9385         u8         reserved_at_7[0x19];
9386 };
9387
9388 union mlx5_ifc_mcqi_reg_data_bits {
9389         struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
9390         struct mlx5_ifc_mcqi_version_bits           mcqi_version;
9391         struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9392 };
9393
9394 struct mlx5_ifc_mcqi_reg_bits {
9395         u8         read_pending_component[0x1];
9396         u8         reserved_at_1[0xf];
9397         u8         component_index[0x10];
9398
9399         u8         reserved_at_20[0x20];
9400
9401         u8         reserved_at_40[0x1b];
9402         u8         info_type[0x5];
9403
9404         u8         info_size[0x20];
9405
9406         u8         offset[0x20];
9407
9408         u8         reserved_at_a0[0x10];
9409         u8         data_size[0x10];
9410
9411         union mlx5_ifc_mcqi_reg_data_bits data[0];
9412 };
9413
9414 struct mlx5_ifc_mcc_reg_bits {
9415         u8         reserved_at_0[0x4];
9416         u8         time_elapsed_since_last_cmd[0xc];
9417         u8         reserved_at_10[0x8];
9418         u8         instruction[0x8];
9419
9420         u8         reserved_at_20[0x10];
9421         u8         component_index[0x10];
9422
9423         u8         reserved_at_40[0x8];
9424         u8         update_handle[0x18];
9425
9426         u8         handle_owner_type[0x4];
9427         u8         handle_owner_host_id[0x4];
9428         u8         reserved_at_68[0x1];
9429         u8         control_progress[0x7];
9430         u8         error_code[0x8];
9431         u8         reserved_at_78[0x4];
9432         u8         control_state[0x4];
9433
9434         u8         component_size[0x20];
9435
9436         u8         reserved_at_a0[0x60];
9437 };
9438
9439 struct mlx5_ifc_mcda_reg_bits {
9440         u8         reserved_at_0[0x8];
9441         u8         update_handle[0x18];
9442
9443         u8         offset[0x20];
9444
9445         u8         reserved_at_40[0x10];
9446         u8         size[0x10];
9447
9448         u8         reserved_at_60[0x20];
9449
9450         u8         data[0][0x20];
9451 };
9452
9453 union mlx5_ifc_ports_control_registers_document_bits {
9454         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9455         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9456         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9457         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9458         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9459         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9460         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9461         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
9462         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
9463         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9464         struct mlx5_ifc_pamp_reg_bits pamp_reg;
9465         struct mlx5_ifc_paos_reg_bits paos_reg;
9466         struct mlx5_ifc_pcap_reg_bits pcap_reg;
9467         struct mlx5_ifc_peir_reg_bits peir_reg;
9468         struct mlx5_ifc_pelc_reg_bits pelc_reg;
9469         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9470         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
9471         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9472         struct mlx5_ifc_pifr_reg_bits pifr_reg;
9473         struct mlx5_ifc_pipg_reg_bits pipg_reg;
9474         struct mlx5_ifc_plbf_reg_bits plbf_reg;
9475         struct mlx5_ifc_plib_reg_bits plib_reg;
9476         struct mlx5_ifc_plpc_reg_bits plpc_reg;
9477         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9478         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9479         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9480         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9481         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9482         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9483         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9484         struct mlx5_ifc_ppad_reg_bits ppad_reg;
9485         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9486         struct mlx5_ifc_mpein_reg_bits mpein_reg;
9487         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
9488         struct mlx5_ifc_pplm_reg_bits pplm_reg;
9489         struct mlx5_ifc_pplr_reg_bits pplr_reg;
9490         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9491         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9492         struct mlx5_ifc_pspa_reg_bits pspa_reg;
9493         struct mlx5_ifc_ptas_reg_bits ptas_reg;
9494         struct mlx5_ifc_ptys_reg_bits ptys_reg;
9495         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
9496         struct mlx5_ifc_pude_reg_bits pude_reg;
9497         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9498         struct mlx5_ifc_slrg_reg_bits slrg_reg;
9499         struct mlx5_ifc_sltp_reg_bits sltp_reg;
9500         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9501         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
9502         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
9503         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9504         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
9505         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9506         struct mlx5_ifc_mcc_reg_bits mcc_reg;
9507         struct mlx5_ifc_mcda_reg_bits mcda_reg;
9508         u8         reserved_at_0[0x60e0];
9509 };
9510
9511 union mlx5_ifc_debug_enhancements_document_bits {
9512         struct mlx5_ifc_health_buffer_bits health_buffer;
9513         u8         reserved_at_0[0x200];
9514 };
9515
9516 union mlx5_ifc_uplink_pci_interface_document_bits {
9517         struct mlx5_ifc_initial_seg_bits initial_seg;
9518         u8         reserved_at_0[0x20060];
9519 };
9520
9521 struct mlx5_ifc_set_flow_table_root_out_bits {
9522         u8         status[0x8];
9523         u8         reserved_at_8[0x18];
9524
9525         u8         syndrome[0x20];
9526
9527         u8         reserved_at_40[0x40];
9528 };
9529
9530 struct mlx5_ifc_set_flow_table_root_in_bits {
9531         u8         opcode[0x10];
9532         u8         reserved_at_10[0x10];
9533
9534         u8         reserved_at_20[0x10];
9535         u8         op_mod[0x10];
9536
9537         u8         other_vport[0x1];
9538         u8         reserved_at_41[0xf];
9539         u8         vport_number[0x10];
9540
9541         u8         reserved_at_60[0x20];
9542
9543         u8         table_type[0x8];
9544         u8         reserved_at_88[0x18];
9545
9546         u8         reserved_at_a0[0x8];
9547         u8         table_id[0x18];
9548
9549         u8         reserved_at_c0[0x8];
9550         u8         underlay_qpn[0x18];
9551         u8         reserved_at_e0[0x120];
9552 };
9553
9554 enum {
9555         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
9556         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
9557 };
9558
9559 struct mlx5_ifc_modify_flow_table_out_bits {
9560         u8         status[0x8];
9561         u8         reserved_at_8[0x18];
9562
9563         u8         syndrome[0x20];
9564
9565         u8         reserved_at_40[0x40];
9566 };
9567
9568 struct mlx5_ifc_modify_flow_table_in_bits {
9569         u8         opcode[0x10];
9570         u8         reserved_at_10[0x10];
9571
9572         u8         reserved_at_20[0x10];
9573         u8         op_mod[0x10];
9574
9575         u8         other_vport[0x1];
9576         u8         reserved_at_41[0xf];
9577         u8         vport_number[0x10];
9578
9579         u8         reserved_at_60[0x10];
9580         u8         modify_field_select[0x10];
9581
9582         u8         table_type[0x8];
9583         u8         reserved_at_88[0x18];
9584
9585         u8         reserved_at_a0[0x8];
9586         u8         table_id[0x18];
9587
9588         struct mlx5_ifc_flow_table_context_bits flow_table_context;
9589 };
9590
9591 struct mlx5_ifc_ets_tcn_config_reg_bits {
9592         u8         g[0x1];
9593         u8         b[0x1];
9594         u8         r[0x1];
9595         u8         reserved_at_3[0x9];
9596         u8         group[0x4];
9597         u8         reserved_at_10[0x9];
9598         u8         bw_allocation[0x7];
9599
9600         u8         reserved_at_20[0xc];
9601         u8         max_bw_units[0x4];
9602         u8         reserved_at_30[0x8];
9603         u8         max_bw_value[0x8];
9604 };
9605
9606 struct mlx5_ifc_ets_global_config_reg_bits {
9607         u8         reserved_at_0[0x2];
9608         u8         r[0x1];
9609         u8         reserved_at_3[0x1d];
9610
9611         u8         reserved_at_20[0xc];
9612         u8         max_bw_units[0x4];
9613         u8         reserved_at_30[0x8];
9614         u8         max_bw_value[0x8];
9615 };
9616
9617 struct mlx5_ifc_qetc_reg_bits {
9618         u8                                         reserved_at_0[0x8];
9619         u8                                         port_number[0x8];
9620         u8                                         reserved_at_10[0x30];
9621
9622         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
9623         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9624 };
9625
9626 struct mlx5_ifc_qpdpm_dscp_reg_bits {
9627         u8         e[0x1];
9628         u8         reserved_at_01[0x0b];
9629         u8         prio[0x04];
9630 };
9631
9632 struct mlx5_ifc_qpdpm_reg_bits {
9633         u8                                     reserved_at_0[0x8];
9634         u8                                     local_port[0x8];
9635         u8                                     reserved_at_10[0x10];
9636         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
9637 };
9638
9639 struct mlx5_ifc_qpts_reg_bits {
9640         u8         reserved_at_0[0x8];
9641         u8         local_port[0x8];
9642         u8         reserved_at_10[0x2d];
9643         u8         trust_state[0x3];
9644 };
9645
9646 struct mlx5_ifc_pptb_reg_bits {
9647         u8         reserved_at_0[0x2];
9648         u8         mm[0x2];
9649         u8         reserved_at_4[0x4];
9650         u8         local_port[0x8];
9651         u8         reserved_at_10[0x6];
9652         u8         cm[0x1];
9653         u8         um[0x1];
9654         u8         pm[0x8];
9655
9656         u8         prio_x_buff[0x20];
9657
9658         u8         pm_msb[0x8];
9659         u8         reserved_at_48[0x10];
9660         u8         ctrl_buff[0x4];
9661         u8         untagged_buff[0x4];
9662 };
9663
9664 struct mlx5_ifc_pbmc_reg_bits {
9665         u8         reserved_at_0[0x8];
9666         u8         local_port[0x8];
9667         u8         reserved_at_10[0x10];
9668
9669         u8         xoff_timer_value[0x10];
9670         u8         xoff_refresh[0x10];
9671
9672         u8         reserved_at_40[0x9];
9673         u8         fullness_threshold[0x7];
9674         u8         port_buffer_size[0x10];
9675
9676         struct mlx5_ifc_bufferx_reg_bits buffer[10];
9677
9678         u8         reserved_at_2e0[0x80];
9679 };
9680
9681 struct mlx5_ifc_qtct_reg_bits {
9682         u8         reserved_at_0[0x8];
9683         u8         port_number[0x8];
9684         u8         reserved_at_10[0xd];
9685         u8         prio[0x3];
9686
9687         u8         reserved_at_20[0x1d];
9688         u8         tclass[0x3];
9689 };
9690
9691 struct mlx5_ifc_mcia_reg_bits {
9692         u8         l[0x1];
9693         u8         reserved_at_1[0x7];
9694         u8         module[0x8];
9695         u8         reserved_at_10[0x8];
9696         u8         status[0x8];
9697
9698         u8         i2c_device_address[0x8];
9699         u8         page_number[0x8];
9700         u8         device_address[0x10];
9701
9702         u8         reserved_at_40[0x10];
9703         u8         size[0x10];
9704
9705         u8         reserved_at_60[0x20];
9706
9707         u8         dword_0[0x20];
9708         u8         dword_1[0x20];
9709         u8         dword_2[0x20];
9710         u8         dword_3[0x20];
9711         u8         dword_4[0x20];
9712         u8         dword_5[0x20];
9713         u8         dword_6[0x20];
9714         u8         dword_7[0x20];
9715         u8         dword_8[0x20];
9716         u8         dword_9[0x20];
9717         u8         dword_10[0x20];
9718         u8         dword_11[0x20];
9719 };
9720
9721 struct mlx5_ifc_dcbx_param_bits {
9722         u8         dcbx_cee_cap[0x1];
9723         u8         dcbx_ieee_cap[0x1];
9724         u8         dcbx_standby_cap[0x1];
9725         u8         reserved_at_3[0x5];
9726         u8         port_number[0x8];
9727         u8         reserved_at_10[0xa];
9728         u8         max_application_table_size[6];
9729         u8         reserved_at_20[0x15];
9730         u8         version_oper[0x3];
9731         u8         reserved_at_38[5];
9732         u8         version_admin[0x3];
9733         u8         willing_admin[0x1];
9734         u8         reserved_at_41[0x3];
9735         u8         pfc_cap_oper[0x4];
9736         u8         reserved_at_48[0x4];
9737         u8         pfc_cap_admin[0x4];
9738         u8         reserved_at_50[0x4];
9739         u8         num_of_tc_oper[0x4];
9740         u8         reserved_at_58[0x4];
9741         u8         num_of_tc_admin[0x4];
9742         u8         remote_willing[0x1];
9743         u8         reserved_at_61[3];
9744         u8         remote_pfc_cap[4];
9745         u8         reserved_at_68[0x14];
9746         u8         remote_num_of_tc[0x4];
9747         u8         reserved_at_80[0x18];
9748         u8         error[0x8];
9749         u8         reserved_at_a0[0x160];
9750 };
9751
9752 struct mlx5_ifc_lagc_bits {
9753         u8         reserved_at_0[0x1d];
9754         u8         lag_state[0x3];
9755
9756         u8         reserved_at_20[0x14];
9757         u8         tx_remap_affinity_2[0x4];
9758         u8         reserved_at_38[0x4];
9759         u8         tx_remap_affinity_1[0x4];
9760 };
9761
9762 struct mlx5_ifc_create_lag_out_bits {
9763         u8         status[0x8];
9764         u8         reserved_at_8[0x18];
9765
9766         u8         syndrome[0x20];
9767
9768         u8         reserved_at_40[0x40];
9769 };
9770
9771 struct mlx5_ifc_create_lag_in_bits {
9772         u8         opcode[0x10];
9773         u8         reserved_at_10[0x10];
9774
9775         u8         reserved_at_20[0x10];
9776         u8         op_mod[0x10];
9777
9778         struct mlx5_ifc_lagc_bits ctx;
9779 };
9780
9781 struct mlx5_ifc_modify_lag_out_bits {
9782         u8         status[0x8];
9783         u8         reserved_at_8[0x18];
9784
9785         u8         syndrome[0x20];
9786
9787         u8         reserved_at_40[0x40];
9788 };
9789
9790 struct mlx5_ifc_modify_lag_in_bits {
9791         u8         opcode[0x10];
9792         u8         reserved_at_10[0x10];
9793
9794         u8         reserved_at_20[0x10];
9795         u8         op_mod[0x10];
9796
9797         u8         reserved_at_40[0x20];
9798         u8         field_select[0x20];
9799
9800         struct mlx5_ifc_lagc_bits ctx;
9801 };
9802
9803 struct mlx5_ifc_query_lag_out_bits {
9804         u8         status[0x8];
9805         u8         reserved_at_8[0x18];
9806
9807         u8         syndrome[0x20];
9808
9809         struct mlx5_ifc_lagc_bits ctx;
9810 };
9811
9812 struct mlx5_ifc_query_lag_in_bits {
9813         u8         opcode[0x10];
9814         u8         reserved_at_10[0x10];
9815
9816         u8         reserved_at_20[0x10];
9817         u8         op_mod[0x10];
9818
9819         u8         reserved_at_40[0x40];
9820 };
9821
9822 struct mlx5_ifc_destroy_lag_out_bits {
9823         u8         status[0x8];
9824         u8         reserved_at_8[0x18];
9825
9826         u8         syndrome[0x20];
9827
9828         u8         reserved_at_40[0x40];
9829 };
9830
9831 struct mlx5_ifc_destroy_lag_in_bits {
9832         u8         opcode[0x10];
9833         u8         reserved_at_10[0x10];
9834
9835         u8         reserved_at_20[0x10];
9836         u8         op_mod[0x10];
9837
9838         u8         reserved_at_40[0x40];
9839 };
9840
9841 struct mlx5_ifc_create_vport_lag_out_bits {
9842         u8         status[0x8];
9843         u8         reserved_at_8[0x18];
9844
9845         u8         syndrome[0x20];
9846
9847         u8         reserved_at_40[0x40];
9848 };
9849
9850 struct mlx5_ifc_create_vport_lag_in_bits {
9851         u8         opcode[0x10];
9852         u8         reserved_at_10[0x10];
9853
9854         u8         reserved_at_20[0x10];
9855         u8         op_mod[0x10];
9856
9857         u8         reserved_at_40[0x40];
9858 };
9859
9860 struct mlx5_ifc_destroy_vport_lag_out_bits {
9861         u8         status[0x8];
9862         u8         reserved_at_8[0x18];
9863
9864         u8         syndrome[0x20];
9865
9866         u8         reserved_at_40[0x40];
9867 };
9868
9869 struct mlx5_ifc_destroy_vport_lag_in_bits {
9870         u8         opcode[0x10];
9871         u8         reserved_at_10[0x10];
9872
9873         u8         reserved_at_20[0x10];
9874         u8         op_mod[0x10];
9875
9876         u8         reserved_at_40[0x40];
9877 };
9878
9879 struct mlx5_ifc_alloc_memic_in_bits {
9880         u8         opcode[0x10];
9881         u8         reserved_at_10[0x10];
9882
9883         u8         reserved_at_20[0x10];
9884         u8         op_mod[0x10];
9885
9886         u8         reserved_at_30[0x20];
9887
9888         u8         reserved_at_40[0x18];
9889         u8         log_memic_addr_alignment[0x8];
9890
9891         u8         range_start_addr[0x40];
9892
9893         u8         range_size[0x20];
9894
9895         u8         memic_size[0x20];
9896 };
9897
9898 struct mlx5_ifc_alloc_memic_out_bits {
9899         u8         status[0x8];
9900         u8         reserved_at_8[0x18];
9901
9902         u8         syndrome[0x20];
9903
9904         u8         memic_start_addr[0x40];
9905 };
9906
9907 struct mlx5_ifc_dealloc_memic_in_bits {
9908         u8         opcode[0x10];
9909         u8         reserved_at_10[0x10];
9910
9911         u8         reserved_at_20[0x10];
9912         u8         op_mod[0x10];
9913
9914         u8         reserved_at_40[0x40];
9915
9916         u8         memic_start_addr[0x40];
9917
9918         u8         memic_size[0x20];
9919
9920         u8         reserved_at_e0[0x20];
9921 };
9922
9923 struct mlx5_ifc_dealloc_memic_out_bits {
9924         u8         status[0x8];
9925         u8         reserved_at_8[0x18];
9926
9927         u8         syndrome[0x20];
9928
9929         u8         reserved_at_40[0x40];
9930 };
9931
9932 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9933         u8         opcode[0x10];
9934         u8         uid[0x10];
9935
9936         u8         vhca_tunnel_id[0x10];
9937         u8         obj_type[0x10];
9938
9939         u8         obj_id[0x20];
9940
9941         u8         reserved_at_60[0x20];
9942 };
9943
9944 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9945         u8         status[0x8];
9946         u8         reserved_at_8[0x18];
9947
9948         u8         syndrome[0x20];
9949
9950         u8         obj_id[0x20];
9951
9952         u8         reserved_at_60[0x20];
9953 };
9954
9955 struct mlx5_ifc_umem_bits {
9956         u8         reserved_at_0[0x80];
9957
9958         u8         reserved_at_80[0x1b];
9959         u8         log_page_size[0x5];
9960
9961         u8         page_offset[0x20];
9962
9963         u8         num_of_mtt[0x40];
9964
9965         struct mlx5_ifc_mtt_bits  mtt[0];
9966 };
9967
9968 struct mlx5_ifc_uctx_bits {
9969         u8         cap[0x20];
9970
9971         u8         reserved_at_20[0x160];
9972 };
9973
9974 struct mlx5_ifc_sw_icm_bits {
9975         u8         modify_field_select[0x40];
9976
9977         u8         reserved_at_40[0x18];
9978         u8         log_sw_icm_size[0x8];
9979
9980         u8         reserved_at_60[0x20];
9981
9982         u8         sw_icm_start_addr[0x40];
9983
9984         u8         reserved_at_c0[0x140];
9985 };
9986
9987 struct mlx5_ifc_geneve_tlv_option_bits {
9988         u8         modify_field_select[0x40];
9989
9990         u8         reserved_at_40[0x18];
9991         u8         geneve_option_fte_index[0x8];
9992
9993         u8         option_class[0x10];
9994         u8         option_type[0x8];
9995         u8         reserved_at_78[0x3];
9996         u8         option_data_length[0x5];
9997
9998         u8         reserved_at_80[0x180];
9999 };
10000
10001 struct mlx5_ifc_create_umem_in_bits {
10002         u8         opcode[0x10];
10003         u8         uid[0x10];
10004
10005         u8         reserved_at_20[0x10];
10006         u8         op_mod[0x10];
10007
10008         u8         reserved_at_40[0x40];
10009
10010         struct mlx5_ifc_umem_bits  umem;
10011 };
10012
10013 struct mlx5_ifc_create_uctx_in_bits {
10014         u8         opcode[0x10];
10015         u8         reserved_at_10[0x10];
10016
10017         u8         reserved_at_20[0x10];
10018         u8         op_mod[0x10];
10019
10020         u8         reserved_at_40[0x40];
10021
10022         struct mlx5_ifc_uctx_bits  uctx;
10023 };
10024
10025 struct mlx5_ifc_destroy_uctx_in_bits {
10026         u8         opcode[0x10];
10027         u8         reserved_at_10[0x10];
10028
10029         u8         reserved_at_20[0x10];
10030         u8         op_mod[0x10];
10031
10032         u8         reserved_at_40[0x10];
10033         u8         uid[0x10];
10034
10035         u8         reserved_at_60[0x20];
10036 };
10037
10038 struct mlx5_ifc_create_sw_icm_in_bits {
10039         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
10040         struct mlx5_ifc_sw_icm_bits                   sw_icm;
10041 };
10042
10043 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
10044         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
10045         struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
10046 };
10047
10048 struct mlx5_ifc_mtrc_string_db_param_bits {
10049         u8         string_db_base_address[0x20];
10050
10051         u8         reserved_at_20[0x8];
10052         u8         string_db_size[0x18];
10053 };
10054
10055 struct mlx5_ifc_mtrc_cap_bits {
10056         u8         trace_owner[0x1];
10057         u8         trace_to_memory[0x1];
10058         u8         reserved_at_2[0x4];
10059         u8         trc_ver[0x2];
10060         u8         reserved_at_8[0x14];
10061         u8         num_string_db[0x4];
10062
10063         u8         first_string_trace[0x8];
10064         u8         num_string_trace[0x8];
10065         u8         reserved_at_30[0x28];
10066
10067         u8         log_max_trace_buffer_size[0x8];
10068
10069         u8         reserved_at_60[0x20];
10070
10071         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
10072
10073         u8         reserved_at_280[0x180];
10074 };
10075
10076 struct mlx5_ifc_mtrc_conf_bits {
10077         u8         reserved_at_0[0x1c];
10078         u8         trace_mode[0x4];
10079         u8         reserved_at_20[0x18];
10080         u8         log_trace_buffer_size[0x8];
10081         u8         trace_mkey[0x20];
10082         u8         reserved_at_60[0x3a0];
10083 };
10084
10085 struct mlx5_ifc_mtrc_stdb_bits {
10086         u8         string_db_index[0x4];
10087         u8         reserved_at_4[0x4];
10088         u8         read_size[0x18];
10089         u8         start_offset[0x20];
10090         u8         string_db_data[0];
10091 };
10092
10093 struct mlx5_ifc_mtrc_ctrl_bits {
10094         u8         trace_status[0x2];
10095         u8         reserved_at_2[0x2];
10096         u8         arm_event[0x1];
10097         u8         reserved_at_5[0xb];
10098         u8         modify_field_select[0x10];
10099         u8         reserved_at_20[0x2b];
10100         u8         current_timestamp52_32[0x15];
10101         u8         current_timestamp31_0[0x20];
10102         u8         reserved_at_80[0x180];
10103 };
10104
10105 struct mlx5_ifc_host_params_context_bits {
10106         u8         host_number[0x8];
10107         u8         reserved_at_8[0x7];
10108         u8         host_pf_disabled[0x1];
10109         u8         host_num_of_vfs[0x10];
10110
10111         u8         host_total_vfs[0x10];
10112         u8         host_pci_bus[0x10];
10113
10114         u8         reserved_at_40[0x10];
10115         u8         host_pci_device[0x10];
10116
10117         u8         reserved_at_60[0x10];
10118         u8         host_pci_function[0x10];
10119
10120         u8         reserved_at_80[0x180];
10121 };
10122
10123 struct mlx5_ifc_query_esw_functions_in_bits {
10124         u8         opcode[0x10];
10125         u8         reserved_at_10[0x10];
10126
10127         u8         reserved_at_20[0x10];
10128         u8         op_mod[0x10];
10129
10130         u8         reserved_at_40[0x40];
10131 };
10132
10133 struct mlx5_ifc_query_esw_functions_out_bits {
10134         u8         status[0x8];
10135         u8         reserved_at_8[0x18];
10136
10137         u8         syndrome[0x20];
10138
10139         u8         reserved_at_40[0x40];
10140
10141         struct mlx5_ifc_host_params_context_bits host_params_context;
10142
10143         u8         reserved_at_280[0x180];
10144         u8         host_sf_enable[0][0x40];
10145 };
10146
10147 struct mlx5_ifc_sf_partition_bits {
10148         u8         reserved_at_0[0x10];
10149         u8         log_num_sf[0x8];
10150         u8         log_sf_bar_size[0x8];
10151 };
10152
10153 struct mlx5_ifc_query_sf_partitions_out_bits {
10154         u8         status[0x8];
10155         u8         reserved_at_8[0x18];
10156
10157         u8         syndrome[0x20];
10158
10159         u8         reserved_at_40[0x18];
10160         u8         num_sf_partitions[0x8];
10161
10162         u8         reserved_at_60[0x20];
10163
10164         struct mlx5_ifc_sf_partition_bits sf_partition[0];
10165 };
10166
10167 struct mlx5_ifc_query_sf_partitions_in_bits {
10168         u8         opcode[0x10];
10169         u8         reserved_at_10[0x10];
10170
10171         u8         reserved_at_20[0x10];
10172         u8         op_mod[0x10];
10173
10174         u8         reserved_at_40[0x40];
10175 };
10176
10177 struct mlx5_ifc_dealloc_sf_out_bits {
10178         u8         status[0x8];
10179         u8         reserved_at_8[0x18];
10180
10181         u8         syndrome[0x20];
10182
10183         u8         reserved_at_40[0x40];
10184 };
10185
10186 struct mlx5_ifc_dealloc_sf_in_bits {
10187         u8         opcode[0x10];
10188         u8         reserved_at_10[0x10];
10189
10190         u8         reserved_at_20[0x10];
10191         u8         op_mod[0x10];
10192
10193         u8         reserved_at_40[0x10];
10194         u8         function_id[0x10];
10195
10196         u8         reserved_at_60[0x20];
10197 };
10198
10199 struct mlx5_ifc_alloc_sf_out_bits {
10200         u8         status[0x8];
10201         u8         reserved_at_8[0x18];
10202
10203         u8         syndrome[0x20];
10204
10205         u8         reserved_at_40[0x40];
10206 };
10207
10208 struct mlx5_ifc_alloc_sf_in_bits {
10209         u8         opcode[0x10];
10210         u8         reserved_at_10[0x10];
10211
10212         u8         reserved_at_20[0x10];
10213         u8         op_mod[0x10];
10214
10215         u8         reserved_at_40[0x10];
10216         u8         function_id[0x10];
10217
10218         u8         reserved_at_60[0x20];
10219 };
10220
10221 struct mlx5_ifc_affiliated_event_header_bits {
10222         u8         reserved_at_0[0x10];
10223         u8         obj_type[0x10];
10224
10225         u8         obj_id[0x20];
10226 };
10227
10228 enum {
10229         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
10230 };
10231
10232 enum {
10233         MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10234 };
10235
10236 struct mlx5_ifc_encryption_key_obj_bits {
10237         u8         modify_field_select[0x40];
10238
10239         u8         reserved_at_40[0x14];
10240         u8         key_size[0x4];
10241         u8         reserved_at_58[0x4];
10242         u8         key_type[0x4];
10243
10244         u8         reserved_at_60[0x8];
10245         u8         pd[0x18];
10246
10247         u8         reserved_at_80[0x180];
10248         u8         key[8][0x20];
10249
10250         u8         reserved_at_300[0x500];
10251 };
10252
10253 struct mlx5_ifc_create_encryption_key_in_bits {
10254         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10255         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10256 };
10257
10258 enum {
10259         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10260         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10261 };
10262
10263 enum {
10264         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
10265 };
10266
10267 struct mlx5_ifc_tls_static_params_bits {
10268         u8         const_2[0x2];
10269         u8         tls_version[0x4];
10270         u8         const_1[0x2];
10271         u8         reserved_at_8[0x14];
10272         u8         encryption_standard[0x4];
10273
10274         u8         reserved_at_20[0x20];
10275
10276         u8         initial_record_number[0x40];
10277
10278         u8         resync_tcp_sn[0x20];
10279
10280         u8         gcm_iv[0x20];
10281
10282         u8         implicit_iv[0x40];
10283
10284         u8         reserved_at_100[0x8];
10285         u8         dek_index[0x18];
10286
10287         u8         reserved_at_120[0xe0];
10288 };
10289
10290 struct mlx5_ifc_tls_progress_params_bits {
10291         u8         reserved_at_0[0x8];
10292         u8         tisn[0x18];
10293
10294         u8         next_record_tcp_sn[0x20];
10295
10296         u8         hw_resync_tcp_sn[0x20];
10297
10298         u8         record_tracker_state[0x2];
10299         u8         auth_state[0x2];
10300         u8         reserved_at_64[0x4];
10301         u8         hw_offset_record_number[0x18];
10302 };
10303
10304 #endif /* MLX5_IFC_H */