2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
41 #include <linux/crash_dump.h>
43 #include <linux/refcount.h>
45 #include <linux/timecounter.h>
47 #define DEFAULT_UAR_PAGE_SHIFT 12
49 #define MAX_MSIX_P_PORT 17
51 #define MIN_MSIX_P_PORT 5
52 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \
53 (dev_cap).num_ports * MIN_MSIX_P_PORT)
55 #define MLX4_MAX_100M_UNITS_VAL 255 /*
56 * work around: can't set values
57 * greater then this value when
58 * using 100 Mbps units.
60 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
61 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
62 #define MLX4_RATELIMIT_DEFAULT 0x00ff
64 #define MLX4_ROCE_MAX_GIDS 128
65 #define MLX4_ROCE_PF_GIDS 16
68 MLX4_FLAG_MSI_X = 1 << 0,
69 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
70 MLX4_FLAG_MASTER = 1 << 2,
71 MLX4_FLAG_SLAVE = 1 << 3,
72 MLX4_FLAG_SRIOV = 1 << 4,
73 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
74 MLX4_FLAG_BONDED = 1 << 7,
75 MLX4_FLAG_SECURE_HOST = 1 << 8,
79 MLX4_PORT_CAP_IS_SM = 1 << 1,
80 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
85 MLX4_MAX_PORT_PKEYS = 128,
86 MLX4_MAX_PORT_GIDS = 128
89 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
90 * These qkeys must not be allowed for general use. This is a 64k range,
91 * and to test for violation, we use the mask (protect against future chg).
93 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
94 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
97 MLX4_BOARD_ID_LEN = 64
101 MLX4_MAX_NUM_PF = 16,
102 MLX4_MAX_NUM_VF = 126,
103 MLX4_MAX_NUM_VF_P_PORT = 64,
104 MLX4_MFUNC_MAX = 128,
105 MLX4_MAX_EQ_NUM = 1024,
106 MLX4_MFUNC_EQ_NUM = 4,
107 MLX4_MFUNC_MAX_EQES = 8,
108 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
111 /* Driver supports 3 different device methods to manage traffic steering:
112 * -device managed - High level API for ib and eth flow steering. FW is
113 * managing flow steering tables.
114 * - B0 steering mode - Common low level API for ib and (if supported) eth.
115 * - A0 steering mode - Limited low level API for eth. In case of IB,
119 MLX4_STEERING_MODE_A0,
120 MLX4_STEERING_MODE_B0,
121 MLX4_STEERING_MODE_DEVICE_MANAGED
125 MLX4_STEERING_DMFS_A0_DEFAULT,
126 MLX4_STEERING_DMFS_A0_DYNAMIC,
127 MLX4_STEERING_DMFS_A0_STATIC,
128 MLX4_STEERING_DMFS_A0_DISABLE,
129 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
132 static inline const char *mlx4_steering_mode_str(int steering_mode)
134 switch (steering_mode) {
135 case MLX4_STEERING_MODE_A0:
136 return "A0 steering";
138 case MLX4_STEERING_MODE_B0:
139 return "B0 steering";
141 case MLX4_STEERING_MODE_DEVICE_MANAGED:
142 return "Device managed flow steering";
145 return "Unrecognize steering mode";
150 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
151 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
155 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
156 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
157 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
158 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
159 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
160 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
161 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
162 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
163 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
164 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
165 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
166 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
167 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
168 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
169 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
170 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
171 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
172 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
173 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
174 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
175 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
176 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
177 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
178 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
179 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
180 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52,
181 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
182 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
183 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
184 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
185 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
189 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
190 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
191 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
192 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
193 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
194 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
195 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
196 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
197 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
198 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
199 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
200 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11,
201 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12,
202 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13,
203 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14,
204 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15,
205 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16,
206 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17,
207 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
208 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19,
209 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
210 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21,
211 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22,
212 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23,
213 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24,
214 MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25,
215 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26,
216 MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27,
217 MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28,
218 MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29,
219 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30,
220 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31,
221 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1ULL << 32,
222 MLX4_DEV_CAP_FLAG2_ROCE_V1_V2 = 1ULL << 33,
223 MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER = 1ULL << 34,
224 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT = 1ULL << 35,
225 MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP = 1ULL << 36,
226 MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT = 1ULL << 37,
227 MLX4_DEV_CAP_FLAG2_USER_MAC_EN = 1ULL << 38,
228 MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW = 1ULL << 39,
229 MLX4_DEV_CAP_FLAG2_SW_CQ_INIT = 1ULL << 40,
233 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0,
234 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1
238 MLX4_VF_CAP_FLAG_RESET = 1 << 0
241 /* bit enums for an 8-bit flags field indicating special use
242 * QPs which require special handling in qp_reserve_range.
243 * Currently, this only includes QPs used by the ETH interface,
244 * where we expect to use blueflame. These QPs must not have
245 * bits 6 and 7 set in their qp number.
247 * This enum may use only bits 0..7.
250 MLX4_RESERVE_A0_QP = 1 << 6,
251 MLX4_RESERVE_ETH_BF_QP = 1 << 7,
255 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
256 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1,
257 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2,
258 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3
262 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0,
263 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1,
264 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2
268 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
271 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
272 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
273 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
274 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
275 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
276 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
277 MLX4_BMME_FLAG_ROCE_V1_V2 = 1 << 19,
278 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24,
279 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28,
283 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP,
284 MLX4_FLAG_ROCE_V1_V2 = MLX4_BMME_FLAG_ROCE_V1_V2
288 MLX4_EVENT_TYPE_COMP = 0x00,
289 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
290 MLX4_EVENT_TYPE_COMM_EST = 0x02,
291 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
292 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
293 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
294 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
295 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
296 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
297 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
298 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
299 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
300 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
301 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
302 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
303 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
304 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
305 MLX4_EVENT_TYPE_CMD = 0x0a,
306 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
307 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
308 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
309 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
310 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
311 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
312 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e,
313 MLX4_EVENT_TYPE_NONE = 0xff,
317 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
318 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
322 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1,
323 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2,
327 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
330 enum slave_port_state {
336 enum slave_port_gen_event {
337 SLAVE_PORT_GEN_EVENT_DOWN = 0,
338 SLAVE_PORT_GEN_EVENT_UP,
339 SLAVE_PORT_GEN_EVENT_NONE,
342 enum slave_port_state_event {
343 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
344 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
345 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
346 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
350 MLX4_PERM_LOCAL_READ = 1 << 10,
351 MLX4_PERM_LOCAL_WRITE = 1 << 11,
352 MLX4_PERM_REMOTE_READ = 1 << 12,
353 MLX4_PERM_REMOTE_WRITE = 1 << 13,
354 MLX4_PERM_ATOMIC = 1 << 14,
355 MLX4_PERM_BIND_MW = 1 << 15,
356 MLX4_PERM_MASK = 0xFC00
360 MLX4_OPCODE_NOP = 0x00,
361 MLX4_OPCODE_SEND_INVAL = 0x01,
362 MLX4_OPCODE_RDMA_WRITE = 0x08,
363 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
364 MLX4_OPCODE_SEND = 0x0a,
365 MLX4_OPCODE_SEND_IMM = 0x0b,
366 MLX4_OPCODE_LSO = 0x0e,
367 MLX4_OPCODE_RDMA_READ = 0x10,
368 MLX4_OPCODE_ATOMIC_CS = 0x11,
369 MLX4_OPCODE_ATOMIC_FA = 0x12,
370 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
371 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
372 MLX4_OPCODE_BIND_MW = 0x18,
373 MLX4_OPCODE_FMR = 0x19,
374 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
375 MLX4_OPCODE_CONFIG_CMD = 0x1f,
377 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
378 MLX4_RECV_OPCODE_SEND = 0x01,
379 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
380 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
382 MLX4_CQE_OPCODE_ERROR = 0x1e,
383 MLX4_CQE_OPCODE_RESIZE = 0x16,
387 MLX4_STAT_RATE_OFFSET = 5
391 MLX4_PROT_IB_IPV6 = 0,
398 MLX4_MTT_FLAG_PRESENT = 1
401 enum mlx4_qp_region {
402 MLX4_QP_REGION_FW = 0,
403 MLX4_QP_REGION_RSS_RAW_ETH,
404 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH,
405 MLX4_QP_REGION_ETH_ADDR,
406 MLX4_QP_REGION_FC_ADDR,
407 MLX4_QP_REGION_FC_EXCH,
411 enum mlx4_port_type {
412 MLX4_PORT_TYPE_NONE = 0,
413 MLX4_PORT_TYPE_IB = 1,
414 MLX4_PORT_TYPE_ETH = 2,
415 MLX4_PORT_TYPE_AUTO = 3
418 enum mlx4_special_vlan_idx {
419 MLX4_NO_VLAN_IDX = 0,
424 enum mlx4_steer_type {
430 enum mlx4_resource_usage {
432 MLX4_RES_USAGE_DRIVER,
433 MLX4_RES_USAGE_USER_VERBS,
437 MLX4_NUM_FEXCH = 64 * 1024,
441 MLX4_MAX_FAST_REG_PAGES = 511,
446 * Max wqe size for rdma read is 512 bytes, so this
447 * limits our max_sge_rd as the wqe needs to fit:
448 * - ctrl segment (16 bytes)
449 * - rdma segment (16 bytes)
450 * - scatter elements (16 bytes each)
452 MLX4_MAX_SGE_RD = (512 - 16 - 16) / 16
456 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
457 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
458 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
459 MLX4_DEV_PMC_SUBTYPE_SL_TO_VL_MAP = 0x17,
462 /* Port mgmt change event handling */
464 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
465 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
466 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
467 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
468 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
471 union sl2vl_tbl_to_u64 {
477 MLX4_DEVICE_STATE_UP = 1 << 0,
478 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1,
482 MLX4_INTERFACE_STATE_UP = 1 << 0,
483 MLX4_INTERFACE_STATE_DELETION = 1 << 1,
484 MLX4_INTERFACE_STATE_NOWAIT = 1 << 2,
487 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
488 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
490 enum mlx4_module_id {
491 MLX4_MODULE_ID_SFP = 0x3,
492 MLX4_MODULE_ID_QSFP = 0xC,
493 MLX4_MODULE_ID_QSFP_PLUS = 0xD,
494 MLX4_MODULE_ID_QSFP28 = 0x11,
498 MLX4_QP_RATE_LIMIT_NONE = 0,
499 MLX4_QP_RATE_LIMIT_KBS = 1,
500 MLX4_QP_RATE_LIMIT_MBS = 2,
501 MLX4_QP_RATE_LIMIT_GBS = 3
504 struct mlx4_rate_limit_caps {
505 u16 num_rates; /* Number of different rates */
512 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
514 return (major << 32) | (minor << 16) | subminor;
517 struct mlx4_phys_caps {
518 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
519 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
523 u32 base_tunnel_sqpn;
526 struct mlx4_spec_qps {
538 int vl_cap[MLX4_MAX_PORTS + 1];
539 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
540 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
541 u64 def_mac[MLX4_MAX_PORTS + 1];
542 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
543 int gid_table_len[MLX4_MAX_PORTS + 1];
544 int pkey_table_len[MLX4_MAX_PORTS + 1];
545 int trans_type[MLX4_MAX_PORTS + 1];
546 int vendor_oui[MLX4_MAX_PORTS + 1];
547 int wavelength[MLX4_MAX_PORTS + 1];
548 u64 trans_code[MLX4_MAX_PORTS + 1];
549 int local_ca_ack_delay;
553 int bf_regs_per_page;
560 int max_qp_init_rdma;
561 int max_qp_dest_rdma;
563 struct mlx4_spec_qps *spec_qps;
574 int num_comp_vectors;
577 int fmr_reserved_mtts;
586 int dmfs_high_steer_mode;
587 int fs_log_max_ucast_qp_range_size;
599 u16 stat_rate_support;
600 u8 port_width_cap[MLX4_MAX_PORTS + 1];
603 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
605 int reserved_qps_base[MLX4_NUM_QP_REGION];
608 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
609 u8 supported_type[MLX4_MAX_PORTS + 1];
610 u8 suggested_type[MLX4_MAX_PORTS + 1];
611 u8 default_sense[MLX4_MAX_PORTS + 1];
612 u32 port_mask[MLX4_MAX_PORTS + 1];
613 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
615 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
620 u32 userspace_caps; /* userspace must be aware of these */
621 u32 function_caps; /* VFs must be aware of these */
623 u64 phys_port_id[MLX4_MAX_PORTS + 1];
624 int tunnel_offload_mode;
625 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
626 u8 phv_bit[MLX4_MAX_PORTS + 1];
627 u8 alloc_res_qp_mask;
628 u32 dmfs_high_rate_qpn_base;
629 u32 dmfs_high_rate_qpn_range;
631 bool wol_port[MLX4_MAX_PORTS + 1];
632 struct mlx4_rate_limit_caps rl_caps;
633 u32 health_buffer_addrs;
634 bool map_clock_to_user;
637 struct mlx4_buf_list {
643 struct mlx4_buf_list direct;
644 struct mlx4_buf_list *page_list;
657 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
660 struct mlx4_db_pgdir {
661 struct list_head list;
662 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
663 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
664 unsigned long *bits[2];
669 struct mlx4_ib_user_db_page;
674 struct mlx4_db_pgdir *pgdir;
675 struct mlx4_ib_user_db_page *user_page;
682 struct mlx4_hwq_resources {
706 enum mlx4_mw_type type;
713 struct list_head bf_list;
714 unsigned free_bf_bmap;
716 void __iomem *bf_map;
722 struct mlx4_uar *uar;
727 void (*comp) (struct mlx4_cq *);
728 void (*event) (struct mlx4_cq *, enum mlx4_event);
730 struct mlx4_uar *uar;
743 struct completion free;
745 struct list_head list;
746 void (*comp)(struct mlx4_cq *);
749 int reset_notify_added;
750 struct list_head reset_notify;
755 void (*event) (struct mlx4_qp *, enum mlx4_event);
760 struct completion free;
765 void (*event) (struct mlx4_srq *, enum mlx4_event);
773 struct completion free;
785 __be32 sl_tclass_flowlabel;
798 __be32 sl_tclass_flowlabel;
808 struct mlx4_eth_av eth;
811 /* Counters should be saturate once they reach their maximum value */
812 #define ASSIGN_32BIT_COUNTER(counter, value) do { \
813 if ((value) > U32_MAX) \
814 counter = cpu_to_be32(U32_MAX); \
816 counter = cpu_to_be32(value); \
819 struct mlx4_counter {
845 struct mlx4_fw_crdump {
846 bool snapshot_enable;
847 struct devlink_region *region_crspace;
848 struct devlink_region *region_fw_health;
851 enum mlx4_pci_status {
852 MLX4_PCI_STATUS_DISABLED,
853 MLX4_PCI_STATUS_ENABLED,
856 struct mlx4_dev_persistent {
857 struct pci_dev *pdev;
858 struct mlx4_dev *dev;
859 int nvfs[MLX4_MAX_PORTS + 1];
861 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1];
862 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1];
863 struct work_struct catas_work;
864 struct workqueue_struct *catas_wq;
865 struct mutex device_state_mutex; /* protect HW state */
867 struct mutex interface_state_mutex; /* protect SW state */
869 struct mutex pci_status_mutex; /* sync pci state */
870 enum mlx4_pci_status pci_status;
871 struct mlx4_fw_crdump crdump;
875 struct mlx4_dev_persistent *persist;
877 unsigned long num_slaves;
878 struct mlx4_caps caps;
879 struct mlx4_phys_caps phys_caps;
880 struct mlx4_quotas quotas;
881 struct radix_tree_root qp_table_tree;
884 char board_id[MLX4_BOARD_ID_LEN];
886 int oper_log_mgm_entry_size;
887 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
888 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
889 struct mlx4_vf_dev *dev_vfs;
893 struct mlx4_clock_params {
932 } __packed port_change;
934 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
936 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
937 } __packed comm_channel_arm;
942 } __packed mac_update;
945 } __packed flr_event;
947 __be16 current_temperature;
948 __be16 warning_threshold;
961 } __packed port_info;
964 __be32 tbl_entries_mask;
965 } __packed tbl_change_info;
968 } __packed sl2vl_tbl_change_info;
970 } __packed port_mgmt_change;
975 } __packed bad_cable;
982 struct mlx4_init_port_param {
996 #define MAD_IFC_DATA_SZ 192
997 /* MAD IFC Mailbox */
998 struct mlx4_mad_ifc {
1004 __be16 class_specific;
1013 u8 data[MAD_IFC_DATA_SZ];
1016 #define mlx4_foreach_port(port, dev, type) \
1017 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
1018 if ((type) == (dev)->caps.port_mask[(port)])
1020 #define mlx4_foreach_ib_transport_port(port, dev) \
1021 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
1022 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
1023 ((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_ETH))
1025 #define MLX4_INVALID_SLAVE_ID 0xFF
1026 #define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1)
1028 void handle_port_mgmt_change_event(struct work_struct *work);
1030 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
1032 return dev->caps.function;
1035 static inline int mlx4_is_master(struct mlx4_dev *dev)
1037 return dev->flags & MLX4_FLAG_MASTER;
1040 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
1042 return dev->phys_caps.base_sqpn + 8 +
1043 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
1046 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
1048 return (qpn < dev->phys_caps.base_sqpn + 8 +
1049 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) &&
1050 qpn >= dev->phys_caps.base_sqpn) ||
1051 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]);
1054 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
1056 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
1058 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
1064 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
1066 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
1069 static inline int mlx4_is_slave(struct mlx4_dev *dev)
1071 return dev->flags & MLX4_FLAG_SLAVE;
1074 static inline int mlx4_is_eth(struct mlx4_dev *dev, int port)
1076 return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1;
1079 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
1080 struct mlx4_buf *buf);
1081 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
1082 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
1084 if (buf->nbufs == 1)
1085 return buf->direct.buf + offset;
1087 return buf->page_list[offset >> PAGE_SHIFT].buf +
1088 (offset & (PAGE_SIZE - 1));
1091 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
1092 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
1093 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1094 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1096 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
1097 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
1098 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
1099 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
1101 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
1102 struct mlx4_mtt *mtt);
1103 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1104 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1106 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
1107 int npages, int page_shift, struct mlx4_mr *mr);
1108 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
1109 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
1110 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
1111 struct mlx4_mw *mw);
1112 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
1113 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
1114 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1115 int start_index, int npages, u64 *page_list);
1116 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1117 struct mlx4_buf *buf);
1119 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
1120 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
1122 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
1124 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
1127 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
1128 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
1129 unsigned int vector, int collapsed, int timestamp_en,
1130 void *buf_addr, bool user_cq);
1131 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
1132 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1133 int *base, u8 flags, u8 usage);
1134 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1136 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
1137 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
1139 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
1140 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
1141 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
1142 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
1143 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
1145 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
1146 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
1148 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1149 int block_mcast_loopback, enum mlx4_protocol prot);
1150 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1151 enum mlx4_protocol prot);
1152 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1153 u8 port, int block_mcast_loopback,
1154 enum mlx4_protocol protocol, u64 *reg_id);
1155 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1156 enum mlx4_protocol protocol, u64 reg_id);
1159 MLX4_DOMAIN_UVERBS = 0x1000,
1160 MLX4_DOMAIN_ETHTOOL = 0x2000,
1161 MLX4_DOMAIN_RFS = 0x3000,
1162 MLX4_DOMAIN_NIC = 0x5000,
1165 enum mlx4_net_trans_rule_id {
1166 MLX4_NET_TRANS_RULE_ID_ETH = 0,
1167 MLX4_NET_TRANS_RULE_ID_IB,
1168 MLX4_NET_TRANS_RULE_ID_IPV6,
1169 MLX4_NET_TRANS_RULE_ID_IPV4,
1170 MLX4_NET_TRANS_RULE_ID_TCP,
1171 MLX4_NET_TRANS_RULE_ID_UDP,
1172 MLX4_NET_TRANS_RULE_ID_VXLAN,
1173 MLX4_NET_TRANS_RULE_NUM, /* should be last */
1176 extern const u16 __sw_id_hw[];
1178 static inline int map_hw_to_sw_id(u16 header_id)
1182 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
1183 if (header_id == __sw_id_hw[i])
1189 enum mlx4_net_trans_promisc_mode {
1190 MLX4_FS_REGULAR = 1,
1191 MLX4_FS_ALL_DEFAULT,
1193 MLX4_FS_MIRROR_RX_PORT,
1194 MLX4_FS_MIRROR_SX_PORT,
1197 MLX4_FS_MODE_NUM, /* should be last */
1200 struct mlx4_spec_eth {
1201 u8 dst_mac[ETH_ALEN];
1202 u8 dst_mac_msk[ETH_ALEN];
1203 u8 src_mac[ETH_ALEN];
1204 u8 src_mac_msk[ETH_ALEN];
1205 u8 ether_type_enable;
1211 struct mlx4_spec_tcp_udp {
1213 __be16 dst_port_msk;
1215 __be16 src_port_msk;
1218 struct mlx4_spec_ipv4 {
1225 struct mlx4_spec_ib {
1232 struct mlx4_spec_vxlan {
1238 struct mlx4_spec_list {
1239 struct list_head list;
1240 enum mlx4_net_trans_rule_id id;
1242 struct mlx4_spec_eth eth;
1243 struct mlx4_spec_ib ib;
1244 struct mlx4_spec_ipv4 ipv4;
1245 struct mlx4_spec_tcp_udp tcp_udp;
1246 struct mlx4_spec_vxlan vxlan;
1250 enum mlx4_net_trans_hw_rule_queue {
1251 MLX4_NET_TRANS_Q_FIFO,
1252 MLX4_NET_TRANS_Q_LIFO,
1255 struct mlx4_net_trans_rule {
1256 struct list_head list;
1257 enum mlx4_net_trans_hw_rule_queue queue_mode;
1259 bool allow_loopback;
1260 enum mlx4_net_trans_promisc_mode promisc_mode;
1266 struct mlx4_net_trans_rule_hw_ctrl {
1278 struct mlx4_net_trans_rule_hw_ib {
1289 struct mlx4_net_trans_rule_hw_eth {
1302 u8 ether_type_enable;
1304 __be16 vlan_tag_msk;
1308 struct mlx4_net_trans_rule_hw_tcp_udp {
1315 __be16 dst_port_msk;
1319 __be16 src_port_msk;
1322 struct mlx4_net_trans_rule_hw_ipv4 {
1333 struct mlx4_net_trans_rule_hw_vxlan {
1349 struct mlx4_net_trans_rule_hw_eth eth;
1350 struct mlx4_net_trans_rule_hw_ib ib;
1351 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1352 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1353 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1358 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1359 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1360 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1361 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1362 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1366 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS = 0x2,
1369 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1370 enum mlx4_net_trans_promisc_mode mode);
1371 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1372 enum mlx4_net_trans_promisc_mode mode);
1373 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1374 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1375 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1376 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1377 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1379 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1380 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1381 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1382 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1383 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1384 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1385 int mlx4_SET_PORT_user_mac(struct mlx4_dev *dev, u8 port, u8 *user_mac);
1386 int mlx4_SET_PORT_user_mtu(struct mlx4_dev *dev, u8 port, u16 user_mtu);
1387 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1389 int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time);
1390 int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port,
1391 u8 ignore_fcs_value);
1392 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
1393 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val);
1394 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv);
1395 int mlx4_get_is_vlan_offload_disabled(struct mlx4_dev *dev, u8 port,
1396 bool *vlan_offload_disabled);
1397 void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl,
1398 struct _rule_hw *eth_header);
1399 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1400 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1401 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1402 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1404 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1405 int mlx4_test_interrupt(struct mlx4_dev *dev, int vector);
1406 int mlx4_test_async(struct mlx4_dev *dev);
1407 int mlx4_query_diag_counters(struct mlx4_dev *dev, u8 op_modifier,
1408 const u32 offset[], u32 value[],
1409 size_t array_len, u8 port);
1410 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port);
1411 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector);
1412 struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port);
1413 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector);
1414 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1416 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector);
1417 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
1419 int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1420 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1421 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1423 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx, u8 usage);
1424 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1425 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port);
1427 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry,
1429 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port);
1430 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port);
1431 int mlx4_flow_attach(struct mlx4_dev *dev,
1432 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1433 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1434 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1435 enum mlx4_net_trans_promisc_mode flow_type);
1436 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1437 enum mlx4_net_trans_rule_id id);
1438 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1440 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
1441 int port, int qpn, u16 prio, u64 *reg_id);
1443 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1446 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1448 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1449 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1450 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1451 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1452 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1453 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1454 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1456 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1457 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1459 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1461 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1464 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1467 u64 mlx4_read_clock(struct mlx4_dev *dev);
1469 struct mlx4_active_ports {
1470 DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
1472 /* Returns a bitmap of the physical ports which are assigned to slave */
1473 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
1475 /* Returns the physical port that represents the virtual port of the slave, */
1476 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1477 /* mapping is returned. */
1478 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
1480 struct mlx4_slaves_pport {
1481 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
1483 /* Returns a bitmap of all slaves that are assigned to port. */
1484 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
1487 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1488 /* the ports that are set in crit_ports. */
1489 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
1490 struct mlx4_dev *dev,
1491 const struct mlx4_active_ports *crit_ports);
1493 /* Returns the slave's virtual port that represents the physical port. */
1494 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1496 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1498 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1499 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis);
1500 int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port);
1501 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2);
1502 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
1503 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
1504 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
1507 struct mlx4_mpt_entry;
1508 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1509 struct mlx4_mpt_entry ***mpt_entry);
1510 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1511 struct mlx4_mpt_entry **mpt_entry);
1512 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
1514 int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
1515 struct mlx4_mpt_entry *mpt_entry,
1517 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
1518 struct mlx4_mpt_entry **mpt_entry);
1519 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
1520 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
1521 u64 iova, u64 size, int npages,
1522 int page_shift, struct mlx4_mpt_entry *mpt_entry);
1524 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
1525 u16 offset, u16 size, u8 *data);
1526 int mlx4_max_tc(struct mlx4_dev *dev);
1528 /* Returns true if running in low memory profile (kdump kernel) */
1529 static inline bool mlx4_low_memory_profile(void)
1531 return is_kdump_kernel();
1534 /* ACCESS REG commands */
1535 enum mlx4_access_reg_method {
1536 MLX4_ACCESS_REG_QUERY = 0x1,
1537 MLX4_ACCESS_REG_WRITE = 0x2,
1540 /* ACCESS PTYS Reg command */
1541 enum mlx4_ptys_proto {
1542 MLX4_PTYS_IB = 1<<0,
1543 MLX4_PTYS_EN = 1<<2,
1546 enum mlx4_ptys_flags {
1547 MLX4_PTYS_AN_DISABLE_CAP = 1 << 5,
1548 MLX4_PTYS_AN_DISABLE_ADMIN = 1 << 6,
1551 struct mlx4_ptys_reg {
1557 __be32 eth_proto_cap;
1558 __be16 ib_width_cap;
1559 __be16 ib_speed_cap;
1561 __be32 eth_proto_admin;
1562 __be16 ib_width_admin;
1563 __be16 ib_speed_admin;
1565 __be32 eth_proto_oper;
1566 __be16 ib_width_oper;
1567 __be16 ib_speed_oper;
1569 __be32 eth_proto_lp_adv;
1572 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
1573 enum mlx4_access_reg_method method,
1574 struct mlx4_ptys_reg *ptys_reg);
1576 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1577 struct mlx4_clock_params *params);
1579 static inline int mlx4_to_hw_uar_index(struct mlx4_dev *dev, int index)
1581 return (index << (PAGE_SHIFT - dev->uar_page_shift));
1584 static inline int mlx4_get_num_reserved_uar(struct mlx4_dev *dev)
1586 /* The first 128 UARs are used for EQ doorbells */
1587 return (128 >> (PAGE_SHIFT - dev->uar_page_shift));
1589 #endif /* MLX4_DEVICE_H */