include/linux/mfd/tps65912.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com/
   4  *      Andrew F. Davis <afd@ti.com>
   5  *
   6  * Based on the TPS65218 driver and the previous TPS65912 driver by
   7  * Margarita Olaya Cabrera <magi@slimlogic.co.uk>
   8  */
   9
  10 #ifndef __LINUX_MFD_TPS65912_H
  11 #define __LINUX_MFD_TPS65912_H
  12
  13 #include <linux/device.h>
  14 #include <linux/regmap.h>
  15
  16 /* List of registers for TPS65912 */
  17 #define TPS65912_DCDC1_CTRL             0x00
  18 #define TPS65912_DCDC2_CTRL             0x01
  19 #define TPS65912_DCDC3_CTRL             0x02
  20 #define TPS65912_DCDC4_CTRL             0x03
  21 #define TPS65912_DCDC1_OP               0x04
  22 #define TPS65912_DCDC1_AVS              0x05
  23 #define TPS65912_DCDC1_LIMIT            0x06
  24 #define TPS65912_DCDC2_OP               0x07
  25 #define TPS65912_DCDC2_AVS              0x08
  26 #define TPS65912_DCDC2_LIMIT            0x09
  27 #define TPS65912_DCDC3_OP               0x0A
  28 #define TPS65912_DCDC3_AVS              0x0B
  29 #define TPS65912_DCDC3_LIMIT            0x0C
  30 #define TPS65912_DCDC4_OP               0x0D
  31 #define TPS65912_DCDC4_AVS              0x0E
  32 #define TPS65912_DCDC4_LIMIT            0x0F
  33 #define TPS65912_LDO1_OP                0x10
  34 #define TPS65912_LDO1_AVS               0x11
  35 #define TPS65912_LDO1_LIMIT             0x12
  36 #define TPS65912_LDO2_OP                0x13
  37 #define TPS65912_LDO2_AVS               0x14
  38 #define TPS65912_LDO2_LIMIT             0x15
  39 #define TPS65912_LDO3_OP                0x16
  40 #define TPS65912_LDO3_AVS               0x17
  41 #define TPS65912_LDO3_LIMIT             0x18
  42 #define TPS65912_LDO4_OP                0x19
  43 #define TPS65912_LDO4_AVS               0x1A
  44 #define TPS65912_LDO4_LIMIT             0x1B
  45 #define TPS65912_LDO5                   0x1C
  46 #define TPS65912_LDO6                   0x1D
  47 #define TPS65912_LDO7                   0x1E
  48 #define TPS65912_LDO8                   0x1F
  49 #define TPS65912_LDO9                   0x20
  50 #define TPS65912_LDO10                  0x21
  51 #define TPS65912_THRM                   0x22
  52 #define TPS65912_CLK32OUT               0x23
  53 #define TPS65912_DEVCTRL                0x24
  54 #define TPS65912_DEVCTRL2               0x25
  55 #define TPS65912_I2C_SPI_CFG            0x26
  56 #define TPS65912_KEEP_ON                0x27
  57 #define TPS65912_KEEP_ON2               0x28
  58 #define TPS65912_SET_OFF1               0x29
  59 #define TPS65912_SET_OFF2               0x2A
  60 #define TPS65912_DEF_VOLT               0x2B
  61 #define TPS65912_DEF_VOLT_MAPPING       0x2C
  62 #define TPS65912_DISCHARGE              0x2D
  63 #define TPS65912_DISCHARGE2             0x2E
  64 #define TPS65912_EN1_SET1               0x2F
  65 #define TPS65912_EN1_SET2               0x30
  66 #define TPS65912_EN2_SET1               0x31
  67 #define TPS65912_EN2_SET2               0x32
  68 #define TPS65912_EN3_SET1               0x33
  69 #define TPS65912_EN3_SET2               0x34
  70 #define TPS65912_EN4_SET1               0x35
  71 #define TPS65912_EN4_SET2               0x36
  72 #define TPS65912_PGOOD                  0x37
  73 #define TPS65912_PGOOD2                 0x38
  74 #define TPS65912_INT_STS                0x39
  75 #define TPS65912_INT_MSK                0x3A
  76 #define TPS65912_INT_STS2               0x3B
  77 #define TPS65912_INT_MSK2               0x3C
  78 #define TPS65912_INT_STS3               0x3D
  79 #define TPS65912_INT_MSK3               0x3E
  80 #define TPS65912_INT_STS4               0x3F
  81 #define TPS65912_INT_MSK4               0x40
  82 #define TPS65912_GPIO1                  0x41
  83 #define TPS65912_GPIO2                  0x42
  84 #define TPS65912_GPIO3                  0x43
  85 #define TPS65912_GPIO4                  0x44
  86 #define TPS65912_GPIO5                  0x45
  87 #define TPS65912_VMON                   0x46
  88 #define TPS65912_LEDA_CTRL1             0x47
  89 #define TPS65912_LEDA_CTRL2             0x48
  90 #define TPS65912_LEDA_CTRL3             0x49
  91 #define TPS65912_LEDA_CTRL4             0x4A
  92 #define TPS65912_LEDA_CTRL5             0x4B
  93 #define TPS65912_LEDA_CTRL6             0x4C
  94 #define TPS65912_LEDA_CTRL7             0x4D
  95 #define TPS65912_LEDA_CTRL8             0x4E
  96 #define TPS65912_LEDB_CTRL1             0x4F
  97 #define TPS65912_LEDB_CTRL2             0x50
  98 #define TPS65912_LEDB_CTRL3             0x51
  99 #define TPS65912_LEDB_CTRL4             0x52
 100 #define TPS65912_LEDB_CTRL5             0x53
 101 #define TPS65912_LEDB_CTRL6             0x54
 102 #define TPS65912_LEDB_CTRL7             0x55
 103 #define TPS65912_LEDB_CTRL8             0x56
 104 #define TPS65912_LEDC_CTRL1             0x57
 105 #define TPS65912_LEDC_CTRL2             0x58
 106 #define TPS65912_LEDC_CTRL3             0x59
 107 #define TPS65912_LEDC_CTRL4             0x5A
 108 #define TPS65912_LEDC_CTRL5             0x5B
 109 #define TPS65912_LEDC_CTRL6             0x5C
 110 #define TPS65912_LEDC_CTRL7             0x5D
 111 #define TPS65912_LEDC_CTRL8             0x5E
 112 #define TPS65912_LED_RAMP_UP_TIME       0x5F
 113 #define TPS65912_LED_RAMP_DOWN_TIME     0x60
 114 #define TPS65912_LED_SEQ_EN             0x61
 115 #define TPS65912_LOADSWITCH             0x62
 116 #define TPS65912_SPARE                  0x63
 117 #define TPS65912_VERNUM                 0x64
 118 #define TPS6591X_MAX_REGISTER           0x64
 119
 120 /* INT_STS Register field definitions */
 121 #define TPS65912_INT_STS_PWRHOLD_F      BIT(0)
 122 #define TPS65912_INT_STS_VMON           BIT(1)
 123 #define TPS65912_INT_STS_PWRON          BIT(2)
 124 #define TPS65912_INT_STS_PWRON_LP       BIT(3)
 125 #define TPS65912_INT_STS_PWRHOLD_R      BIT(4)
 126 #define TPS65912_INT_STS_HOTDIE         BIT(5)
 127 #define TPS65912_INT_STS_GPIO1_R        BIT(6)
 128 #define TPS65912_INT_STS_GPIO1_F        BIT(7)
 129
 130 /* INT_STS Register field definitions */
 131 #define TPS65912_INT_STS2_GPIO2_R       BIT(0)
 132 #define TPS65912_INT_STS2_GPIO2_F       BIT(1)
 133 #define TPS65912_INT_STS2_GPIO3_R       BIT(2)
 134 #define TPS65912_INT_STS2_GPIO3_F       BIT(3)
 135 #define TPS65912_INT_STS2_GPIO4_R       BIT(4)
 136 #define TPS65912_INT_STS2_GPIO4_F       BIT(5)
 137 #define TPS65912_INT_STS2_GPIO5_R       BIT(6)
 138 #define TPS65912_INT_STS2_GPIO5_F       BIT(7)
 139
 140 /* INT_STS Register field definitions */
 141 #define TPS65912_INT_STS3_PGOOD_DCDC1   BIT(0)
 142 #define TPS65912_INT_STS3_PGOOD_DCDC2   BIT(1)
 143 #define TPS65912_INT_STS3_PGOOD_DCDC3   BIT(2)
 144 #define TPS65912_INT_STS3_PGOOD_DCDC4   BIT(3)
 145 #define TPS65912_INT_STS3_PGOOD_LDO1    BIT(4)
 146 #define TPS65912_INT_STS3_PGOOD_LDO2    BIT(5)
 147 #define TPS65912_INT_STS3_PGOOD_LDO3    BIT(6)
 148 #define TPS65912_INT_STS3_PGOOD_LDO4    BIT(7)
 149
 150 /* INT_STS Register field definitions */
 151 #define TPS65912_INT_STS4_PGOOD_LDO5    BIT(0)
 152 #define TPS65912_INT_STS4_PGOOD_LDO6    BIT(1)
 153 #define TPS65912_INT_STS4_PGOOD_LDO7    BIT(2)
 154 #define TPS65912_INT_STS4_PGOOD_LDO8    BIT(3)
 155 #define TPS65912_INT_STS4_PGOOD_LDO9    BIT(4)
 156 #define TPS65912_INT_STS4_PGOOD_LDO10   BIT(5)
 157
 158 /* GPIO 1 and 2 Register field definitions */
 159 #define GPIO_SLEEP_MASK                 0x80
 160 #define GPIO_SLEEP_SHIFT                7
 161 #define GPIO_DEB_MASK                   0x10
 162 #define GPIO_DEB_SHIFT                  4
 163 #define GPIO_CFG_MASK                   0x04
 164 #define GPIO_CFG_SHIFT                  2
 165 #define GPIO_STS_MASK                   0x02
 166 #define GPIO_STS_SHIFT                  1
 167 #define GPIO_SET_MASK                   0x01
 168 #define GPIO_SET_SHIFT                  0
 169
 170 /* GPIO 3 Register field definitions */
 171 #define GPIO3_SLEEP_MASK                0x80
 172 #define GPIO3_SLEEP_SHIFT               7
 173 #define GPIO3_SEL_MASK                  0x40
 174 #define GPIO3_SEL_SHIFT                 6
 175 #define GPIO3_ODEN_MASK                 0x20
 176 #define GPIO3_ODEN_SHIFT                5
 177 #define GPIO3_DEB_MASK                  0x10
 178 #define GPIO3_DEB_SHIFT                 4
 179 #define GPIO3_PDEN_MASK                 0x08
 180 #define GPIO3_PDEN_SHIFT                3
 181 #define GPIO3_CFG_MASK                  0x04
 182 #define GPIO3_CFG_SHIFT                 2
 183 #define GPIO3_STS_MASK                  0x02
 184 #define GPIO3_STS_SHIFT                 1
 185 #define GPIO3_SET_MASK                  0x01
 186 #define GPIO3_SET_SHIFT                 0
 187
 188 /* GPIO 4 Register field definitions */
 189 #define GPIO4_SLEEP_MASK                0x80
 190 #define GPIO4_SLEEP_SHIFT               7
 191 #define GPIO4_SEL_MASK                  0x40
 192 #define GPIO4_SEL_SHIFT                 6
 193 #define GPIO4_ODEN_MASK                 0x20
 194 #define GPIO4_ODEN_SHIFT                5
 195 #define GPIO4_DEB_MASK                  0x10
 196 #define GPIO4_DEB_SHIFT                 4
 197 #define GPIO4_PDEN_MASK                 0x08
 198 #define GPIO4_PDEN_SHIFT                3
 199 #define GPIO4_CFG_MASK                  0x04
 200 #define GPIO4_CFG_SHIFT                 2
 201 #define GPIO4_STS_MASK                  0x02
 202 #define GPIO4_STS_SHIFT                 1
 203 #define GPIO4_SET_MASK                  0x01
 204 #define GPIO4_SET_SHIFT                 0
 205
 206 /* Register THERM  (0x80) register.RegisterDescription */
 207 #define THERM_THERM_HD_MASK             0x20
 208 #define THERM_THERM_HD_SHIFT            5
 209 #define THERM_THERM_TS_MASK             0x10
 210 #define THERM_THERM_TS_SHIFT            4
 211 #define THERM_THERM_HDSEL_MASK          0x0C
 212 #define THERM_THERM_HDSEL_SHIFT         2
 213 #define THERM_RSVD1_MASK                0x02
 214 #define THERM_RSVD1_SHIFT               1
 215 #define THERM_THERM_STATE_MASK          0x01
 216 #define THERM_THERM_STATE_SHIFT         0
 217
 218 /* Register DCDCCTRL1 register.RegisterDescription */
 219 #define DCDCCTRL_VCON_ENABLE_MASK       0x80
 220 #define DCDCCTRL_VCON_ENABLE_SHIFT      7
 221 #define DCDCCTRL_VCON_RANGE1_MASK       0x40
 222 #define DCDCCTRL_VCON_RANGE1_SHIFT      6
 223 #define DCDCCTRL_VCON_RANGE0_MASK       0x20
 224 #define DCDCCTRL_VCON_RANGE0_SHIFT      5
 225 #define DCDCCTRL_TSTEP2_MASK            0x10
 226 #define DCDCCTRL_TSTEP2_SHIFT           4
 227 #define DCDCCTRL_TSTEP1_MASK            0x08
 228 #define DCDCCTRL_TSTEP1_SHIFT           3
 229 #define DCDCCTRL_TSTEP0_MASK            0x04
 230 #define DCDCCTRL_TSTEP0_SHIFT           2
 231 #define DCDCCTRL_DCDC1_MODE_MASK        0x02
 232 #define DCDCCTRL_DCDC1_MODE_SHIFT       1
 233
 234 /* Register DCDCCTRL2 and DCDCCTRL3 register.RegisterDescription */
 235 #define DCDCCTRL_TSTEP2_MASK            0x10
 236 #define DCDCCTRL_TSTEP2_SHIFT           4
 237 #define DCDCCTRL_TSTEP1_MASK            0x08
 238 #define DCDCCTRL_TSTEP1_SHIFT           3
 239 #define DCDCCTRL_TSTEP0_MASK            0x04
 240 #define DCDCCTRL_TSTEP0_SHIFT           2
 241 #define DCDCCTRL_DCDC_MODE_MASK         0x02
 242 #define DCDCCTRL_DCDC_MODE_SHIFT        1
 243 #define DCDCCTRL_RSVD0_MASK             0x01
 244 #define DCDCCTRL_RSVD0_SHIFT            0
 245
 246 /* Register DCDCCTRL4 register.RegisterDescription */
 247 #define DCDCCTRL_RAMP_TIME_MASK         0x01
 248 #define DCDCCTRL_RAMP_TIME_SHIFT        0
 249
 250 /* Register DCDCx_AVS */
 251 #define DCDC_AVS_ENABLE_MASK            0x80
 252 #define DCDC_AVS_ENABLE_SHIFT           7
 253 #define DCDC_AVS_ECO_MASK               0x40
 254 #define DCDC_AVS_ECO_SHIFT              6
 255
 256 /* Register DCDCx_LIMIT */
 257 #define DCDC_LIMIT_RANGE_MASK           0xC0
 258 #define DCDC_LIMIT_RANGE_SHIFT          6
 259 #define DCDC_LIMIT_MAX_SEL_MASK         0x3F
 260 #define DCDC_LIMIT_MAX_SEL_SHIFT        0
 261
 262 /* Define the TPS65912 IRQ numbers */
 263 enum tps65912_irqs {
 264         /* INT_STS registers */
 265         TPS65912_IRQ_PWRHOLD_F,
 266         TPS65912_IRQ_VMON,
 267         TPS65912_IRQ_PWRON,
 268         TPS65912_IRQ_PWRON_LP,
 269         TPS65912_IRQ_PWRHOLD_R,
 270         TPS65912_IRQ_HOTDIE,
 271         TPS65912_IRQ_GPIO1_R,
 272         TPS65912_IRQ_GPIO1_F,
 273         /* INT_STS2 registers */
 274         TPS65912_IRQ_GPIO2_R,
 275         TPS65912_IRQ_GPIO2_F,
 276         TPS65912_IRQ_GPIO3_R,
 277         TPS65912_IRQ_GPIO3_F,
 278         TPS65912_IRQ_GPIO4_R,
 279         TPS65912_IRQ_GPIO4_F,
 280         TPS65912_IRQ_GPIO5_R,
 281         TPS65912_IRQ_GPIO5_F,
 282         /* INT_STS3 registers */
 283         TPS65912_IRQ_PGOOD_DCDC1,
 284         TPS65912_IRQ_PGOOD_DCDC2,
 285         TPS65912_IRQ_PGOOD_DCDC3,
 286         TPS65912_IRQ_PGOOD_DCDC4,
 287         TPS65912_IRQ_PGOOD_LDO1,
 288         TPS65912_IRQ_PGOOD_LDO2,
 289         TPS65912_IRQ_PGOOD_LDO3,
 290         TPS65912_IRQ_PGOOD_LDO4,
 291         /* INT_STS4 registers */
 292         TPS65912_IRQ_PGOOD_LDO5,
 293         TPS65912_IRQ_PGOOD_LDO6,
 294         TPS65912_IRQ_PGOOD_LDO7,
 295         TPS65912_IRQ_PGOOD_LDO8,
 296         TPS65912_IRQ_PGOOD_LDO9,
 297         TPS65912_IRQ_PGOOD_LDO10,
 298 };
 299
 300 /*
 301  * struct tps65912 - state holder for the tps65912 driver
 302  *
 303  * Device data may be used to access the TPS65912 chip
 304  */
 305 struct tps65912 {
 306         struct device *dev;
 307         struct regmap *regmap;
 308
 309         /* IRQ Data */
 310         int irq;
 311         struct regmap_irq_chip_data *irq_data;
 312 };
 313
 314 extern const struct regmap_config tps65912_regmap_config;
 315
 316 int tps65912_device_init(struct tps65912 *tps);
 317 void tps65912_device_exit(struct tps65912 *tps);
 318
 319 #endif /*  __LINUX_MFD_TPS65912_H */