1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Intel MAX 10 Board Management Controller chip.
5 * Copyright (C) 2018-2020 Intel Corporation, Inc.
7 #ifndef __MFD_INTEL_M10_BMC_H
8 #define __MFD_INTEL_M10_BMC_H
10 #include <linux/regmap.h>
12 #define M10BMC_LEGACY_SYS_BASE 0x300400
13 #define M10BMC_SYS_BASE 0x300800
14 #define M10BMC_MEM_END 0x1fffffff
16 /* Register offset of system registers */
17 #define NIOS2_FW_VERSION 0x0
18 #define M10BMC_TEST_REG 0x3c
19 #define M10BMC_BUILD_VER 0x68
20 #define M10BMC_VER_MAJOR_MSK GENMASK(23, 16)
21 #define M10BMC_VER_PCB_INFO_MSK GENMASK(31, 24)
22 #define M10BMC_VER_LEGACY_INVALID 0xffffffff
25 * struct intel_m10bmc - Intel MAX 10 BMC parent driver data structure
27 * @regmap: the regmap used to access registers by m10bmc itself
31 struct regmap *regmap;
35 * register access helper functions.
37 * m10bmc_raw_read - read m10bmc register per addr
38 * m10bmc_sys_read - read m10bmc system register per offset
41 m10bmc_raw_read(struct intel_m10bmc *m10bmc, unsigned int addr,
46 ret = regmap_read(m10bmc->regmap, addr, val);
48 dev_err(m10bmc->dev, "fail to read raw reg %x: %d\n",
55 * The base of the system registers could be configured by HW developers, and
56 * in HW SPEC, the base is not added to the addresses of the system registers.
58 * This macro helps to simplify the accessing of the system registers. And if
59 * the base is reconfigured in HW, SW developers could simply change the
60 * M10BMC_SYS_BASE accordingly.
62 #define m10bmc_sys_read(m10bmc, offset, val) \
63 m10bmc_raw_read(m10bmc, M10BMC_SYS_BASE + (offset), val)
65 #endif /* __MFD_INTEL_M10_BMC_H */