1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Register Map - Based on AN888_SMUforIEEE_SynchEther_82P33xxx_RevH.pdf
5 * Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company.
7 #ifndef HAVE_IDT82P33_REG
8 #define HAVE_IDT82P33_REG
10 /* Register address */
11 #define DPLL1_TOD_CNFG 0x134
12 #define DPLL2_TOD_CNFG 0x1B4
14 #define DPLL1_TOD_STS 0x10B
15 #define DPLL2_TOD_STS 0x18B
17 #define DPLL1_TOD_TRIGGER 0x115
18 #define DPLL2_TOD_TRIGGER 0x195
20 #define DPLL1_OPERATING_MODE_CNFG 0x120
21 #define DPLL2_OPERATING_MODE_CNFG 0x1A0
23 #define DPLL1_HOLDOVER_FREQ_CNFG 0x12C
24 #define DPLL2_HOLDOVER_FREQ_CNFG 0x1AC
26 #define DPLL1_PHASE_OFFSET_CNFG 0x143
27 #define DPLL2_PHASE_OFFSET_CNFG 0x1C3
29 #define DPLL1_SYNC_EDGE_CNFG 0x140
30 #define DPLL2_SYNC_EDGE_CNFG 0x1C0
32 #define DPLL1_INPUT_MODE_CNFG 0x116
33 #define DPLL2_INPUT_MODE_CNFG 0x196
35 #define DPLL1_OPERATING_STS 0x102
36 #define DPLL2_OPERATING_STS 0x182
38 #define DPLL1_CURRENT_FREQ_STS 0x103
39 #define DPLL2_CURRENT_FREQ_STS 0x183
41 #define REG_SOFT_RESET 0X381
43 #define OUT_MUX_CNFG(outn) REG_ADDR(0x6, (0xC * (outn)))
45 /* Register bit definitions */
46 #define SYNC_TOD BIT(1)
47 #define PH_OFFSET_EN BIT(7)
48 #define SQUELCH_ENABLE BIT(5)
50 /* Bit definitions for the DPLL_MODE register */
51 #define PLL_MODE_SHIFT (0)
52 #define PLL_MODE_MASK (0x1F)
53 #define COMBO_MODE_EN BIT(5)
54 #define COMBO_MODE_SHIFT (6)
55 #define COMBO_MODE_MASK (0x3)
57 /* Bit definitions for DPLL_OPERATING_STS register */
58 #define OPERATING_STS_MASK (0x7)
59 #define OPERATING_STS_SHIFT (0x0)
61 /* Bit definitions for DPLL_TOD_TRIGGER register */
62 #define READ_TRIGGER_MASK (0xF)
63 #define READ_TRIGGER_SHIFT (0x0)
64 #define WRITE_TRIGGER_MASK (0xF0)
65 #define WRITE_TRIGGER_SHIFT (0x4)
67 /* Bit definitions for REG_SOFT_RESET register */
68 #define SOFT_RESET_EN BIT(7)
72 PLL_MODE_AUTOMATIC = PLL_MODE_MIN,
73 PLL_MODE_FORCE_FREERUN = 1,
74 PLL_MODE_FORCE_HOLDOVER = 2,
75 PLL_MODE_FORCE_LOCKED = 4,
76 PLL_MODE_FORCE_PRE_LOCKED2 = 5,
77 PLL_MODE_FORCE_PRE_LOCKED = 6,
78 PLL_MODE_FORCE_LOST_PHASE = 7,
81 PLL_MODE_MAX = PLL_MODE_WPH,
84 enum hw_tod_trig_sel {
85 HW_TOD_TRIG_SEL_MIN = 0,
86 HW_TOD_TRIG_SEL_NO_WRITE = HW_TOD_TRIG_SEL_MIN,
87 HW_TOD_TRIG_SEL_NO_READ = HW_TOD_TRIG_SEL_MIN,
88 HW_TOD_TRIG_SEL_SYNC_SEL = 1,
89 HW_TOD_TRIG_SEL_IN12 = 2,
90 HW_TOD_TRIG_SEL_IN13 = 3,
91 HW_TOD_TRIG_SEL_IN14 = 4,
92 HW_TOD_TRIG_SEL_TOD_PPS = 5,
93 HW_TOD_TRIG_SEL_TIMER_INTERVAL = 6,
94 HW_TOD_TRIG_SEL_MSB_PHASE_OFFSET_CNFG = 7,
95 HW_TOD_TRIG_SEL_MSB_HOLDOVER_FREQ_CNFG = 8,
96 HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG = 9,
97 HW_TOD_RD_TRIG_SEL_LSB_TOD_STS = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
98 WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
101 /** @brief Enumerated type listing DPLL operational modes */
103 DPLL_STATE_FREERUN = 1,
104 DPLL_STATE_HOLDOVER = 2,
105 DPLL_STATE_LOCKED = 4,
106 DPLL_STATE_PRELOCKED2 = 5,
107 DPLL_STATE_PRELOCKED = 6,
108 DPLL_STATE_LOSTPHASE = 7,