1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __LINUX_GPIO_DRIVER_H
3 #define __LINUX_GPIO_DRIVER_H
5 #include <linux/device.h>
6 #include <linux/types.h>
8 #include <linux/irqchip/chained_irq.h>
9 #include <linux/irqdomain.h>
10 #include <linux/lockdep.h>
11 #include <linux/pinctrl/pinctrl.h>
12 #include <linux/pinctrl/pinconf-generic.h>
15 struct of_phandle_args;
21 enum gpio_lookup_flags;
25 #define GPIO_LINE_DIRECTION_IN 1
26 #define GPIO_LINE_DIRECTION_OUT 0
29 * struct gpio_irq_chip - GPIO interrupt controller
31 struct gpio_irq_chip {
35 * GPIO IRQ chip implementation, provided by GPIO driver.
37 struct irq_chip *chip;
42 * Interrupt translation domain; responsible for mapping between GPIO
43 * hwirq number and Linux IRQ number.
45 struct irq_domain *domain;
50 * Table of interrupt domain operations for this IRQ chip.
52 const struct irq_domain_ops *domain_ops;
54 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
58 * Firmware node corresponding to this gpiochip/irqchip, necessary
59 * for hierarchical irqdomain support.
61 struct fwnode_handle *fwnode;
66 * If non-NULL, will be set as the parent of this GPIO interrupt
67 * controller's IRQ domain to establish a hierarchical interrupt
68 * domain. The presence of this will activate the hierarchical
71 struct irq_domain *parent_domain;
74 * @child_to_parent_hwirq:
76 * This callback translates a child hardware IRQ offset to a parent
77 * hardware IRQ offset on a hierarchical interrupt chip. The child
78 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
79 * ngpio field of struct gpio_chip) and the corresponding parent
80 * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by
81 * the driver. The driver can calculate this from an offset or using
82 * a lookup table or whatever method is best for this chip. Return
83 * 0 on successful translation in the driver.
85 * If some ranges of hardware IRQs do not have a corresponding parent
86 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and
87 * @need_valid_mask to make these GPIO lines unavailable for
90 int (*child_to_parent_hwirq)(struct gpio_chip *gc,
91 unsigned int child_hwirq,
92 unsigned int child_type,
93 unsigned int *parent_hwirq,
94 unsigned int *parent_type);
97 * @populate_parent_alloc_arg :
99 * This optional callback allocates and populates the specific struct
100 * for the parent's IRQ domain. If this is not specified, then
101 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell
102 * variant named &gpiochip_populate_parent_fwspec_fourcell is also
105 void *(*populate_parent_alloc_arg)(struct gpio_chip *gc,
106 unsigned int parent_hwirq,
107 unsigned int parent_type);
110 * @child_offset_to_irq:
112 * This optional callback is used to translate the child's GPIO line
113 * offset on the GPIO chip to an IRQ number for the GPIO to_irq()
114 * callback. If this is not specified, then a default callback will be
115 * provided that returns the line offset.
117 unsigned int (*child_offset_to_irq)(struct gpio_chip *gc,
121 * @child_irq_domain_ops:
123 * The IRQ domain operations that will be used for this GPIO IRQ
124 * chip. If no operations are provided, then default callbacks will
125 * be populated to setup the IRQ hierarchy. Some drivers need to
126 * supply their own translate function.
128 struct irq_domain_ops child_irq_domain_ops;
134 * The IRQ handler to use (often a predefined IRQ core function) for
135 * GPIO IRQs, provided by GPIO driver.
137 irq_flow_handler_t handler;
142 * Default IRQ triggering type applied during GPIO driver
143 * initialization, provided by GPIO driver.
145 unsigned int default_type;
150 * Per GPIO IRQ chip lockdep class for IRQ lock.
152 struct lock_class_key *lock_key;
157 * Per GPIO IRQ chip lockdep class for IRQ request.
159 struct lock_class_key *request_key;
164 * The interrupt handler for the GPIO chip's parent interrupts, may be
165 * NULL if the parent interrupts are nested rather than cascaded.
167 irq_flow_handler_t parent_handler;
170 * @parent_handler_data:
172 * Data associated, and passed to, the handler for the parent
175 void *parent_handler_data;
180 * The number of interrupt parents of a GPIO chip.
182 unsigned int num_parents;
187 * A list of interrupt parents of a GPIO chip. This is owned by the
188 * driver, so the core will only reference this list, not modify it.
190 unsigned int *parents;
195 * A list of interrupt parents for each line of a GPIO chip.
202 * True if set the interrupt handling uses nested threads.
207 * @init_hw: optional routine to initialize hardware before
208 * an IRQ chip will be added. This is quite useful when
209 * a particular driver wants to clear IRQ related registers
210 * in order to avoid undesired events.
212 int (*init_hw)(struct gpio_chip *gc);
215 * @init_valid_mask: optional routine to initialize @valid_mask, to be
216 * used if not all GPIO lines are valid interrupts. Sometimes some
217 * lines just cannot fire interrupts, and this routine, when defined,
218 * is passed a bitmap in "valid_mask" and it will have ngpios
219 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can
220 * then directly set some bits to "0" if they cannot be used for
223 void (*init_valid_mask)(struct gpio_chip *gc,
224 unsigned long *valid_mask,
225 unsigned int ngpios);
230 * Flag to track GPIO chip irq member's initialization.
231 * This flag will make sure GPIO chip irq members are not used
232 * before they are initialized.
239 * If not %NULL, holds bitmask of GPIOs which are valid to be included
240 * in IRQ domain of the chip.
242 unsigned long *valid_mask;
247 * Required for static IRQ allocation. If set, irq_domain_add_simple()
248 * will allocate and map all IRQs during initialization.
255 * Store old irq_chip irq_enable callback
257 void (*irq_enable)(struct irq_data *data);
262 * Store old irq_chip irq_disable callback
264 void (*irq_disable)(struct irq_data *data);
268 * Store old irq_chip irq_unmask callback
270 void (*irq_unmask)(struct irq_data *data);
275 * Store old irq_chip irq_mask callback
277 void (*irq_mask)(struct irq_data *data);
281 * struct gpio_chip - abstract a GPIO controller
282 * @label: a functional name for the GPIO device, such as a part
283 * number or the name of the SoC IP-block implementing it.
284 * @gpiodev: the internal state holder, opaque struct
285 * @parent: optional parent device providing the GPIOs
286 * @owner: helps prevent removal of modules exporting active GPIOs
287 * @request: optional hook for chip-specific activation, such as
288 * enabling module power and clock; may sleep
289 * @free: optional hook for chip-specific deactivation, such as
290 * disabling module power and clock; may sleep
291 * @get_direction: returns direction for signal "offset", 0=out, 1=in,
292 * (same as GPIO_LINE_DIRECTION_OUT / GPIO_LINE_DIRECTION_IN),
293 * or negative error. It is recommended to always implement this
294 * function, even on input-only or output-only gpio chips.
295 * @direction_input: configures signal "offset" as input, or returns error
296 * This can be omitted on input-only or output-only gpio chips.
297 * @direction_output: configures signal "offset" as output, or returns error
298 * This can be omitted on input-only or output-only gpio chips.
299 * @get: returns value for signal "offset", 0=low, 1=high, or negative error
300 * @get_multiple: reads values for multiple signals defined by "mask" and
301 * stores them in "bits", returns 0 on success or negative error
302 * @set: assigns output value for signal "offset"
303 * @set_multiple: assigns output values for multiple signals defined by "mask"
304 * @set_config: optional hook for all kinds of settings. Uses the same
305 * packed config format as generic pinconf.
306 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
307 * implementation may not sleep
308 * @dbg_show: optional routine to show contents in debugfs; default code
309 * will be used when this is omitted, but custom code can show extra
310 * state (such as pullup/pulldown configuration).
311 * @init_valid_mask: optional routine to initialize @valid_mask, to be used if
312 * not all GPIOs are valid.
313 * @add_pin_ranges: optional routine to initialize pin ranges, to be used when
314 * requires special mapping of the pins that provides GPIO functionality.
315 * It is called after adding GPIO chip and before adding IRQ chip.
316 * @base: identifies the first GPIO number handled by this chip;
317 * or, if negative during registration, requests dynamic ID allocation.
318 * DEPRECATION: providing anything non-negative and nailing the base
319 * offset of GPIO chips is deprecated. Please pass -1 as base to
320 * let gpiolib select the chip base in all possible cases. We want to
321 * get rid of the static GPIO number space in the long run.
322 * @ngpio: the number of GPIOs handled by this controller; the last GPIO
323 * handled is (base + ngpio - 1).
324 * @offset: when multiple gpio chips belong to the same device this
325 * can be used as offset within the device so friendly names can
326 * be properly assigned.
327 * @names: if set, must be an array of strings to use as alternative
328 * names for the GPIOs in this chip. Any entry in the array
329 * may be NULL if there is no alias for the GPIO, however the
330 * array must be @ngpio entries long. A name can include a single printk
331 * format specifier for an unsigned int. It is substituted by the actual
332 * number of the gpio.
333 * @can_sleep: flag must be set iff get()/set() methods sleep, as they
334 * must while accessing GPIO expander chips over I2C or SPI. This
335 * implies that if the chip supports IRQs, these IRQs need to be threaded
336 * as the chip access may sleep when e.g. reading out the IRQ status
338 * @read_reg: reader function for generic GPIO
339 * @write_reg: writer function for generic GPIO
340 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
341 * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
342 * generic GPIO core. It is for internal housekeeping only.
343 * @reg_dat: data (in) register for generic GPIO
344 * @reg_set: output set register (out=high) for generic GPIO
345 * @reg_clr: output clear register (out=low) for generic GPIO
346 * @reg_dir_out: direction out setting register for generic GPIO
347 * @reg_dir_in: direction in setting register for generic GPIO
348 * @bgpio_dir_unreadable: indicates that the direction register(s) cannot
349 * be read and we need to rely on out internal state tracking.
350 * @bgpio_bits: number of register bits used for a generic GPIO i.e.
351 * <register width> * 8
352 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
353 * shadowed and real data registers writes together.
354 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits
356 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
357 * direction safely. A "1" in this word means the line is set as
360 * A gpio_chip can help platforms abstract various sources of GPIOs so
361 * they can all be accessed through a common programming interface.
362 * Example sources would be SOC controllers, FPGAs, multifunction
363 * chips, dedicated GPIO expanders, and so on.
365 * Each chip controls a number of signals, identified in method calls
366 * by "offset" values in the range 0..(@ngpio - 1). When those signals
367 * are referenced through calls like gpio_get_value(gpio), the offset
368 * is calculated by subtracting @base from the gpio number.
372 struct gpio_device *gpiodev;
373 struct device *parent;
374 struct module *owner;
376 int (*request)(struct gpio_chip *gc,
377 unsigned int offset);
378 void (*free)(struct gpio_chip *gc,
379 unsigned int offset);
380 int (*get_direction)(struct gpio_chip *gc,
381 unsigned int offset);
382 int (*direction_input)(struct gpio_chip *gc,
383 unsigned int offset);
384 int (*direction_output)(struct gpio_chip *gc,
385 unsigned int offset, int value);
386 int (*get)(struct gpio_chip *gc,
387 unsigned int offset);
388 int (*get_multiple)(struct gpio_chip *gc,
390 unsigned long *bits);
391 void (*set)(struct gpio_chip *gc,
392 unsigned int offset, int value);
393 void (*set_multiple)(struct gpio_chip *gc,
395 unsigned long *bits);
396 int (*set_config)(struct gpio_chip *gc,
398 unsigned long config);
399 int (*to_irq)(struct gpio_chip *gc,
400 unsigned int offset);
402 void (*dbg_show)(struct seq_file *s,
403 struct gpio_chip *gc);
405 int (*init_valid_mask)(struct gpio_chip *gc,
406 unsigned long *valid_mask,
407 unsigned int ngpios);
409 int (*add_pin_ranges)(struct gpio_chip *gc);
414 const char *const *names;
417 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
418 unsigned long (*read_reg)(void __iomem *reg);
419 void (*write_reg)(void __iomem *reg, unsigned long data);
421 void __iomem *reg_dat;
422 void __iomem *reg_set;
423 void __iomem *reg_clr;
424 void __iomem *reg_dir_out;
425 void __iomem *reg_dir_in;
426 bool bgpio_dir_unreadable;
428 spinlock_t bgpio_lock;
429 unsigned long bgpio_data;
430 unsigned long bgpio_dir;
431 #endif /* CONFIG_GPIO_GENERIC */
433 #ifdef CONFIG_GPIOLIB_IRQCHIP
435 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
436 * to handle IRQs for most practical cases.
442 * Integrates interrupt chip functionality with the GPIO chip. Can be
443 * used to handle IRQs for most practical cases.
445 struct gpio_irq_chip irq;
446 #endif /* CONFIG_GPIOLIB_IRQCHIP */
451 * If not %NULL, holds bitmask of GPIOs which are valid to be used
454 unsigned long *valid_mask;
456 #if defined(CONFIG_OF_GPIO)
458 * If CONFIG_OF_GPIO is enabled, then all GPIO controllers described in
459 * the device tree automatically may have an OF translation
465 * Pointer to a device tree node representing this GPIO controller.
467 struct device_node *of_node;
472 * Number of cells used to form the GPIO specifier.
474 unsigned int of_gpio_n_cells;
479 * Callback to translate a device tree GPIO specifier into a chip-
480 * relative GPIO number and flags.
482 int (*of_xlate)(struct gpio_chip *gc,
483 const struct of_phandle_args *gpiospec, u32 *flags);
486 * @of_gpio_ranges_fallback:
488 * Optional hook for the case that no gpio-ranges property is defined
489 * within the device tree node "np" (usually DT before introduction
490 * of gpio-ranges). So this callback is helpful to provide the
491 * necessary backward compatibility for the pin ranges.
493 int (*of_gpio_ranges_fallback)(struct gpio_chip *gc,
494 struct device_node *np);
496 #endif /* CONFIG_OF_GPIO */
499 extern const char *gpiochip_is_requested(struct gpio_chip *gc,
500 unsigned int offset);
503 * for_each_requested_gpio_in_range - iterates over requested GPIOs in a given range
504 * @chip: the chip to query
506 * @base: first GPIO in the range
507 * @size: amount of GPIOs to check starting from @base
508 * @label: label of current GPIO
510 #define for_each_requested_gpio_in_range(chip, i, base, size, label) \
511 for (i = 0; i < size; i++) \
512 if ((label = gpiochip_is_requested(chip, base + i)) == NULL) {} else
514 /* Iterates over all requested GPIO of the given @chip */
515 #define for_each_requested_gpio(chip, i, label) \
516 for_each_requested_gpio_in_range(chip, i, 0, chip->ngpio, label)
518 /* add/remove chips */
519 extern int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,
520 struct lock_class_key *lock_key,
521 struct lock_class_key *request_key);
524 * gpiochip_add_data() - register a gpio_chip
525 * @gc: the chip to register, with gc->base initialized
526 * @data: driver-private data associated with this chip
528 * Context: potentially before irqs will work
530 * When gpiochip_add_data() is called very early during boot, so that GPIOs
531 * can be freely used, the gc->parent device must be registered before
532 * the gpio framework's arch_initcall(). Otherwise sysfs initialization
533 * for GPIOs will fail rudely.
535 * gpiochip_add_data() must only be called after gpiolib initialization,
536 * i.e. after core_initcall().
538 * If gc->base is negative, this requests dynamic assignment of
539 * a range of valid GPIOs.
542 * A negative errno if the chip can't be registered, such as because the
543 * gc->base is invalid or already associated with a different chip.
544 * Otherwise it returns zero as a success code.
546 #ifdef CONFIG_LOCKDEP
547 #define gpiochip_add_data(gc, data) ({ \
548 static struct lock_class_key lock_key; \
549 static struct lock_class_key request_key; \
550 gpiochip_add_data_with_key(gc, data, &lock_key, \
553 #define devm_gpiochip_add_data(dev, gc, data) ({ \
554 static struct lock_class_key lock_key; \
555 static struct lock_class_key request_key; \
556 devm_gpiochip_add_data_with_key(dev, gc, data, &lock_key, \
560 #define gpiochip_add_data(gc, data) gpiochip_add_data_with_key(gc, data, NULL, NULL)
561 #define devm_gpiochip_add_data(dev, gc, data) \
562 devm_gpiochip_add_data_with_key(dev, gc, data, NULL, NULL)
563 #endif /* CONFIG_LOCKDEP */
565 static inline int gpiochip_add(struct gpio_chip *gc)
567 return gpiochip_add_data(gc, NULL);
569 extern void gpiochip_remove(struct gpio_chip *gc);
570 extern int devm_gpiochip_add_data_with_key(struct device *dev, struct gpio_chip *gc, void *data,
571 struct lock_class_key *lock_key,
572 struct lock_class_key *request_key);
574 extern struct gpio_chip *gpiochip_find(void *data,
575 int (*match)(struct gpio_chip *gc, void *data));
577 bool gpiochip_line_is_irq(struct gpio_chip *gc, unsigned int offset);
578 int gpiochip_reqres_irq(struct gpio_chip *gc, unsigned int offset);
579 void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset);
580 void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset);
581 void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset);
583 /* Line status inquiry for drivers */
584 bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset);
585 bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset);
587 /* Sleep persistence inquiry for drivers */
588 bool gpiochip_line_is_persistent(struct gpio_chip *gc, unsigned int offset);
589 bool gpiochip_line_is_valid(const struct gpio_chip *gc, unsigned int offset);
591 /* get driver data */
592 void *gpiochip_get_data(struct gpio_chip *gc);
600 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
602 void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
603 unsigned int parent_hwirq,
604 unsigned int parent_type);
605 void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
606 unsigned int parent_hwirq,
607 unsigned int parent_type);
611 static inline void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
612 unsigned int parent_hwirq,
613 unsigned int parent_type)
618 static inline void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
619 unsigned int parent_hwirq,
620 unsigned int parent_type)
625 #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
627 int bgpio_init(struct gpio_chip *gc, struct device *dev,
628 unsigned long sz, void __iomem *dat, void __iomem *set,
629 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
630 unsigned long flags);
632 #define BGPIOF_BIG_ENDIAN BIT(0)
633 #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
634 #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
635 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
636 #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
637 #define BGPIOF_NO_OUTPUT BIT(5) /* only input */
638 #define BGPIOF_NO_SET_ON_INPUT BIT(6)
640 int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
641 irq_hw_number_t hwirq);
642 void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq);
644 int gpiochip_irq_domain_activate(struct irq_domain *domain,
645 struct irq_data *data, bool reserve);
646 void gpiochip_irq_domain_deactivate(struct irq_domain *domain,
647 struct irq_data *data);
649 bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gc,
650 unsigned int offset);
652 #ifdef CONFIG_GPIOLIB_IRQCHIP
653 int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
654 struct irq_domain *domain);
656 static inline int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
657 struct irq_domain *domain)
664 int gpiochip_generic_request(struct gpio_chip *gc, unsigned int offset);
665 void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset);
666 int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset,
667 unsigned long config);
670 * struct gpio_pin_range - pin range controlled by a gpio chip
671 * @node: list for maintaining set of pin ranges, used internally
672 * @pctldev: pinctrl device which handles corresponding pins
673 * @range: actual range of pins controlled by a gpio controller
675 struct gpio_pin_range {
676 struct list_head node;
677 struct pinctrl_dev *pctldev;
678 struct pinctrl_gpio_range range;
681 #ifdef CONFIG_PINCTRL
683 int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
684 unsigned int gpio_offset, unsigned int pin_offset,
686 int gpiochip_add_pingroup_range(struct gpio_chip *gc,
687 struct pinctrl_dev *pctldev,
688 unsigned int gpio_offset, const char *pin_group);
689 void gpiochip_remove_pin_ranges(struct gpio_chip *gc);
691 #else /* ! CONFIG_PINCTRL */
694 gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
695 unsigned int gpio_offset, unsigned int pin_offset,
701 gpiochip_add_pingroup_range(struct gpio_chip *gc,
702 struct pinctrl_dev *pctldev,
703 unsigned int gpio_offset, const char *pin_group)
709 gpiochip_remove_pin_ranges(struct gpio_chip *gc)
713 #endif /* CONFIG_PINCTRL */
715 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *gc,
718 enum gpio_lookup_flags lflags,
719 enum gpiod_flags dflags);
720 void gpiochip_free_own_desc(struct gpio_desc *desc);
722 #ifdef CONFIG_GPIOLIB
724 /* lock/unlock as IRQ */
725 int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset);
726 void gpiochip_unlock_as_irq(struct gpio_chip *gc, unsigned int offset);
729 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
731 #else /* CONFIG_GPIOLIB */
733 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
735 /* GPIO can never have been requested */
737 return ERR_PTR(-ENODEV);
740 static inline int gpiochip_lock_as_irq(struct gpio_chip *gc,
747 static inline void gpiochip_unlock_as_irq(struct gpio_chip *gc,
752 #endif /* CONFIG_GPIOLIB */
754 #endif /* __LINUX_GPIO_DRIVER_H */