1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __LINUX_GPIO_DRIVER_H
3 #define __LINUX_GPIO_DRIVER_H
5 #include <linux/device.h>
6 #include <linux/types.h>
8 #include <linux/irqchip/chained_irq.h>
9 #include <linux/irqdomain.h>
10 #include <linux/lockdep.h>
11 #include <linux/pinctrl/pinctrl.h>
12 #include <linux/pinctrl/pinconf-generic.h>
15 struct of_phandle_args;
21 enum gpio_lookup_flags;
25 #define GPIO_LINE_DIRECTION_IN 1
26 #define GPIO_LINE_DIRECTION_OUT 0
29 * struct gpio_irq_chip - GPIO interrupt controller
31 struct gpio_irq_chip {
35 * GPIO IRQ chip implementation, provided by GPIO driver.
37 struct irq_chip *chip;
42 * Interrupt translation domain; responsible for mapping between GPIO
43 * hwirq number and Linux IRQ number.
45 struct irq_domain *domain;
50 * Table of interrupt domain operations for this IRQ chip.
52 const struct irq_domain_ops *domain_ops;
54 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
58 * Firmware node corresponding to this gpiochip/irqchip, necessary
59 * for hierarchical irqdomain support.
61 struct fwnode_handle *fwnode;
66 * If non-NULL, will be set as the parent of this GPIO interrupt
67 * controller's IRQ domain to establish a hierarchical interrupt
68 * domain. The presence of this will activate the hierarchical
71 struct irq_domain *parent_domain;
74 * @child_to_parent_hwirq:
76 * This callback translates a child hardware IRQ offset to a parent
77 * hardware IRQ offset on a hierarchical interrupt chip. The child
78 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
79 * ngpio field of struct gpio_chip) and the corresponding parent
80 * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by
81 * the driver. The driver can calculate this from an offset or using
82 * a lookup table or whatever method is best for this chip. Return
83 * 0 on successful translation in the driver.
85 * If some ranges of hardware IRQs do not have a corresponding parent
86 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and
87 * @need_valid_mask to make these GPIO lines unavailable for
90 int (*child_to_parent_hwirq)(struct gpio_chip *gc,
91 unsigned int child_hwirq,
92 unsigned int child_type,
93 unsigned int *parent_hwirq,
94 unsigned int *parent_type);
97 * @populate_parent_alloc_arg :
99 * This optional callback allocates and populates the specific struct
100 * for the parent's IRQ domain. If this is not specified, then
101 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell
102 * variant named &gpiochip_populate_parent_fwspec_fourcell is also
105 void *(*populate_parent_alloc_arg)(struct gpio_chip *gc,
106 unsigned int parent_hwirq,
107 unsigned int parent_type);
110 * @child_offset_to_irq:
112 * This optional callback is used to translate the child's GPIO line
113 * offset on the GPIO chip to an IRQ number for the GPIO to_irq()
114 * callback. If this is not specified, then a default callback will be
115 * provided that returns the line offset.
117 unsigned int (*child_offset_to_irq)(struct gpio_chip *gc,
121 * @child_irq_domain_ops:
123 * The IRQ domain operations that will be used for this GPIO IRQ
124 * chip. If no operations are provided, then default callbacks will
125 * be populated to setup the IRQ hierarchy. Some drivers need to
126 * supply their own translate function.
128 struct irq_domain_ops child_irq_domain_ops;
134 * The IRQ handler to use (often a predefined IRQ core function) for
135 * GPIO IRQs, provided by GPIO driver.
137 irq_flow_handler_t handler;
142 * Default IRQ triggering type applied during GPIO driver
143 * initialization, provided by GPIO driver.
145 unsigned int default_type;
150 * Per GPIO IRQ chip lockdep class for IRQ lock.
152 struct lock_class_key *lock_key;
157 * Per GPIO IRQ chip lockdep class for IRQ request.
159 struct lock_class_key *request_key;
164 * The interrupt handler for the GPIO chip's parent interrupts, may be
165 * NULL if the parent interrupts are nested rather than cascaded.
167 irq_flow_handler_t parent_handler;
170 * @parent_handler_data:
171 * @parent_handler_data_array:
173 * Data associated, and passed to, the handler for the parent
174 * interrupt. Can either be a single pointer if @per_parent_data
175 * is false, or an array of @num_parents pointers otherwise. If
176 * @per_parent_data is true, @parent_handler_data_array cannot be
180 void *parent_handler_data;
181 void **parent_handler_data_array;
187 * The number of interrupt parents of a GPIO chip.
189 unsigned int num_parents;
194 * A list of interrupt parents of a GPIO chip. This is owned by the
195 * driver, so the core will only reference this list, not modify it.
197 unsigned int *parents;
202 * A list of interrupt parents for each line of a GPIO chip.
209 * True if set the interrupt handling uses nested threads.
216 * True if parent_handler_data_array describes a @num_parents
217 * sized array to be used as parent data.
219 bool per_parent_data;
222 * @init_hw: optional routine to initialize hardware before
223 * an IRQ chip will be added. This is quite useful when
224 * a particular driver wants to clear IRQ related registers
225 * in order to avoid undesired events.
227 int (*init_hw)(struct gpio_chip *gc);
230 * @init_valid_mask: optional routine to initialize @valid_mask, to be
231 * used if not all GPIO lines are valid interrupts. Sometimes some
232 * lines just cannot fire interrupts, and this routine, when defined,
233 * is passed a bitmap in "valid_mask" and it will have ngpios
234 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can
235 * then directly set some bits to "0" if they cannot be used for
238 void (*init_valid_mask)(struct gpio_chip *gc,
239 unsigned long *valid_mask,
240 unsigned int ngpios);
245 * Flag to track GPIO chip irq member's initialization.
246 * This flag will make sure GPIO chip irq members are not used
247 * before they are initialized.
254 * If not %NULL holds bitmask of GPIOs which are valid to be included
255 * in IRQ domain of the chip.
257 unsigned long *valid_mask;
262 * Required for static IRQ allocation. If set, irq_domain_add_simple()
263 * will allocate and map all IRQs during initialization.
270 * Store old irq_chip irq_enable callback
272 void (*irq_enable)(struct irq_data *data);
277 * Store old irq_chip irq_disable callback
279 void (*irq_disable)(struct irq_data *data);
283 * Store old irq_chip irq_unmask callback
285 void (*irq_unmask)(struct irq_data *data);
290 * Store old irq_chip irq_mask callback
292 void (*irq_mask)(struct irq_data *data);
296 * struct gpio_chip - abstract a GPIO controller
297 * @label: a functional name for the GPIO device, such as a part
298 * number or the name of the SoC IP-block implementing it.
299 * @gpiodev: the internal state holder, opaque struct
300 * @parent: optional parent device providing the GPIOs
301 * @owner: helps prevent removal of modules exporting active GPIOs
302 * @request: optional hook for chip-specific activation, such as
303 * enabling module power and clock; may sleep
304 * @free: optional hook for chip-specific deactivation, such as
305 * disabling module power and clock; may sleep
306 * @get_direction: returns direction for signal "offset", 0=out, 1=in,
307 * (same as GPIO_LINE_DIRECTION_OUT / GPIO_LINE_DIRECTION_IN),
308 * or negative error. It is recommended to always implement this
309 * function, even on input-only or output-only gpio chips.
310 * @direction_input: configures signal "offset" as input, or returns error
311 * This can be omitted on input-only or output-only gpio chips.
312 * @direction_output: configures signal "offset" as output, or returns error
313 * This can be omitted on input-only or output-only gpio chips.
314 * @get: returns value for signal "offset", 0=low, 1=high, or negative error
315 * @get_multiple: reads values for multiple signals defined by "mask" and
316 * stores them in "bits", returns 0 on success or negative error
317 * @set: assigns output value for signal "offset"
318 * @set_multiple: assigns output values for multiple signals defined by "mask"
319 * @set_config: optional hook for all kinds of settings. Uses the same
320 * packed config format as generic pinconf.
321 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
322 * implementation may not sleep
323 * @dbg_show: optional routine to show contents in debugfs; default code
324 * will be used when this is omitted, but custom code can show extra
325 * state (such as pullup/pulldown configuration).
326 * @init_valid_mask: optional routine to initialize @valid_mask, to be used if
327 * not all GPIOs are valid.
328 * @add_pin_ranges: optional routine to initialize pin ranges, to be used when
329 * requires special mapping of the pins that provides GPIO functionality.
330 * It is called after adding GPIO chip and before adding IRQ chip.
331 * @base: identifies the first GPIO number handled by this chip;
332 * or, if negative during registration, requests dynamic ID allocation.
333 * DEPRECATION: providing anything non-negative and nailing the base
334 * offset of GPIO chips is deprecated. Please pass -1 as base to
335 * let gpiolib select the chip base in all possible cases. We want to
336 * get rid of the static GPIO number space in the long run.
337 * @ngpio: the number of GPIOs handled by this controller; the last GPIO
338 * handled is (base + ngpio - 1).
339 * @names: if set, must be an array of strings to use as alternative
340 * names for the GPIOs in this chip. Any entry in the array
341 * may be NULL if there is no alias for the GPIO, however the
342 * array must be @ngpio entries long. A name can include a single printk
343 * format specifier for an unsigned int. It is substituted by the actual
344 * number of the gpio.
345 * @can_sleep: flag must be set iff get()/set() methods sleep, as they
346 * must while accessing GPIO expander chips over I2C or SPI. This
347 * implies that if the chip supports IRQs, these IRQs need to be threaded
348 * as the chip access may sleep when e.g. reading out the IRQ status
350 * @read_reg: reader function for generic GPIO
351 * @write_reg: writer function for generic GPIO
352 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
353 * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
354 * generic GPIO core. It is for internal housekeeping only.
355 * @reg_dat: data (in) register for generic GPIO
356 * @reg_set: output set register (out=high) for generic GPIO
357 * @reg_clr: output clear register (out=low) for generic GPIO
358 * @reg_dir_out: direction out setting register for generic GPIO
359 * @reg_dir_in: direction in setting register for generic GPIO
360 * @bgpio_dir_unreadable: indicates that the direction register(s) cannot
361 * be read and we need to rely on out internal state tracking.
362 * @bgpio_bits: number of register bits used for a generic GPIO i.e.
363 * <register width> * 8
364 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
365 * shadowed and real data registers writes together.
366 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits
368 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
369 * direction safely. A "1" in this word means the line is set as
372 * A gpio_chip can help platforms abstract various sources of GPIOs so
373 * they can all be accessed through a common programing interface.
374 * Example sources would be SOC controllers, FPGAs, multifunction
375 * chips, dedicated GPIO expanders, and so on.
377 * Each chip controls a number of signals, identified in method calls
378 * by "offset" values in the range 0..(@ngpio - 1). When those signals
379 * are referenced through calls like gpio_get_value(gpio), the offset
380 * is calculated by subtracting @base from the gpio number.
384 struct gpio_device *gpiodev;
385 struct device *parent;
386 struct module *owner;
388 int (*request)(struct gpio_chip *gc,
389 unsigned int offset);
390 void (*free)(struct gpio_chip *gc,
391 unsigned int offset);
392 int (*get_direction)(struct gpio_chip *gc,
393 unsigned int offset);
394 int (*direction_input)(struct gpio_chip *gc,
395 unsigned int offset);
396 int (*direction_output)(struct gpio_chip *gc,
397 unsigned int offset, int value);
398 int (*get)(struct gpio_chip *gc,
399 unsigned int offset);
400 int (*get_multiple)(struct gpio_chip *gc,
402 unsigned long *bits);
403 void (*set)(struct gpio_chip *gc,
404 unsigned int offset, int value);
405 void (*set_multiple)(struct gpio_chip *gc,
407 unsigned long *bits);
408 int (*set_config)(struct gpio_chip *gc,
410 unsigned long config);
411 int (*to_irq)(struct gpio_chip *gc,
412 unsigned int offset);
414 void (*dbg_show)(struct seq_file *s,
415 struct gpio_chip *gc);
417 int (*init_valid_mask)(struct gpio_chip *gc,
418 unsigned long *valid_mask,
419 unsigned int ngpios);
421 int (*add_pin_ranges)(struct gpio_chip *gc);
425 const char *const *names;
428 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
429 unsigned long (*read_reg)(void __iomem *reg);
430 void (*write_reg)(void __iomem *reg, unsigned long data);
432 void __iomem *reg_dat;
433 void __iomem *reg_set;
434 void __iomem *reg_clr;
435 void __iomem *reg_dir_out;
436 void __iomem *reg_dir_in;
437 bool bgpio_dir_unreadable;
439 spinlock_t bgpio_lock;
440 unsigned long bgpio_data;
441 unsigned long bgpio_dir;
442 #endif /* CONFIG_GPIO_GENERIC */
444 #ifdef CONFIG_GPIOLIB_IRQCHIP
446 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
447 * to handle IRQs for most practical cases.
453 * Integrates interrupt chip functionality with the GPIO chip. Can be
454 * used to handle IRQs for most practical cases.
456 struct gpio_irq_chip irq;
457 #endif /* CONFIG_GPIOLIB_IRQCHIP */
462 * If not %NULL holds bitmask of GPIOs which are valid to be used
465 unsigned long *valid_mask;
467 #if defined(CONFIG_OF_GPIO)
469 * If CONFIG_OF is enabled, then all GPIO controllers described in the
470 * device tree automatically may have an OF translation
476 * Pointer to a device tree node representing this GPIO controller.
478 struct device_node *of_node;
483 * Number of cells used to form the GPIO specifier.
485 unsigned int of_gpio_n_cells;
490 * Callback to translate a device tree GPIO specifier into a chip-
491 * relative GPIO number and flags.
493 int (*of_xlate)(struct gpio_chip *gc,
494 const struct of_phandle_args *gpiospec, u32 *flags);
497 * @of_gpio_ranges_fallback:
499 * Optional hook for the case that no gpio-ranges property is defined
500 * within the device tree node "np" (usually DT before introduction
501 * of gpio-ranges). So this callback is helpful to provide the
502 * necessary backward compatibility for the pin ranges.
504 int (*of_gpio_ranges_fallback)(struct gpio_chip *gc,
505 struct device_node *np);
507 #endif /* CONFIG_OF_GPIO */
510 extern const char *gpiochip_is_requested(struct gpio_chip *gc,
511 unsigned int offset);
514 * for_each_requested_gpio_in_range - iterates over requested GPIOs in a given range
515 * @chip: the chip to query
517 * @base: first GPIO in the range
518 * @size: amount of GPIOs to check starting from @base
519 * @label: label of current GPIO
521 #define for_each_requested_gpio_in_range(chip, i, base, size, label) \
522 for (i = 0; i < size; i++) \
523 if ((label = gpiochip_is_requested(chip, base + i)) == NULL) {} else
525 /* Iterates over all requested GPIO of the given @chip */
526 #define for_each_requested_gpio(chip, i, label) \
527 for_each_requested_gpio_in_range(chip, i, 0, chip->ngpio, label)
529 /* add/remove chips */
530 extern int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,
531 struct lock_class_key *lock_key,
532 struct lock_class_key *request_key);
535 * gpiochip_add_data() - register a gpio_chip
536 * @gc: the chip to register, with gc->base initialized
537 * @data: driver-private data associated with this chip
539 * Context: potentially before irqs will work
541 * When gpiochip_add_data() is called very early during boot, so that GPIOs
542 * can be freely used, the gc->parent device must be registered before
543 * the gpio framework's arch_initcall(). Otherwise sysfs initialization
544 * for GPIOs will fail rudely.
546 * gpiochip_add_data() must only be called after gpiolib initialization,
547 * ie after core_initcall().
549 * If gc->base is negative, this requests dynamic assignment of
550 * a range of valid GPIOs.
553 * A negative errno if the chip can't be registered, such as because the
554 * gc->base is invalid or already associated with a different chip.
555 * Otherwise it returns zero as a success code.
557 #ifdef CONFIG_LOCKDEP
558 #define gpiochip_add_data(gc, data) ({ \
559 static struct lock_class_key lock_key; \
560 static struct lock_class_key request_key; \
561 gpiochip_add_data_with_key(gc, data, &lock_key, \
564 #define devm_gpiochip_add_data(dev, gc, data) ({ \
565 static struct lock_class_key lock_key; \
566 static struct lock_class_key request_key; \
567 devm_gpiochip_add_data_with_key(dev, gc, data, &lock_key, \
571 #define gpiochip_add_data(gc, data) gpiochip_add_data_with_key(gc, data, NULL, NULL)
572 #define devm_gpiochip_add_data(dev, gc, data) \
573 devm_gpiochip_add_data_with_key(dev, gc, data, NULL, NULL)
574 #endif /* CONFIG_LOCKDEP */
576 static inline int gpiochip_add(struct gpio_chip *gc)
578 return gpiochip_add_data(gc, NULL);
580 extern void gpiochip_remove(struct gpio_chip *gc);
581 extern int devm_gpiochip_add_data_with_key(struct device *dev, struct gpio_chip *gc, void *data,
582 struct lock_class_key *lock_key,
583 struct lock_class_key *request_key);
585 extern struct gpio_chip *gpiochip_find(void *data,
586 int (*match)(struct gpio_chip *gc, void *data));
588 bool gpiochip_line_is_irq(struct gpio_chip *gc, unsigned int offset);
589 int gpiochip_reqres_irq(struct gpio_chip *gc, unsigned int offset);
590 void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset);
591 void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset);
592 void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset);
594 /* Line status inquiry for drivers */
595 bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset);
596 bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset);
598 /* Sleep persistence inquiry for drivers */
599 bool gpiochip_line_is_persistent(struct gpio_chip *gc, unsigned int offset);
600 bool gpiochip_line_is_valid(const struct gpio_chip *gc, unsigned int offset);
602 /* get driver data */
603 void *gpiochip_get_data(struct gpio_chip *gc);
611 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
613 void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
614 unsigned int parent_hwirq,
615 unsigned int parent_type);
616 void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
617 unsigned int parent_hwirq,
618 unsigned int parent_type);
622 static inline void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
623 unsigned int parent_hwirq,
624 unsigned int parent_type)
629 static inline void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
630 unsigned int parent_hwirq,
631 unsigned int parent_type)
636 #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
638 int bgpio_init(struct gpio_chip *gc, struct device *dev,
639 unsigned long sz, void __iomem *dat, void __iomem *set,
640 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
641 unsigned long flags);
643 #define BGPIOF_BIG_ENDIAN BIT(0)
644 #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
645 #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
646 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
647 #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
648 #define BGPIOF_NO_OUTPUT BIT(5) /* only input */
649 #define BGPIOF_NO_SET_ON_INPUT BIT(6)
651 int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
652 irq_hw_number_t hwirq);
653 void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq);
655 int gpiochip_irq_domain_activate(struct irq_domain *domain,
656 struct irq_data *data, bool reserve);
657 void gpiochip_irq_domain_deactivate(struct irq_domain *domain,
658 struct irq_data *data);
660 void gpiochip_set_nested_irqchip(struct gpio_chip *gc,
661 struct irq_chip *irqchip,
662 unsigned int parent_irq);
664 int gpiochip_irqchip_add_key(struct gpio_chip *gc,
665 struct irq_chip *irqchip,
666 unsigned int first_irq,
667 irq_flow_handler_t handler,
670 struct lock_class_key *lock_key,
671 struct lock_class_key *request_key);
673 bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gc,
674 unsigned int offset);
676 #ifdef CONFIG_GPIOLIB_IRQCHIP
677 int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
678 struct irq_domain *domain);
680 static inline int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
681 struct irq_domain *domain)
688 #ifdef CONFIG_LOCKDEP
691 * Lockdep requires that each irqchip instance be created with a
692 * unique key so as to avoid unnecessary warnings. This upfront
693 * boilerplate static inlines provides such a key for each
696 static inline int gpiochip_irqchip_add(struct gpio_chip *gc,
697 struct irq_chip *irqchip,
698 unsigned int first_irq,
699 irq_flow_handler_t handler,
702 static struct lock_class_key lock_key;
703 static struct lock_class_key request_key;
705 return gpiochip_irqchip_add_key(gc, irqchip, first_irq,
706 handler, type, false,
707 &lock_key, &request_key);
710 static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gc,
711 struct irq_chip *irqchip,
712 unsigned int first_irq,
713 irq_flow_handler_t handler,
717 static struct lock_class_key lock_key;
718 static struct lock_class_key request_key;
720 return gpiochip_irqchip_add_key(gc, irqchip, first_irq,
722 &lock_key, &request_key);
724 #else /* ! CONFIG_LOCKDEP */
725 static inline int gpiochip_irqchip_add(struct gpio_chip *gc,
726 struct irq_chip *irqchip,
727 unsigned int first_irq,
728 irq_flow_handler_t handler,
731 return gpiochip_irqchip_add_key(gc, irqchip, first_irq,
732 handler, type, false, NULL, NULL);
735 static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gc,
736 struct irq_chip *irqchip,
737 unsigned int first_irq,
738 irq_flow_handler_t handler,
741 return gpiochip_irqchip_add_key(gc, irqchip, first_irq,
742 handler, type, true, NULL, NULL);
744 #endif /* CONFIG_LOCKDEP */
746 int gpiochip_generic_request(struct gpio_chip *gc, unsigned int offset);
747 void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset);
748 int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset,
749 unsigned long config);
752 * struct gpio_pin_range - pin range controlled by a gpio chip
753 * @node: list for maintaining set of pin ranges, used internally
754 * @pctldev: pinctrl device which handles corresponding pins
755 * @range: actual range of pins controlled by a gpio controller
757 struct gpio_pin_range {
758 struct list_head node;
759 struct pinctrl_dev *pctldev;
760 struct pinctrl_gpio_range range;
763 #ifdef CONFIG_PINCTRL
765 int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
766 unsigned int gpio_offset, unsigned int pin_offset,
768 int gpiochip_add_pingroup_range(struct gpio_chip *gc,
769 struct pinctrl_dev *pctldev,
770 unsigned int gpio_offset, const char *pin_group);
771 void gpiochip_remove_pin_ranges(struct gpio_chip *gc);
773 #else /* ! CONFIG_PINCTRL */
776 gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
777 unsigned int gpio_offset, unsigned int pin_offset,
783 gpiochip_add_pingroup_range(struct gpio_chip *gc,
784 struct pinctrl_dev *pctldev,
785 unsigned int gpio_offset, const char *pin_group)
791 gpiochip_remove_pin_ranges(struct gpio_chip *gc)
795 #endif /* CONFIG_PINCTRL */
797 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *gc,
800 enum gpio_lookup_flags lflags,
801 enum gpiod_flags dflags);
802 void gpiochip_free_own_desc(struct gpio_desc *desc);
804 #ifdef CONFIG_GPIOLIB
806 /* lock/unlock as IRQ */
807 int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset);
808 void gpiochip_unlock_as_irq(struct gpio_chip *gc, unsigned int offset);
811 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
813 #else /* CONFIG_GPIOLIB */
815 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
817 /* GPIO can never have been requested */
819 return ERR_PTR(-ENODEV);
822 static inline int gpiochip_lock_as_irq(struct gpio_chip *gc,
829 static inline void gpiochip_unlock_as_irq(struct gpio_chip *gc,
834 #endif /* CONFIG_GPIOLIB */
836 #endif /* __LINUX_GPIO_DRIVER_H */