GNU Linux-libre 6.7.9-gnu
[releases.git] / include / linux / dpll.h
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  *  Copyright (c) 2023 Meta Platforms, Inc. and affiliates
4  *  Copyright (c) 2023 Intel and affiliates
5  */
6
7 #ifndef __DPLL_H__
8 #define __DPLL_H__
9
10 #include <uapi/linux/dpll.h>
11 #include <linux/device.h>
12 #include <linux/netlink.h>
13
14 struct dpll_device;
15 struct dpll_pin;
16
17 struct dpll_device_ops {
18         int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv,
19                         enum dpll_mode *mode, struct netlink_ext_ack *extack);
20         bool (*mode_supported)(const struct dpll_device *dpll, void *dpll_priv,
21                                const enum dpll_mode mode,
22                                struct netlink_ext_ack *extack);
23         int (*lock_status_get)(const struct dpll_device *dpll, void *dpll_priv,
24                                enum dpll_lock_status *status,
25                                struct netlink_ext_ack *extack);
26         int (*temp_get)(const struct dpll_device *dpll, void *dpll_priv,
27                         s32 *temp, struct netlink_ext_ack *extack);
28 };
29
30 struct dpll_pin_ops {
31         int (*frequency_set)(const struct dpll_pin *pin, void *pin_priv,
32                              const struct dpll_device *dpll, void *dpll_priv,
33                              const u64 frequency,
34                              struct netlink_ext_ack *extack);
35         int (*frequency_get)(const struct dpll_pin *pin, void *pin_priv,
36                              const struct dpll_device *dpll, void *dpll_priv,
37                              u64 *frequency, struct netlink_ext_ack *extack);
38         int (*direction_set)(const struct dpll_pin *pin, void *pin_priv,
39                              const struct dpll_device *dpll, void *dpll_priv,
40                              const enum dpll_pin_direction direction,
41                              struct netlink_ext_ack *extack);
42         int (*direction_get)(const struct dpll_pin *pin, void *pin_priv,
43                              const struct dpll_device *dpll, void *dpll_priv,
44                              enum dpll_pin_direction *direction,
45                              struct netlink_ext_ack *extack);
46         int (*state_on_pin_get)(const struct dpll_pin *pin, void *pin_priv,
47                                 const struct dpll_pin *parent_pin,
48                                 void *parent_pin_priv,
49                                 enum dpll_pin_state *state,
50                                 struct netlink_ext_ack *extack);
51         int (*state_on_dpll_get)(const struct dpll_pin *pin, void *pin_priv,
52                                  const struct dpll_device *dpll,
53                                  void *dpll_priv, enum dpll_pin_state *state,
54                                  struct netlink_ext_ack *extack);
55         int (*state_on_pin_set)(const struct dpll_pin *pin, void *pin_priv,
56                                 const struct dpll_pin *parent_pin,
57                                 void *parent_pin_priv,
58                                 const enum dpll_pin_state state,
59                                 struct netlink_ext_ack *extack);
60         int (*state_on_dpll_set)(const struct dpll_pin *pin, void *pin_priv,
61                                  const struct dpll_device *dpll,
62                                  void *dpll_priv,
63                                  const enum dpll_pin_state state,
64                                  struct netlink_ext_ack *extack);
65         int (*prio_get)(const struct dpll_pin *pin,  void *pin_priv,
66                         const struct dpll_device *dpll,  void *dpll_priv,
67                         u32 *prio, struct netlink_ext_ack *extack);
68         int (*prio_set)(const struct dpll_pin *pin, void *pin_priv,
69                         const struct dpll_device *dpll, void *dpll_priv,
70                         const u32 prio, struct netlink_ext_ack *extack);
71         int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv,
72                                 const struct dpll_device *dpll, void *dpll_priv,
73                                 s64 *phase_offset,
74                                 struct netlink_ext_ack *extack);
75         int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv,
76                                 const struct dpll_device *dpll, void *dpll_priv,
77                                 s32 *phase_adjust,
78                                 struct netlink_ext_ack *extack);
79         int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv,
80                                 const struct dpll_device *dpll, void *dpll_priv,
81                                 const s32 phase_adjust,
82                                 struct netlink_ext_ack *extack);
83 };
84
85 struct dpll_pin_frequency {
86         u64 min;
87         u64 max;
88 };
89
90 #define DPLL_PIN_FREQUENCY_RANGE(_min, _max)    \
91         {                                       \
92                 .min = _min,                    \
93                 .max = _max,                    \
94         }
95
96 #define DPLL_PIN_FREQUENCY(_val) DPLL_PIN_FREQUENCY_RANGE(_val, _val)
97 #define DPLL_PIN_FREQUENCY_1PPS \
98         DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_1_HZ)
99 #define DPLL_PIN_FREQUENCY_10MHZ \
100         DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_MHZ)
101 #define DPLL_PIN_FREQUENCY_IRIG_B \
102         DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_KHZ)
103 #define DPLL_PIN_FREQUENCY_DCF77 \
104         DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ)
105
106 struct dpll_pin_phase_adjust_range {
107         s32 min;
108         s32 max;
109 };
110
111 struct dpll_pin_properties {
112         const char *board_label;
113         const char *panel_label;
114         const char *package_label;
115         enum dpll_pin_type type;
116         unsigned long capabilities;
117         u32 freq_supported_num;
118         struct dpll_pin_frequency *freq_supported;
119         struct dpll_pin_phase_adjust_range phase_range;
120 };
121
122 #if IS_ENABLED(CONFIG_DPLL)
123 size_t dpll_msg_pin_handle_size(struct dpll_pin *pin);
124 int dpll_msg_add_pin_handle(struct sk_buff *msg, struct dpll_pin *pin);
125 #else
126 static inline size_t dpll_msg_pin_handle_size(struct dpll_pin *pin)
127 {
128         return 0;
129 }
130
131 static inline int dpll_msg_add_pin_handle(struct sk_buff *msg, struct dpll_pin *pin)
132 {
133         return 0;
134 }
135 #endif
136
137 struct dpll_device *
138 dpll_device_get(u64 clock_id, u32 dev_driver_id, struct module *module);
139
140 void dpll_device_put(struct dpll_device *dpll);
141
142 int dpll_device_register(struct dpll_device *dpll, enum dpll_type type,
143                          const struct dpll_device_ops *ops, void *priv);
144
145 void dpll_device_unregister(struct dpll_device *dpll,
146                             const struct dpll_device_ops *ops, void *priv);
147
148 struct dpll_pin *
149 dpll_pin_get(u64 clock_id, u32 dev_driver_id, struct module *module,
150              const struct dpll_pin_properties *prop);
151
152 int dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin,
153                       const struct dpll_pin_ops *ops, void *priv);
154
155 void dpll_pin_unregister(struct dpll_device *dpll, struct dpll_pin *pin,
156                          const struct dpll_pin_ops *ops, void *priv);
157
158 void dpll_pin_put(struct dpll_pin *pin);
159
160 int dpll_pin_on_pin_register(struct dpll_pin *parent, struct dpll_pin *pin,
161                              const struct dpll_pin_ops *ops, void *priv);
162
163 void dpll_pin_on_pin_unregister(struct dpll_pin *parent, struct dpll_pin *pin,
164                                 const struct dpll_pin_ops *ops, void *priv);
165
166 int dpll_device_change_ntf(struct dpll_device *dpll);
167
168 int dpll_pin_change_ntf(struct dpll_pin *pin);
169
170 #endif