1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
6 #ifndef K3_UDMA_GLUE_H_
7 #define K3_UDMA_GLUE_H_
9 #include <linux/types.h>
10 #include <linux/soc/ti/k3-ringacc.h>
11 #include <linux/dma/ti-cppi5.h>
13 struct k3_udma_glue_tx_channel_cfg {
14 struct k3_ring_cfg tx_cfg;
15 struct k3_ring_cfg txcq_cfg;
24 struct k3_udma_glue_tx_channel;
26 struct k3_udma_glue_tx_channel *k3_udma_glue_request_tx_chn(struct device *dev,
27 const char *name, struct k3_udma_glue_tx_channel_cfg *cfg);
29 void k3_udma_glue_release_tx_chn(struct k3_udma_glue_tx_channel *tx_chn);
30 int k3_udma_glue_push_tx_chn(struct k3_udma_glue_tx_channel *tx_chn,
31 struct cppi5_host_desc_t *desc_tx,
33 int k3_udma_glue_pop_tx_chn(struct k3_udma_glue_tx_channel *tx_chn,
34 dma_addr_t *desc_dma);
35 int k3_udma_glue_enable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn);
36 void k3_udma_glue_disable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn);
37 void k3_udma_glue_tdown_tx_chn(struct k3_udma_glue_tx_channel *tx_chn,
39 void k3_udma_glue_reset_tx_chn(struct k3_udma_glue_tx_channel *tx_chn,
40 void *data, void (*cleanup)(void *data, dma_addr_t desc_dma));
41 u32 k3_udma_glue_tx_get_hdesc_size(struct k3_udma_glue_tx_channel *tx_chn);
42 u32 k3_udma_glue_tx_get_txcq_id(struct k3_udma_glue_tx_channel *tx_chn);
43 int k3_udma_glue_tx_get_irq(struct k3_udma_glue_tx_channel *tx_chn);
45 k3_udma_glue_tx_get_dma_device(struct k3_udma_glue_tx_channel *tx_chn);
46 void k3_udma_glue_tx_dma_to_cppi5_addr(struct k3_udma_glue_tx_channel *tx_chn,
48 void k3_udma_glue_tx_cppi5_to_dma_addr(struct k3_udma_glue_tx_channel *tx_chn,
52 K3_UDMA_GLUE_SRC_TAG_LO_KEEP = 0,
53 K3_UDMA_GLUE_SRC_TAG_LO_USE_FLOW_REG = 1,
54 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_FLOW_ID = 2,
55 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG = 4,
59 * k3_udma_glue_rx_flow_cfg - UDMA RX flow cfg
61 * @rx_cfg: RX ring configuration
62 * @rxfdq_cfg: RX free Host PD ring configuration
63 * @ring_rxq_id: RX ring id (or -1 for any)
64 * @ring_rxfdq0_id: RX free Host PD ring (FDQ) if (or -1 for any)
65 * @rx_error_handling: Rx Error Handling Mode (0 - drop, 1 - re-try)
66 * @src_tag_lo_sel: Rx Source Tag Low Byte Selector in Host PD
68 struct k3_udma_glue_rx_flow_cfg {
69 struct k3_ring_cfg rx_cfg;
70 struct k3_ring_cfg rxfdq_cfg;
73 bool rx_error_handling;
78 * k3_udma_glue_rx_channel_cfg - UDMA RX channel cfg
80 * @psdata_size: SW Data is present in Host PD of @swdata_size bytes
81 * @flow_id_base: first flow_id used by channel.
82 * if @flow_id_base = -1 - range of GP rflows will be
83 * allocated dynamically.
84 * @flow_id_num: number of RX flows used by channel
85 * @flow_id_use_rxchan_id: use RX channel id as flow id,
86 * used only if @flow_id_num = 1
87 * @remote indication that RX channel is remote - some remote CPU
88 * core owns and control the RX channel. Linux Host only
89 * allowed to attach and configure RX Flow within RX
90 * channel. if set - not RX channel operation will be
91 * performed by K3 NAVSS DMA glue interface.
92 * @def_flow_cfg default RX flow configuration,
93 * used only if @flow_id_num = 1
95 struct k3_udma_glue_rx_channel_cfg {
99 bool flow_id_use_rxchan_id;
102 struct k3_udma_glue_rx_flow_cfg *def_flow_cfg;
105 struct k3_udma_glue_rx_channel;
107 struct k3_udma_glue_rx_channel *k3_udma_glue_request_rx_chn(
110 struct k3_udma_glue_rx_channel_cfg *cfg);
112 void k3_udma_glue_release_rx_chn(struct k3_udma_glue_rx_channel *rx_chn);
113 int k3_udma_glue_enable_rx_chn(struct k3_udma_glue_rx_channel *rx_chn);
114 void k3_udma_glue_disable_rx_chn(struct k3_udma_glue_rx_channel *rx_chn);
115 void k3_udma_glue_tdown_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
117 int k3_udma_glue_push_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
118 u32 flow_num, struct cppi5_host_desc_t *desc_tx,
119 dma_addr_t desc_dma);
120 int k3_udma_glue_pop_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
121 u32 flow_num, dma_addr_t *desc_dma);
122 int k3_udma_glue_rx_flow_init(struct k3_udma_glue_rx_channel *rx_chn,
123 u32 flow_idx, struct k3_udma_glue_rx_flow_cfg *flow_cfg);
124 u32 k3_udma_glue_rx_flow_get_fdq_id(struct k3_udma_glue_rx_channel *rx_chn,
126 u32 k3_udma_glue_rx_get_flow_id_base(struct k3_udma_glue_rx_channel *rx_chn);
127 int k3_udma_glue_rx_get_irq(struct k3_udma_glue_rx_channel *rx_chn,
129 void k3_udma_glue_rx_put_irq(struct k3_udma_glue_rx_channel *rx_chn,
131 void k3_udma_glue_reset_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
132 u32 flow_num, void *data,
133 void (*cleanup)(void *data, dma_addr_t desc_dma),
135 int k3_udma_glue_rx_flow_enable(struct k3_udma_glue_rx_channel *rx_chn,
137 int k3_udma_glue_rx_flow_disable(struct k3_udma_glue_rx_channel *rx_chn,
140 k3_udma_glue_rx_get_dma_device(struct k3_udma_glue_rx_channel *rx_chn);
141 void k3_udma_glue_rx_dma_to_cppi5_addr(struct k3_udma_glue_rx_channel *rx_chn,
143 void k3_udma_glue_rx_cppi5_to_dma_addr(struct k3_udma_glue_rx_channel *rx_chn,
146 #endif /* K3_UDMA_GLUE_H_ */