1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 #ifndef __LINUX_CLK_PROVIDER_H
7 #define __LINUX_CLK_PROVIDER_H
10 #include <linux/of_clk.h>
13 * flags used across common struct clk. these flags should only affect the
14 * top-level framework. custom flags for dealing with hardware specifics
15 * belong in struct clk_foo
17 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
19 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
22 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
28 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
30 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
31 /* parents need enable during gate/ungate, set rate and re-parent */
32 #define CLK_OPS_PARENT_ENABLE BIT(12)
33 /* duty cycle call may be forwarded to the parent clock */
34 #define CLK_DUTY_CYCLE_PARENT BIT(13)
42 * struct clk_rate_request - Structure encoding the clk constraints that
43 * a clock user might require.
45 * @rate: Requested clock rate. This field will be adjusted by
46 * clock drivers according to hardware capabilities.
47 * @min_rate: Minimum rate imposed by clk users.
48 * @max_rate: Maximum rate imposed by clk users.
49 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
50 * requested constraints.
51 * @best_parent_hw: The most appropriate parent clock that fulfills the
52 * requested constraints.
55 struct clk_rate_request {
57 unsigned long min_rate;
58 unsigned long max_rate;
59 unsigned long best_parent_rate;
60 struct clk_hw *best_parent_hw;
64 * struct clk_duty - Structure encoding the duty cycle ratio of a clock
66 * @num: Numerator of the duty cycle ratio
67 * @den: Denominator of the duty cycle ratio
75 * struct clk_ops - Callback operations for hardware clocks; these are to
76 * be provided by the clock implementation, and will be called by drivers
77 * through the clk_* api.
79 * @prepare: Prepare the clock for enabling. This must not return until
80 * the clock is fully prepared, and it's safe to call clk_enable.
81 * This callback is intended to allow clock implementations to
82 * do any initialisation that may sleep. Called with
85 * @unprepare: Release the clock from its prepared state. This will typically
86 * undo any work done in the @prepare callback. Called with
89 * @is_prepared: Queries the hardware to determine if the clock is prepared.
90 * This function is allowed to sleep. Optional, if this op is not
91 * set then the prepare count will be used.
93 * @unprepare_unused: Unprepare the clock atomically. Only called from
94 * clk_disable_unused for prepare clocks with special needs.
95 * Called with prepare mutex held. This function may sleep.
97 * @enable: Enable the clock atomically. This must not return until the
98 * clock is generating a valid clock signal, usable by consumer
99 * devices. Called with enable_lock held. This function must not
102 * @disable: Disable the clock atomically. Called with enable_lock held.
103 * This function must not sleep.
105 * @is_enabled: Queries the hardware to determine if the clock is enabled.
106 * This function must not sleep. Optional, if this op is not
107 * set then the enable count will be used.
109 * @disable_unused: Disable the clock atomically. Only called from
110 * clk_disable_unused for gate clocks with special needs.
111 * Called with enable_lock held. This function must not
114 * @save_context: Save the context of the clock in prepration for poweroff.
116 * @restore_context: Restore the context of the clock after a restoration
119 * @recalc_rate: Recalculate the rate of this clock, by querying hardware. The
120 * parent rate is an input parameter. It is up to the caller to
121 * ensure that the prepare_mutex is held across this call.
122 * Returns the calculated rate. Optional, but recommended - if
123 * this op is not set then clock rate will be initialized to 0.
125 * @round_rate: Given a target rate as input, returns the closest rate actually
126 * supported by the clock. The parent rate is an input/output
129 * @determine_rate: Given a target rate as input, returns the closest rate
130 * actually supported by the clock, and optionally the parent clock
131 * that should be used to provide the clock rate.
133 * @set_parent: Change the input source of this clock; for clocks with multiple
134 * possible parents specify a new parent by passing in the index
135 * as a u8 corresponding to the parent in either the .parent_names
136 * or .parents arrays. This function in affect translates an
137 * array index into the value programmed into the hardware.
138 * Returns 0 on success, -EERROR otherwise.
140 * @get_parent: Queries the hardware to determine the parent of a clock. The
141 * return value is a u8 which specifies the index corresponding to
142 * the parent clock. This index can be applied to either the
143 * .parent_names or .parents arrays. In short, this function
144 * translates the parent value read from hardware into an array
145 * index. Currently only called when the clock is initialized by
146 * __clk_init. This callback is mandatory for clocks with
147 * multiple parents. It is optional (and unnecessary) for clocks
148 * with 0 or 1 parents.
150 * @set_rate: Change the rate of this clock. The requested rate is specified
151 * by the second argument, which should typically be the return
152 * of .round_rate call. The third argument gives the parent rate
153 * which is likely helpful for most .set_rate implementation.
154 * Returns 0 on success, -EERROR otherwise.
156 * @set_rate_and_parent: Change the rate and the parent of this clock. The
157 * requested rate is specified by the second argument, which
158 * should typically be the return of .round_rate call. The
159 * third argument gives the parent rate which is likely helpful
160 * for most .set_rate_and_parent implementation. The fourth
161 * argument gives the parent index. This callback is optional (and
162 * unnecessary) for clocks with 0 or 1 parents as well as
163 * for clocks that can tolerate switching the rate and the parent
164 * separately via calls to .set_parent and .set_rate.
165 * Returns 0 on success, -EERROR otherwise.
167 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
168 * is expressed in ppb (parts per billion). The parent accuracy is
169 * an input parameter.
170 * Returns the calculated accuracy. Optional - if this op is not
171 * set then clock accuracy will be initialized to parent accuracy
172 * or 0 (perfect clock) if clock has no parent.
174 * @get_phase: Queries the hardware to get the current phase of a clock.
175 * Returned values are 0-359 degrees on success, negative
176 * error codes on failure.
178 * @set_phase: Shift the phase this clock signal in degrees specified
179 * by the second argument. Valid values for degrees are
180 * 0-359. Return 0 on success, otherwise -EERROR.
182 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
183 * of a clock. Returned values denominator cannot be 0 and must be
184 * superior or equal to the numerator.
186 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
187 * the numerator (2nd argurment) and denominator (3rd argument).
188 * Argument must be a valid ratio (denominator > 0
189 * and >= numerator) Return 0 on success, otherwise -EERROR.
191 * @init: Perform platform-specific initialization magic.
192 * This is not used by any of the basic clock types.
193 * This callback exist for HW which needs to perform some
194 * initialisation magic for CCF to get an accurate view of the
195 * clock. It may also be used dynamic resource allocation is
196 * required. It shall not used to deal with clock parameters,
197 * such as rate or parents.
198 * Returns 0 on success, -EERROR otherwise.
200 * @terminate: Free any resource allocated by init.
202 * @debug_init: Set up type-specific debugfs entries for this clock. This
203 * is called once, after the debugfs directory entry for this
204 * clock has been created. The dentry pointer representing that
205 * directory is provided as an argument. Called with
206 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
209 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
210 * implementations to split any work between atomic (enable) and sleepable
211 * (prepare) contexts. If enabling a clock requires code that might sleep,
212 * this must be done in clk_prepare. Clock enable code that will never be
213 * called in a sleepable context may be implemented in clk_enable.
215 * Typically, drivers will call clk_prepare when a clock may be needed later
216 * (eg. when a device is opened), and clk_enable when the clock is actually
217 * required (eg. from an interrupt). Note that clk_prepare MUST have been
218 * called before clk_enable.
221 int (*prepare)(struct clk_hw *hw);
222 void (*unprepare)(struct clk_hw *hw);
223 int (*is_prepared)(struct clk_hw *hw);
224 void (*unprepare_unused)(struct clk_hw *hw);
225 int (*enable)(struct clk_hw *hw);
226 void (*disable)(struct clk_hw *hw);
227 int (*is_enabled)(struct clk_hw *hw);
228 void (*disable_unused)(struct clk_hw *hw);
229 int (*save_context)(struct clk_hw *hw);
230 void (*restore_context)(struct clk_hw *hw);
231 unsigned long (*recalc_rate)(struct clk_hw *hw,
232 unsigned long parent_rate);
233 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
234 unsigned long *parent_rate);
235 int (*determine_rate)(struct clk_hw *hw,
236 struct clk_rate_request *req);
237 int (*set_parent)(struct clk_hw *hw, u8 index);
238 u8 (*get_parent)(struct clk_hw *hw);
239 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
240 unsigned long parent_rate);
241 int (*set_rate_and_parent)(struct clk_hw *hw,
243 unsigned long parent_rate, u8 index);
244 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
245 unsigned long parent_accuracy);
246 int (*get_phase)(struct clk_hw *hw);
247 int (*set_phase)(struct clk_hw *hw, int degrees);
248 int (*get_duty_cycle)(struct clk_hw *hw,
249 struct clk_duty *duty);
250 int (*set_duty_cycle)(struct clk_hw *hw,
251 struct clk_duty *duty);
252 int (*init)(struct clk_hw *hw);
253 void (*terminate)(struct clk_hw *hw);
254 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
258 * struct clk_parent_data - clk parent information
259 * @hw: parent clk_hw pointer (used for clk providers with internal clks)
260 * @fw_name: parent name local to provider registering clk
261 * @name: globally unique parent name (used as a fallback)
262 * @index: parent index local to provider registering clk (if @fw_name absent)
264 struct clk_parent_data {
265 const struct clk_hw *hw;
272 * struct clk_init_data - holds init data that's common to all clocks and is
273 * shared between the clock provider and the common clock framework.
276 * @ops: operations this clock supports
277 * @parent_names: array of string names for all possible parents
278 * @parent_data: array of parent data for all possible parents (when some
279 * parents are external to the clk controller)
280 * @parent_hws: array of pointers to all possible parents (when all parents
281 * are internal to the clk controller)
282 * @num_parents: number of possible parents
283 * @flags: framework-level hints and quirks
285 struct clk_init_data {
287 const struct clk_ops *ops;
288 /* Only one of the following three should be assigned */
289 const char * const *parent_names;
290 const struct clk_parent_data *parent_data;
291 const struct clk_hw **parent_hws;
297 * struct clk_hw - handle for traversing from a struct clk to its corresponding
298 * hardware-specific structure. struct clk_hw should be declared within struct
299 * clk_foo and then referenced by the struct clk instance that uses struct
302 * @core: pointer to the struct clk_core instance that points back to this
303 * struct clk_hw instance
305 * @clk: pointer to the per-user struct clk instance that can be used to call
308 * @init: pointer to struct clk_init_data that contains the init data shared
309 * with the common clock framework. This pointer will be set to NULL once
310 * a clk_register() variant is called on this clk_hw pointer.
313 struct clk_core *core;
315 const struct clk_init_data *init;
319 * DOC: Basic clock implementations common to many platforms
321 * Each basic clock hardware type is comprised of a structure describing the
322 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
323 * unique flags for that hardware type, a registration function and an
324 * alternative macro for static initialization
328 * struct clk_fixed_rate - fixed-rate clock
329 * @hw: handle between common and hardware-specific interfaces
330 * @fixed_rate: constant frequency of clock
331 * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
332 * @flags: hardware specific flags
335 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
336 * instead of what's set in @fixed_accuracy.
338 struct clk_fixed_rate {
340 unsigned long fixed_rate;
341 unsigned long fixed_accuracy;
345 #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
347 extern const struct clk_ops clk_fixed_rate_ops;
348 struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
349 struct device_node *np, const char *name,
350 const char *parent_name, const struct clk_hw *parent_hw,
351 const struct clk_parent_data *parent_data, unsigned long flags,
352 unsigned long fixed_rate, unsigned long fixed_accuracy,
353 unsigned long clk_fixed_flags, bool devm);
354 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
355 const char *parent_name, unsigned long flags,
356 unsigned long fixed_rate);
358 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
360 * @dev: device that is registering this clock
361 * @name: name of this clock
362 * @parent_name: name of clock's parent
363 * @flags: framework-specific flags
364 * @fixed_rate: non-adjustable clock rate
366 #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
367 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
368 NULL, (flags), (fixed_rate), 0, 0, false)
371 * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock
373 * @dev: device that is registering this clock
374 * @name: name of this clock
375 * @parent_name: name of clock's parent
376 * @flags: framework-specific flags
377 * @fixed_rate: non-adjustable clock rate
379 #define devm_clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
380 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
381 NULL, (flags), (fixed_rate), 0, 0, true)
383 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
384 * the clock framework
385 * @dev: device that is registering this clock
386 * @name: name of this clock
387 * @parent_hw: pointer to parent clk
388 * @flags: framework-specific flags
389 * @fixed_rate: non-adjustable clock rate
391 #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \
393 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
394 NULL, (flags), (fixed_rate), 0, 0, false)
396 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
397 * the clock framework
398 * @dev: device that is registering this clock
399 * @name: name of this clock
400 * @parent_data: parent clk data
401 * @flags: framework-specific flags
402 * @fixed_rate: non-adjustable clock rate
404 #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags, \
406 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
407 (parent_data), (flags), (fixed_rate), 0, \
410 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
411 * the clock framework
412 * @dev: device that is registering this clock
413 * @name: name of this clock
414 * @parent_name: name of clock's parent
415 * @flags: framework-specific flags
416 * @fixed_rate: non-adjustable clock rate
417 * @fixed_accuracy: non-adjustable clock accuracy
419 #define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \
422 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \
423 NULL, NULL, (flags), (fixed_rate), \
424 (fixed_accuracy), 0, false)
426 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
427 * clock with the clock framework
428 * @dev: device that is registering this clock
429 * @name: name of this clock
430 * @parent_hw: pointer to parent clk
431 * @flags: framework-specific flags
432 * @fixed_rate: non-adjustable clock rate
433 * @fixed_accuracy: non-adjustable clock accuracy
435 #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \
436 parent_hw, flags, fixed_rate, fixed_accuracy) \
437 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
438 NULL, (flags), (fixed_rate), \
439 (fixed_accuracy), 0, false)
441 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
442 * clock with the clock framework
443 * @dev: device that is registering this clock
444 * @name: name of this clock
445 * @parent_data: name of clock's parent
446 * @flags: framework-specific flags
447 * @fixed_rate: non-adjustable clock rate
448 * @fixed_accuracy: non-adjustable clock accuracy
450 #define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \
451 parent_data, flags, fixed_rate, fixed_accuracy) \
452 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
453 (parent_data), NULL, (flags), \
454 (fixed_rate), (fixed_accuracy), 0, false)
456 * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with
457 * the clock framework
458 * @dev: device that is registering this clock
459 * @name: name of this clock
460 * @parent_data: name of clock's parent
461 * @flags: framework-specific flags
462 * @fixed_rate: non-adjustable clock rate
464 #define clk_hw_register_fixed_rate_parent_accuracy(dev, name, parent_data, \
466 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
467 (parent_data), (flags), (fixed_rate), 0, \
468 CLK_FIXED_RATE_PARENT_ACCURACY, false)
470 void clk_unregister_fixed_rate(struct clk *clk);
471 void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
473 void of_fixed_clk_setup(struct device_node *np);
476 * struct clk_gate - gating clock
478 * @hw: handle between common and hardware-specific interfaces
479 * @reg: register controlling gate
480 * @bit_idx: single bit controlling gate
481 * @flags: hardware-specific flags
482 * @lock: register lock
484 * Clock which can gate its output. Implements .enable & .disable
487 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
488 * enable the clock. Setting this flag does the opposite: setting the bit
489 * disable the clock and clearing it enables the clock
490 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
491 * of this register, and mask of gate bits are in higher 16-bit of this
492 * register. While setting the gate bits, higher 16-bit should also be
493 * updated to indicate changing gate bits.
494 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
495 * the gate register. Setting this flag makes the register accesses big
506 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
508 #define CLK_GATE_SET_TO_DISABLE BIT(0)
509 #define CLK_GATE_HIWORD_MASK BIT(1)
510 #define CLK_GATE_BIG_ENDIAN BIT(2)
512 extern const struct clk_ops clk_gate_ops;
513 struct clk_hw *__clk_hw_register_gate(struct device *dev,
514 struct device_node *np, const char *name,
515 const char *parent_name, const struct clk_hw *parent_hw,
516 const struct clk_parent_data *parent_data,
518 void __iomem *reg, u8 bit_idx,
519 u8 clk_gate_flags, spinlock_t *lock);
520 struct clk *clk_register_gate(struct device *dev, const char *name,
521 const char *parent_name, unsigned long flags,
522 void __iomem *reg, u8 bit_idx,
523 u8 clk_gate_flags, spinlock_t *lock);
525 * clk_hw_register_gate - register a gate clock with the clock framework
526 * @dev: device that is registering this clock
527 * @name: name of this clock
528 * @parent_name: name of this clock's parent
529 * @flags: framework-specific flags for this clock
530 * @reg: register address to control gating of this clock
531 * @bit_idx: which bit in the register controls gating of this clock
532 * @clk_gate_flags: gate-specific flags for this clock
533 * @lock: shared register lock for this clock
535 #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \
536 clk_gate_flags, lock) \
537 __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
538 NULL, (flags), (reg), (bit_idx), \
539 (clk_gate_flags), (lock))
541 * clk_hw_register_gate_parent_hw - register a gate clock with the clock
543 * @dev: device that is registering this clock
544 * @name: name of this clock
545 * @parent_hw: pointer to parent clk
546 * @flags: framework-specific flags for this clock
547 * @reg: register address to control gating of this clock
548 * @bit_idx: which bit in the register controls gating of this clock
549 * @clk_gate_flags: gate-specific flags for this clock
550 * @lock: shared register lock for this clock
552 #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \
553 bit_idx, clk_gate_flags, lock) \
554 __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
555 NULL, (flags), (reg), (bit_idx), \
556 (clk_gate_flags), (lock))
558 * clk_hw_register_gate_parent_data - register a gate clock with the clock
560 * @dev: device that is registering this clock
561 * @name: name of this clock
562 * @parent_data: parent clk data
563 * @flags: framework-specific flags for this clock
564 * @reg: register address to control gating of this clock
565 * @bit_idx: which bit in the register controls gating of this clock
566 * @clk_gate_flags: gate-specific flags for this clock
567 * @lock: shared register lock for this clock
569 #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \
570 bit_idx, clk_gate_flags, lock) \
571 __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
572 (flags), (reg), (bit_idx), \
573 (clk_gate_flags), (lock))
574 void clk_unregister_gate(struct clk *clk);
575 void clk_hw_unregister_gate(struct clk_hw *hw);
576 int clk_gate_is_enabled(struct clk_hw *hw);
578 struct clk_div_table {
584 * struct clk_divider - adjustable divider clock
586 * @hw: handle between common and hardware-specific interfaces
587 * @reg: register containing the divider
588 * @shift: shift to the divider bit field
589 * @width: width of the divider bit field
590 * @table: array of value/divider pairs, last entry should have div = 0
591 * @lock: register lock
593 * Clock with an adjustable divider affecting its output frequency. Implements
594 * .recalc_rate, .set_rate and .round_rate
597 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
598 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
599 * the raw value read from the register, with the value of zero considered
600 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
601 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
602 * the hardware register
603 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
604 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
605 * Some hardware implementations gracefully handle this case and allow a
606 * zero divisor by not modifying their input clock
607 * (divide by one / bypass).
608 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
609 * of this register, and mask of divider bits are in higher 16-bit of this
610 * register. While setting the divider bits, higher 16-bit should also be
611 * updated to indicate changing divider bits.
612 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
613 * to the closest integer instead of the up one.
614 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
615 * not be changed by the clock framework.
616 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
617 * except when the value read from the register is zero, the divisor is
618 * 2^width of the field.
619 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
620 * for the divider register. Setting this flag makes the register accesses
629 const struct clk_div_table *table;
633 #define clk_div_mask(width) ((1 << (width)) - 1)
634 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
636 #define CLK_DIVIDER_ONE_BASED BIT(0)
637 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
638 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
639 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
640 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
641 #define CLK_DIVIDER_READ_ONLY BIT(5)
642 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
643 #define CLK_DIVIDER_BIG_ENDIAN BIT(7)
645 extern const struct clk_ops clk_divider_ops;
646 extern const struct clk_ops clk_divider_ro_ops;
648 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
649 unsigned int val, const struct clk_div_table *table,
650 unsigned long flags, unsigned long width);
651 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
652 unsigned long rate, unsigned long *prate,
653 const struct clk_div_table *table,
654 u8 width, unsigned long flags);
655 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
656 unsigned long rate, unsigned long *prate,
657 const struct clk_div_table *table, u8 width,
658 unsigned long flags, unsigned int val);
659 int divider_get_val(unsigned long rate, unsigned long parent_rate,
660 const struct clk_div_table *table, u8 width,
661 unsigned long flags);
663 struct clk_hw *__clk_hw_register_divider(struct device *dev,
664 struct device_node *np, const char *name,
665 const char *parent_name, const struct clk_hw *parent_hw,
666 const struct clk_parent_data *parent_data, unsigned long flags,
667 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
668 const struct clk_div_table *table, spinlock_t *lock);
669 struct clk *clk_register_divider_table(struct device *dev, const char *name,
670 const char *parent_name, unsigned long flags,
671 void __iomem *reg, u8 shift, u8 width,
672 u8 clk_divider_flags, const struct clk_div_table *table,
675 * clk_register_divider - register a divider clock with the clock framework
676 * @dev: device registering this clock
677 * @name: name of this clock
678 * @parent_name: name of clock's parent
679 * @flags: framework-specific flags
680 * @reg: register address to adjust divider
681 * @shift: number of bits to shift the bitfield
682 * @width: width of the bitfield
683 * @clk_divider_flags: divider-specific flags for this clock
684 * @lock: shared register lock for this clock
686 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \
687 clk_divider_flags, lock) \
688 clk_register_divider_table((dev), (name), (parent_name), (flags), \
689 (reg), (shift), (width), \
690 (clk_divider_flags), NULL, (lock))
692 * clk_hw_register_divider - register a divider clock with the clock framework
693 * @dev: device registering this clock
694 * @name: name of this clock
695 * @parent_name: name of clock's parent
696 * @flags: framework-specific flags
697 * @reg: register address to adjust divider
698 * @shift: number of bits to shift the bitfield
699 * @width: width of the bitfield
700 * @clk_divider_flags: divider-specific flags for this clock
701 * @lock: shared register lock for this clock
703 #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
704 width, clk_divider_flags, lock) \
705 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
706 NULL, (flags), (reg), (shift), (width), \
707 (clk_divider_flags), NULL, (lock))
709 * clk_hw_register_divider_parent_hw - register a divider clock with the clock
711 * @dev: device registering this clock
712 * @name: name of this clock
713 * @parent_hw: pointer to parent clk
714 * @flags: framework-specific flags
715 * @reg: register address to adjust divider
716 * @shift: number of bits to shift the bitfield
717 * @width: width of the bitfield
718 * @clk_divider_flags: divider-specific flags for this clock
719 * @lock: shared register lock for this clock
721 #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \
722 shift, width, clk_divider_flags, \
724 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
725 NULL, (flags), (reg), (shift), (width), \
726 (clk_divider_flags), NULL, (lock))
728 * clk_hw_register_divider_parent_data - register a divider clock with the clock
730 * @dev: device registering this clock
731 * @name: name of this clock
732 * @parent_data: parent clk data
733 * @flags: framework-specific flags
734 * @reg: register address to adjust divider
735 * @shift: number of bits to shift the bitfield
736 * @width: width of the bitfield
737 * @clk_divider_flags: divider-specific flags for this clock
738 * @lock: shared register lock for this clock
740 #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \
742 clk_divider_flags, lock) \
743 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
744 (parent_data), (flags), (reg), (shift), \
745 (width), (clk_divider_flags), NULL, (lock))
747 * clk_hw_register_divider_table - register a table based divider clock with
748 * the clock framework
749 * @dev: device registering this clock
750 * @name: name of this clock
751 * @parent_name: name of clock's parent
752 * @flags: framework-specific flags
753 * @reg: register address to adjust divider
754 * @shift: number of bits to shift the bitfield
755 * @width: width of the bitfield
756 * @clk_divider_flags: divider-specific flags for this clock
757 * @table: array of divider/value pairs ending with a div set to 0
758 * @lock: shared register lock for this clock
760 #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \
761 shift, width, clk_divider_flags, table, \
763 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
764 NULL, (flags), (reg), (shift), (width), \
765 (clk_divider_flags), (table), (lock))
767 * clk_hw_register_divider_table_parent_hw - register a table based divider
768 * clock with the clock framework
769 * @dev: device registering this clock
770 * @name: name of this clock
771 * @parent_hw: pointer to parent clk
772 * @flags: framework-specific flags
773 * @reg: register address to adjust divider
774 * @shift: number of bits to shift the bitfield
775 * @width: width of the bitfield
776 * @clk_divider_flags: divider-specific flags for this clock
777 * @table: array of divider/value pairs ending with a div set to 0
778 * @lock: shared register lock for this clock
780 #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \
782 clk_divider_flags, table, \
784 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
785 NULL, (flags), (reg), (shift), (width), \
786 (clk_divider_flags), (table), (lock))
788 * clk_hw_register_divider_table_parent_data - register a table based divider
789 * clock with the clock framework
790 * @dev: device registering this clock
791 * @name: name of this clock
792 * @parent_data: parent clk data
793 * @flags: framework-specific flags
794 * @reg: register address to adjust divider
795 * @shift: number of bits to shift the bitfield
796 * @width: width of the bitfield
797 * @clk_divider_flags: divider-specific flags for this clock
798 * @table: array of divider/value pairs ending with a div set to 0
799 * @lock: shared register lock for this clock
801 #define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \
802 flags, reg, shift, width, \
803 clk_divider_flags, table, \
805 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
806 (parent_data), (flags), (reg), (shift), \
807 (width), (clk_divider_flags), (table), \
810 void clk_unregister_divider(struct clk *clk);
811 void clk_hw_unregister_divider(struct clk_hw *hw);
814 * struct clk_mux - multiplexer clock
816 * @hw: handle between common and hardware-specific interfaces
817 * @reg: register controlling multiplexer
818 * @table: array of register values corresponding to the parent index
819 * @shift: shift to multiplexer bit field
820 * @mask: mask of mutliplexer bit field
821 * @flags: hardware-specific flags
822 * @lock: register lock
824 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
828 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
829 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
830 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
831 * register, and mask of mux bits are in higher 16-bit of this register.
832 * While setting the mux bits, higher 16-bit should also be updated to
833 * indicate changing mux bits.
834 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
835 * .get_parent clk_op.
836 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
838 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
839 * the mux register. Setting this flag makes the register accesses big
852 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
854 #define CLK_MUX_INDEX_ONE BIT(0)
855 #define CLK_MUX_INDEX_BIT BIT(1)
856 #define CLK_MUX_HIWORD_MASK BIT(2)
857 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
858 #define CLK_MUX_ROUND_CLOSEST BIT(4)
859 #define CLK_MUX_BIG_ENDIAN BIT(5)
861 extern const struct clk_ops clk_mux_ops;
862 extern const struct clk_ops clk_mux_ro_ops;
864 struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
865 const char *name, u8 num_parents,
866 const char * const *parent_names,
867 const struct clk_hw **parent_hws,
868 const struct clk_parent_data *parent_data,
869 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
870 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
871 struct clk *clk_register_mux_table(struct device *dev, const char *name,
872 const char * const *parent_names, u8 num_parents,
873 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
874 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
876 #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \
877 shift, width, clk_mux_flags, lock) \
878 clk_register_mux_table((dev), (name), (parent_names), (num_parents), \
879 (flags), (reg), (shift), BIT((width)) - 1, \
880 (clk_mux_flags), NULL, (lock))
881 #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \
882 flags, reg, shift, mask, clk_mux_flags, \
884 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
885 (parent_names), NULL, NULL, (flags), (reg), \
886 (shift), (mask), (clk_mux_flags), (table), \
888 #define clk_hw_register_mux_table_parent_data(dev, name, parent_data, \
889 num_parents, flags, reg, shift, mask, \
890 clk_mux_flags, table, lock) \
891 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
892 NULL, NULL, (parent_data), (flags), (reg), \
893 (shift), (mask), (clk_mux_flags), (table), \
895 #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
896 shift, width, clk_mux_flags, lock) \
897 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
898 (parent_names), NULL, NULL, (flags), (reg), \
899 (shift), BIT((width)) - 1, (clk_mux_flags), \
901 #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \
902 reg, shift, width, clk_mux_flags, lock) \
903 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
904 (parent_hws), NULL, (flags), (reg), (shift), \
905 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
906 #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \
907 flags, reg, shift, width, \
908 clk_mux_flags, lock) \
909 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
910 (parent_data), (flags), (reg), (shift), \
911 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
913 int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
915 unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
917 void clk_unregister_mux(struct clk *clk);
918 void clk_hw_unregister_mux(struct clk_hw *hw);
920 void of_fixed_factor_clk_setup(struct device_node *node);
923 * struct clk_fixed_factor - fixed multiplier and divider clock
925 * @hw: handle between common and hardware-specific interfaces
929 * Clock with a fixed multiplier and divider. The output frequency is the
930 * parent clock rate divided by div and multiplied by mult.
931 * Implements .recalc_rate, .set_rate and .round_rate
934 struct clk_fixed_factor {
940 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
942 extern const struct clk_ops clk_fixed_factor_ops;
943 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
944 const char *parent_name, unsigned long flags,
945 unsigned int mult, unsigned int div);
946 void clk_unregister_fixed_factor(struct clk *clk);
947 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
948 const char *name, const char *parent_name, unsigned long flags,
949 unsigned int mult, unsigned int div);
950 void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
953 * struct clk_fractional_divider - adjustable fractional divider clock
955 * @hw: handle between common and hardware-specific interfaces
956 * @reg: register containing the divider
957 * @mshift: shift to the numerator bit field
958 * @mwidth: width of the numerator bit field
959 * @nshift: shift to the denominator bit field
960 * @nwidth: width of the denominator bit field
961 * @approximation: clk driver's callback for calculating the divider clock
962 * @lock: register lock
964 * Clock with adjustable fractional divider affecting its output frequency.
967 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
968 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
969 * is set then the numerator and denominator are both the value read
971 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
972 * used for the divider register. Setting this flag makes the register
973 * accesses big endian.
975 struct clk_fractional_divider {
985 void (*approximation)(struct clk_hw *hw,
986 unsigned long rate, unsigned long *parent_rate,
987 unsigned long *m, unsigned long *n);
991 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
993 #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
994 #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
996 extern const struct clk_ops clk_fractional_divider_ops;
997 struct clk *clk_register_fractional_divider(struct device *dev,
998 const char *name, const char *parent_name, unsigned long flags,
999 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
1000 u8 clk_divider_flags, spinlock_t *lock);
1001 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
1002 const char *name, const char *parent_name, unsigned long flags,
1003 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
1004 u8 clk_divider_flags, spinlock_t *lock);
1005 void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
1008 * struct clk_multiplier - adjustable multiplier clock
1010 * @hw: handle between common and hardware-specific interfaces
1011 * @reg: register containing the multiplier
1012 * @shift: shift to the multiplier bit field
1013 * @width: width of the multiplier bit field
1014 * @lock: register lock
1016 * Clock with an adjustable multiplier affecting its output frequency.
1017 * Implements .recalc_rate, .set_rate and .round_rate
1020 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1021 * from the register, with 0 being a valid value effectively
1022 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
1023 * set, then a null multiplier will be considered as a bypass,
1024 * leaving the parent rate unmodified.
1025 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1026 * rounded to the closest integer instead of the down one.
1027 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1028 * used for the multiplier register. Setting this flag makes the register
1029 * accesses big endian.
1031 struct clk_multiplier {
1040 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
1042 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
1043 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
1044 #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
1046 extern const struct clk_ops clk_multiplier_ops;
1049 * struct clk_composite - aggregate clock of mux, divider and gate clocks
1051 * @hw: handle between common and hardware-specific interfaces
1052 * @mux_hw: handle between composite and hardware-specific mux clock
1053 * @rate_hw: handle between composite and hardware-specific rate clock
1054 * @gate_hw: handle between composite and hardware-specific gate clock
1055 * @mux_ops: clock ops for mux
1056 * @rate_ops: clock ops for rate
1057 * @gate_ops: clock ops for gate
1059 struct clk_composite {
1063 struct clk_hw *mux_hw;
1064 struct clk_hw *rate_hw;
1065 struct clk_hw *gate_hw;
1067 const struct clk_ops *mux_ops;
1068 const struct clk_ops *rate_ops;
1069 const struct clk_ops *gate_ops;
1072 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
1074 struct clk *clk_register_composite(struct device *dev, const char *name,
1075 const char * const *parent_names, int num_parents,
1076 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1077 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1078 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1079 unsigned long flags);
1080 struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1081 const struct clk_parent_data *parent_data, int num_parents,
1082 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1083 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1084 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1085 unsigned long flags);
1086 void clk_unregister_composite(struct clk *clk);
1087 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
1088 const char * const *parent_names, int num_parents,
1089 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1090 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1091 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1092 unsigned long flags);
1093 struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
1095 const struct clk_parent_data *parent_data, int num_parents,
1096 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1097 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1098 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1099 unsigned long flags);
1100 void clk_hw_unregister_composite(struct clk_hw *hw);
1102 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
1103 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
1105 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
1106 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
1107 int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
1109 void clk_unregister(struct clk *clk);
1110 void devm_clk_unregister(struct device *dev, struct clk *clk);
1112 void clk_hw_unregister(struct clk_hw *hw);
1113 void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
1115 /* helper functions */
1116 const char *__clk_get_name(const struct clk *clk);
1117 const char *clk_hw_get_name(const struct clk_hw *hw);
1118 #ifdef CONFIG_COMMON_CLK
1119 struct clk_hw *__clk_get_hw(struct clk *clk);
1121 static inline struct clk_hw *__clk_get_hw(struct clk *clk)
1123 return (struct clk_hw *)clk;
1126 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
1127 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
1128 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
1129 unsigned int index);
1130 int clk_hw_get_parent_index(struct clk_hw *hw);
1131 int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
1132 unsigned int __clk_get_enable_count(struct clk *clk);
1133 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
1134 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
1135 #define clk_hw_can_set_rate_parent(hw) \
1136 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
1138 bool clk_hw_is_prepared(const struct clk_hw *hw);
1139 bool clk_hw_rate_is_protected(const struct clk_hw *hw);
1140 bool clk_hw_is_enabled(const struct clk_hw *hw);
1141 bool __clk_is_enabled(struct clk *clk);
1142 struct clk *__clk_lookup(const char *name);
1143 int __clk_mux_determine_rate(struct clk_hw *hw,
1144 struct clk_rate_request *req);
1145 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
1146 int __clk_mux_determine_rate_closest(struct clk_hw *hw,
1147 struct clk_rate_request *req);
1148 int clk_mux_determine_rate_flags(struct clk_hw *hw,
1149 struct clk_rate_request *req,
1150 unsigned long flags);
1151 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
1152 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
1153 unsigned long max_rate);
1155 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
1157 dst->clk = src->clk;
1158 dst->core = src->core;
1161 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
1162 unsigned long *prate,
1163 const struct clk_div_table *table,
1164 u8 width, unsigned long flags)
1166 return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
1167 rate, prate, table, width, flags);
1170 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
1171 unsigned long *prate,
1172 const struct clk_div_table *table,
1173 u8 width, unsigned long flags,
1176 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
1177 rate, prate, table, width, flags,
1182 * FIXME clock api without lock protection
1184 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
1186 struct clk_onecell_data {
1188 unsigned int clk_num;
1191 struct clk_hw_onecell_data {
1193 struct clk_hw *hws[];
1196 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
1199 * Use this macro when you have a driver that requires two initialization
1200 * routines, one at of_clk_init(), and one at platform device probe
1202 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
1203 static void __init name##_of_clk_init_driver(struct device_node *np) \
1205 of_node_clear_flag(np, OF_POPULATED); \
1208 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
1210 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \
1211 (&(struct clk_init_data) { \
1214 .parent_names = (const char *[]) { _parent }, \
1219 #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \
1220 (&(struct clk_init_data) { \
1223 .parent_hws = (const struct clk_hw*[]) { _parent }, \
1229 * This macro is intended for drivers to be able to share the otherwise
1230 * individual struct clk_hw[] compound literals created by the compiler
1231 * when using CLK_HW_INIT_HW. It does NOT support multiple parents.
1233 #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \
1234 (&(struct clk_init_data) { \
1237 .parent_hws = _parent, \
1242 #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \
1243 (&(struct clk_init_data) { \
1246 .parent_data = (const struct clk_parent_data[]) { \
1247 { .fw_name = _parent }, \
1253 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
1254 (&(struct clk_init_data) { \
1257 .parent_names = _parents, \
1258 .num_parents = ARRAY_SIZE(_parents), \
1262 #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \
1263 (&(struct clk_init_data) { \
1266 .parent_hws = _parents, \
1267 .num_parents = ARRAY_SIZE(_parents), \
1271 #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \
1272 (&(struct clk_init_data) { \
1275 .parent_data = _parents, \
1276 .num_parents = ARRAY_SIZE(_parents), \
1280 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
1281 (&(struct clk_init_data) { \
1284 .parent_names = NULL, \
1289 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \
1290 _div, _mult, _flags) \
1291 struct clk_fixed_factor _struct = { \
1294 .hw.init = CLK_HW_INIT(_name, \
1296 &clk_fixed_factor_ops, \
1300 #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \
1301 _div, _mult, _flags) \
1302 struct clk_fixed_factor _struct = { \
1305 .hw.init = CLK_HW_INIT_HW(_name, \
1307 &clk_fixed_factor_ops, \
1312 * This macro allows the driver to reuse the _parent array for multiple
1313 * fixed factor clk declarations.
1315 #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \
1316 _div, _mult, _flags) \
1317 struct clk_fixed_factor _struct = { \
1320 .hw.init = CLK_HW_INIT_HWS(_name, \
1322 &clk_fixed_factor_ops, \
1326 #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \
1327 _div, _mult, _flags) \
1328 struct clk_fixed_factor _struct = { \
1331 .hw.init = CLK_HW_INIT_FW_NAME(_name, \
1333 &clk_fixed_factor_ops, \
1338 int of_clk_add_provider(struct device_node *np,
1339 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1342 int of_clk_add_hw_provider(struct device_node *np,
1343 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1346 int devm_of_clk_add_hw_provider(struct device *dev,
1347 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1350 void of_clk_del_provider(struct device_node *np);
1351 void devm_of_clk_del_provider(struct device *dev);
1352 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
1354 struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
1356 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1357 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
1359 int of_clk_parent_fill(struct device_node *np, const char **parents,
1361 int of_clk_detect_critical(struct device_node *np, int index,
1362 unsigned long *flags);
1364 #else /* !CONFIG_OF */
1366 static inline int of_clk_add_provider(struct device_node *np,
1367 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1373 static inline int of_clk_add_hw_provider(struct device_node *np,
1374 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1380 static inline int devm_of_clk_add_hw_provider(struct device *dev,
1381 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1387 static inline void of_clk_del_provider(struct device_node *np) {}
1388 static inline void devm_of_clk_del_provider(struct device *dev) {}
1389 static inline struct clk *of_clk_src_simple_get(
1390 struct of_phandle_args *clkspec, void *data)
1392 return ERR_PTR(-ENOENT);
1394 static inline struct clk_hw *
1395 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
1397 return ERR_PTR(-ENOENT);
1399 static inline struct clk *of_clk_src_onecell_get(
1400 struct of_phandle_args *clkspec, void *data)
1402 return ERR_PTR(-ENOENT);
1404 static inline struct clk_hw *
1405 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
1407 return ERR_PTR(-ENOENT);
1409 static inline int of_clk_parent_fill(struct device_node *np,
1410 const char **parents, unsigned int size)
1414 static inline int of_clk_detect_critical(struct device_node *np, int index,
1415 unsigned long *flags)
1419 #endif /* CONFIG_OF */
1421 void clk_gate_restore_context(struct clk_hw *hw);
1423 #endif /* CLK_PROVIDER_H */