2 * linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel.
6 * Copyright (C) 2001 ARM Limited
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main directory of this archive
13 #include <linux/amba/clcd-regs.h>
16 /* individual formats */
17 CLCD_CAP_RGB444 = (1 << 0),
18 CLCD_CAP_RGB5551 = (1 << 1),
19 CLCD_CAP_RGB565 = (1 << 2),
20 CLCD_CAP_RGB888 = (1 << 3),
21 CLCD_CAP_BGR444 = (1 << 4),
22 CLCD_CAP_BGR5551 = (1 << 5),
23 CLCD_CAP_BGR565 = (1 << 6),
24 CLCD_CAP_BGR888 = (1 << 7),
26 /* connection layouts */
27 CLCD_CAP_444 = CLCD_CAP_RGB444 | CLCD_CAP_BGR444,
28 CLCD_CAP_5551 = CLCD_CAP_RGB5551 | CLCD_CAP_BGR5551,
29 CLCD_CAP_565 = CLCD_CAP_RGB565 | CLCD_CAP_BGR565,
30 CLCD_CAP_888 = CLCD_CAP_RGB888 | CLCD_CAP_BGR888,
32 /* red/blue ordering */
33 CLCD_CAP_RGB = CLCD_CAP_RGB444 | CLCD_CAP_RGB5551 |
34 CLCD_CAP_RGB565 | CLCD_CAP_RGB888,
35 CLCD_CAP_BGR = CLCD_CAP_BGR444 | CLCD_CAP_BGR5551 |
36 CLCD_CAP_BGR565 | CLCD_CAP_BGR888,
38 CLCD_CAP_ALL = CLCD_CAP_BGR | CLCD_CAP_RGB,
41 struct backlight_device;
44 struct fb_videomode mode;
45 signed short width; /* width in mm */
46 signed short height; /* height in mm */
54 unsigned int connector;
55 struct backlight_device *backlight;
57 * If the B/R lines are switched between the CLCD
58 * and the panel we need to know this and not try to
59 * compensate with the BGR bit in the control register.
70 unsigned long pixclock;
76 * the board-type specific routines
82 * Optional. Hardware capability flags.
87 * Optional. Check whether the var structure is acceptable
90 int (*check)(struct clcd_fb *fb, struct fb_var_screeninfo *var);
93 * Compulsory. Decode fb->fb.var into regs->*. In the case of
94 * fixed timing, set regs->* to the register values required.
96 void (*decode)(struct clcd_fb *fb, struct clcd_regs *regs);
99 * Optional. Disable any extra display hardware.
101 void (*disable)(struct clcd_fb *);
104 * Optional. Enable any extra display hardware.
106 void (*enable)(struct clcd_fb *);
109 * Setup platform specific parts of CLCD driver
111 int (*setup)(struct clcd_fb *);
114 * mmap the framebuffer memory
116 int (*mmap)(struct clcd_fb *, struct vm_area_struct *);
119 * Remove platform specific parts of CLCD driver
121 void (*remove)(struct clcd_fb *);
128 * struct clcd_vendor_data - holds hardware (IP-block) vendor-specific
129 * variant information
131 * @clock_timregs: the CLCD needs to be clocked when accessing the
132 * timer registers, or the hardware will hang.
133 * @packed_24_bit_pixels: this variant supports 24bit packed pixel data,
134 * so that RGB accesses 3 bytes at a time, not just on even 32bit
135 * boundaries, packing the pixel data in memory. ST Microelectronics
137 * @st_bitmux_control: ST Microelectronics have implemented output
138 * bit line multiplexing into the CLCD control register. This indicates
139 * that we need to use this.
140 * @init_board: custom board init function for this variant
141 * @init_panel: custom panel init function for this variant
143 struct clcd_vendor_data {
145 bool packed_24_bit_pixels;
146 bool st_bitmux_control;
147 int (*init_board)(struct amba_device *adev,
148 struct clcd_board *board);
149 int (*init_panel)(struct clcd_fb *fb,
150 struct device_node *panel);
153 /* this data structure describes each frame buffer device we find */
156 struct amba_device *dev;
158 struct clcd_vendor_data *vendor;
159 struct clcd_panel *panel;
160 struct clcd_board *board;
170 static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
172 struct fb_var_screeninfo *var = &fb->fb.var;
176 * Program the CLCD controller registers and start the CLCD
178 val = ((var->xres / 16) - 1) << 2;
179 val |= (var->hsync_len - 1) << 8;
180 val |= (var->right_margin - 1) << 16;
181 val |= (var->left_margin - 1) << 24;
185 if (fb->panel->cntl & CNTL_LCDDUAL)
188 val |= (var->vsync_len - 1) << 10;
189 val |= var->lower_margin << 16;
190 val |= var->upper_margin << 24;
193 val = fb->panel->tim2;
194 val |= var->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : TIM2_IHS;
195 val |= var->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : TIM2_IVS;
197 cpl = var->xres_virtual;
198 if (fb->panel->cntl & CNTL_LCDTFT) /* TFT */
200 else if (!var->grayscale) /* STN color */
202 else if (fb->panel->cntl & CNTL_LCDMONO8) /* STN monochrome, 8bit */
204 else /* STN monochrome, 4bit */
207 regs->tim2 = val | ((cpl - 1) << 16);
209 regs->tim3 = fb->panel->tim3;
211 val = fb->panel->cntl;
215 if (fb->panel->caps && fb->board->caps && var->bits_per_pixel >= 16) {
217 * if board and panel supply capabilities, we can support
218 * changing BGR/RGB depending on supplied parameters. Here
219 * we switch to what the framebuffer is providing if need
220 * be, so if the framebuffer is BGR but the display connection
221 * is RGB (first case) we switch it around. Vice versa mutatis
222 * mutandis if the framebuffer is RGB but the display connection
223 * is BGR, we flip it around.
225 if (var->red.offset == 0)
229 if (fb->panel->bgr_connection)
233 switch (var->bits_per_pixel) {
248 * PL110 cannot choose between 5551 and 565 modes in its
249 * control register. It is possible to use 565 with
250 * custom external wiring.
252 if (amba_part(fb->dev) == 0x110 ||
253 var->green.length == 5)
254 val |= CNTL_LCDBPP16;
255 else if (var->green.length == 6)
256 val |= CNTL_LCDBPP16_565;
258 val |= CNTL_LCDBPP16_444;
261 /* Modified variant supporting 24 bit packed pixels */
262 val |= CNTL_ST_LCDBPP24_PACKED;
265 val |= CNTL_LCDBPP24;
270 regs->pixclock = var->pixclock;
273 static inline int clcdfb_check(struct clcd_fb *fb, struct fb_var_screeninfo *var)
275 var->xres_virtual = var->xres = (var->xres + 15) & ~15;
276 var->yres_virtual = var->yres = (var->yres + 1) & ~1;
278 #define CHECK(e,l,h) (var->e < l || var->e > h)
279 if (CHECK(right_margin, (5+1), 256) || /* back porch */
280 CHECK(left_margin, (5+1), 256) || /* front porch */
281 CHECK(hsync_len, (5+1), 256) ||
283 var->lower_margin > 255 || /* back porch */
284 var->upper_margin > 255 || /* front porch */
285 var->vsync_len > 32 ||
290 /* single panel mode: PCD = max(PCD, 1) */
291 /* dual panel mode: PCD = max(PCD, 5) */
294 * You can't change the grayscale setting, and
295 * we can only do non-interlaced video.
297 if (var->grayscale != fb->fb.var.grayscale ||
298 (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
301 #define CHECK(e) (var->e != fb->fb.var.e)
302 if (fb->panel->fixedtimings &&
305 CHECK(bits_per_pixel) ||
307 CHECK(left_margin) ||
308 CHECK(right_margin) ||
309 CHECK(upper_margin) ||
310 CHECK(lower_margin) ||
318 var->accel_flags = 0;