include/dt-bindings/reset/tegra234-reset.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
   3
   4 #ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H
   5 #define DT_BINDINGS_RESET_TEGRA234_RESET_H
   6
   7 /**
   8  * @file
   9  * @defgroup bpmp_reset_ids Reset ID's
  10  * @brief Identifiers for Resets controllable by firmware
  11  * @{
  12  */
  13 #define TEGRA234_RESET_PEX1_CORE_6              11U
  14 #define TEGRA234_RESET_PEX1_CORE_6_APB          12U
  15 #define TEGRA234_RESET_PEX1_COMMON_APB          13U
  16 #define TEGRA234_RESET_PEX2_CORE_7              14U
  17 #define TEGRA234_RESET_PEX2_CORE_7_APB          15U
  18 #define TEGRA234_RESET_HDA                      20U
  19 #define TEGRA234_RESET_HDACODEC                 21U
  20 #define TEGRA234_RESET_I2C1                     24U
  21 #define TEGRA234_RESET_PEX2_CORE_8              25U
  22 #define TEGRA234_RESET_PEX2_CORE_8_APB          26U
  23 #define TEGRA234_RESET_PEX2_CORE_9              27U
  24 #define TEGRA234_RESET_PEX2_CORE_9_APB          28U
  25 #define TEGRA234_RESET_I2C2                     29U
  26 #define TEGRA234_RESET_I2C3                     30U
  27 #define TEGRA234_RESET_I2C4                     31U
  28 #define TEGRA234_RESET_I2C6                     32U
  29 #define TEGRA234_RESET_I2C7                     33U
  30 #define TEGRA234_RESET_I2C8                     34U
  31 #define TEGRA234_RESET_I2C9                     35U
  32 #define TEGRA234_RESET_PEX2_CORE_10             56U
  33 #define TEGRA234_RESET_PEX2_CORE_10_APB         57U
  34 #define TEGRA234_RESET_PEX2_COMMON_APB          58U
  35 #define TEGRA234_RESET_PWM1                     68U
  36 #define TEGRA234_RESET_PWM2                     69U
  37 #define TEGRA234_RESET_PWM3                     70U
  38 #define TEGRA234_RESET_PWM4                     71U
  39 #define TEGRA234_RESET_PWM5                     72U
  40 #define TEGRA234_RESET_PWM6                     73U
  41 #define TEGRA234_RESET_PWM7                     74U
  42 #define TEGRA234_RESET_PWM8                     75U
  43 #define TEGRA234_RESET_QSPI0                    76U
  44 #define TEGRA234_RESET_QSPI1                    77U
  45 #define TEGRA234_RESET_SDMMC4                   85U
  46 #define TEGRA234_RESET_UARTA                    100U
  47 #define TEGRA234_RESET_PEX0_CORE_0              116U
  48 #define TEGRA234_RESET_PEX0_CORE_1              117U
  49 #define TEGRA234_RESET_PEX0_CORE_2              118U
  50 #define TEGRA234_RESET_PEX0_CORE_3              119U
  51 #define TEGRA234_RESET_PEX0_CORE_4              120U
  52 #define TEGRA234_RESET_PEX0_CORE_0_APB          121U
  53 #define TEGRA234_RESET_PEX0_CORE_1_APB          122U
  54 #define TEGRA234_RESET_PEX0_CORE_2_APB          123U
  55 #define TEGRA234_RESET_PEX0_CORE_3_APB          124U
  56 #define TEGRA234_RESET_PEX0_CORE_4_APB          125U
  57 #define TEGRA234_RESET_PEX0_COMMON_APB          126U
  58 #define TEGRA234_RESET_PEX1_CORE_5              129U
  59 #define TEGRA234_RESET_PEX1_CORE_5_APB          130U
  60
  61 /** @} */
  62
  63 #endif